From patchwork Mon Jul 10 10:37:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Praveenkumar I X-Patchwork-Id: 701161 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3D8A1EB64D9 for ; Mon, 10 Jul 2023 10:38:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229577AbjGJKiM (ORCPT ); Mon, 10 Jul 2023 06:38:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45304 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233500AbjGJKiJ (ORCPT ); Mon, 10 Jul 2023 06:38:09 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2AA1CCC; Mon, 10 Jul 2023 03:38:07 -0700 (PDT) Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 36AABES2030520; Mon, 10 Jul 2023 10:38:02 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=VcEOrIXnrgQ7Syrp9H4WKh6EvvZP7BoE9m1n0+Q/CbE=; b=fgMwhCh1Gs0l0L+SfMMzJ/8X87exBi/CTjlJsRCW39XToRKna3MqTI6A4aruCqJn2q5o HvuqhnLR8EradClfzFjf2yq7F/ZL+xTPSH6NRK5DErwI8uivzH9MeGrNBKyzbwMU3uw/ d/RLDrIYKNSoKP68XWRPrnTZBnqWW3p1I2UQh5JpZEcq1C+sGBCJ/DeLdZPcyZG/r6Ln j1IxezEQLBzmJuUWHYiCvUow7Jf+rXzJFzuq1+9zoDPMQbwFZSpyi+UQeadATsWcdGAx K/j3by3YF5go55P43eOjdSaJ5EAUraQNQVtxmT5q/OU4sD8z1A2jPOM5ui8IDaMRMVhh 1g== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3rpyw1ua24-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 10 Jul 2023 10:38:02 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 36AAc1eq012815 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 10 Jul 2023 10:38:01 GMT Received: from hu-ipkumar-blr.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Mon, 10 Jul 2023 03:37:56 -0700 From: Praveenkumar I To: , , , , , , , , , , , , , , CC: Subject: [PATCH 1/6] dt-bindings: thermal: tsens: Add nvmem cells for calibration data Date: Mon, 10 Jul 2023 16:07:30 +0530 Message-ID: <20230710103735.1375847-2-quic_ipkumar@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230710103735.1375847-1-quic_ipkumar@quicinc.com> References: <20230710103735.1375847-1-quic_ipkumar@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: scTWEqQJ8M4Gs3QxE_13-qnneS268xR7 X-Proofpoint-ORIG-GUID: scTWEqQJ8M4Gs3QxE_13-qnneS268xR7 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-10_08,2023-07-06_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 priorityscore=1501 clxscore=1011 lowpriorityscore=0 adultscore=0 phishscore=0 mlxlogscore=999 bulkscore=0 malwarescore=0 impostorscore=0 mlxscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2307100096 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add TSENS V2 calibration nvmem cells for IPQ5332 Signed-off-by: Praveenkumar I --- .../bindings/thermal/qcom-tsens.yaml | 26 +++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml index 27e9e16e6455..8b7863c3989e 100644 --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml @@ -91,7 +91,7 @@ properties: maxItems: 2 nvmem-cells: - oneOf: + anyOf: - minItems: 1 maxItems: 2 description: @@ -106,9 +106,13 @@ properties: description: | Reference to nvmem cells for the calibration mode, two calibration bases and two cells per each sensor, main and backup copies, plus use_backup cell + - maxItems: 17 + description: | + V2 of TSENS, reference to nvmem cells for the calibration mode, two calibration + bases and one cell per each sensor nvmem-cell-names: - oneOf: + anyOf: - minItems: 1 items: - const: calib @@ -205,6 +209,24 @@ properties: - const: s9_p2_backup - const: s10_p1_backup - const: s10_p2_backup + - items: + - const: mode + - const: base0 + - const: base1 + - const: s0_offset + - const: s3_offset + - const: s4_offset + - const: s5_offset + - const: s6_offset + - const: s7_offset + - const: s8_offset + - const: s9_offset + - const: s10_offset + - const: s11_offset + - const: s12_offset + - const: s13_offset + - const: s14_offset + - const: s15_offset "#qcom,sensors": description: From patchwork Mon Jul 10 10:37:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Praveenkumar I X-Patchwork-Id: 701646 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F1255EB64DA for ; Mon, 10 Jul 2023 10:38:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233389AbjGJKij (ORCPT ); Mon, 10 Jul 2023 06:38:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45710 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231919AbjGJKic (ORCPT ); Mon, 10 Jul 2023 06:38:32 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9F45FF1; Mon, 10 Jul 2023 03:38:24 -0700 (PDT) Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 36A8iCUq000759; Mon, 10 Jul 2023 10:38:19 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=oyvSZCnrjiwfW283ewhhiGsaeUGlLsIHbf5b37AONNs=; b=HYgo3g9wZGh+HxdPlAQ6Ob68wO2XdLaJehYgKoVWjUTpnYYZzUDz7BR6fmk0KkCJ/9nw gMP/fro51otCMkzLKMkVqlgdqr5aNqaiEhW3ZTDiZuQDESuWYzByD6lp3KQGP2ef8kEw 9d6AVmFPIMONaHm/tMh+5i4JcIhCm68MDyhewGj35A5GHtEOUuWLMR54XyHvIDJgFjXe NSuCmRK9XP7RaxrFBLMSjncjVrsJLZxWCcaOVP767Y+27PPwqla9iU4IBsQPgMqq4skb fcNzPNspzKlA7ZGZfE5sNm/SHW4Auid+l0AVh+yI+85Y1DeiCqoHOahfvah3tykj28me 2w== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3rpyw1ua4d-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 10 Jul 2023 10:38:18 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 36AAc5qc013356 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 10 Jul 2023 10:38:05 GMT Received: from hu-ipkumar-blr.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Mon, 10 Jul 2023 03:38:01 -0700 From: Praveenkumar I To: , , , , , , , , , , , , , , CC: Subject: [PATCH 2/6] thermal/drivers/tsens: Add TSENS enable and calibration support for V2 Date: Mon, 10 Jul 2023 16:07:31 +0530 Message-ID: <20230710103735.1375847-3-quic_ipkumar@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230710103735.1375847-1-quic_ipkumar@quicinc.com> References: <20230710103735.1375847-1-quic_ipkumar@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 79QeMqjAxdI8INhqjXsabpLLg1tiLdt4 X-Proofpoint-ORIG-GUID: 79QeMqjAxdI8INhqjXsabpLLg1tiLdt4 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-10_08,2023-07-06_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 priorityscore=1501 clxscore=1015 lowpriorityscore=0 adultscore=0 phishscore=0 mlxlogscore=999 bulkscore=0 malwarescore=0 impostorscore=0 mlxscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2307100096 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org SoCs without RPM have to enable sensors and calibrate from the kernel. Though TSENS IP supports 16 sensors, not all are used. So added sensors_to_en in tsens data help enable the relevant sensors. Added new calibration function for V2 as the tsens.c calib function only supports V1. Signed-off-by: Praveenkumar I --- drivers/thermal/qcom/tsens-v2.c | 116 ++++++++++++++++++++++++++++++++ drivers/thermal/qcom/tsens.c | 37 +++++++++- drivers/thermal/qcom/tsens.h | 56 +++++++++++++++ 3 files changed, 208 insertions(+), 1 deletion(-) diff --git a/drivers/thermal/qcom/tsens-v2.c b/drivers/thermal/qcom/tsens-v2.c index 29a61d2d6ca3..db48b1d95348 100644 --- a/drivers/thermal/qcom/tsens-v2.c +++ b/drivers/thermal/qcom/tsens-v2.c @@ -6,11 +6,20 @@ #include #include +#include #include "tsens.h" /* ----- SROT ------ */ #define SROT_HW_VER_OFF 0x0000 #define SROT_CTRL_OFF 0x0004 +#define SROT_MEASURE_PERIOD 0x0008 +#define SROT_Sn_CONVERSION 0x0060 +#define V2_SHIFT_DEFAULT 0x0003 +#define V2_SLOPE_DEFAULT 0x0cd0 +#define V2_CZERO_DEFAULT 0x016a +#define ONE_PT_SLOPE 0x0cd0 +#define TWO_PT_SHIFTED_GAIN 921600 +#define ONE_PT_CZERO_CONST 94 /* ----- TM ------ */ #define TM_INT_EN_OFF 0x0004 @@ -59,6 +68,16 @@ static const struct reg_field tsens_v2_regfields[MAX_REGFIELDS] = { /* CTRL_OFF */ [TSENS_EN] = REG_FIELD(SROT_CTRL_OFF, 0, 0), [TSENS_SW_RST] = REG_FIELD(SROT_CTRL_OFF, 1, 1), + [SENSOR_EN] = REG_FIELD(SROT_CTRL_OFF, 3, 18), + [CODE_OR_TEMP] = REG_FIELD(SROT_CTRL_OFF, 21, 21), + + /* MAIN_MEASURE_PERIOD */ + [MAIN_MEASURE_PERIOD] = REG_FIELD(SROT_MEASURE_PERIOD, 0, 7), + + /* Sn Conversion */ + REG_FIELD_FOR_EACH_SENSOR16(SHIFT, SROT_Sn_CONVERSION, 23, 24), + REG_FIELD_FOR_EACH_SENSOR16(SLOPE, SROT_Sn_CONVERSION, 10, 22), + REG_FIELD_FOR_EACH_SENSOR16(CZERO, SROT_Sn_CONVERSION, 0, 9), /* ----- TM ------ */ /* INTERRUPT ENABLE */ @@ -104,6 +123,103 @@ static const struct reg_field tsens_v2_regfields[MAX_REGFIELDS] = { [TRDY] = REG_FIELD(TM_TRDY_OFF, 0, 0), }; +static int tsens_v2_calibration(struct tsens_priv *priv) +{ + struct device *dev = priv->dev; + u32 mode, base0, base1; + u32 slope, czero; + char name[15]; + int i, j, ret; + + if (priv->num_sensors > MAX_SENSORS) + return -EINVAL; + + ret = nvmem_cell_read_variable_le_u32(priv->dev, "mode", &mode); + if (ret == -ENOENT) + dev_warn(priv->dev, "Calibration data not present in DT\n"); + if (ret < 0) + return ret; + + dev_dbg(priv->dev, "calibration mode is %d\n", mode); + + ret = nvmem_cell_read_variable_le_u32(priv->dev, "base0", &base0); + if (ret < 0) + return ret; + + ret = nvmem_cell_read_variable_le_u32(priv->dev, "base1", &base1); + if (ret < 0) + return ret; + + /* Read offset values and allocate SHIFT, SLOPE & CZERO regmap for enabled sensors */ + for (i = 0; i < priv->num_sensors; i++) { + if (!(priv->sensors_to_en & (0x1 << i))) + continue; + + ret = snprintf(name, sizeof(name), "s%d_offset", priv->sensor[i].hw_id); + if (ret < 0) + return ret; + + ret = nvmem_cell_read_variable_le_u32(priv->dev, name, &priv->sensor[i].offset); + if (ret) + return ret; + + for (j = SHIFT_0; j <= CZERO_0; j++) { + int idx = (i * 3) + j; + + priv->rf[idx] = devm_regmap_field_alloc(dev, priv->srot_map, + priv->fields[idx]); + if (IS_ERR(priv->rf[idx])) + return PTR_ERR(priv->rf[idx]); + } + } + + /* Based on calib mode, program SHIFT, SLOPE and CZERO for enabled sensors */ + switch (mode) { + case TWO_PT_CALIB: + slope = (TWO_PT_SHIFTED_GAIN / (base1 - base0)); + + for (i = 0; i < priv->num_sensors; i++) { + if (!(priv->sensors_to_en & (0x1 << i))) + continue; + + int idx = i * 3; + + czero = (base0 + priv->sensor[i].offset - ((base1 - base0) / 3)); + regmap_field_write(priv->rf[SHIFT_0 + idx], V2_SHIFT_DEFAULT); + regmap_field_write(priv->rf[SLOPE_0 + idx], slope); + regmap_field_write(priv->rf[CZERO_0 + idx], czero); + } + fallthrough; + case ONE_PT_CALIB2: + for (i = 0; i < priv->num_sensors; i++) { + if (!(priv->sensors_to_en & (0x1 << i))) + continue; + + int idx = i * 3; + + czero = base0 + priv->sensor[i].offset - ONE_PT_CZERO_CONST; + regmap_field_write(priv->rf[SHIFT_0 + idx], V2_SHIFT_DEFAULT); + regmap_field_write(priv->rf[SLOPE_0 + idx], ONE_PT_SLOPE); + regmap_field_write(priv->rf[CZERO_0 + idx], czero); + } + break; + default: + dev_dbg(priv->dev, "calibrationless mode\n"); + for (i = 0; i < priv->num_sensors; i++) { + if (!(priv->sensors_to_en & (0x1 << i))) + continue; + + int idx = i * 3; + + regmap_field_write(priv->rf[SHIFT_0 + idx], V2_SHIFT_DEFAULT); + regmap_field_write(priv->rf[SLOPE_0 + idx], V2_SLOPE_DEFAULT); + regmap_field_write(priv->rf[CZERO_0 + idx], V2_CZERO_DEFAULT); + } + } + + return 0; +} + static const struct tsens_ops ops_generic_v2 = { .init = init_common, .get_temp = get_temp_tsens_valid, diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index 98c356acfe98..169690355dad 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -974,7 +974,7 @@ int __init init_common(struct tsens_priv *priv) ret = regmap_field_read(priv->rf[TSENS_EN], &enabled); if (ret) goto err_put_device; - if (!enabled) { + if (!enabled && !priv->sensors_to_en) { dev_err(dev, "%s: device not enabled\n", __func__); ret = -ENODEV; goto err_put_device; @@ -1006,6 +1006,40 @@ int __init init_common(struct tsens_priv *priv) goto err_put_device; } + /* Do TSENS initialization if required */ + if (priv->sensors_to_en) { + priv->rf[CODE_OR_TEMP] = devm_regmap_field_alloc(dev, priv->srot_map, + priv->fields[CODE_OR_TEMP]); + if (IS_ERR(priv->rf[CODE_OR_TEMP])) { + ret = PTR_ERR(priv->rf[CODE_OR_TEMP]); + goto err_put_device; + } + + priv->rf[MAIN_MEASURE_PERIOD] = + devm_regmap_field_alloc(dev, priv->srot_map, + priv->fields[MAIN_MEASURE_PERIOD]); + if (IS_ERR(priv->rf[MAIN_MEASURE_PERIOD])) { + ret = PTR_ERR(priv->rf[MAIN_MEASURE_PERIOD]); + goto err_put_device; + } + + regmap_field_write(priv->rf[TSENS_SW_RST], 0x1); + + /* Update measure period to 2ms */ + regmap_field_write(priv->rf[MAIN_MEASURE_PERIOD], 0x1); + + /* Enable available sensors */ + regmap_field_write(priv->rf[SENSOR_EN], priv->sensors_to_en); + + /* Real temperature format */ + regmap_field_write(priv->rf[CODE_OR_TEMP], 0x1); + + regmap_field_write(priv->rf[TSENS_SW_RST], 0x0); + + /* Enable TSENS */ + regmap_field_write(priv->rf[TSENS_EN], 0x1); + } + /* This loop might need changes if enum regfield_ids is reordered */ for (j = LAST_TEMP_0; j <= UP_THRESH_15; j += 16) { for (i = 0; i < priv->feat->max_sensors; i++) { @@ -1282,6 +1316,7 @@ static int tsens_probe(struct platform_device *pdev) priv->dev = dev; priv->num_sensors = num_sensors; + priv->sensors_to_en = data->sensors_to_en; priv->ops = data->ops; for (i = 0; i < priv->num_sensors; i++) { if (data->hw_ids) diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index 2805de1c6827..f8897bc8944e 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -168,6 +168,58 @@ enum regfield_ids { TSENS_SW_RST, SENSOR_EN, CODE_OR_TEMP, + /* MEASURE_PERIOD */ + MAIN_MEASURE_PERIOD, + + /* Sn_CONVERSION */ + SHIFT_0, + SLOPE_0, + CZERO_0, + SHIFT_1, + SLOPE_1, + CZERO_1, + SHIFT_2, + SLOPE_2, + CZERO_2, + SHIFT_3, + SLOPE_3, + CZERO_3, + SHIFT_4, + SLOPE_4, + CZERO_4, + SHIFT_5, + SLOPE_5, + CZERO_5, + SHIFT_6, + SLOPE_6, + CZERO_6, + SHIFT_7, + SLOPE_7, + CZERO_7, + SHIFT_8, + SLOPE_8, + CZERO_8, + SHIFT_9, + SLOPE_9, + CZERO_9, + SHIFT_10, + SLOPE_10, + CZERO_10, + SHIFT_11, + SLOPE_11, + CZERO_11, + SHIFT_12, + SLOPE_12, + CZERO_12, + SHIFT_13, + SLOPE_13, + CZERO_13, + SHIFT_14, + SLOPE_14, + CZERO_14, + SHIFT_15, + SLOPE_15, + CZERO_15, /* ----- TM ------ */ /* TRDY */ @@ -524,6 +576,7 @@ struct tsens_features { /** * struct tsens_plat_data - tsens compile-time platform data * @num_sensors: Number of sensors supported by platform + * @sensors_to_en: Sensors to be enabled. Each bit represent a sensor * @ops: operations the tsens instance supports * @hw_ids: Subset of sensors ids supported by platform, if not the first n * @feat: features of the IP @@ -531,6 +584,7 @@ struct tsens_features { */ struct tsens_plat_data { const u32 num_sensors; + const u16 sensors_to_en; const struct tsens_ops *ops; unsigned int *hw_ids; struct tsens_features *feat; @@ -551,6 +605,7 @@ struct tsens_context { * struct tsens_priv - private data for each instance of the tsens IP * @dev: pointer to struct device * @num_sensors: number of sensors enabled on this device + * @sensors_to_en: sensors to be enabled. Each bit represents a sensor * @tm_map: pointer to TM register address space * @srot_map: pointer to SROT register address space * @tm_offset: deal with old device trees that don't address TM and SROT @@ -569,6 +624,7 @@ struct tsens_context { struct tsens_priv { struct device *dev; u32 num_sensors; + u16 sensors_to_en; struct regmap *tm_map; struct regmap *srot_map; u32 tm_offset; From patchwork Mon Jul 10 10:37:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Praveenkumar I X-Patchwork-Id: 701159 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 83FD8EB64D9 for ; Mon, 10 Jul 2023 10:38:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233532AbjGJKi5 (ORCPT ); Mon, 10 Jul 2023 06:38:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45816 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232798AbjGJKiw (ORCPT ); Mon, 10 Jul 2023 06:38:52 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B72E8E3; Mon, 10 Jul 2023 03:38:29 -0700 (PDT) Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 36A8xhIe008012; Mon, 10 Jul 2023 10:38:23 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=u/DwDH2n/Z0MxREbI5gMlCljTRrvD0J9NWub+hZfLOU=; b=h7b+ltl+yiarms2ZBzsuoVMziCpNVidHC2a0WvQicJzufJwHAovrScpndwQPWEukhyGf Z+CK6/VX2NGMiCoaa6/mQoQdBHpLYgid3cdej7ESNM/OIuGL6YwLWWgTUqIbPZ6+D7Z8 XzKr3k4MGXVAMsB0Q0ADvVXHb7V8VfQVDhRWYhZdwJWSksxw/cqYTpCs3XuFa6jxNzeW y8LsshUdzrJ1R341GuIUNqcHTBkKet79Rsi6abeXvSl0HtKqKSYlEymHMzdz/NSRKPrR 7C2CuSZNfy4TOi37l73cWYyAnaDc8LXQ9hGxqG1SBmgu2maB4EDczJy1k7swufRhNOM4 ow== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3rpyd6uag4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 10 Jul 2023 10:38:23 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 36AAcAr9017283 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 10 Jul 2023 10:38:10 GMT Received: from hu-ipkumar-blr.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Mon, 10 Jul 2023 03:38:05 -0700 From: Praveenkumar I To: , , , , , , , , , , , , , , CC: Subject: [PATCH 3/6] dt-bindings: thermal: tsens: Add ipq5332 compatible Date: Mon, 10 Jul 2023 16:07:32 +0530 Message-ID: <20230710103735.1375847-4-quic_ipkumar@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230710103735.1375847-1-quic_ipkumar@quicinc.com> References: <20230710103735.1375847-1-quic_ipkumar@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: LUbr4zSV2sMbANqKIGt0_PVh6CVBKtTa X-Proofpoint-ORIG-GUID: LUbr4zSV2sMbANqKIGt0_PVh6CVBKtTa X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-10_08,2023-07-06_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 impostorscore=0 adultscore=0 spamscore=0 phishscore=0 mlxlogscore=999 priorityscore=1501 clxscore=1015 bulkscore=0 suspectscore=0 malwarescore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2307100096 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org IPQ5332 uses TSENS v2.3.3 with combined interrupt. RPM is not available in the SoC, hence adding new compatible to have the sensor enablement and calibration function. Signed-off-by: Praveenkumar I --- Documentation/devicetree/bindings/thermal/qcom-tsens.yaml | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml index 8b7863c3989e..ee57713f6131 100644 --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml @@ -68,8 +68,10 @@ properties: - const: qcom,tsens-v2 - description: v2 of TSENS with combined interrupt - enum: - - qcom,ipq8074-tsens + items: + - enum: + - qcom,ipq8074-tsens + - qcom,ipq5332-tsens - description: v2 of TSENS with combined interrupt items: @@ -289,6 +291,7 @@ allOf: contains: enum: - qcom,ipq8074-tsens + - qcom,ipq5332-tsens then: properties: interrupts: @@ -304,6 +307,7 @@ allOf: contains: enum: - qcom,ipq8074-tsens + - qcom,ipq5332-tsens - qcom,tsens-v0_1 - qcom,tsens-v1 - qcom,tsens-v2 From patchwork Mon Jul 10 10:37:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Praveenkumar I X-Patchwork-Id: 701160 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6F6EBEB64DA for ; Mon, 10 Jul 2023 10:38:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232678AbjGJKia (ORCPT ); Mon, 10 Jul 2023 06:38:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45436 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232524AbjGJKi1 (ORCPT ); Mon, 10 Jul 2023 06:38:27 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C5851FB; Mon, 10 Jul 2023 03:38:22 -0700 (PDT) Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 36A9jTjN022183; Mon, 10 Jul 2023 10:38:16 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=bfNOF/GRWeeHJbmWyRnvqYdWgqv/8yp+BQB3y1VQsOk=; b=WRL+3hqVse1KujBZ6Kz6IE+NuxM7XVgE75oqHRiIiiYbuJpyzS1omyguAPW3AVVNWKRF k7HgHrU5rPikPdj8dMmxighOV2GYOpkP49U49RzWM4WANm+M6+2Jh2n4pQ7O1lV5POms pAeBWyQqbINdKmvn2xMexhtzhRFyW0wbaOYxuD9NHQ6p1ZWWF5zSvRLK/bufCKHbcypi qWvqflpyt8hL8phL6SARCvEXdS0vi1Ind/WCJhUVclNGcGEtVnp7o2iVB845Gd7G3J4B 3HPD/5/pGeyeH88gdPvx/iAUbkufGisYiwVet+/77iSf7vLfg58nNqfAnyZvJu6H+KNy Rg== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3rpxteuac2-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 10 Jul 2023 10:38:16 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 36AAcFIl013695 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 10 Jul 2023 10:38:15 GMT Received: from hu-ipkumar-blr.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Mon, 10 Jul 2023 03:38:10 -0700 From: Praveenkumar I To: , , , , , , , , , , , , , , CC: Subject: [PATCH 4/6] arm64: dts: qcom: ipq5332: Add tsens node Date: Mon, 10 Jul 2023 16:07:33 +0530 Message-ID: <20230710103735.1375847-5-quic_ipkumar@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230710103735.1375847-1-quic_ipkumar@quicinc.com> References: <20230710103735.1375847-1-quic_ipkumar@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: Q1tzYNmWuLQ9shshDY-jcNDnomCiK-pT X-Proofpoint-ORIG-GUID: Q1tzYNmWuLQ9shshDY-jcNDnomCiK-pT X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-10_08,2023-07-06_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 priorityscore=1501 clxscore=1011 impostorscore=0 mlxlogscore=696 bulkscore=0 spamscore=0 malwarescore=0 adultscore=0 phishscore=0 suspectscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2307100096 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org IPQ5332 has tsens v2.3.3 peripheral. This patch adds the tsense node with nvmem cells for calibration data. Signed-off-by: Praveenkumar I --- arch/arm64/boot/dts/qcom/ipq5332.dtsi | 113 ++++++++++++++++++++++++++ 1 file changed, 113 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi index 8bfc2db44624..a1e3527178c0 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -150,6 +150,91 @@ qfprom: efuse@a4000 { reg = <0x000a4000 0x721>; #address-cells = <1>; #size-cells = <1>; + + tsens_mode: mode@3e1 { + reg = <0x3e1 0x1>; + bits = <0 3>; + }; + + tsens_base0: base0@3e1 { + reg = <0x3e1 0x2>; + bits = <3 10>; + }; + + tsens_base1: base1@3e2 { + reg = <0x3e2 0x2>; + bits = <5 10>; + }; + + s0_offset: s0_offset@3e4 { + reg = <0x3e4 0x1>; + bits = <0 4>; + }; + + s3_offset: s3_offset@3e5 { + reg = <0x3e5 0x1>; + bits = <4 4>; + }; + + s4_offset: s4_offset@3e6 { + reg = <0x3e6 0x1>; + bits = <0 4>; + }; + + s5_offset: s5_offset@3e6 { + reg = <0x3e6 0x1>; + bits = <4 4>; + }; + + s6_offset: s6_offset@3e8 { + reg = <0x3e8 0x1>; + bits = <0 4>; + }; + + s7_offset: s7_offset@3e8 { + reg = <0x3e8 0x1>; + bits = <4 4>; + }; + + s8_offset: s8_offset@3a4 { + reg = <0x3a4 0x1>; + bits = <0 4>; + }; + + s9_offset: s9_offset@3a4 { + reg = <0x3a4 0x1>; + bits = <4 4>; + }; + + s10_offset: s10_offset@3a5 { + reg = <0x3a5 0x1>; + bits = <0 4>; + }; + + s11_offset: s11_offset@3a5 { + reg = <0x3a5 0x1>; + bits = <4 4>; + }; + + s12_offset: s12_offset@3a6 { + reg = <0x3a6 0x1>; + bits = <0 4>; + }; + + s13_offset: s13_offset@3a6 { + reg = <0x3a6 0x1>; + bits = <4 4>; + }; + + s14_offset: s14_offset@3ad { + reg = <0x3ad 0x2>; + bits = <7 4>; + }; + + s15_offset: s0_offset@3ae { + reg = <0x3ae 0x1>; + bits = <3 4>; + }; }; rng: rng@e3000 { @@ -159,6 +244,34 @@ rng: rng@e3000 { clock-names = "core"; }; + tsens: thermal-sensor@4a9000 { + compatible = "qcom,ipq5332-tsens"; + reg = <0x4a9000 0x1000>, + <0x4a8000 0x1000>; + nvmem-cells = <&tsens_mode>, <&tsens_base0>, + <&tsens_base1>, <&s0_offset>, + <&s3_offset>, <&s4_offset>, + <&s5_offset>, <&s6_offset>, + <&s7_offset>, <&s8_offset>, + <&s9_offset>, <&s10_offset>, + <&s11_offset>, <&s12_offset>, + <&s13_offset>, <&s14_offset>, + <&s15_offset>; + nvmem-cell-names = "mode", "base0", + "base1", "s0_offset", + "s3_offset", "s4_offset", + "s5_offset", "s6_offset", + "s7_offset", "s8_offset", + "s9_offset", "s10_offset", + "s11_offset", "s12_offset", + "s13_offset", "s14_offset", + "s15_offset"; + interrupts = ; + interrupt-names = "combined"; + #qcom,sensors = <16>; + #thermal-sensor-cells = <1>; + }; + tlmm: pinctrl@1000000 { compatible = "qcom,ipq5332-tlmm"; reg = <0x01000000 0x300000>; From patchwork Mon Jul 10 10:37:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Praveenkumar I X-Patchwork-Id: 701645 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F3B62EB64DA for ; Mon, 10 Jul 2023 10:39:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233055AbjGJKju (ORCPT ); Mon, 10 Jul 2023 06:39:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47070 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232817AbjGJKjt (ORCPT ); Mon, 10 Jul 2023 06:39:49 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 19EE5CE; Mon, 10 Jul 2023 03:39:26 -0700 (PDT) Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 36AALgsw026255; Mon, 10 Jul 2023 10:39:21 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=O/eNFZy9xqFiZx6qf6Rm/D0FTnp0IhavKpq2owOSfVM=; b=ZymbNJGfNMWXngXGbMPU1jI701LHmmG4jGXpVxdJcMzFkAjfHySMTT1erbVIhVwlig9w axm4ETrFr+EZF4Nekc00DLJWOhu8WezZEvJUW7AreewX43/nShPno9fSapRxY4se38Jw ZG+SASTcfApbQYsQs63iYBZtGyScK+XUAhYXw6eZJ3KBIbWh8DXlIhxtHfGuMlguPpgH MEhApy0jEtesXbfOWhd/KfcVu7eaDw7vM/uNhuGe/tFYbTPFDjrsICmyFAxh6gB4lE5N hQ0Icp2YAEINYve50VOK35Yv0oBF8ZQ6+Wo1A/do3eQIGoAv+/M6FvKe1uQPdu08vQ+i Xg== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3rrg5mg1sn-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 10 Jul 2023 10:39:21 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 36AAcJ3e017993 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 10 Jul 2023 10:38:19 GMT Received: from hu-ipkumar-blr.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Mon, 10 Jul 2023 03:38:15 -0700 From: Praveenkumar I To: , , , , , , , , , , , , , , CC: Subject: [PATCH 5/6] arm64: dts: qcom: ipq5332: Add thermal zone nodes Date: Mon, 10 Jul 2023 16:07:34 +0530 Message-ID: <20230710103735.1375847-6-quic_ipkumar@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230710103735.1375847-1-quic_ipkumar@quicinc.com> References: <20230710103735.1375847-1-quic_ipkumar@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: ULff9JgC8pPBePj-EWrcvzpIRKXasci9 X-Proofpoint-ORIG-GUID: ULff9JgC8pPBePj-EWrcvzpIRKXasci9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-10_08,2023-07-06_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 malwarescore=0 phishscore=0 adultscore=0 spamscore=0 priorityscore=1501 mlxlogscore=929 clxscore=1015 mlxscore=0 suspectscore=0 lowpriorityscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2307100096 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This patch adds thermal zone nodes for sensors present in IPQ5332. Signed-off-by: Praveenkumar I --- arch/arm64/boot/dts/qcom/ipq5332.dtsi | 72 +++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi index a1e3527178c0..8b276aeca53e 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -527,4 +527,76 @@ timer { , ; }; + + thermal-zones { + rfa-0-thermal{ + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 11>; + + trips { + rfa-0-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + rfa-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 12>; + + trips { + rfa-1-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + misc-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 13>; + + trips { + misc-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-top-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 14>; + + trips { + cpu-top-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + top-glue-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 15>; + + trips { + top-glue-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + }; }; From patchwork Mon Jul 10 10:37:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Praveenkumar I X-Patchwork-Id: 701158 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 86825EB64DC for ; Mon, 10 Jul 2023 10:41:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232243AbjGJKlL (ORCPT ); Mon, 10 Jul 2023 06:41:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48256 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229831AbjGJKlJ (ORCPT ); Mon, 10 Jul 2023 06:41:09 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1DB9BE7; Mon, 10 Jul 2023 03:41:05 -0700 (PDT) Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 36A8emHC028581; Mon, 10 Jul 2023 10:41:01 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=aYM+VhhL/noCdx5e6LwN0rToSkbZN8EkGwcPCz2bMkE=; b=lYYksZ0T/gxfYjzGAU5W9nMuIyVkzp9zRtCHscew/7sUde3lTW8f/9ixWf8pl5w5ik4p zqXvbcTRr2aTem+0EIaRZPcu07CN7M31AL9nhjrpwbZovxIO8xG/Mpw6O5qMalVNoONo 7QgzSDBIhFETw95D2vvjlrWzYUiYe3+qATNuBgg3PLwBIXPkcdT4guqJzmUJcP+A5MQi WYJZH1+QmzlugXRG19FEXScVH+7+vzZeGMTV7wlLeusYIWjN6Spw+co4FiGl1dGWr3c/ sb3EzFkLVMratA1MrToB1oqJvUM18nQG4HmPWRK/ap7uA2CggXWhKKwRRp1q84GU+WYg Lw== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3rrdpn0fu6-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 10 Jul 2023 10:41:00 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 36AAcOM4008941 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 10 Jul 2023 10:38:24 GMT Received: from hu-ipkumar-blr.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Mon, 10 Jul 2023 03:38:19 -0700 From: Praveenkumar I To: , , , , , , , , , , , , , , CC: Subject: [PATCH 6/6] thermal/drivers/tsens: Add IPQ5332 support Date: Mon, 10 Jul 2023 16:07:35 +0530 Message-ID: <20230710103735.1375847-7-quic_ipkumar@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230710103735.1375847-1-quic_ipkumar@quicinc.com> References: <20230710103735.1375847-1-quic_ipkumar@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: nI6BaXxuRS0Mk8yDz92637YYSHG4XCVN X-Proofpoint-ORIG-GUID: nI6BaXxuRS0Mk8yDz92637YYSHG4XCVN X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-10_08,2023-07-06_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 malwarescore=0 phishscore=0 impostorscore=0 priorityscore=1501 adultscore=0 mlxlogscore=999 mlxscore=0 suspectscore=0 spamscore=0 bulkscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2307100097 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org IPQ5332 uses tsens v2.3.3 IP and it is having combined interrupt as like IPQ8074. But as the SoCs does not have RPM, kernel needs to take care of sensor enablement and calibration. Hence introduced new ops and data for IPQ5332 and reused the feature_config from IPQ8074. Signed-off-by: Praveenkumar I --- drivers/thermal/qcom/tsens-v2.c | 13 +++++++++++++ drivers/thermal/qcom/tsens.c | 3 +++ drivers/thermal/qcom/tsens.h | 2 +- 3 files changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/thermal/qcom/tsens-v2.c b/drivers/thermal/qcom/tsens-v2.c index db48b1d95348..8b6e3876fd2c 100644 --- a/drivers/thermal/qcom/tsens-v2.c +++ b/drivers/thermal/qcom/tsens-v2.c @@ -237,6 +237,19 @@ struct tsens_plat_data data_ipq8074 = { .fields = tsens_v2_regfields, }; +static const struct tsens_ops ops_ipq5332_v2 = { + .init = init_common, + .get_temp = get_temp_tsens_valid, + .calibrate = tsens_v2_calibration, +}; + +struct tsens_plat_data data_ipq5332 = { + .sensors_to_en = 0xF800, + .ops = &ops_ipq5332_v2, + .feat = &ipq8074_feat, + .fields = tsens_v2_regfields, +}; + /* Kept around for backward compatibility with old msm8996.dtsi */ struct tsens_plat_data data_8996 = { .num_sensors = 13, diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index 169690355dad..e8ba2901cda8 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -1140,6 +1140,9 @@ static const struct of_device_id tsens_table[] = { }, { .compatible = "qcom,ipq8074-tsens", .data = &data_ipq8074, + }, { + .compatible = "qcom,ipq5332-tsens", + .data = &data_ipq5332, }, { .compatible = "qcom,mdm9607-tsens", .data = &data_9607, diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index f8897bc8944e..36040f9beebc 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -701,6 +701,6 @@ extern struct tsens_plat_data data_8226, data_8909, data_8916, data_8939, data_8 extern struct tsens_plat_data data_tsens_v1, data_8976, data_8956; /* TSENS v2 targets */ -extern struct tsens_plat_data data_8996, data_ipq8074, data_tsens_v2; +extern struct tsens_plat_data data_8996, data_ipq8074, data_ipq5332, data_tsens_v2; #endif /* __QCOM_TSENS_H__ */