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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v16-20020a5d6790000000b003112ab916cdsm19337737wru.73.2023.07.17.05.47.48 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jul 2023 05:47:48 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 1/7] hw/arm/sbsa-ref: set 'slots' property of xhci Date: Mon, 17 Jul 2023 13:47:40 +0100 Message-Id: <20230717124746.759085-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230717124746.759085-1-peter.maydell@linaro.org> References: <20230717124746.759085-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Yuquan Wang This extends the slots of xhci to 64, since the default xhci_sysbus just supports one slot. Signed-off-by: Wang Yuquan Signed-off-by: Chen Baozi Reviewed-by: Richard Henderson Reviewed-by: Marcin Juszkiewicz Tested-by: Marcin Juszkiewicz Message-id: 20230710063750.473510-2-wangyuquan1236@phytium.com.cn Signed-off-by: Peter Maydell --- hw/arm/sbsa-ref.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index 64e1cbce171..bc89eb48062 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -611,6 +611,7 @@ static void create_xhci(const SBSAMachineState *sms) hwaddr base = sbsa_ref_memmap[SBSA_XHCI].base; int irq = sbsa_ref_irqmap[SBSA_XHCI]; DeviceState *dev = qdev_new(TYPE_XHCI_SYSBUS); + qdev_prop_set_uint32(dev, "slots", XHCI_MAXSLOTS); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); From patchwork Mon Jul 17 12:47:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 703718 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e4d:0:b0:314:25da:8dc4 with SMTP id r13csp979720wrt; Mon, 17 Jul 2023 05:52:49 -0700 (PDT) X-Google-Smtp-Source: APBJJlHn/A2p/XAX+EZySbaob3xLSVr3v+4OMxjCpfO8rqygI+jCi4+SM223Zfe2m4sxhtUOpoG4 X-Received: by 2002:a05:620a:469e:b0:767:400b:bbca with SMTP id bq30-20020a05620a469e00b00767400bbbcamr11041456qkb.48.1689598369503; Mon, 17 Jul 2023 05:52:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689598369; cv=none; d=google.com; s=arc-20160816; b=slYC8+vR6EgsSDI1NZ5dXwpXOjZimDwAhdTVgBQi1aNq0ld9TfzEmQDlG+XtXcDU93 fvlRjKMgxL7RAxsn9uXxZmmvPdUx82uN0bEIFx0B+qS3FHoq+Wgg+yqRmt8P2nW6oLHY vSJvUfrISwX+1M9anYvbuO7Z3T9vzTBwSBn0zIwLJRLaYqfjL5pEASYZMK3ekHzPBGyK HTUShaF2sM1WR5/RTZwOE37gMRcrqkqqR9xhL2sI9APGmomMfNc7jwiwFrXJg87hk4qL 2/ZOoMEDL7MW8nfspahUjH/c/ztbmodsjsQqVTgFAtycoDATXOaMQcPNwvp6cES5GPj6 w/8A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=+E+optEz0nYwCwN2hJQhLLatmGokjisG+592zq4NO/8=; fh=bFDrUYhlTVi/QyetgXx/byg2+yO/22Hp9SjwoefyKLk=; b=cDK3VB74sR/PyApFAsr9GJ5bCdsF2kPrbB/SqxPiC/KgFrk1HF5d9HEoIl2mzuMmQ6 +YTWRjefs+N+WBY8zo1zXHCuCvvMYjeE4rE59y7SQgAkm95INZC86N2rjC7uocHEucm3 BenJG1X29C7FBDRBVlp3EYVQ5nF7M/s1XYsMUfhHVDwLhnR4ZHSq/LVIPopwtpx+Q+6l pw2mkAR+xQn3CbR9XbU1NaASJSlBIilXlxgVPHSGXd4KmFT4Nu0VEDamLmcZficnIN9I QKiE2lM1fcmPwK/npYs8zc2HH7beHCLfi8wWTyDfEUePN9p3CpiHhYGuEd0pYyIav9pr uAXw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Ivq7E0ZQ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v16-20020a5d6790000000b003112ab916cdsm19337737wru.73.2023.07.17.05.47.48 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jul 2023 05:47:48 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 2/7] linux-user: Remove pointless NULL check in clock_adjtime handling Date: Mon, 17 Jul 2023 13:47:41 +0100 Message-Id: <20230717124746.759085-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230717124746.759085-1-peter.maydell@linaro.org> References: <20230717124746.759085-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In the code for TARGET_NR_clock_adjtime, we set the pointer phtx to the address of the local variable htx. This means it can never be NULL, but later in the code we check it for NULL anyway. Coverity complains about this (CID 1507683) because the NULL check comes after a call to clock_adjtime() that assumes it is non-NULL. Since phtx is always &htx, and is used only in three places, it's not really necessary. Remove it, bringing the code structure in to line with that for TARGET_NR_clock_adjtime64, which already uses a simple '&htx' when it wants a pointer to 'htx'. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20230623144410.1837261-1-peter.maydell@linaro.org --- linux-user/syscall.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 14641518262..c99ef9c01ef 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -11190,16 +11190,14 @@ static abi_long do_syscall1(CPUArchState *cpu_env, int num, abi_long arg1, #if defined(TARGET_NR_clock_adjtime) && defined(CONFIG_CLOCK_ADJTIME) case TARGET_NR_clock_adjtime: { - struct timex htx, *phtx = &htx; + struct timex htx; - if (target_to_host_timex(phtx, arg2) != 0) { + if (target_to_host_timex(&htx, arg2) != 0) { return -TARGET_EFAULT; } - ret = get_errno(clock_adjtime(arg1, phtx)); - if (!is_error(ret) && phtx) { - if (host_to_target_timex(arg2, phtx) != 0) { - return -TARGET_EFAULT; - } + ret = get_errno(clock_adjtime(arg1, &htx)); + if (!is_error(ret) && host_to_target_timex(arg2, &htx)) { + return -TARGET_EFAULT; } } return ret; From patchwork Mon Jul 17 12:47:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 703723 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e4d:0:b0:314:25da:8dc4 with SMTP id r13csp981328wrt; Mon, 17 Jul 2023 05:57:02 -0700 (PDT) X-Google-Smtp-Source: APBJJlEcQ4fX3vpeon6du1Lc5yCCbU/Bhw7SgJ75pw6Ph38flOd6o37WgumP25gBBw5hoLehwAMA X-Received: by 2002:a0c:b353:0:b0:636:34e2:fad9 with SMTP id a19-20020a0cb353000000b0063634e2fad9mr10087269qvf.8.1689598622416; Mon, 17 Jul 2023 05:57:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689598622; cv=none; d=google.com; s=arc-20160816; b=cNepMTdOV40cjNHZu53q4n36lkOIBkvPVH4+pp9D6Ayjl7QzA7wfmlhjdwjkeX6Dqe x5FRvCTU75Ccy1Kua3yOuEoCGL2+Ck4MHpajfURDzHu48pVZdwo2A3UG1r8hmA8ZHi5E B/9mhgjc64VtsF1geqbBIvzFs++VfPrSjuyj/8XFKsd3cIxXUQATE59CxkTTi5JW9UIS b+HdVEwbHHT52mGdTK4yeWn4Dmy5ZCgbrCSnoemFS5Jn/k98YZGCjYjpSEJFLgc64jgE xRP2dzMPUoaUYOQbnGx74Euxs7REmKrPiAeh54YNW8Lwx09bFTbANGs6btEbU+nRpXWP 8QmQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=rRttNqKmS3icTZXVSo6Zoczfc48IgD7HZ3JpXissknE=; fh=bFDrUYhlTVi/QyetgXx/byg2+yO/22Hp9SjwoefyKLk=; b=MA25eSokbk9flgAAquch54gOMrRrbFthlnhzH+O4RA6VIxwdo6vKbylPHas52CfAy1 +Tc0fqn7CnjOzB/Pt8nXSilqtyVShoj65ewLkhyTOWT2WbOMWedhS6H0A20U25EBNOyq 6N4cQn1cYK40Ho2qN3+WgPi29zL3b3cQpIjeFvd7TrUT3EY+8XRF3NKdPZEdTrg9ls92 DysY8TwB0o8Ktp1LiKY+I6pDwd32Ukl9wkT8cIc/Q0UPrwTmrXbwUSd/rtTDNpBZya0C sTToV7C287DhgTCbTnHsss1KE/Egg/DJ2ku5yGkhArMtKvQCpzM12jRpjmU9cEu4luA1 OnZA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="G0/XIEWu"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v16-20020a5d6790000000b003112ab916cdsm19337737wru.73.2023.07.17.05.47.48 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jul 2023 05:47:49 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 3/7] target/arm/ptw.c: Add comments to S1Translate struct fields Date: Mon, 17 Jul 2023 13:47:42 +0100 Message-Id: <20230717124746.759085-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230717124746.759085-1-peter.maydell@linaro.org> References: <20230717124746.759085-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Add comments to the in_* fields in the S1Translate struct that explain what they're doing. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230710152130.3928330-2-peter.maydell@linaro.org --- target/arm/ptw.c | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 9aaff1546a6..21749375f97 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -19,10 +19,50 @@ #endif typedef struct S1Translate { + /* + * in_mmu_idx : specifies which TTBR, TCR, etc to use for the walk. + * Together with in_space, specifies the architectural translation regime. + */ ARMMMUIdx in_mmu_idx; + /* + * in_ptw_idx: specifies which mmuidx to use for the actual + * page table descriptor load operations. This will be one of the + * ARMMMUIdx_Stage2* or one of the ARMMMUIdx_Phys_* indexes. + * If a Secure ptw is "downgraded" to NonSecure by an NSTable bit, + * this field is updated accordingly. + */ ARMMMUIdx in_ptw_idx; + /* + * in_space: the security space for this walk. This plus + * the in_mmu_idx specify the architectural translation regime. + * If a Secure ptw is "downgraded" to NonSecure by an NSTable bit, + * this field is updated accordingly. + * + * Note that the security space for the in_ptw_idx may be different + * from that for the in_mmu_idx. We do not need to explicitly track + * the in_ptw_idx security space because: + * - if the in_ptw_idx is an ARMMMUIdx_Phys_* then the mmuidx + * itself specifies the security space + * - if the in_ptw_idx is an ARMMMUIdx_Stage2* then the security + * space used for ptw reads is the same as that of the security + * space of the stage 1 translation for all cases except where + * stage 1 is Secure; in that case the only possibilities for + * the ptw read are Secure and NonSecure, and the in_ptw_idx + * value being Stage2 vs Stage2_S distinguishes those. + */ ARMSecuritySpace in_space; + /* + * in_secure: whether the translation regime is a Secure one. + * This is always equal to arm_space_is_secure(in_space). + * If a Secure ptw is "downgraded" to NonSecure by an NSTable bit, + * this field is updated accordingly. + */ bool in_secure; + /* + * in_debug: is this a QEMU debug access (gdbstub, etc)? Debug + * accesses will not update the guest page table access flags + * and will not change the state of the softmmu TLBs. + */ bool in_debug; /* * If this is stage 2 of a stage 1+2 page table walk, then this must From patchwork Mon Jul 17 12:47:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 703724 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e4d:0:b0:314:25da:8dc4 with SMTP id r13csp981455wrt; Mon, 17 Jul 2023 05:57:21 -0700 (PDT) X-Google-Smtp-Source: APBJJlHnVugzsis6bthT1NV0Pk64v5MeHkwCliyWwNWraHUAlYT6e4rnZypb9BizJsa1MKUclv5o X-Received: by 2002:a67:f797:0:b0:440:ab90:7c95 with SMTP id j23-20020a67f797000000b00440ab907c95mr5352519vso.9.1689598641218; Mon, 17 Jul 2023 05:57:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689598641; cv=none; d=google.com; s=arc-20160816; b=IOPaocdBPkll+Fz1YN5mfHOSfbJMkBzCoscpQWPVsRW2SkH2L4wYCMoACYkBwmtiYZ eieyvXOFou5SaOXJjWuYIOSIs0bv/RkpOJRMsCEeYk0evP5ZZEdZ1SYbvvCYj9FtPovs QvWS3nk8ChVgl2LoTSrfBWEvM8VpMCOQCNfhlJmppZgu/wUX6vd1RLY/E2SZfzuQhFWH uz5QjE5JsKR02Bqi2WSt7X3K5VjWRnrNGfTDDOn3ABXiBDQW5yaigO+ZWwk6jAbe4f3M obFEy95E9p4YWmNYRKX9G0ggCFewOezv+67f5TCxmu7aL42vBajgH9G1YJHWdENGCwrJ YyqA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=6/kWyXsyxk23z+UX5RxhswptfdLynFYZwEMDMUpOvjE=; fh=bFDrUYhlTVi/QyetgXx/byg2+yO/22Hp9SjwoefyKLk=; b=wan7uqHxrg4puNMus0JQPeHS+wAptYT+OszfMAJKNFXOa9fEZu2Z1bgi5Lz44UiGEh O2qT9w/3gHknqWjirhZ6L6lDQSLHFFNTTAB1iAHf2Ux5XZ5sUFKfLfl6VT9kye7Z1JwU 9O2ZSoDSNc9ednXGYCYgrDNI3F09MNgt7h4jZ9kTL3Xg0xa8IhPu/cMCTRYF24De9EO7 XfINeIHtu7pq9JGs9/UpnvVCOBsGQ/AfT5IbiJmDWTsNvURsLJ4cyUZt+fYDL2HFTqKS YlZUFW0je2nj+E2QciFuiFhzN7gmXEysDvAPgF8XpBYu4bj2zcIUXohvuiQd5YtBcGlI kaYQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=mxmdPB+L; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v16-20020a5d6790000000b003112ab916cdsm19337737wru.73.2023.07.17.05.47.49 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jul 2023 05:47:49 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 4/7] target/arm: Fix S1_ptw_translate() debug path Date: Mon, 17 Jul 2023 13:47:43 +0100 Message-Id: <20230717124746.759085-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230717124746.759085-1-peter.maydell@linaro.org> References: <20230717124746.759085-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In commit fe4a5472ccd6 we rearranged the logic in S1_ptw_translate() so that the debug-access "call get_phys_addr_*" codepath is used both when S1 is doing ptw reads from stage 2 and when it is doing ptw reads from physical memory. However, we didn't update the calculation of s2ptw->in_space and s2ptw->in_secure to account for the "ptw reads from physical memory" case. This meant that debug accesses when in Secure state broke. Create a new function S2_security_space() which returns the correct security space to use for the ptw load, and use it to determine the correct .in_secure and .in_space fields for the stage 2 lookup for the ptw load. Reported-by: Jean-Philippe Brucker Signed-off-by: Peter Maydell Tested-by: Jean-Philippe Brucker Reviewed-by: Richard Henderson Message-id: 20230710152130.3928330-3-peter.maydell@linaro.org Fixes: fe4a5472ccd6 ("target/arm: Use get_phys_addr_with_struct in S1_ptw_translate") Signed-off-by: Peter Maydell --- target/arm/ptw.c | 37 ++++++++++++++++++++++++++++++++----- 1 file changed, 32 insertions(+), 5 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 21749375f97..c0b9cee5843 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -485,11 +485,39 @@ static bool S2_attrs_are_device(uint64_t hcr, uint8_t attrs) } } +static ARMSecuritySpace S2_security_space(ARMSecuritySpace s1_space, + ARMMMUIdx s2_mmu_idx) +{ + /* + * Return the security space to use for stage 2 when doing + * the S1 page table descriptor load. + */ + if (regime_is_stage2(s2_mmu_idx)) { + /* + * The security space for ptw reads is almost always the same + * as that of the security space of the stage 1 translation. + * The only exception is when stage 1 is Secure; in that case + * the ptw read might be to the Secure or the NonSecure space + * (but never Realm or Root), and the s2_mmu_idx tells us which. + * Root translations are always single-stage. + */ + if (s1_space == ARMSS_Secure) { + return arm_secure_to_space(s2_mmu_idx == ARMMMUIdx_Stage2_S); + } else { + assert(s2_mmu_idx != ARMMMUIdx_Stage2_S); + assert(s1_space != ARMSS_Root); + return s1_space; + } + } else { + /* ptw loads are from phys: the mmu idx itself says which space */ + return arm_phys_to_space(s2_mmu_idx); + } +} + /* Translate a S1 pagetable walk through S2 if needed. */ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, hwaddr addr, ARMMMUFaultInfo *fi) { - ARMSecuritySpace space = ptw->in_space; bool is_secure = ptw->in_secure; ARMMMUIdx mmu_idx = ptw->in_mmu_idx; ARMMMUIdx s2_mmu_idx = ptw->in_ptw_idx; @@ -502,13 +530,12 @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, * From gdbstub, do not use softmmu so that we don't modify the * state of the cpu at all, including softmmu tlb contents. */ + ARMSecuritySpace s2_space = S2_security_space(ptw->in_space, s2_mmu_idx); S1Translate s2ptw = { .in_mmu_idx = s2_mmu_idx, .in_ptw_idx = ptw_idx_for_stage_2(env, s2_mmu_idx), - .in_secure = s2_mmu_idx == ARMMMUIdx_Stage2_S, - .in_space = (s2_mmu_idx == ARMMMUIdx_Stage2_S ? ARMSS_Secure - : space == ARMSS_Realm ? ARMSS_Realm - : ARMSS_NonSecure), + .in_secure = arm_space_is_secure(s2_space), + .in_space = s2_space, .in_debug = true, }; GetPhysAddrResult s2 = { }; From patchwork Mon Jul 17 12:47:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 703719 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e4d:0:b0:314:25da:8dc4 with SMTP id r13csp980605wrt; Mon, 17 Jul 2023 05:55:09 -0700 (PDT) X-Google-Smtp-Source: APBJJlEYuALzBR+zSpGY0fobIO+5Ubi59z5wJjA+CtiG8HIvEEN/EAySle7FLODIvs8h0BhLUAzh X-Received: by 2002:a0c:ab58:0:b0:62d:e416:a0de with SMTP id i24-20020a0cab58000000b0062de416a0demr10244434qvb.41.1689598508798; Mon, 17 Jul 2023 05:55:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689598508; cv=none; d=google.com; s=arc-20160816; b=izdsL/uJWs8XSnKgKgKemSQOWNR+e8gU0SF8u6Ruk/kLVF/XPVJdzXG5hG6eocSn59 cU04NtPUd448LGbDbkB0x33xAnUb1ALzcZtE6i3gnxt4Mf5d4sE8b+Vx8ALho5M+08iN TQgDYrzmPfxlw5xSV9m2dgYXGOUIjEGScw9LbFkGUfmUnZ6EK9l1do856qnOnhxk1pjq qrUm7Y5gF3vVkjIQCC35Ybm8zLDGdJSN64cOcP8yTTLH146PtajDOlajGpj6xZAoU8O6 8xj2wjEFMPCOpesVdiqKr4u8ew1pK9TPh5gFp8CkEmc0U12u2W4CU98NiV8s17iIHg/o t2SQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=uo7Bz898x5rT9AwvwOzRLp/mDtj2e+zf8fXMK+RWos4=; fh=bFDrUYhlTVi/QyetgXx/byg2+yO/22Hp9SjwoefyKLk=; b=PtF/IU0YNzM6nacIgl3tOx6KIswHJ95L+klVLoSHP3J317B/+5EfCEK+ntzc6yzHTP 7myCdIjXN0Lfk7BkCbCRITd7SyatXs9AT8y3SWtnur8KErAJZP1sPuhhLu2rr4svR34+ 9Te9dN98BTuJaWozndjSrtuAVqGgQ4EzU6ew1G708hpQ/piobn6F9WhB0dFHTo4Q7ikJ YR285QgGWkD4Wqpubg59Oe7C6M35sKwvjM8N1zRAAI48A4WOg89mCq42YL0WGCG8BPgS j72pucmyOukymfXyUII1TTDOk+BJ2JN/oqfr4viWnSYKpK/Ge21Bbwv8JNoW2kZuvzMk yHew== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GYUsfFKR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v16-20020a5d6790000000b003112ab916cdsm19337737wru.73.2023.07.17.05.47.49 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jul 2023 05:47:49 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 5/7] target/arm/ptw.c: Account for FEAT_RME when applying {N}SW, SA bits Date: Mon, 17 Jul 2023 13:47:44 +0100 Message-Id: <20230717124746.759085-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230717124746.759085-1-peter.maydell@linaro.org> References: <20230717124746.759085-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In get_phys_addr_twostage() the code that applies the effects of VSTCR.{SA,SW} and VTCR.{NSA,NSW} only updates result->f.attrs.secure. Now we also have f.attrs.space for FEAT_RME, we need to keep the two in sync. These bits only have an effect for Secure space translations, not for Root, so use the input in_space field to determine whether to apply them rather than the input is_secure. This doesn't actually make a difference because Root translations are never two-stage, but it's a little clearer. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230710152130.3928330-4-peter.maydell@linaro.org --- target/arm/ptw.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index c0b9cee5843..8f94100c61f 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -3118,6 +3118,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, hwaddr ipa; int s1_prot, s1_lgpgsz; bool is_secure = ptw->in_secure; + ARMSecuritySpace in_space = ptw->in_space; bool ret, ipa_secure; ARMCacheAttrs cacheattrs1; ARMSecuritySpace ipa_space; @@ -3200,11 +3201,13 @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, * Check if IPA translates to secure or non-secure PA space. * Note that VSTCR overrides VTCR and {N}SW overrides {N}SA. */ - result->f.attrs.secure = - (is_secure - && !(env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW)) - && (ipa_secure - || !(env->cp15.vtcr_el2 & (VTCR_NSA | VTCR_NSW)))); + if (in_space == ARMSS_Secure) { + result->f.attrs.secure = + !(env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW)) + && (ipa_secure + || !(env->cp15.vtcr_el2 & (VTCR_NSA | VTCR_NSW))); + result->f.attrs.space = arm_secure_to_space(result->f.attrs.secure); + } return false; } From patchwork Mon Jul 17 12:47:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 703717 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e4d:0:b0:314:25da:8dc4 with SMTP id r13csp979714wrt; Mon, 17 Jul 2023 05:52:49 -0700 (PDT) X-Google-Smtp-Source: APBJJlFH/diSLiYf0XPBLEyhZhQkd82an2gecWLIz6TDSlIN9cVMOY153EP9NkLTTiArVk3XdK6s X-Received: by 2002:a0c:ae89:0:b0:636:cc10:4767 with SMTP id j9-20020a0cae89000000b00636cc104767mr12202866qvd.28.1689598369043; Mon, 17 Jul 2023 05:52:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689598369; cv=none; d=google.com; s=arc-20160816; b=e9hWQcb26IrsY14j7MOFZboxJx85tPpWd+QCIq22U57NJ7oR6SuHtFgjYIUke0cci6 UhHF/j9I3jS9sa71VGT+Z6Qo+/hTTNCxz1h9h4Vk0gYTFcWnX568iYcP83jw+R4WTgT4 OviU2CvgqahYNUBhf/Ozj4H3RSO72N3L2I1EIvC2gxSsZ3YvyFLlZaxvtBKye0Zm1W77 erVljTq4QpuDb09PU94XS4x85INsogvlH2ju/BapuqJHVvxmiQaLgyTWpc0ecVMCOdH1 z2FY1qGZZMuEGZH8Ts+QGAWxlbarGxhOhOcNySW3fZD9/ZaN8HM5kcQb42I5rGcB7fY7 L3xg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=edbJjO1yTMsccjp+1Oi4Tpx97oGTrv0Dg957zzrUT/c=; fh=bFDrUYhlTVi/QyetgXx/byg2+yO/22Hp9SjwoefyKLk=; b=v9nPmEFTaf+r+FLbd/qv3/oiN2nsHWi0dDtM9OkcsNKGCogvd8rUIk0zX6GUksVNn7 4Dj1lTH11UWQ781crQJvzoE52a4shk1trfj7EmbEPpJEGNz/4xUrZ7IJyUViHQdk2dzd hAAjIMxwxbOVGRrAWiJKol2on+viI2BpVNeLtuR2GeANs4G0Re3yTgF7WD4pHh6dAjO4 PHegLK/L2udPhggMTt/QhxhSqHl9rNtt8WtTNA1Te53i/8zDkE/cY2jmefJnVzj5rEgX JuxTahQyG3KCmH6xkNK5oyo8dXOaPrB3lkWc5Rx1KQ22Pn2wmF68kmcF56YWRplbnVbH r9Xw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=P0wB2kGq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v16-20020a5d6790000000b003112ab916cdsm19337737wru.73.2023.07.17.05.47.50 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jul 2023 05:47:50 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 6/7] accel/tcg: Zero-pad PC in TCG CPU exec trace lines Date: Mon, 17 Jul 2023 13:47:45 +0100 Message-Id: <20230717124746.759085-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230717124746.759085-1-peter.maydell@linaro.org> References: <20230717124746.759085-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In commit f0a08b0913befbd we changed the type of the PC from target_ulong to vaddr. In doing so we inadvertently dropped the zero-padding on the PC in trace lines (the second item inside the [] in these lines). They used to look like this on AArch64, for instance: Trace 0: 0x7f2260000100 [00000000/0000000040000000/00000061/ff200000] and now they look like this: Trace 0: 0x7f4f50000100 [00000000/40000000/00000061/ff200000] and if the PC happens to be somewhere low like 0x5000 then the field is shown as /5000/. This is because TARGET_FMT_lx is a "%08x" or "%016x" specifier, depending on TARGET_LONG_SIZE, whereas VADDR_PRIx is just PRIx64 with no width specifier. Restore the zero-padding by adding an 016 width specifier to this tracing and a couple of others that were similarly recently changed to use VADDR_PRIx without a width specifier. We can't unfortunately restore the "32-bit guests are padded to 8 hex digits and 64-bit guests to 16 hex digits" behaviour so easily. Fixes: f0a08b0913befbd ("accel/tcg/cpu-exec.c: Widen pc to vaddr") Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Anton Johansson Message-id: 20230711165434.4123674-1-peter.maydell@linaro.org --- accel/tcg/cpu-exec.c | 4 ++-- accel/tcg/translate-all.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index fdd6d3e0e44..e2c494e75ef 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -298,7 +298,7 @@ static void log_cpu_exec(vaddr pc, CPUState *cpu, if (qemu_log_in_addr_range(pc)) { qemu_log_mask(CPU_LOG_EXEC, "Trace %d: %p [%08" PRIx64 - "/%" VADDR_PRIx "/%08x/%08x] %s\n", + "/%016" VADDR_PRIx "/%08x/%08x] %s\n", cpu->cpu_index, tb->tc.ptr, tb->cs_base, pc, tb->flags, tb->cflags, lookup_symbol(pc)); @@ -487,7 +487,7 @@ cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *tb_exit) if (qemu_loglevel_mask(CPU_LOG_EXEC)) { vaddr pc = log_pc(cpu, last_tb); if (qemu_log_in_addr_range(pc)) { - qemu_log("Stopped execution of TB chain before %p [%" + qemu_log("Stopped execution of TB chain before %p [%016" VADDR_PRIx "] %s\n", last_tb->tc.ptr, pc, lookup_symbol(pc)); } diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 4c17474fa22..a1782db5dd7 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -637,7 +637,7 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr) if (qemu_loglevel_mask(CPU_LOG_EXEC)) { vaddr pc = log_pc(cpu, tb); if (qemu_log_in_addr_range(pc)) { - qemu_log("cpu_io_recompile: rewound execution of TB to %" + qemu_log("cpu_io_recompile: rewound execution of TB to %016" VADDR_PRIx "\n", pc); } } From patchwork Mon Jul 17 12:47:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 703721 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e4d:0:b0:314:25da:8dc4 with SMTP id r13csp981106wrt; Mon, 17 Jul 2023 05:56:33 -0700 (PDT) X-Google-Smtp-Source: APBJJlFYEvgWbqI8lkZvQ0jyAPC+wFIUtxW0vFprPbQHiOJ8uao0R3l6sfIlsHQuuD3J9AEogciK X-Received: by 2002:ac8:4e94:0:b0:403:b88d:1e60 with SMTP id 20-20020ac84e94000000b00403b88d1e60mr18290249qtp.51.1689598593460; Mon, 17 Jul 2023 05:56:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689598593; cv=none; d=google.com; s=arc-20160816; b=jnbi0orE5rlszr4uhYHIyp8nOuzSnoXv4taKc/ra3Cb6+8FNlFAQVJhYDrK0a7hjjB ALpc7uZflwbPjEG3FGlNNESSpArM3FghUZUux907u4R9Ai6Py06t3nYZurQm26ZLGIEg N9gRBRimLcCXAK6HSgLuhxPxZPg2/kYEC/Cyq7RAc9/0nxCm3LvMTVruBgbLAusZhU9K h29xdjN9G4fV4jhFhJPwe5cE+t7s8n1l5z+nEGyANnelX6yz8h75omfXUSUvB71T872D YaevnKwfGEovHpw6NQY1UhOZXufJId2pXjLfwVGM3AS2jKMf+IPDRuIJyx0/BgW6DXAG vGZw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=fm7KSG5NrB8kIIZoFYKUbYE9OkMwBur5haFqwy0lLuU=; fh=bFDrUYhlTVi/QyetgXx/byg2+yO/22Hp9SjwoefyKLk=; b=p5f+qPtXPknEmBqDZhn7DoaLwoFUpfXLVQvX7MWyISj5gmRfLRaTmyWSVAcQ5rv9Xj jkuoKQyk8j3jrAXCJC+zoJgzO7G7dH0Cx1u4LJvlP0lyLYzII3ynFjBbN5VKmk+/MwE6 2Das6pNQ0FoYUpjRce8e1IWA4rNbsABQNphqgAErbN2EmChXwyJ382hAlR8+c00DUW4r oDx64XXzzgT96JlNLFNotCGhE5Ch4D+ni++yp+A7/FHstZkZaXUe/XhQOw9wX0TQuqWM 8wg22hZMS4kmUMlGZTovENjScYmBnwpMU2Mgm9OdvgU1TLYOGEQqlNhJBc/KoO+oL0Jl I27A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=LBJBrnKH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v16-20020a5d6790000000b003112ab916cdsm19337737wru.73.2023.07.17.05.47.50 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jul 2023 05:47:50 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 7/7] hw/nvram: Avoid unnecessary Xilinx eFuse backstore write Date: Mon, 17 Jul 2023 13:47:46 +0100 Message-Id: <20230717124746.759085-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230717124746.759085-1-peter.maydell@linaro.org> References: <20230717124746.759085-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Tong Ho Add a check in the bit-set operation to write the backstore only if the affected bit is 0 before. With this in place, there will be no need for callers to do the checking in order to avoid unnecessary writes. Signed-off-by: Tong Ho Reviewed-by: Alistair Francis Reviewed-by: Francisco Iglesias Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Peter Maydell --- hw/nvram/xlnx-efuse.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/hw/nvram/xlnx-efuse.c b/hw/nvram/xlnx-efuse.c index fdfffaab99c..655c40b8d1e 100644 --- a/hw/nvram/xlnx-efuse.c +++ b/hw/nvram/xlnx-efuse.c @@ -143,6 +143,8 @@ static bool efuse_ro_bits_find(XlnxEFuse *s, uint32_t k) bool xlnx_efuse_set_bit(XlnxEFuse *s, unsigned int bit) { + uint32_t set, *row; + if (efuse_ro_bits_find(s, bit)) { g_autofree char *path = object_get_canonical_path(OBJECT(s)); @@ -152,8 +154,13 @@ bool xlnx_efuse_set_bit(XlnxEFuse *s, unsigned int bit) return false; } - s->fuse32[bit / 32] |= 1 << (bit % 32); - efuse_bdrv_sync(s, bit); + /* Avoid back-end write unless there is a real update */ + row = &s->fuse32[bit / 32]; + set = 1 << (bit % 32); + if (!(set & *row)) { + *row |= set; + efuse_bdrv_sync(s, bit); + } return true; }