From patchwork Mon Jul 17 10:32:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhupesh Sharma X-Patchwork-Id: 703838 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3E28BC001DE for ; Mon, 17 Jul 2023 10:33:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230366AbjGQKdb (ORCPT ); Mon, 17 Jul 2023 06:33:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42256 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230273AbjGQKd3 (ORCPT ); Mon, 17 Jul 2023 06:33:29 -0400 Received: from mail-pl1-x632.google.com (mail-pl1-x632.google.com [IPv6:2607:f8b0:4864:20::632]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C2B0419A8 for ; Mon, 17 Jul 2023 03:33:07 -0700 (PDT) Received: by mail-pl1-x632.google.com with SMTP id d9443c01a7336-1b8a8154f9cso26321605ad.1 for ; Mon, 17 Jul 2023 03:33:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1689589978; x=1692181978; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=f6nS90cTjCSY7Tyo8KTgzDnh4BrkTy5UxyLb8PDeWUE=; b=c+09fdJb79CO8X/gmJ74r6rTnBbn0Pe5L63/elKMcPDbT0DESKOvmxcIxAPsxoBw0J A46rI4QatHrxVoCEz/OJCQUX8b3B54nHbRBYEF/xNUx3EWhZmoDSkkOmRAGE7Jcg39lv Q+AVd6RfWm9ahCcWtAVEqQSogWV+HKcoBnviU8b+4yGDVcXK7/XySHfHTYU7rtuN6Y4G Kx2LHT0begdXwscKvyf3ZDhWTe/mpX7RL51MWN/XAi6rZ2ZhyG0zRzORjerTPzVi1w8f 4XpwZAldTnrds8BvA1jf+TqoJ88O7+8Pl+bkkQkW4Atii46aC/u0KQp9yxXA6pCUXYDh NYAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689589978; x=1692181978; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=f6nS90cTjCSY7Tyo8KTgzDnh4BrkTy5UxyLb8PDeWUE=; b=WdFqeeqTuEjRFWpw2hUxEUeiemlKCdsEQOfufc9QTn8tAF2jjuA8B49/QGd76wTNGz 9KJ8nn0q9GYbRf0RgCiHFXYwIDNl+MuE0wTBp4zsoDL3GedtL/ByEuyFiSVpU9zRQEBO PIIt/D15oaiexHAp2FIxY2iyyG7BZxu+3OZtQ7hKMKhUhS8iYySuiaNP0++zsqX5ZS6i NOxUPqEGcgCovvATVw1oSD+fQdyPT3X27F790FJOyJJKQ7HhmM1KlWaHHl4vq1yWulk4 dOwqA1cZCbUCCd2njIP++xH1jIYqQi1QlDdRBnCFNv1KZTZJmB+kzdEtxJhGfpRuzYeX SdNA== X-Gm-Message-State: ABy/qLbF4Y5t+46qtHeOOeyrR5cv+eUDeF9r67t2Guqu7cqAgVfW5+PJ K+W25V16sKktVzYPP1Mda7UHZQ== X-Google-Smtp-Source: APBJJlErZNuNmI4xKteu0wKevQatiM0x7wY/pvfwrBifAyKv1RyfDNKDm/Xj0yP3UaAu/ubjT54MZg== X-Received: by 2002:a17:903:32c9:b0:1b5:5162:53bd with SMTP id i9-20020a17090332c900b001b5516253bdmr13332000plr.33.1689589977999; Mon, 17 Jul 2023 03:32:57 -0700 (PDT) Received: from localhost.localdomain ([223.233.68.54]) by smtp.gmail.com with ESMTPSA id ij9-20020a170902ab4900b001b9de67285dsm12633616plb.156.2023.07.17.03.32.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jul 2023 03:32:57 -0700 (PDT) From: Bhupesh Sharma To: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-usb@vger.kernel.org Cc: agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, linux-kernel@vger.kernel.org, bhupesh.linux@gmail.com, bhupesh.sharma@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, krzysztof.kozlowski@linaro.org, quic_schowdhu@quicinc.com, gregkh@linuxfoundation.org Subject: [PATCH v8 1/4] dt-bindings: soc: qcom: eud: Add SM6115 / SM4250 support Date: Mon, 17 Jul 2023 16:02:33 +0530 Message-Id: <20230717103236.1246771-2-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230717103236.1246771-1-bhupesh.sharma@linaro.org> References: <20230717103236.1246771-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add dt-bindings for EUD found on Qualcomm SM6115 / SM4250 SoC. On this SoC (and derivatives) the enable bit inside 'tcsr_check_reg' needs to be set first to 'enable' the eud module. So, update the dt-bindings to accommodate the third register property (TCSR Base) required by the driver on these SoCs. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bhupesh Sharma --- .../bindings/soc/qcom/qcom,eud.yaml | 42 +++++++++++++++++-- 1 file changed, 39 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml index f2c5ec7e6437b..71274bc978584 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml @@ -18,12 +18,16 @@ properties: items: - enum: - qcom,sc7280-eud + - qcom,sm6115-eud - const: qcom,eud reg: - items: - - description: EUD Base Register Region - - description: EUD Mode Manager Register + minItems: 2 + maxItems: 3 + + reg-names: + minItems: 2 + maxItems: 3 interrupts: description: EUD interrupt @@ -50,6 +54,38 @@ required: - reg - ports +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,sc7280-eud + then: + properties: + reg: + maxItems: 2 + reg-names: + items: + - const: eud-base + - const: eud-mode-mgr + + - if: + properties: + compatible: + contains: + enum: + - qcom,sm6115-eud + then: + properties: + reg: + maxItems: 3 + reg-names: + items: + - const: eud-base + - const: eud-mode-mgr + - const: tcsr-base + additionalProperties: false examples: From patchwork Mon Jul 17 10:32:34 2023 Content-Type: text/plain; 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On some SoCs (like the SM6115 / SM4250 SoC), the mode manager needs to be accessed only via the secure world (through 'scm' calls). Also, the enable bit inside 'tcsr_check_reg' needs to be set first to set the eud in 'enable' mode on these SoCs. Signed-off-by: Bhupesh Sharma --- drivers/usb/misc/Kconfig | 2 +- drivers/usb/misc/qcom_eud.c | 62 ++++++++++++++++++++++++++++++++++--- 2 files changed, 58 insertions(+), 6 deletions(-) diff --git a/drivers/usb/misc/Kconfig b/drivers/usb/misc/Kconfig index 99b15b77dfd57..51eb5140caa14 100644 --- a/drivers/usb/misc/Kconfig +++ b/drivers/usb/misc/Kconfig @@ -146,7 +146,7 @@ config USB_APPLEDISPLAY config USB_QCOM_EUD tristate "QCOM Embedded USB Debugger(EUD) Driver" - depends on ARCH_QCOM || COMPILE_TEST + depends on (ARCH_QCOM && QCOM_SCM) || COMPILE_TEST select USB_ROLE_SWITCH help This module enables support for Qualcomm Technologies, Inc. diff --git a/drivers/usb/misc/qcom_eud.c b/drivers/usb/misc/qcom_eud.c index 7f371ea1248c3..136cac90228a0 100644 --- a/drivers/usb/misc/qcom_eud.c +++ b/drivers/usb/misc/qcom_eud.c @@ -11,9 +11,11 @@ #include #include #include +#include #include #include #include +#include #include #define EUD_REG_INT1_EN_MASK 0x0024 @@ -30,15 +32,25 @@ #define EUD_INT_SAFE_MODE BIT(4) #define EUD_INT_ALL (EUD_INT_VBUS | EUD_INT_SAFE_MODE) +#define EUD_EN2_EN BIT(0) +#define EUD_EN2_DISABLE (0) +#define TCSR_CHECK_EN BIT(0) + +struct eud_soc_cfg { + u32 tcsr_check_offset; +}; + struct eud_chip { struct device *dev; struct usb_role_switch *role_sw; + const struct eud_soc_cfg *eud_cfg; void __iomem *base; void __iomem *mode_mgr; unsigned int int_status; int irq; bool enabled; bool usb_attached; + phys_addr_t secure_mode_mgr; }; static int enable_eud(struct eud_chip *priv) @@ -46,7 +58,11 @@ static int enable_eud(struct eud_chip *priv) writel(EUD_ENABLE, priv->base + EUD_REG_CSR_EUD_EN); writel(EUD_INT_VBUS | EUD_INT_SAFE_MODE, priv->base + EUD_REG_INT1_EN_MASK); - writel(1, priv->mode_mgr + EUD_REG_EUD_EN2); + + if (priv->secure_mode_mgr) + qcom_scm_io_writel(priv->secure_mode_mgr + EUD_REG_EUD_EN2, EUD_EN2_EN); + else + writel(EUD_EN2_EN, priv->mode_mgr + EUD_REG_EUD_EN2); return usb_role_switch_set_role(priv->role_sw, USB_ROLE_DEVICE); } @@ -54,7 +70,11 @@ static int enable_eud(struct eud_chip *priv) static void disable_eud(struct eud_chip *priv) { writel(0, priv->base + EUD_REG_CSR_EUD_EN); - writel(0, priv->mode_mgr + EUD_REG_EUD_EN2); + + if (priv->secure_mode_mgr) + qcom_scm_io_writel(priv->secure_mode_mgr + EUD_REG_EUD_EN2, EUD_EN2_DISABLE); + else + writel(EUD_EN2_DISABLE, priv->mode_mgr + EUD_REG_EUD_EN2); } static ssize_t enable_show(struct device *dev, @@ -178,6 +198,8 @@ static void eud_role_switch_release(void *data) static int eud_probe(struct platform_device *pdev) { struct eud_chip *chip; + struct resource *res; + phys_addr_t tcsr_check; int ret; chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); @@ -200,9 +222,34 @@ static int eud_probe(struct platform_device *pdev) if (IS_ERR(chip->base)) return PTR_ERR(chip->base); - chip->mode_mgr = devm_platform_ioremap_resource(pdev, 1); - if (IS_ERR(chip->mode_mgr)) - return PTR_ERR(chip->mode_mgr); + /* + * EUD block on a few Qualcomm SoCs needs secure register access. + * Check for the same via SoC specific config data. + */ + chip->eud_cfg = of_device_get_match_data(&pdev->dev); + if (chip->eud_cfg) { + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (!res) + return dev_err_probe(chip->dev, -ENODEV, + "failed to get secure_mode_mgr reg base\n"); + + chip->secure_mode_mgr = res->start; + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "tcsr-base"); + if (!res) + return dev_err_probe(chip->dev, -ENODEV, + "failed to get tcsr reg base\n"); + + tcsr_check = res->start + chip->eud_cfg->tcsr_check_offset; + + ret = qcom_scm_io_writel(tcsr_check, TCSR_CHECK_EN); + if (ret) + return dev_err_probe(chip->dev, ret, "failed to write tcsr check reg\n"); + } else { + chip->mode_mgr = devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(chip->mode_mgr)) + return PTR_ERR(chip->mode_mgr); + } chip->irq = platform_get_irq(pdev, 0); ret = devm_request_threaded_irq(&pdev->dev, chip->irq, handle_eud_irq, @@ -228,8 +275,13 @@ static void eud_remove(struct platform_device *pdev) disable_irq_wake(chip->irq); } +static const struct eud_soc_cfg sm6115_eud_cfg = { + .tcsr_check_offset = 0x25018, +}; + static const struct of_device_id eud_dt_match[] = { { .compatible = "qcom,sc7280-eud" }, + { .compatible = "qcom,sm6115-eud", .data = &sm6115_eud_cfg }, { } }; MODULE_DEVICE_TABLE(of, eud_dt_match); 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Now, the EUD debug peripheral can be enabled by executing: $ echo 1 > /sys/bus/platform/drivers/qcom_eud/1610000.eud/enable Reviewed-by: Konrad Dybcio Signed-off-by: Bhupesh Sharma --- arch/arm64/boot/dts/qcom/qrb4210-rb2.dts | 27 +++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts index a7278a9472ed9..640668960deb0 100644 --- a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts +++ b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts @@ -264,6 +264,10 @@ &pon_resin { status = "okay"; }; +&eud { + status = "okay"; +}; + &qupv3_id_0 { status = "okay"; }; @@ -518,7 +522,28 @@ &usb { &usb_dwc3 { maximum-speed = "super-speed"; - dr_mode = "peripheral"; + + /* + * There is only one USB DWC3 controller on QRB4210 board and it is connected + * via a DIP Switch: + * - to either an USB - C type connector or an USB - A type connector + * (via a GL3590-S hub), and + * - to either an USB - A type connector (via a GL3590-S hub) or a connector + * for further connection with a mezzanine board. + * + * All of the above hardware muxes would allow us to hook things up in + * different ways to some potential benefit for static configurations (for e.g. + * on one hand we can have two USB - A type connectors and a USB - Ethernet + * connection available and on the other we can use the USB - C type in + * peripheral mode). + * + * Note that since the USB - C type can be used only in peripehral mode, + * so hardcoding the mode to 'peripheral' here makes sense. + * + * However since we want to use the EUD debug device, we set the mode as + * 'otg' here. + */ + dr_mode = "otg"; }; &usb_hsphy {