From patchwork Wed Jul 19 15:30:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Philippe Brucker X-Patchwork-Id: 704318 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e4d:0:b0:314:25da:8dc4 with SMTP id r13csp2191818wrt; Wed, 19 Jul 2023 08:57:50 -0700 (PDT) X-Google-Smtp-Source: APBJJlHuZGT3BY24MLicisw1TwTl0lGheKeCK+DOl+gk7CkRCXnEEBTBueG8Q39XTovGeOUafGpF X-Received: by 2002:ac8:5949:0:b0:403:aa49:606e with SMTP id 9-20020ac85949000000b00403aa49606emr24450014qtz.30.1689782269961; Wed, 19 Jul 2023 08:57:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689782269; cv=none; d=google.com; s=arc-20160816; b=uNZazVKNqXxNuQhGDJgB8rdm2nmtO4eSlGVuRivsy7Ly2TdT9xidhUrPL+tfm/5Etm 8pkMxi2wwCyMxAVlKj7e28xYQ8xJlLpNozqFn9OW6SahfUPGzaoHS3pHPJYWqXjqpOQE YTRgXqmybe4LRT1gYvIK7eoT3mKYTjiDwgUZazpxHSf2xq/XCorMFlBhkW/mQjGHyP7Z GKRIcQ4z4O6W7hqIYGQke3ZH9AwH9w1vzpUU+mhuQzFcEga8QuGhIOAtCiGxT7MHpgiT zvHxKwRqAhrHqJIJ/QaHKXuTOBsSQDDc3VUDOcAtNxwljJyH6hMCV9FAMZIEgMKNJ4gA CJgw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=WNPqefvQgMivoBtumxDAYGfl0jiPjDA6sqhpbGZ4NhE=; fh=zMLmPP9ozJY0jj0bAXqZquWHP0BgmjJZ9lKiHhJNaWU=; b=laTQ8G94fxoA3yFuc9flhzMvbQB41Z6sPb9TtzrVY+6wGXcB5UkXgZ8prDQBNbUIsA xTKhtfpxeSnqqrN9tdHUqx0rNnsWOFX/tTiKcF8NcEkSWe0amG5xwtakckFH3mUbiObO rw5D9MsBk09o+urylsjAvw51ty0Gh/6rGjx10/Y1aciEEhCUAFfScFTueOVW2ycgjDfW mWjilgAdV7aSlehhDZY+ftY73EcMSWWR1j00zHGTvrgwygkRjCW/BBwcLciWPWDQEuY7 /nLzs1XokvYuvXnrnbQKTsFpXoLyiKbGIcLFK7nsHHLMW6FtIWT2xXB8Q2bPLW+ik9fE gKRg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="b/0hKs0Q"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d20-20020a05622a101400b003f1fba7038csi2959925qte.429.2023.07.19.08.57.49 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 19 Jul 2023 08:57:49 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="b/0hKs0Q"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qM9Xv-00038G-2Q; Wed, 19 Jul 2023 11:56:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qM9Xq-00036d-V4 for qemu-devel@nongnu.org; Wed, 19 Jul 2023 11:56:55 -0400 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qM9Xl-0007IS-8A for qemu-devel@nongnu.org; Wed, 19 Jul 2023 11:56:54 -0400 Received: by mail-wm1-x335.google.com with SMTP id 5b1f17b1804b1-3fbdfda88f4so64928055e9.1 for ; Wed, 19 Jul 2023 08:56:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1689782205; x=1690387005; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WNPqefvQgMivoBtumxDAYGfl0jiPjDA6sqhpbGZ4NhE=; b=b/0hKs0QxDQccRusYNa5gcfxhSGWwRIFg3RS7TS0wQgh2xg/t4sOawHxqaNGQdze5u Y1ZS1No5vF3tbx5w5qdPbQ74gugYWY0XVGl8bOALogHaofJA5C4+8eYamZKn8poVx48A IFpqCc11TaMrB3JdRllZ+M1ZheG03HCZllNjiLBzGroGFcDX57QYxtQqo7vR9JqEShDO uxltFYAXNfBGZM9zMEk2d3pDUSzHsVcx1WS1S2yahaK1zn9UTrNwVxbvK8RwoZafVRTU whrKLmX53YODwWc9yc0AMp2S5DJn/J8FZjp/SIRBhKd3LwRlyDfUVyEbwiO+JZf/94rn Irdg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689782205; x=1690387005; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WNPqefvQgMivoBtumxDAYGfl0jiPjDA6sqhpbGZ4NhE=; b=NfRWYN8rqCIBpWbMMDFZ4FFNekeEY6vgoHAL04FfTxlF66//c4Sr3q/bPFVPzsxK+P 7vQIA7PT9yEmm+Ydup/FAR0EYiRGoqMFt4dSyDhMTnWlOepvinVGvOKJhUd9b0leYVhp ltV7gJlcQWVHUI4z5FVnBqrzGTZ5DAeJkuP23g7jG2X4jx9daEZWIi7Ssy1A2y9POJRt +LWUu99OQHO9w/jzvxeBA6UeY7gYwHonOO5zkuUNVgWXcdeU36GhFKvY5W4eX2amezTb 8uEgMO7EENrkIryBtKSaaQoWye4CWc0CT6xY4JIdZhpPd5PmCgIo/rl3onbtUKgOJhMa mn6A== X-Gm-Message-State: ABy/qLazkGmp/fwmrLQiRNVoIAuNNR5pGneeFEM/uwF+UBn8aFToM+Q4 cyHq3VOFycU79e77AYnYWbRO5w== X-Received: by 2002:a05:600c:20d1:b0:3fc:80a:993e with SMTP id y17-20020a05600c20d100b003fc080a993emr4651088wmm.17.1689782205641; Wed, 19 Jul 2023 08:56:45 -0700 (PDT) Received: from localhost.localdomain ([2.219.138.198]) by smtp.gmail.com with ESMTPSA id l14-20020a1c790e000000b003fc3b03caa4sm2351006wme.0.2023.07.19.08.56.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Jul 2023 08:56:45 -0700 (PDT) From: Jean-Philippe Brucker To: peter.maydell@linaro.org Cc: richard.henderson@linaro.org, qemu-arm@nongnu.org, qemu-devel@nongnu.org, Jean-Philippe Brucker Subject: [PATCH 1/5] target/arm/ptw: Load stage-2 tables from realm physical space Date: Wed, 19 Jul 2023 16:30:15 +0100 Message-ID: <20230719153018.1456180-3-jean-philippe@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230719153018.1456180-2-jean-philippe@linaro.org> References: <20230719153018.1456180-2-jean-philippe@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=jean-philippe@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In realm state, stage-2 translation tables are fetched from the realm physical address space (R_PGRQD). Signed-off-by: Jean-Philippe Brucker --- target/arm/ptw.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index d1de934702..6318e13b98 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -164,7 +164,11 @@ static ARMMMUIdx ptw_idx_for_stage_2(CPUARMState *env, ARMMMUIdx stage2idx) * an NS stage 1+2 lookup while the NS bit is 0.) */ if (!arm_is_secure_below_el3(env) || !arm_el_is_aa64(env, 3)) { - return ARMMMUIdx_Phys_NS; + if (arm_security_space_below_el3(env) == ARMSS_Realm) { + return ARMMMUIdx_Phys_Realm; + } else { + return ARMMMUIdx_Phys_NS; + } } if (stage2idx == ARMMMUIdx_Stage2_S) { s2walk_secure = !(env->cp15.vstcr_el2 & VSTCR_SW); From patchwork Wed Jul 19 15:30:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Philippe Brucker X-Patchwork-Id: 704321 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e4d:0:b0:314:25da:8dc4 with SMTP id r13csp2191954wrt; Wed, 19 Jul 2023 08:58:03 -0700 (PDT) X-Google-Smtp-Source: APBJJlH27muZT+AEpCHGlY3sSFC8QGFoUxoNAFD8EDcgU1FGgR9NqiOo/pks/l8PJrU0KKROjJug X-Received: by 2002:ac8:5750:0:b0:403:c2dc:929d with SMTP id 16-20020ac85750000000b00403c2dc929dmr3926716qtx.48.1689782283586; Wed, 19 Jul 2023 08:58:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689782283; cv=none; d=google.com; s=arc-20160816; b=gV4Qrnt6BkK28QIxVSjW6kYnPh5wtCz4kiT68TjSb/0jLGkISzygcofWVU4k6FYV1M 7s8+C1IvHEO4+2AINXy9AgU9AJKByb6/ZOEvUTXBO4KjJL6bZrg9wAgLVH4dKQ3P3VZ7 VG6zDHmB6hy/6w9mnccPSJg23fo5e1D22RmBVoYDMbhIeo8Pk14wM8cBP5rgJvw1v/Wp RxgnbVx/iBkInXltVc1IusRxafB7ZC1BKlR1AueLNGj6NzNGKhU+CovYbFuvTGESr4x9 hOIj/biLe2KMTy7hgPw/E2QkP0r4q5M7nPnqa1qzOPPIf4IQNHo6BzTbNaZLz5yA+LIZ hlyA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=1ZtPVN3lBHeAgdj1nKPqBU2sV0M1JQVXfLkLVtYjNIk=; fh=zMLmPP9ozJY0jj0bAXqZquWHP0BgmjJZ9lKiHhJNaWU=; b=POQa5vPf7jeM1rsynIKts3vcKGBjOgYQe9TPGxpQl17aFl42tINTMTmN3LlEAWL8uN J9TZgu9dbZyp7EZ2bweUVYzu5bDCXFK0/7FgIFri300LC+ItkxusZA3y9ln62yGSp/po fERHaWEduIG48eWpHGucVf9lWhUEBk0/nuoE3kZAbtijzmIoMT9ZP5vJJF1ghrztyvnc GBZ3KutxxM0hWWMiGlHw/Z/MW/LLT7atPpEpvNtQxxKfMSU8uPHVzkEMZmFJcR/rPAS1 ttvFLE7U+dNwDM37hoRnLkCz+n0DRmsh1attSMnxhM4T01dKPPBUOXdo+U3kygXglq+o Z3gA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=LcMW5US7; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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The TLB VAE2* instructions invalidate the regime that corresponds to the current value of HCR_EL2.E2H. At the moment we only invalidate the EL2 translation regime. This causes problems with RMM, which issues TLBI VAE2IS instructions with HCR_EL2.E2H enabled. Update vae2_tlbmask() to take HCR_EL2.E2H into account. Signed-off-by: Jean-Philippe Brucker --- target/arm/helper.c | 26 ++++++++++++++++++-------- 1 file changed, 18 insertions(+), 8 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index e1b3db6f5f..07a9ac70f5 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4663,6 +4663,21 @@ static int vae1_tlbmask(CPUARMState *env) return mask; } +static int vae2_tlbmask(CPUARMState *env) +{ + uint64_t hcr = arm_hcr_el2_eff(env); + uint16_t mask; + + if (hcr & HCR_E2H) { + mask = ARMMMUIdxBit_E20_2 | + ARMMMUIdxBit_E20_2_PAN | + ARMMMUIdxBit_E20_0; + } else { + mask = ARMMMUIdxBit_E2; + } + return mask; +} + /* Return 56 if TBI is enabled, 64 otherwise. */ static int tlbbits_for_regime(CPUARMState *env, ARMMMUIdx mmu_idx, uint64_t addr) @@ -4781,7 +4796,7 @@ static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri, * flush-last-level-only. */ CPUState *cs = env_cpu(env); - int mask = e2_tlbmask(env); + int mask = vae2_tlbmask(env); uint64_t pageaddr = sextract64(value << 12, 0, 56); tlb_flush_page_by_mmuidx(cs, pageaddr, mask); @@ -4838,11 +4853,11 @@ static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { CPUState *cs = env_cpu(env); + int mask = vae2_tlbmask(env); uint64_t pageaddr = sextract64(value << 12, 0, 56); int bits = tlbbits_for_regime(env, ARMMMUIdx_E2, pageaddr); - tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, - ARMMMUIdxBit_E2, bits); + tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, bits); } static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -5014,11 +5029,6 @@ static void tlbi_aa64_rvae1is_write(CPUARMState *env, do_rvae_write(env, value, vae1_tlbmask(env), true); } -static int vae2_tlbmask(CPUARMState *env) -{ - return ARMMMUIdxBit_E2; -} - static void tlbi_aa64_rvae2_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) From patchwork Wed Jul 19 15:30:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Philippe Brucker X-Patchwork-Id: 704320 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e4d:0:b0:314:25da:8dc4 with SMTP id r13csp2191821wrt; Wed, 19 Jul 2023 08:57:50 -0700 (PDT) X-Google-Smtp-Source: APBJJlF6g+RdELeyzoZaf1aM97M9lghu+wCfabFKaOHO2O6YoUodTZKfl28JxyGCal/i7toBxXjE X-Received: by 2002:ac8:5b44:0:b0:403:b33f:5d21 with SMTP id n4-20020ac85b44000000b00403b33f5d21mr3806978qtw.12.1689782270159; Wed, 19 Jul 2023 08:57:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689782270; cv=none; d=google.com; s=arc-20160816; b=j5nkhiWtxjDHMMVh6U89tVMe1rNb2d3vqxe0CP4973Gwc1fyex13gpr0ypYC1A5l8k Fu6r19Z5hp7C9AnE26i3/KHbpsplgGV/clPxb2q2JKwf5lsMvgzL6n65TdePBr+KWMox x0sMVX4RETWNI+5Pf+YbCSx1llc1a6x+4iTvGiXpnpASjqrbkIFTKpG2Tt0GzIe0vsHv gzzljL1x46buQcoyYnL9IcYHJZ1i08Keoo2qm2NUldFYbRAKPt01ph9JIGr9yXH0z9DT YdM3mnbsXzdaKriFWgp50mEzdmthys7kum5XYPnA3LE/NbL3RAYwTPPOxov/2r0f6RgM x9qw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=gGmNjom1dWAWIl07haN1UV6R0kEmVNpwwthNJP86YHc=; fh=zMLmPP9ozJY0jj0bAXqZquWHP0BgmjJZ9lKiHhJNaWU=; b=ORAJR2gpn2x7mrZNzcjMfd9uw1TDmmx67TImqK+kSSvOnYu8BpXNOJ/ylhDz6EfbPo yUAMpgnGAUVIr4Acyhh0EHdqfms3oSkNVC+fU0rUFxMG8uyMZAFCNkooirr8214se59v CKHjXUEPOe7+MXu1VHPS60cCHQ9H58+WDrLerYhfdYOpPmQ5jsi8kmm0rgeJw4JkuwmO EmqxahhyWitHXE2Pk8VO6Gx+3h/IMHimbqZDLvVoaM6PgWZSBxbpBO3oxDs44o2gJVKA JYT/E+NH2eJ5TxVmVMalXO80jj+CUPow0BEEfviLfGU+OuNhe4oRGZG4glSTf2Zshgjp Yhcg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=yc3U8vt2; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Rename get_phys_addr_with_secure(), since it's only used to handle AT instructions. Signed-off-by: Jean-Philippe Brucker Reviewed-by: Peter Maydell --- This incidentally fixes a problem with AT S1E1 instructions which can output an IPA and should definitely not cause a GPC. --- target/arm/internals.h | 25 ++++++++++++++----------- target/arm/helper.c | 8 ++++++-- target/arm/ptw.c | 11 ++++++----- 3 files changed, 26 insertions(+), 18 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 0f01bc32a8..fc90c364f7 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1190,12 +1190,11 @@ typedef struct GetPhysAddrResult { } GetPhysAddrResult; /** - * get_phys_addr_with_secure: get the physical address for a virtual address + * get_phys_addr: get the physical address for a virtual address * @env: CPUARMState * @address: virtual address to get physical address for * @access_type: 0 for read, 1 for write, 2 for execute * @mmu_idx: MMU index indicating required translation regime - * @is_secure: security state for the access * @result: set on translation success. * @fi: set to fault info if the translation fails * @@ -1212,26 +1211,30 @@ typedef struct GetPhysAddrResult { * * for PSMAv5 based systems we don't bother to return a full FSR format * value. */ -bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address, - MMUAccessType access_type, - ARMMMUIdx mmu_idx, bool is_secure, - GetPhysAddrResult *result, ARMMMUFaultInfo *fi) +bool get_phys_addr(CPUARMState *env, target_ulong address, + MMUAccessType access_type, ARMMMUIdx mmu_idx, + GetPhysAddrResult *result, ARMMMUFaultInfo *fi) __attribute__((nonnull)); /** - * get_phys_addr: get the physical address for a virtual address + * get_phys_addr_with_secure_nogpc: get the physical address for a virtual + * address * @env: CPUARMState * @address: virtual address to get physical address for * @access_type: 0 for read, 1 for write, 2 for execute * @mmu_idx: MMU index indicating required translation regime + * @is_secure: security state for the access * @result: set on translation success. * @fi: set to fault info if the translation fails * - * Similarly, but use the security regime of @mmu_idx. + * Similar to get_phys_addr, but use the given security regime and don't perform + * a Granule Protection Check on the resulting address. */ -bool get_phys_addr(CPUARMState *env, target_ulong address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, - GetPhysAddrResult *result, ARMMMUFaultInfo *fi) +bool get_phys_addr_with_secure_nogpc(CPUARMState *env, target_ulong address, + MMUAccessType access_type, + ARMMMUIdx mmu_idx, bool is_secure, + GetPhysAddrResult *result, + ARMMMUFaultInfo *fi) __attribute__((nonnull)); bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, diff --git a/target/arm/helper.c b/target/arm/helper.c index 07a9ac70f5..3ee2bb5fe1 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3365,8 +3365,12 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value, ARMMMUFaultInfo fi = {}; GetPhysAddrResult res = {}; - ret = get_phys_addr_with_secure(env, value, access_type, mmu_idx, - is_secure, &res, &fi); + /* + * I_MXTJT: Granule protection checks are not performed on the final address + * of a successful translation. + */ + ret = get_phys_addr_with_secure_nogpc(env, value, access_type, mmu_idx, + is_secure, &res, &fi); /* * ATS operations only do S1 or S1+S2 translations, so we never diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 6318e13b98..1aef2b8cef 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -3412,16 +3412,17 @@ static bool get_phys_addr_gpc(CPUARMState *env, S1Translate *ptw, return false; } -bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, - bool is_secure, GetPhysAddrResult *result, - ARMMMUFaultInfo *fi) +bool get_phys_addr_with_secure_nogpc(CPUARMState *env, target_ulong address, + MMUAccessType access_type, + ARMMMUIdx mmu_idx, bool is_secure, + GetPhysAddrResult *result, + ARMMMUFaultInfo *fi) { S1Translate ptw = { .in_mmu_idx = mmu_idx, .in_space = arm_secure_to_space(is_secure), }; - return get_phys_addr_gpc(env, &ptw, address, access_type, result, fi); + return get_phys_addr_nogpc(env, &ptw, address, access_type, result, fi); } bool get_phys_addr(CPUARMState *env, target_ulong address, From patchwork Wed Jul 19 15:30:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Philippe Brucker X-Patchwork-Id: 704317 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e4d:0:b0:314:25da:8dc4 with SMTP id r13csp2191750wrt; Wed, 19 Jul 2023 08:57:40 -0700 (PDT) X-Google-Smtp-Source: APBJJlGBf0B+FSm57B0w+QtiHShkWn0qO9MiN5O1xKg5PLnc2/SOkg/P/0+x5u9t+GCk790il5BJ X-Received: by 2002:a54:4f89:0:b0:3a3:6364:2b73 with SMTP id g9-20020a544f89000000b003a363642b73mr2926988oiy.52.1689782260580; Wed, 19 Jul 2023 08:57:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689782260; cv=none; d=google.com; s=arc-20160816; b=KJQaCmYgypJ0rS39QiEVi1gpaTWxZNhMMQoPiaCch2qHh6+Y4sV3WGYDMSa2Di2kw6 TKr1+6T54AFa/CKQ96kMGIuKa0Sy+JSjTH1qTmxLtsz+t/2nGaQTUILawf6CE7EGcOe/ uclZ28wBf3qCwT8uuy4Lfenz/0FlvNRciDE0xoTnSaJIAC99r8WN1gFpDdN5lktSuFDy Kdh6wzZBdGhg74nS8FbZAqw0bgJU/C0YE0XAd8hZ0Ar6BJILyJ9HhE+AwUM85AthN8Rj B3o4AEHERi+3l1+ChSEDem21ycAZ1FrNDKfN7InIPndI6NNuNQ2RDmfFjZEPBInAU2Mx TAnw== ARC-Message-Signature: i=1; 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[209.51.188.17]) by mx.google.com with ESMTPS id q20-20020a05622a031400b00403b6f13edesi2949184qtw.212.2023.07.19.08.57.40 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 19 Jul 2023 08:57:40 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xzLpRR+h; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qM9Xr-00037e-V9; Wed, 19 Jul 2023 11:56:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qM9Xq-00036P-Ai for qemu-devel@nongnu.org; Wed, 19 Jul 2023 11:56:54 -0400 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qM9Xl-0007Iy-80 for qemu-devel@nongnu.org; Wed, 19 Jul 2023 11:56:54 -0400 Received: by mail-wm1-x335.google.com with SMTP id 5b1f17b1804b1-3fbc244d384so65681855e9.0 for ; Wed, 19 Jul 2023 08:56:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1689782207; x=1690387007; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FZ2bPahlx3LV2sRcFrJrnz1tXtkeMss0dhYnH4Xs6LA=; b=xzLpRR+hUzGzodg93yn4hDtKLGUPfQFnr/koe3PzlsNGsxvnAA5XuvR6Yr0LOS5ZNc EwL3noelyk8srQszf7xT8aHq4OLPZg6EGZf3rBmuC568hr9ZURbjgAyaaZWl7ldpFVaI 6t1akIBKXsS1DZynLvcKB16BzT+JE4FW/iNTCdr2lFvmR0tiKdjWWzxfjzwikSQktQsG ckiWG8z45g/xrkdjHIB9Egt5F3IBunT/Oz2Qns1PMQY4jl74o8c1MrSjuvWzvyvHh6gQ 7C0+DtBTor5xoUx15Q4MV8MDmcNODwoMECzx1AanU0zF2N95VP+rb4tXA2RlmIlP7pZd K1cA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689782207; x=1690387007; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FZ2bPahlx3LV2sRcFrJrnz1tXtkeMss0dhYnH4Xs6LA=; b=g7KZHLAgNXivqeNriyx/My8c9wUmec8FlSploksdfLXjo01WB9yAG7JOTvzinhEUCH 0URSVaFsBBJl2Xx1JlIxjc8r8SnVo5YM5EQRvFracnDqCVJWhdFO2/3EQL1NuXwKX9vO EW4Lg3MPRN7wPxvWBdlb32XGfU/kb6Btvj9Bl8rwQkruMh3opFgJBo4pGCNv3Ps48TDB CzMkx2Nh8UJRCRuVDyu3dKT8tS9xd9wEu7BtTaWGib8Ow8EsJJpILnhCca1gEfd471tH hWTXqkHXEjKMQZRd2WrkwG8gaOboVoIILRjDH9DqMQoDRWdsnhaTxqTHdssPhzjMJX93 Onlg== X-Gm-Message-State: ABy/qLaUN8JwCdQj0h3pU14n2EyTsoDyYLg9HGgRORnxLRwE3O4OBaNM cxxXnxNb0ejwf7ANK9s6RGGOiGm+wr9gaT7qsFM= X-Received: by 2002:a7b:cd93:0:b0:3fc:1fb:79d3 with SMTP id y19-20020a7bcd93000000b003fc01fb79d3mr4796514wmj.15.1689782207102; Wed, 19 Jul 2023 08:56:47 -0700 (PDT) Received: from localhost.localdomain ([2.219.138.198]) by smtp.gmail.com with ESMTPSA id l14-20020a1c790e000000b003fc3b03caa4sm2351006wme.0.2023.07.19.08.56.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Jul 2023 08:56:46 -0700 (PDT) From: Jean-Philippe Brucker To: peter.maydell@linaro.org Cc: richard.henderson@linaro.org, qemu-arm@nongnu.org, qemu-devel@nongnu.org, Jean-Philippe Brucker Subject: [PATCH 4/5] target/arm: Pass security space rather than flag for AT instructions Date: Wed, 19 Jul 2023 16:30:18 +0100 Message-ID: <20230719153018.1456180-6-jean-philippe@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230719153018.1456180-2-jean-philippe@linaro.org> References: <20230719153018.1456180-2-jean-philippe@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=jean-philippe@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org At the moment we only handle Secure and Nonsecure security spaces for the AT instructions. Add support for Realm and Root. For AArch64, arm_security_space() gives the desired space. ARM DDI0487J says (R_NYXTL): If EL3 is implemented, then when an address translation instruction that applies to an Exception level lower than EL3 is executed, the Effective value of SCR_EL3.{NSE, NS} determines the target Security state that the instruction applies to. For AArch32, some instructions can access NonSecure space from Secure, so we still need to pass the state explicitly to do_ats_write(). Signed-off-by: Jean-Philippe Brucker Reviewed-by: Peter Maydell --- I haven't tested AT instructions in Realm/Root space yet, but it looks like the patch is needed. RMM doesn't issue AT instructions like KVM does in non-secure state (which triggered the bug in the previous patch). --- target/arm/internals.h | 18 +++++++++--------- target/arm/helper.c | 27 ++++++++++++--------------- target/arm/ptw.c | 12 ++++++------ 3 files changed, 27 insertions(+), 30 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index fc90c364f7..cf13bb94f5 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1217,24 +1217,24 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, __attribute__((nonnull)); /** - * get_phys_addr_with_secure_nogpc: get the physical address for a virtual - * address + * get_phys_addr_with_space_nogpc: get the physical address for a virtual + * address * @env: CPUARMState * @address: virtual address to get physical address for * @access_type: 0 for read, 1 for write, 2 for execute * @mmu_idx: MMU index indicating required translation regime - * @is_secure: security state for the access + * @space: security space for the access * @result: set on translation success. * @fi: set to fault info if the translation fails * - * Similar to get_phys_addr, but use the given security regime and don't perform + * Similar to get_phys_addr, but use the given security space and don't perform * a Granule Protection Check on the resulting address. */ -bool get_phys_addr_with_secure_nogpc(CPUARMState *env, target_ulong address, - MMUAccessType access_type, - ARMMMUIdx mmu_idx, bool is_secure, - GetPhysAddrResult *result, - ARMMMUFaultInfo *fi) +bool get_phys_addr_with_space_nogpc(CPUARMState *env, target_ulong address, + MMUAccessType access_type, + ARMMMUIdx mmu_idx, ARMSecuritySpace space, + GetPhysAddrResult *result, + ARMMMUFaultInfo *fi) __attribute__((nonnull)); bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, diff --git a/target/arm/helper.c b/target/arm/helper.c index 3ee2bb5fe1..2017b11795 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3357,7 +3357,7 @@ static int par_el1_shareability(GetPhysAddrResult *res) static uint64_t do_ats_write(CPUARMState *env, uint64_t value, MMUAccessType access_type, ARMMMUIdx mmu_idx, - bool is_secure) + ARMSecuritySpace ss) { bool ret; uint64_t par64; @@ -3369,8 +3369,8 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value, * I_MXTJT: Granule protection checks are not performed on the final address * of a successful translation. */ - ret = get_phys_addr_with_secure_nogpc(env, value, access_type, mmu_idx, - is_secure, &res, &fi); + ret = get_phys_addr_with_space_nogpc(env, value, access_type, mmu_idx, ss, + &res, &fi); /* * ATS operations only do S1 or S1+S2 translations, so we never @@ -3535,7 +3535,7 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) uint64_t par64; ARMMMUIdx mmu_idx; int el = arm_current_el(env); - bool secure = arm_is_secure_below_el3(env); + ARMSecuritySpace ss = arm_security_space(env); switch (ri->opc2 & 6) { case 0: @@ -3543,10 +3543,9 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) switch (el) { case 3: mmu_idx = ARMMMUIdx_E3; - secure = true; break; case 2: - g_assert(!secure); /* ARMv8.4-SecEL2 is 64-bit only */ + g_assert(ss != ARMSS_Secure); /* ARMv8.4-SecEL2 is 64-bit only */ /* fall through */ case 1: if (ri->crm == 9 && (env->uncached_cpsr & CPSR_PAN)) { @@ -3564,10 +3563,9 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) switch (el) { case 3: mmu_idx = ARMMMUIdx_E10_0; - secure = true; break; case 2: - g_assert(!secure); /* ARMv8.4-SecEL2 is 64-bit only */ + g_assert(ss != ARMSS_Secure); /* ARMv8.4-SecEL2 is 64-bit only */ mmu_idx = ARMMMUIdx_Stage1_E0; break; case 1: @@ -3580,18 +3578,18 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) case 4: /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */ mmu_idx = ARMMMUIdx_E10_1; - secure = false; + ss = ARMSS_NonSecure; break; case 6: /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */ mmu_idx = ARMMMUIdx_E10_0; - secure = false; + ss = ARMSS_NonSecure; break; default: g_assert_not_reached(); } - par64 = do_ats_write(env, value, access_type, mmu_idx, secure); + par64 = do_ats_write(env, value, access_type, mmu_idx, ss); A32_BANKED_CURRENT_REG_SET(env, par, par64); #else @@ -3608,7 +3606,8 @@ static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t par64; /* There is no SecureEL2 for AArch32. */ - par64 = do_ats_write(env, value, access_type, ARMMMUIdx_E2, false); + par64 = do_ats_write(env, value, access_type, ARMMMUIdx_E2, + ARMSS_NonSecure); A32_BANKED_CURRENT_REG_SET(env, par, par64); #else @@ -3633,7 +3632,6 @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, #ifdef CONFIG_TCG MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD; ARMMMUIdx mmu_idx; - int secure = arm_is_secure_below_el3(env); uint64_t hcr_el2 = arm_hcr_el2_eff(env); bool regime_e20 = (hcr_el2 & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE); @@ -3653,7 +3651,6 @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, break; case 6: /* AT S1E3R, AT S1E3W */ mmu_idx = ARMMMUIdx_E3; - secure = true; break; default: g_assert_not_reached(); @@ -3673,7 +3670,7 @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, } env->cp15.par_el[1] = do_ats_write(env, value, access_type, - mmu_idx, secure); + mmu_idx, arm_security_space(env)); #else /* Handled by hardware accelerator. */ g_assert_not_reached(); diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 1aef2b8cef..d0270776be 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -3412,15 +3412,15 @@ static bool get_phys_addr_gpc(CPUARMState *env, S1Translate *ptw, return false; } -bool get_phys_addr_with_secure_nogpc(CPUARMState *env, target_ulong address, - MMUAccessType access_type, - ARMMMUIdx mmu_idx, bool is_secure, - GetPhysAddrResult *result, - ARMMMUFaultInfo *fi) +bool get_phys_addr_with_space_nogpc(CPUARMState *env, target_ulong address, + MMUAccessType access_type, + ARMMMUIdx mmu_idx, ARMSecuritySpace space, + GetPhysAddrResult *result, + ARMMMUFaultInfo *fi) { S1Translate ptw = { .in_mmu_idx = mmu_idx, - .in_space = arm_secure_to_space(is_secure), + .in_space = space, }; return get_phys_addr_nogpc(env, &ptw, address, access_type, result, fi); } From patchwork Wed Jul 19 15:30:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Philippe Brucker X-Patchwork-Id: 704319 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e4d:0:b0:314:25da:8dc4 with SMTP id r13csp2191817wrt; Wed, 19 Jul 2023 08:57:50 -0700 (PDT) X-Google-Smtp-Source: APBJJlF60khp99z47YZAdRVnpVBqbkWPFpEGYJiWn9KdcHXMEwHFHknJR5nD/VbOfwuDvoe4hzQD X-Received: by 2002:a37:8685:0:b0:768:1572:ebd0 with SMTP id i127-20020a378685000000b007681572ebd0mr2579512qkd.31.1689782269795; Wed, 19 Jul 2023 08:57:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689782269; cv=none; d=google.com; s=arc-20160816; b=ypvyMFRWJFs8PfdMgd4KSri4f4FMfciysITdm34GJhY16K//RxUq6R1Y1rIMex3IJh AYjpim2hh3ypJrQKnp+M9dBY0yylLv8NmolHtfdwEjyU4MRU860SqWhm7E1ijAFhlMN2 uTLoRvKfUEULEJQMQGiy39pDST4fymZvWldK2/4HkH/rHKQCbhsraPRavY7eDbn69c9s vuC3lchevtWGsugjW1qwE6KQKD195y1+DS1TAZoI/2SuhzpQzYBw3y8Vkyu5O3JizkVZ bKFaAF0Mew/uB9n0Wp0GyKRvsFqMBIunb3nw4/VY69yLt3rxwzUPiH8SNLY1LMAxtbwu 5sig== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=YiCD4uNJS7qGPlDJ8wSaAHyyMfjOlkg6Lkn5GrdcJ70=; fh=zMLmPP9ozJY0jj0bAXqZquWHP0BgmjJZ9lKiHhJNaWU=; b=FAHyc+IiKZ19NpguRPsOp9LU76tRCqshJRVyDZas6JCB2mMpHrutdmdD53q/PNdBQZ Jc4cOMJSMB2XxxNLCJe2YHLw8U9mSxPDVbeKAdIw6JOpRX5hbDxsVFNY4ANtxIDVIdve tkO/vChP0s1s8NairNxzIDRmWptdFJOE43g+MIpWWzzB+eyxsXzCMfIlMDP9OKzzU1bu pY4EpnuJ7PaRDcjpapX7Hng81lidWlJKvxZRDuvIH+jZOSUT0HKGav0s4gWCAQZiwKTV bI+OvX73GefTjJ2wsPeFjxzhxVysqOh5HuVnO4nHUhsTlrg3WPKDpGZxqu/Xf2KQGo6y P1og== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gD7+eh4J; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Jean-Philippe Brucker --- target/arm/helper.c | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 2017b11795..5b173a827f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2608,6 +2608,23 @@ static uint64_t gt_get_countervalue(CPUARMState *env) return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / gt_cntfrq_period_ns(cpu); } +static bool gt_is_masked(CPUARMState *env, int timeridx) +{ + ARMSecuritySpace ss = arm_security_space(env); + + /* + * If bits CNTHCTL_EL2.CNT[VP]MASK are set, they override + * CNT[VP]_CTL_EL0.IMASK. They are RES0 in Secure and NonSecure state. + */ + if ((ss == ARMSS_Root || ss == ARMSS_Realm) && + ((timeridx == GTIMER_VIRT && extract64(env->cp15.cnthctl_el2, 18, 1)) || + (timeridx == GTIMER_PHYS && extract64(env->cp15.cnthctl_el2, 19, 1)))) { + return true; + } + + return env->cp15.c14_timer[timeridx].ctl & 2; +} + static void gt_recalc_timer(ARMCPU *cpu, int timeridx) { ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx]; @@ -2627,7 +2644,7 @@ static void gt_recalc_timer(ARMCPU *cpu, int timeridx) gt->ctl = deposit32(gt->ctl, 2, 1, istatus); - irqstate = (istatus && !(gt->ctl & 2)); + irqstate = (istatus && !gt_is_masked(&cpu->env, timeridx)); qemu_set_irq(cpu->gt_timer_outputs[timeridx], irqstate); if (istatus) { @@ -2759,7 +2776,7 @@ static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, * IMASK toggled: don't need to recalculate, * just set the interrupt line based on ISTATUS */ - int irqstate = (oldval & 4) && !(value & 2); + int irqstate = (oldval & 4) && !gt_is_masked(env, timeridx); trace_arm_gt_imask_toggle(timeridx, irqstate); qemu_set_irq(cpu->gt_timer_outputs[timeridx], irqstate);