From patchwork Thu Jul 27 22:32:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Kurapati PSSNV X-Patchwork-Id: 707061 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 55E23C001DC for ; Thu, 27 Jul 2023 22:34:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232835AbjG0Wea (ORCPT ); Thu, 27 Jul 2023 18:34:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48942 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232954AbjG0We2 (ORCPT ); Thu, 27 Jul 2023 18:34:28 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9703C3ABB; Thu, 27 Jul 2023 15:34:03 -0700 (PDT) Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 36RLctbF006908; Thu, 27 Jul 2023 22:33:29 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=Eyj1W0f1tqQbWRnBrD1S3yvtvmKEeJVd/+EQPHcbWRo=; b=CYwKl0QlwjETkp5fpsHQiJ4lY3j5DKxMClq9IC4562AEEuLwYZEVeXEYAFJSqTrbkE13 MJQn70vZPrN89D6habA68/yrRPb+gd/vpeVfFxeYY9Qn4CLkyXEBo/K5AlAHGlfM4HXm YuJQ1BNHhV19UuVfQBdZpiE0HHZ4mcLFxdvLAjmxkZ7I1NmNpGqRmYGKrOcWv9D7F30n qn1FAOcPv0SNhgYFFM1c3hIVmxjdr18/lT+DmC2XJKGpQfML59nocNWHg8UY5T9AgA+U Fuds/A+VxrZlamajGEWLUxi78kqtmfvFyLfmjpZ+aBjUgvASgsXg5qZM0O8jzyHFL0Cn TA== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3s3ufurut6-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 27 Jul 2023 22:33:29 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 36RMXSXE006957 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 27 Jul 2023 22:33:28 GMT Received: from hu-kriskura-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Thu, 27 Jul 2023 15:33:22 -0700 From: Krishna Kurapati To: Thinh Nguyen , Greg Kroah-Hartman , Philipp Zabel , "Andy Gross" , Bjorn Andersson , "Konrad Dybcio" , Rob Herring , Krzysztof Kozlowski , Felipe Balbi , Wesley Cheng , Johan Hovold , Mathias Nyman CC: , , , , , , , , , Krishna Kurapati Subject: [PATCH v10 01/11] dt-bindings: usb: qcom,dwc3: Add bindings for SC8280 Multiport Date: Fri, 28 Jul 2023 04:02:57 +0530 Message-ID: <20230727223307.8096-2-quic_kriskura@quicinc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230727223307.8096-1-quic_kriskura@quicinc.com> References: <20230727223307.8096-1-quic_kriskura@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 4WW3koMxcL7KCvGovDAHnEUKdiaCMpCc X-Proofpoint-ORIG-GUID: 4WW3koMxcL7KCvGovDAHnEUKdiaCMpCc X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-27_10,2023-07-26_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 lowpriorityscore=0 impostorscore=0 bulkscore=0 mlxlogscore=860 mlxscore=0 clxscore=1015 priorityscore=1501 adultscore=0 phishscore=0 suspectscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2307270205 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add the compatible string for SC8280 Multiport USB controller from Qualcomm. There are 4 power event irq interrupts supported by this controller (one for each port of multiport). Added all the 4 as non-optional interrupts for SC8280XP-MP Also each port of multiport has one DP and oen DM IRQ. Add all DP/DM IRQ's related to 4 ports of SC8280XP Teritiary controller. Also added ss phy irq for both SS Ports. Signed-off-by: Krishna Kurapati Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/usb/qcom,dwc3.yaml | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml index ae24dac78d9a..80a0a7be18e3 100644 --- a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml +++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml @@ -28,6 +28,7 @@ properties: - qcom,sc7180-dwc3 - qcom,sc7280-dwc3 - qcom,sc8280xp-dwc3 + - qcom,sc8280xp-dwc3-mp - qcom,sdm660-dwc3 - qcom,sdm670-dwc3 - qcom,sdm845-dwc3 @@ -265,6 +266,7 @@ allOf: contains: enum: - qcom,sc8280xp-dwc3 + - qcom,sc8280xp-dwc3-mp then: properties: clocks: @@ -477,6 +479,33 @@ allOf: - const: dm_hs_phy_irq - const: ss_phy_irq + - if: + properties: + compatible: + contains: + enum: + - qcom,sc8280xp-dwc3-mp + then: + properties: + interrupts: + maxItems: 14 + interrupt-names: + items: + - const: pwr_event_1 + - const: pwr_event_2 + - const: pwr_event_3 + - const: pwr_event_4 + - const: dp_hs_phy_1 + - const: dm_hs_phy_1 + - const: dp_hs_phy_2 + - const: dm_hs_phy_2 + - const: dp_hs_phy_3 + - const: dm_hs_phy_3 + - const: dp_hs_phy_4 + - const: dm_hs_phy_4 + - const: ss_phy_1 + - const: ss_phy_2 + additionalProperties: false examples: From patchwork Thu Jul 27 22:32:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Kurapati PSSNV X-Patchwork-Id: 707060 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2BE5DEB64DD for ; Thu, 27 Jul 2023 22:34:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233041AbjG0Wed (ORCPT ); Thu, 27 Jul 2023 18:34:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49012 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233013AbjG0Wec (ORCPT ); Thu, 27 Jul 2023 18:34:32 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2D6C930E9; Thu, 27 Jul 2023 15:34:05 -0700 (PDT) Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 36RMDhvJ008853; Thu, 27 Jul 2023 22:33:36 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=xPzC+712P7Ufvv5f/4cV6rywwdnlyTHUs98cxTtIqxg=; b=RtpdtQWtWAOeBTWTDVXJY7+v1swSL8QniE/BhACAgnnUkIS8YT0WGa5C6W2v6hhlOtE4 RvWQtwdwsx/+BM39AxroeNinbPhD8sd6KLUlbjYAWbO65z/fx3ujh4Xt7Z0WOg9/b/u2 hoMYGHfnAHqg+TAskJehAFUn14+01e8GBnyQ4LRzRaJWZjnc0gZSgy8dgelRe2N7Qjmu pyfUXRa1NsOX94IjXrMp+o5V7HugHBB7FpoKjZf8Xk2jTuDvO1AWv6+SiQqcKa/O0LSq yiIWWX5mRVv8i8xlSWcon5Q0fE5Fm/tWEiV+4cbOicWPfoRz3DUuOv4+dDR0VCj2rv8N xA== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3s416m80vq-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 27 Jul 2023 22:33:36 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 36RMXZ1r010690 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 27 Jul 2023 22:33:35 GMT Received: from hu-kriskura-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Thu, 27 Jul 2023 15:33:28 -0700 From: Krishna Kurapati To: Thinh Nguyen , Greg Kroah-Hartman , Philipp Zabel , "Andy Gross" , Bjorn Andersson , "Konrad Dybcio" , Rob Herring , Krzysztof Kozlowski , Felipe Balbi , Wesley Cheng , Johan Hovold , Mathias Nyman CC: , , , , , , , , , Krishna Kurapati , Bjorn Andersson , Rob Herring Subject: [PATCH v10 02/11] dt-bindings: usb: Add bindings for multiport properties on DWC3 controller Date: Fri, 28 Jul 2023 04:02:58 +0530 Message-ID: <20230727223307.8096-3-quic_kriskura@quicinc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230727223307.8096-1-quic_kriskura@quicinc.com> References: <20230727223307.8096-1-quic_kriskura@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: rzP9HGSVb5YGSIYplzyO-XXrpkcTjWsE X-Proofpoint-ORIG-GUID: rzP9HGSVb5YGSIYplzyO-XXrpkcTjWsE X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-27_10,2023-07-26_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 bulkscore=0 malwarescore=0 suspectscore=0 clxscore=1011 mlxlogscore=999 impostorscore=0 spamscore=0 mlxscore=0 adultscore=0 priorityscore=1501 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2307270205 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add bindings to indicate properties required to support multiport on Synopsys DWC3 controller. Suggested-by: Bjorn Andersson Signed-off-by: Krishna Kurapati Reviewed-by: Rob Herring --- .../devicetree/bindings/usb/snps,dwc3.yaml | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml b/Documentation/devicetree/bindings/usb/snps,dwc3.yaml index a696f23730d3..5bc941355b43 100644 --- a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml +++ b/Documentation/devicetree/bindings/usb/snps,dwc3.yaml @@ -85,15 +85,16 @@ properties: phys: minItems: 1 - maxItems: 2 + maxItems: 8 phy-names: minItems: 1 - maxItems: 2 - items: - enum: - - usb2-phy - - usb3-phy + maxItems: 8 + oneOf: + - items: + enum: [ usb2-phy, usb3-phy ] + - items: + pattern: "^usb[23]-port[0-3]$" power-domains: description: From patchwork Thu Jul 27 22:33:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Kurapati PSSNV X-Patchwork-Id: 707059 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 693E0C001DC for ; Thu, 27 Jul 2023 22:34:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233141AbjG0Wer (ORCPT ); Thu, 27 Jul 2023 18:34:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49066 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233058AbjG0Wee (ORCPT ); Thu, 27 Jul 2023 18:34:34 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5E08830FA; Thu, 27 Jul 2023 15:34:08 -0700 (PDT) Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 36RLkvlE012619; Thu, 27 Jul 2023 22:33:49 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=trzGwprsJpXjVWUmjWpumkqZX7u5nXeiSfpQWjSVkj8=; b=GUO4cVsagqb8YgRTOQ7tk7CBxkbXyRWGP57HkJ21bkJcFNjt6q4J1NCHE4gnGmJKYKfQ An4LAtAK/NL2rc7xQYuMzn89TNB2Sej3DBrHjv290oHvmjTIu9GcUVOVaq5oeqP7T7Av BoXsgrp7m6KqqwNRT3amew27FJ2BubOF4LkNyHcc2vqh62ZL8G25l+CqOadhP2DTqUIO BTUjoOsa4GfJpFwel/LzbxXSqFIDtLye+JJcTxUCdjmz8xdi/5T56/5xDHH//u7V3jdF c3Q9zt5i3/CR2YtXwQkDahdOaNp0OlOH9ew4W9TUkUszZ5X+fn8kd3+ArUGw1wEPhVHd Hg== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3s403vg510-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 27 Jul 2023 22:33:48 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 36RMXlmp006008 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 27 Jul 2023 22:33:47 GMT Received: from hu-kriskura-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Thu, 27 Jul 2023 15:33:41 -0700 From: Krishna Kurapati To: Thinh Nguyen , Greg Kroah-Hartman , Philipp Zabel , "Andy Gross" , Bjorn Andersson , "Konrad Dybcio" , Rob Herring , Krzysztof Kozlowski , Felipe Balbi , Wesley Cheng , Johan Hovold , Mathias Nyman CC: , , , , , , , , , Krishna Kurapati Subject: [PATCH v10 04/11] usb: dwc3: core: Skip setting event buffers for host only controllers Date: Fri, 28 Jul 2023 04:03:00 +0530 Message-ID: <20230727223307.8096-5-quic_kriskura@quicinc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230727223307.8096-1-quic_kriskura@quicinc.com> References: <20230727223307.8096-1-quic_kriskura@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: foYwvw71ZLYKjwInc93oUs04af32xBpK X-Proofpoint-ORIG-GUID: foYwvw71ZLYKjwInc93oUs04af32xBpK X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-27_10,2023-07-26_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 suspectscore=0 priorityscore=1501 adultscore=0 impostorscore=0 phishscore=0 mlxlogscore=973 mlxscore=0 malwarescore=0 lowpriorityscore=0 spamscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2307270205 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On some SoC's like SA8295P where the tertiary controller is host-only capable, GEVTADDRHI/LO, GEVTSIZ, GEVTCOUNT registers are not accessible. Trying to access them leads to a crash. For DRD/Peripheral supported controllers, event buffer setup is done again in gadget_pullup. Skip setup or cleanup of event buffers if controller is host-only capable. Suggested-by: Johan Hovold Signed-off-by: Krishna Kurapati Acked-by: Thinh Nguyen --- drivers/usb/dwc3/core.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index edc79ce70588..0aa58600a566 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -486,6 +486,13 @@ static void dwc3_free_event_buffers(struct dwc3 *dwc) static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned int length) { struct dwc3_event_buffer *evt; + unsigned int hw_mode; + + hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); + if (hw_mode == DWC3_GHWPARAMS0_MODE_HOST) { + dwc->ev_buf = NULL; + return 0; + } evt = dwc3_alloc_one_event_buffer(dwc, length); if (IS_ERR(evt)) { @@ -507,6 +514,9 @@ int dwc3_event_buffers_setup(struct dwc3 *dwc) { struct dwc3_event_buffer *evt; + if (!dwc->ev_buf) + return 0; + evt = dwc->ev_buf; evt->lpos = 0; dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), @@ -524,6 +534,9 @@ void dwc3_event_buffers_cleanup(struct dwc3 *dwc) { struct dwc3_event_buffer *evt; + if (!dwc->ev_buf) + return; + evt = dwc->ev_buf; evt->lpos = 0; From patchwork Thu Jul 27 22:33:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Kurapati PSSNV X-Patchwork-Id: 707058 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F19BBC41513 for ; Thu, 27 Jul 2023 22:34:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233194AbjG0Wew (ORCPT ); Thu, 27 Jul 2023 18:34:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49350 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233128AbjG0Wer (ORCPT ); Thu, 27 Jul 2023 18:34:47 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D3560358B; Thu, 27 Jul 2023 15:34:12 -0700 (PDT) Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 36RJF92G018598; Thu, 27 Jul 2023 22:34:02 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=jsWb+qEQKFTty1cr8bPdRK+e2mc6+ibu0kXw6ysDFzM=; b=Kn9/XbXOftZlC3PbQB/dKZsRg4Avk5bwdtzY51/huo+Bs21ovcJov7d5XHwS8tyKgp+L erxfaSVGLNU+a4FwB+td7NZnycynNCv1LgizRX+pooDnE0n4r4DJdrc5MXgoFsiwah4Q pkzFbDhjLcLVeazZAoC+MCZwA63XvyxyIjfoWoNjYcJHZftn3D2JVfo5z7KqZxzCWJtH gFVCipHNTUrGhXDZQzWaTmpWmYSVNopX7f53er8gziKTmHwy8ezxGyKUbTCMqPLG88Ob ulhAf3IGTDIdcQ0dFxJDqCDB/UbxlQsuDgQXUK/YOMf19A+IYbXwkARzvFLu2BuxQu/F ug== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3s3k7u2594-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 27 Jul 2023 22:34:01 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 36RMY0Cg007132 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 27 Jul 2023 22:34:00 GMT Received: from hu-kriskura-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Thu, 27 Jul 2023 15:33:54 -0700 From: Krishna Kurapati To: Thinh Nguyen , Greg Kroah-Hartman , Philipp Zabel , "Andy Gross" , Bjorn Andersson , "Konrad Dybcio" , Rob Herring , Krzysztof Kozlowski , Felipe Balbi , Wesley Cheng , Johan Hovold , Mathias Nyman CC: , , , , , , , , , Krishna Kurapati Subject: [PATCH v10 06/11] usb: dwc3: qcom: Refactor IRQ handling in QCOM Glue driver Date: Fri, 28 Jul 2023 04:03:02 +0530 Message-ID: <20230727223307.8096-7-quic_kriskura@quicinc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230727223307.8096-1-quic_kriskura@quicinc.com> References: <20230727223307.8096-1-quic_kriskura@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: uHA3XX-zuE3HNkMicqNVb6nxyEz1rRoS X-Proofpoint-ORIG-GUID: uHA3XX-zuE3HNkMicqNVb6nxyEz1rRoS X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-27_10,2023-07-26_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 spamscore=0 mlxscore=0 lowpriorityscore=0 malwarescore=0 bulkscore=0 mlxlogscore=999 suspectscore=0 priorityscore=1501 clxscore=1015 phishscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2307270205 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Refactor setup_irq call to facilitate reading multiport IRQ's along with non mulitport ones. For SA8295, there are 4-DP/4-DM and 2-SS IRQ's. Check whether device is multiport capable or not and read all interrupts for DP/DM/SS on each port accordingly. Signed-off-by: Krishna Kurapati Signed-off-by: Krishna Kurapati --- drivers/usb/dwc3/dwc3-qcom.c | 277 ++++++++++++++++++++++++----------- 1 file changed, 190 insertions(+), 87 deletions(-) diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c index 3de43df6bbe8..ad89ded116d3 100644 --- a/drivers/usb/dwc3/dwc3-qcom.c +++ b/drivers/usb/dwc3/dwc3-qcom.c @@ -64,33 +64,61 @@ struct dwc3_acpi_pdata { bool is_urs; }; +struct dwc3_qcom_of_match_data { + u8 num_ports; +}; + struct dwc3_qcom { - struct device *dev; - void __iomem *qscratch_base; - struct platform_device *dwc3; - struct platform_device *urs_usb; - struct clk **clks; - int num_clocks; - struct reset_control *resets; - - int hs_phy_irq; - int dp_hs_phy_irq; - int dm_hs_phy_irq; - int ss_phy_irq; - enum usb_device_speed usb2_speed; - - struct extcon_dev *edev; - struct extcon_dev *host_edev; - struct notifier_block vbus_nb; - struct notifier_block host_nb; + struct device *dev; + void __iomem *qscratch_base; + struct platform_device *dwc3; + struct platform_device *urs_usb; + struct clk **clks; + int num_clocks; + struct reset_control *resets; + + int hs_phy_irq; + int dp_hs_phy_irq[DWC3_MAX_PORTS]; + int dm_hs_phy_irq[DWC3_MAX_PORTS]; + int ss_phy_irq[DWC3_MAX_PORTS]; + enum usb_device_speed usb2_speed; + + struct extcon_dev *edev; + struct extcon_dev *host_edev; + struct notifier_block vbus_nb; + struct notifier_block host_nb; + + const struct dwc3_acpi_pdata *acpi_pdata; + + enum usb_dr_mode mode; + bool is_suspended; + bool pm_suspended; + struct icc_path *icc_path_ddr; + struct icc_path *icc_path_apps; + const struct dwc3_qcom_of_match_data *data; +}; + +static const struct dwc3_qcom_of_match_data qcom_dwc3 = { + .num_ports = 1, +}; - const struct dwc3_acpi_pdata *acpi_pdata; +static const struct dwc3_qcom_of_match_data sx8280xp_qcom_dwc3 = { + .num_ports = 4, +}; - enum usb_dr_mode mode; - bool is_suspended; - bool pm_suspended; - struct icc_path *icc_path_ddr; - struct icc_path *icc_path_apps; +/* + * Driver needs to read HS/DP_HS/DM_HS/SS IRQ's. Currently, for + * SA8295 which supports mutliport, thre are 4 DP/ 4 DM/ 2 SS IRQ's + * and 1 HS IRQ present. So avoid trying to read HS_PHY_IRQ for 4 + * ports of SA8295. + */ +#define MAX_PHY_IRQ 4 + +enum dwc3_qcom_phy_irq_identifier { + HS_PHY_IRQ = 0, + DP_HS_PHY_IRQ, + DM_HS_PHY_IRQ, + SS_PHY_IRQ, }; static inline void dwc3_qcom_setbits(void __iomem *base, u32 offset, u32 val) @@ -375,16 +403,16 @@ static void dwc3_qcom_disable_interrupts(struct dwc3_qcom *qcom) dwc3_qcom_disable_wakeup_irq(qcom->hs_phy_irq); if (qcom->usb2_speed == USB_SPEED_LOW) { - dwc3_qcom_disable_wakeup_irq(qcom->dm_hs_phy_irq); + dwc3_qcom_disable_wakeup_irq(qcom->dm_hs_phy_irq[0]); } else if ((qcom->usb2_speed == USB_SPEED_HIGH) || (qcom->usb2_speed == USB_SPEED_FULL)) { - dwc3_qcom_disable_wakeup_irq(qcom->dp_hs_phy_irq); + dwc3_qcom_disable_wakeup_irq(qcom->dp_hs_phy_irq[0]); } else { - dwc3_qcom_disable_wakeup_irq(qcom->dp_hs_phy_irq); - dwc3_qcom_disable_wakeup_irq(qcom->dm_hs_phy_irq); + dwc3_qcom_disable_wakeup_irq(qcom->dp_hs_phy_irq[0]); + dwc3_qcom_disable_wakeup_irq(qcom->dm_hs_phy_irq[0]); } - dwc3_qcom_disable_wakeup_irq(qcom->ss_phy_irq); + dwc3_qcom_disable_wakeup_irq(qcom->ss_phy_irq[0]); } static void dwc3_qcom_enable_interrupts(struct dwc3_qcom *qcom) @@ -401,20 +429,20 @@ static void dwc3_qcom_enable_interrupts(struct dwc3_qcom *qcom) */ if (qcom->usb2_speed == USB_SPEED_LOW) { - dwc3_qcom_enable_wakeup_irq(qcom->dm_hs_phy_irq, + dwc3_qcom_enable_wakeup_irq(qcom->dm_hs_phy_irq[0], IRQ_TYPE_EDGE_FALLING); } else if ((qcom->usb2_speed == USB_SPEED_HIGH) || (qcom->usb2_speed == USB_SPEED_FULL)) { - dwc3_qcom_enable_wakeup_irq(qcom->dp_hs_phy_irq, + dwc3_qcom_enable_wakeup_irq(qcom->dp_hs_phy_irq[0], IRQ_TYPE_EDGE_FALLING); } else { - dwc3_qcom_enable_wakeup_irq(qcom->dp_hs_phy_irq, + dwc3_qcom_enable_wakeup_irq(qcom->dp_hs_phy_irq[0], IRQ_TYPE_EDGE_RISING); - dwc3_qcom_enable_wakeup_irq(qcom->dm_hs_phy_irq, + dwc3_qcom_enable_wakeup_irq(qcom->dm_hs_phy_irq[0], IRQ_TYPE_EDGE_RISING); } - dwc3_qcom_enable_wakeup_irq(qcom->ss_phy_irq, 0); + dwc3_qcom_enable_wakeup_irq(qcom->ss_phy_irq[0], 0); } static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bool wakeup) @@ -535,72 +563,138 @@ static int dwc3_qcom_get_irq(struct platform_device *pdev, return ret; } -static int dwc3_qcom_setup_irq(struct platform_device *pdev) +static int dwc3_qcom_prep_irq(struct dwc3_qcom *qcom, char *irq_name, + char *disp_name, int irq) { - struct dwc3_qcom *qcom = platform_get_drvdata(pdev); - const struct dwc3_acpi_pdata *pdata = qcom->acpi_pdata; - int irq; int ret; - irq = dwc3_qcom_get_irq(pdev, "hs_phy_irq", - pdata ? pdata->hs_phy_irq_index : -1); - if (irq > 0) { - /* Keep wakeup interrupts disabled until suspend */ - irq_set_status_flags(irq, IRQ_NOAUTOEN); - ret = devm_request_threaded_irq(qcom->dev, irq, NULL, + /* Keep wakeup interrupts disabled until suspend */ + irq_set_status_flags(irq, IRQ_NOAUTOEN); + ret = devm_request_threaded_irq(qcom->dev, irq, NULL, qcom_dwc3_resume_irq, IRQF_TRIGGER_HIGH | IRQF_ONESHOT, - "qcom_dwc3 HS", qcom); - if (ret) { - dev_err(qcom->dev, "hs_phy_irq failed: %d\n", ret); - return ret; + disp_name, qcom); + if (ret) + dev_err(qcom->dev, "%s failed: %d\n", irq_name, ret); + + return ret; +} + +static int dwc3_get_acpi_index(const struct dwc3_acpi_pdata *pdata, int irq_index) +{ + int acpi_index = -1; + + if (!pdata) + return -1; + + if (irq_index == DP_HS_PHY_IRQ) + acpi_index = pdata->dp_hs_phy_irq_index; + else if (irq_index == DM_HS_PHY_IRQ) + acpi_index = pdata->dm_hs_phy_irq_index; + else if (irq_index == SS_PHY_IRQ) + acpi_index = pdata->ss_phy_irq_index; + + return acpi_index; +} + +static int dwc3_get_port_irq(struct platform_device *pdev, u8 port_index) +{ + struct dwc3_qcom *qcom = platform_get_drvdata(pdev); + bool is_mp_supported = (qcom->data->num_ports > 1) ? true : false; + const struct dwc3_acpi_pdata *pdata = qcom->acpi_pdata; + char *disp_name; + int acpi_index; + char *dt_name; + int ret; + int irq; + int i; + + /* + * We need to read only DP/DM/SS IRQ's here. + * So loop over from 1->3 and accordingly modify respective phy_irq[]. + */ + for (i = 1; i < MAX_PHY_IRQ; i++) { + + if (!is_mp_supported && (port_index == 0)) { + if (i == DP_HS_PHY_IRQ) { + dt_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, + "dp_hs_phy_irq"); + disp_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, + "qcom_dwc3 DP_HS"); + } else if (i == DM_HS_PHY_IRQ) { + dt_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, + "dm_hs_phy_irq"); + disp_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, + "qcom_dwc3 DM_HS"); + } else if (i == SS_PHY_IRQ) { + dt_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, + "ss_phy_irq"); + disp_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, + "qcom_dwc3 SS"); + } + } else { + if (i == DP_HS_PHY_IRQ) { + dt_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, + "dp_hs_phy_%d", port_index + 1); + disp_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, + "qcom_dwc3 DP_HS%d", port_index + 1); + } else if (i == DM_HS_PHY_IRQ) { + dt_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, + "dm_hs_phy_%d", port_index + 1); + disp_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, + "qcom_dwc3 DM_HS%d", port_index + 1); + } else if (i == SS_PHY_IRQ) { + dt_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, + "ss_phy_%d", port_index + 1); + disp_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, + "qcom_dwc3 SS%d", port_index + 1); + } } - qcom->hs_phy_irq = irq; - } - irq = dwc3_qcom_get_irq(pdev, "dp_hs_phy_irq", - pdata ? pdata->dp_hs_phy_irq_index : -1); - if (irq > 0) { - irq_set_status_flags(irq, IRQ_NOAUTOEN); - ret = devm_request_threaded_irq(qcom->dev, irq, NULL, - qcom_dwc3_resume_irq, - IRQF_TRIGGER_HIGH | IRQF_ONESHOT, - "qcom_dwc3 DP_HS", qcom); - if (ret) { - dev_err(qcom->dev, "dp_hs_phy_irq failed: %d\n", ret); - return ret; + if (!dt_name || !disp_name) + return -ENOMEM; + + acpi_index = !is_mp_supported ? dwc3_get_acpi_index(pdata, i) : -1; + + irq = dwc3_qcom_get_irq(pdev, dt_name, acpi_index); + if (irq > 0) { + ret = dwc3_qcom_prep_irq(qcom, dt_name, disp_name, irq); + if (ret) + return ret; + + if (i == DP_HS_PHY_IRQ) + qcom->dp_hs_phy_irq[port_index] = irq; + else if (i == DM_HS_PHY_IRQ) + qcom->dm_hs_phy_irq[port_index] = irq; + else if (i == SS_PHY_IRQ) + qcom->ss_phy_irq[port_index] = irq; } - qcom->dp_hs_phy_irq = irq; } - irq = dwc3_qcom_get_irq(pdev, "dm_hs_phy_irq", - pdata ? pdata->dm_hs_phy_irq_index : -1); + return 0; +} + +static int dwc3_qcom_setup_irq(struct platform_device *pdev) +{ + struct dwc3_qcom *qcom = platform_get_drvdata(pdev); + const struct dwc3_acpi_pdata *pdata = qcom->acpi_pdata; + int irq; + int ret; + int i; + + irq = dwc3_qcom_get_irq(pdev, "hs_phy_irq", + pdata ? pdata->hs_phy_irq_index : -1); if (irq > 0) { - irq_set_status_flags(irq, IRQ_NOAUTOEN); - ret = devm_request_threaded_irq(qcom->dev, irq, NULL, - qcom_dwc3_resume_irq, - IRQF_TRIGGER_HIGH | IRQF_ONESHOT, - "qcom_dwc3 DM_HS", qcom); - if (ret) { - dev_err(qcom->dev, "dm_hs_phy_irq failed: %d\n", ret); + ret = dwc3_qcom_prep_irq(qcom, "hs_phy_irq", "qcom_dwc3 HS",irq); + if (ret) return ret; - } - qcom->dm_hs_phy_irq = irq; + qcom->hs_phy_irq = irq; } - irq = dwc3_qcom_get_irq(pdev, "ss_phy_irq", - pdata ? pdata->ss_phy_irq_index : -1); - if (irq > 0) { - irq_set_status_flags(irq, IRQ_NOAUTOEN); - ret = devm_request_threaded_irq(qcom->dev, irq, NULL, - qcom_dwc3_resume_irq, - IRQF_TRIGGER_HIGH | IRQF_ONESHOT, - "qcom_dwc3 SS", qcom); - if (ret) { - dev_err(qcom->dev, "ss_phy_irq failed: %d\n", ret); + for (i = 0; i < qcom->data->num_ports; i++) { + ret = dwc3_get_port_irq(pdev, i); + if (ret) return ret; - } - qcom->ss_phy_irq = irq; } return 0; @@ -811,6 +905,8 @@ static int dwc3_qcom_probe(struct platform_device *pdev) platform_set_drvdata(pdev, qcom); qcom->dev = &pdev->dev; + qcom->data = of_device_get_match_data(qcom->dev); + if (has_acpi_companion(dev)) { qcom->acpi_pdata = acpi_device_get_match_data(dev); if (!qcom->acpi_pdata) { @@ -1023,8 +1119,15 @@ static const struct dev_pm_ops dwc3_qcom_dev_pm_ops = { }; static const struct of_device_id dwc3_qcom_of_match[] = { - { .compatible = "qcom,dwc3" }, - { } + { + .compatible = "qcom,dwc3", + .data = &qcom_dwc3, + }, + { + .compatible = "qcom,sc8280xp-dwc3-mp", + .data = &sx8280xp_qcom_dwc3, + }, + { }, }; MODULE_DEVICE_TABLE(of, dwc3_qcom_of_match); From patchwork Thu Jul 27 22:33:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Kurapati PSSNV X-Patchwork-Id: 707057 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3F45C41513 for ; Thu, 27 Jul 2023 22:35:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233230AbjG0WfI (ORCPT ); Thu, 27 Jul 2023 18:35:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49054 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233150AbjG0Wer (ORCPT ); Thu, 27 Jul 2023 18:34:47 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ED5BC35AB; Thu, 27 Jul 2023 15:34:16 -0700 (PDT) Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 36RKIj74015134; Thu, 27 Jul 2023 22:34:08 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=VSgr7GQMu0oxXRIZ+p2Owp962oHKtnM365/vgl+plDg=; b=V5ylW/sXOB8auPO30vYZ5uOWe45qO8gv8H94APt628dk7IgeZ01eBeIZeQb0ZU8j0eJ+ oWG7jdQ7Fp1VD2d6ftkNBtbYESKnWRCbzf2Kk3fIHW4RoXqQF6NRg5USSyF0UX8ezSOU 34RI54fyQbO95oL1VbrCEwRmRfKJFBlHdSSwu6n7Hi4YJfz3JMql+YBb7DX3oCINetQ7 MloXIBuwrUQwRfROQstNxEsrsmJYa0f14NNgbHeDVSK9R0PCdl0NMhFGkJjiXgGdTdxq htGCkKk0oNN5waLjddh93TSI8klVX6lwjbIMcN0OYbPLYHI80VXDNPLHc36o4w10KF8x 8A== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3s3mpt20jc-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 27 Jul 2023 22:34:07 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 36RMY6GU013461 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 27 Jul 2023 22:34:06 GMT Received: from hu-kriskura-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Thu, 27 Jul 2023 15:34:00 -0700 From: Krishna Kurapati To: Thinh Nguyen , Greg Kroah-Hartman , Philipp Zabel , "Andy Gross" , Bjorn Andersson , "Konrad Dybcio" , Rob Herring , Krzysztof Kozlowski , Felipe Balbi , Wesley Cheng , Johan Hovold , Mathias Nyman CC: , , , , , , , , , Krishna Kurapati Subject: [PATCH v10 07/11] usb: dwc3: qcom: Enable wakeup for applicable ports of multiport Date: Fri, 28 Jul 2023 04:03:03 +0530 Message-ID: <20230727223307.8096-8-quic_kriskura@quicinc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230727223307.8096-1-quic_kriskura@quicinc.com> References: <20230727223307.8096-1-quic_kriskura@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: mkGJOnaucjrSbnzEPhtgQyxglIfnyZsl X-Proofpoint-GUID: mkGJOnaucjrSbnzEPhtgQyxglIfnyZsl X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-27_10,2023-07-26_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 adultscore=0 spamscore=0 mlxscore=0 phishscore=0 suspectscore=0 lowpriorityscore=0 bulkscore=0 clxscore=1015 mlxlogscore=866 malwarescore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2307270205 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Currently wakeup is supported by only single port controllers. Read speed of each port and accordingly enable IRQ's for those ports. Signed-off-by: Krishna Kurapati --- drivers/usb/dwc3/dwc3-qcom.c | 64 ++++++++++++++++++++---------------- 1 file changed, 35 insertions(+), 29 deletions(-) diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c index ad89ded116d3..a98223291306 100644 --- a/drivers/usb/dwc3/dwc3-qcom.c +++ b/drivers/usb/dwc3/dwc3-qcom.c @@ -81,7 +81,7 @@ struct dwc3_qcom { int dp_hs_phy_irq[DWC3_MAX_PORTS]; int dm_hs_phy_irq[DWC3_MAX_PORTS]; int ss_phy_irq[DWC3_MAX_PORTS]; - enum usb_device_speed usb2_speed; + enum usb_device_speed usb2_speed[DWC3_MAX_PORTS]; struct extcon_dev *edev; struct extcon_dev *host_edev; @@ -349,7 +349,8 @@ static bool dwc3_qcom_is_host(struct dwc3_qcom *qcom) return dwc->xhci; } -static enum usb_device_speed dwc3_qcom_read_usb2_speed(struct dwc3_qcom *qcom) +static enum usb_device_speed dwc3_qcom_read_usb2_speed(struct dwc3_qcom *qcom, + int port_index) { struct dwc3 *dwc = platform_get_drvdata(qcom->dwc3); struct usb_device *udev; @@ -362,12 +363,10 @@ static enum usb_device_speed dwc3_qcom_read_usb2_speed(struct dwc3_qcom *qcom) /* * It is possible to query the speed of all children of - * USB2.0 root hub via usb_hub_for_each_child(). DWC3 code - * currently supports only 1 port per controller. So - * this is sufficient. + * USB2.0 root hub via usb_hub_for_each_child(). */ #ifdef CONFIG_USB - udev = usb_hub_find_child(hcd->self.root_hub, 1); + udev = usb_hub_find_child(hcd->self.root_hub, port_index + 1); #else udev = NULL; #endif @@ -400,23 +399,29 @@ static void dwc3_qcom_disable_wakeup_irq(int irq) static void dwc3_qcom_disable_interrupts(struct dwc3_qcom *qcom) { + int i; + dwc3_qcom_disable_wakeup_irq(qcom->hs_phy_irq); - if (qcom->usb2_speed == USB_SPEED_LOW) { - dwc3_qcom_disable_wakeup_irq(qcom->dm_hs_phy_irq[0]); - } else if ((qcom->usb2_speed == USB_SPEED_HIGH) || - (qcom->usb2_speed == USB_SPEED_FULL)) { - dwc3_qcom_disable_wakeup_irq(qcom->dp_hs_phy_irq[0]); - } else { - dwc3_qcom_disable_wakeup_irq(qcom->dp_hs_phy_irq[0]); - dwc3_qcom_disable_wakeup_irq(qcom->dm_hs_phy_irq[0]); - } + for (i = 0; i < qcom->data->num_ports; i++) { + if (qcom->usb2_speed[i] == USB_SPEED_LOW) { + dwc3_qcom_disable_wakeup_irq(qcom->dm_hs_phy_irq[i]); + } else if ((qcom->usb2_speed[i] == USB_SPEED_HIGH) || + (qcom->usb2_speed[i] == USB_SPEED_FULL)) { + dwc3_qcom_disable_wakeup_irq(qcom->dp_hs_phy_irq[i]); + } else { + dwc3_qcom_disable_wakeup_irq(qcom->dp_hs_phy_irq[i]); + dwc3_qcom_disable_wakeup_irq(qcom->dm_hs_phy_irq[i]); + } - dwc3_qcom_disable_wakeup_irq(qcom->ss_phy_irq[0]); + dwc3_qcom_disable_wakeup_irq(qcom->ss_phy_irq[i]); + } } static void dwc3_qcom_enable_interrupts(struct dwc3_qcom *qcom) { + int i; + dwc3_qcom_enable_wakeup_irq(qcom->hs_phy_irq, 0); /* @@ -427,22 +432,25 @@ static void dwc3_qcom_enable_interrupts(struct dwc3_qcom *qcom) * disconnect and remote wakeup. When no device is connected, configure both * DP and DM lines as rising edge to detect HS/HS/LS device connect scenario. */ + for (i = 0; i < qcom->data->num_ports; i++) { + qcom->usb2_speed[i] = dwc3_qcom_read_usb2_speed(qcom, i); - if (qcom->usb2_speed == USB_SPEED_LOW) { - dwc3_qcom_enable_wakeup_irq(qcom->dm_hs_phy_irq[0], + if (qcom->usb2_speed[i] == USB_SPEED_LOW) { + dwc3_qcom_enable_wakeup_irq(qcom->dm_hs_phy_irq[i], IRQ_TYPE_EDGE_FALLING); - } else if ((qcom->usb2_speed == USB_SPEED_HIGH) || - (qcom->usb2_speed == USB_SPEED_FULL)) { - dwc3_qcom_enable_wakeup_irq(qcom->dp_hs_phy_irq[0], + } else if ((qcom->usb2_speed[i] == USB_SPEED_HIGH) || + (qcom->usb2_speed[i] == USB_SPEED_FULL)) { + dwc3_qcom_enable_wakeup_irq(qcom->dp_hs_phy_irq[i], IRQ_TYPE_EDGE_FALLING); - } else { - dwc3_qcom_enable_wakeup_irq(qcom->dp_hs_phy_irq[0], + } else { + dwc3_qcom_enable_wakeup_irq(qcom->dp_hs_phy_irq[i], IRQ_TYPE_EDGE_RISING); - dwc3_qcom_enable_wakeup_irq(qcom->dm_hs_phy_irq[0], + dwc3_qcom_enable_wakeup_irq(qcom->dm_hs_phy_irq[i], IRQ_TYPE_EDGE_RISING); - } + } - dwc3_qcom_enable_wakeup_irq(qcom->ss_phy_irq[0], 0); + dwc3_qcom_enable_wakeup_irq(qcom->ss_phy_irq[i], 0); + } } static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bool wakeup) @@ -468,10 +476,8 @@ static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bool wakeup) * The role is stable during suspend as role switching is done from a * freezable workqueue. */ - if (dwc3_qcom_is_host(qcom) && wakeup) { - qcom->usb2_speed = dwc3_qcom_read_usb2_speed(qcom); + if (dwc3_qcom_is_host(qcom) && wakeup) dwc3_qcom_enable_interrupts(qcom); - } qcom->is_suspended = true; From patchwork Thu Jul 27 22:33:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Kurapati PSSNV X-Patchwork-Id: 707056 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 074EAC41513 for ; Thu, 27 Jul 2023 22:36:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233046AbjG0WgW (ORCPT ); Thu, 27 Jul 2023 18:36:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49332 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233221AbjG0WgG (ORCPT ); Thu, 27 Jul 2023 18:36:06 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9CB703AAA; Thu, 27 Jul 2023 15:35:37 -0700 (PDT) Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 36RKxKhl007301; Thu, 27 Jul 2023 22:34:33 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=Y0ayW8WEjPSLgxGdaTnQfXuDQNueBAnSTw7btlG1/bE=; b=f7XoOJ984F/yZjY/3lcsFEinXoVxIAeagx5mlzgC3mOvw0J/5PM/smMPzUpveT9yCMMh U1/hknbzZVb7lNEGKFYsW0NT//H9OTCFcmHraYUaHJjXS2UYYslyE0oumvHT7Mf7qSUZ NhF2iPULQJ0Ir7V8rFyyvkZajfwTnPrBJqWMHpPqSEC9oVsL+Gs8OX7JuS8AXMSosIHE YiI6I2b7Ly/C+0WvVabObxXc/PtENMxfROMGi3u2JltsJh10EfIokJn8uFZ/kM6c4Z2S yT8/CARLzqFFVavyGj7FcOM/euc4K/0rHls144FpUiiQt8kwTjoZWknk3PeB6ilZH9CR Og== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3s3k7u259q-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 27 Jul 2023 22:34:32 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 36RMYUfa014087 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 27 Jul 2023 22:34:30 GMT Received: from hu-kriskura-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Thu, 27 Jul 2023 15:34:24 -0700 From: Krishna Kurapati To: Thinh Nguyen , Greg Kroah-Hartman , Philipp Zabel , "Andy Gross" , Bjorn Andersson , "Konrad Dybcio" , Rob Herring , Krzysztof Kozlowski , Felipe Balbi , Wesley Cheng , Johan Hovold , Mathias Nyman CC: , , , , , , , , , Krishna Kurapati Subject: [PATCH v10 11/11] arm64: dts: qcom: sa8540-ride: Enable first port of tertiary usb controller Date: Fri, 28 Jul 2023 04:03:07 +0530 Message-ID: <20230727223307.8096-12-quic_kriskura@quicinc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230727223307.8096-1-quic_kriskura@quicinc.com> References: <20230727223307.8096-1-quic_kriskura@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: jGbX45zOtCufsFRXOvcRX2TmfkElXwVZ X-Proofpoint-ORIG-GUID: jGbX45zOtCufsFRXOvcRX2TmfkElXwVZ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-27_10,2023-07-26_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 spamscore=0 mlxscore=0 lowpriorityscore=0 malwarescore=0 bulkscore=0 mlxlogscore=955 suspectscore=0 priorityscore=1501 clxscore=1015 phishscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2307270205 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Andrew Halaney There is now support for the multiport USB controller this uses so enable it. The board only has a single port hooked up (despite it being wired up to the multiport IP on the SoC). There's also a USB 2.0 mux hooked up, which by default on boot is selected to mux properly. Grab the gpio controlling that and ensure it stays in the right position so USB 2.0 continues to be routed from the external port to the SoC. Co-developed-by: Andrew Halaney Signed-off-by: Andrew Halaney [Krishna: Rebased on top of usb-next] Co-developed-by: Krishna Kurapati Signed-off-by: Krishna Kurapati --- arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts index 5a26974dcf8f..69f6b13e6197 100644 --- a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts @@ -488,6 +488,19 @@ &usb_2_qmpphy0 { status = "okay"; }; +&usb_2 { + pinctrl-0 = <&usb2_en_state>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&usb_2_dwc3 { + dr_mode = "host"; + phy-names = "usb2-port0", "usb3-port0"; + phys = <&usb_2_hsphy0>, <&usb_2_qmpphy0>; +}; + &xo_board_clk { clock-frequency = <38400000>; }; @@ -640,4 +653,13 @@ wake-pins { bias-pull-up; }; }; + + usb2_en_state: usb2-en-state { + /* TS3USB221A USB2.0 mux select */ + pins = "gpio24"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; };