From patchwork Sun Jul 30 00:35:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 708531 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 88136C04A6A for ; Sun, 30 Jul 2023 00:35:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229510AbjG3AfY (ORCPT ); Sat, 29 Jul 2023 20:35:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50814 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229456AbjG3AfX (ORCPT ); Sat, 29 Jul 2023 20:35:23 -0400 Received: from mail-lf1-x131.google.com (mail-lf1-x131.google.com [IPv6:2a00:1450:4864:20::131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3B2181BDD for ; Sat, 29 Jul 2023 17:35:22 -0700 (PDT) Received: by mail-lf1-x131.google.com with SMTP id 2adb3069b0e04-4fe27849e6aso1336073e87.1 for ; Sat, 29 Jul 2023 17:35:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1690677320; x=1691282120; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=B08+U/XiL1/l6dGTvcLD4HwsDFsKFx3gFQfwyphkLoE=; b=IhlpL+2CV3gPonbpS6zYM3Zx6w8mkhwAh4iiUCLpWCYRS3JL13M4/ZNaeyb+Lzdr2h CLG/qSR6ujhVH3BJROEX6QbQ7kDHbrEXSfn2abI+sW2jFN9TwwGo/yOk+mDJDpWKiZ01 4MmoSTELmeG9h/Ahnqtv3iTor3sO0FGyE+QopGxR1/oF87D4D+LMapZs4SOs5lDqGmPH t/GeLH1IoFc/IhcMJ1Qj8LZTfTNJsnFcUeIueQHJCVgMpRWU/d6bHLsnNeOU2JtI1To0 RZaZHpvZ4nz+Jfq8Fetld1r+pbrI81qLCpPGUy6kcw5SLbwTrTlS54Wrj6tVAJxpy3e1 ecoQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690677320; x=1691282120; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=B08+U/XiL1/l6dGTvcLD4HwsDFsKFx3gFQfwyphkLoE=; b=kZoCHGVlNClI1hsEOgSiPdXzsiSs0Zy9xIP3qOjcTzEI15lswrH3JSUE4Slv+Ymj93 VJ1fw+0r5W7K6VNMhFl2vZYAARCxthowPGrS2mwa4N7SHb/rXUiBFpRYmBKYuMhoH/3g pRkBAdAjW98Srebo0Efc3wGffZhnxeSUaKLcHrQvPbZUsqggAtlApWhKj+3LE4CdVnd9 FDKLF8VQqdVoEaAX8gXDw/6AX/auOCZgMJgv4ckhBsEiyL2y0DrgwDK+pXrPJXXM/2f3 wJKMLdgdrIyrFw36pc2t6ol2Kpc8h8Osg6D/0xXJTbJ/OILKB8JLfBi3qXkjE+tsVMpJ vi8A== X-Gm-Message-State: ABy/qLbQmWscrGu7QkfwPBmNKuw0X6okFsfQBo8ZA8TmmLquWG6dCNGW ggP1kxL8fISlmDPLjuBIMcpeeg== X-Google-Smtp-Source: APBJJlGCO6R4FOu45zyNfCfgOEGN3dn4q7ZAFQLIJkdmLEBmM9VEiFjGCaDhmqulLWa3Tgn3QMxANA== X-Received: by 2002:a2e:988b:0:b0:2b6:decf:5cbd with SMTP id b11-20020a2e988b000000b002b6decf5cbdmr3901235ljj.36.1690677320513; Sat, 29 Jul 2023 17:35:20 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id j22-20020a2e8016000000b002b6ffa50896sm1780482ljg.128.2023.07.29.17.35.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 29 Jul 2023 17:35:20 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar , Marijn Suijten Cc: Stephen Boyd , David Airlie , Daniel Vetter , Bjorn Andersson , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH v2 1/8] drm/msm/dpu: inline _setup_pingpong_ops() Date: Sun, 30 Jul 2023 03:35:11 +0300 Message-Id: <20230730003518.349197-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230730003518.349197-1-dmitry.baryshkov@linaro.org> References: <20230730003518.349197-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Inline the _setup_pingpong_ops() function, it makes it easier to handle different conditions involving PINGPONG configuration. Signed-off-by: Dmitry Baryshkov --- .../gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c | 39 ++++++++----------- 1 file changed, 17 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c index 437d9e62a841..9298c166b213 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c @@ -281,27 +281,6 @@ static int dpu_hw_pp_setup_dsc(struct dpu_hw_pingpong *pp) return 0; } -static void _setup_pingpong_ops(struct dpu_hw_pingpong *c, - unsigned long features) -{ - if (test_bit(DPU_PINGPONG_TE, &features)) { - c->ops.enable_tearcheck = dpu_hw_pp_enable_te; - c->ops.disable_tearcheck = dpu_hw_pp_disable_te; - c->ops.connect_external_te = dpu_hw_pp_connect_external_te; - c->ops.get_line_count = dpu_hw_pp_get_line_count; - c->ops.disable_autorefresh = dpu_hw_pp_disable_autorefresh; - } - - if (test_bit(DPU_PINGPONG_DSC, &features)) { - c->ops.setup_dsc = dpu_hw_pp_setup_dsc; - c->ops.enable_dsc = dpu_hw_pp_dsc_enable; - c->ops.disable_dsc = dpu_hw_pp_dsc_disable; - } - - if (test_bit(DPU_PINGPONG_DITHER, &features)) - c->ops.setup_dither = dpu_hw_pp_setup_dither; -}; - struct dpu_hw_pingpong *dpu_hw_pingpong_init(const struct dpu_pingpong_cfg *cfg, void __iomem *addr) { @@ -316,7 +295,23 @@ struct dpu_hw_pingpong *dpu_hw_pingpong_init(const struct dpu_pingpong_cfg *cfg, c->idx = cfg->id; c->caps = cfg; - _setup_pingpong_ops(c, c->caps->features); + + if (test_bit(DPU_PINGPONG_TE, &cfg->features)) { + c->ops.enable_tearcheck = dpu_hw_pp_enable_te; + c->ops.disable_tearcheck = dpu_hw_pp_disable_te; + c->ops.connect_external_te = dpu_hw_pp_connect_external_te; + c->ops.get_line_count = dpu_hw_pp_get_line_count; + c->ops.disable_autorefresh = dpu_hw_pp_disable_autorefresh; + } + + if (test_bit(DPU_PINGPONG_DSC, &cfg->features)) { + c->ops.setup_dsc = dpu_hw_pp_setup_dsc; + c->ops.enable_dsc = dpu_hw_pp_dsc_enable; + c->ops.disable_dsc = dpu_hw_pp_dsc_disable; + } + + if (test_bit(DPU_PINGPONG_DITHER, &cfg->features)) + c->ops.setup_dither = dpu_hw_pp_setup_dither; return c; } From patchwork Sun Jul 30 00:35:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 708330 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 61ACEC00528 for ; Sun, 30 Jul 2023 00:35:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229379AbjG3AfZ (ORCPT ); Sat, 29 Jul 2023 20:35:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50816 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229468AbjG3AfY (ORCPT ); Sat, 29 Jul 2023 20:35:24 -0400 Received: from mail-lj1-x233.google.com (mail-lj1-x233.google.com [IPv6:2a00:1450:4864:20::233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 101002134 for ; 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Rather than checking for the flag, check for the presense of the corresponding interrupt line. Reviewed-by: Marijn Suijten Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c | 6 ++++-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h | 3 ++- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 2 +- 3 files changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c index 9298c166b213..057cac7f5d93 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c @@ -282,7 +282,7 @@ static int dpu_hw_pp_setup_dsc(struct dpu_hw_pingpong *pp) } struct dpu_hw_pingpong *dpu_hw_pingpong_init(const struct dpu_pingpong_cfg *cfg, - void __iomem *addr) + void __iomem *addr, const struct dpu_mdss_version *mdss_rev) { struct dpu_hw_pingpong *c; @@ -296,7 +296,9 @@ struct dpu_hw_pingpong *dpu_hw_pingpong_init(const struct dpu_pingpong_cfg *cfg, c->idx = cfg->id; c->caps = cfg; - if (test_bit(DPU_PINGPONG_TE, &cfg->features)) { + if (mdss_rev->core_major_ver < 5) { + WARN_ON(!cfg->intr_rdptr); + c->ops.enable_tearcheck = dpu_hw_pp_enable_te; c->ops.disable_tearcheck = dpu_hw_pp_disable_te; c->ops.connect_external_te = dpu_hw_pp_connect_external_te; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h index d3246a9a5808..0d541ca5b056 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h @@ -123,10 +123,11 @@ static inline struct dpu_hw_pingpong *to_dpu_hw_pingpong(struct dpu_hw_blk *hw) * pingpong catalog entry. * @cfg: Pingpong catalog entry for which driver object is required * @addr: Mapped register io address of MDP + * @mdss_rev: dpu core's major and minor versions * Return: Error code or allocated dpu_hw_pingpong context */ struct dpu_hw_pingpong *dpu_hw_pingpong_init(const struct dpu_pingpong_cfg *cfg, - void __iomem *addr); + void __iomem *addr, const struct dpu_mdss_version *mdss_rev); /** * dpu_hw_pingpong_destroy - destroys pingpong driver context diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c index 4a53e2c931d6..9894eea77b5f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c @@ -145,7 +145,7 @@ int dpu_rm_init(struct dpu_rm *rm, struct dpu_hw_pingpong *hw; const struct dpu_pingpong_cfg *pp = &cat->pingpong[i]; - hw = dpu_hw_pingpong_init(pp, mmio); + hw = dpu_hw_pingpong_init(pp, mmio, cat->mdss_ver); if (IS_ERR(hw)) { rc = PTR_ERR(hw); DPU_ERROR("failed pingpong object creation: err %d\n", From patchwork Sun Jul 30 00:35:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 708329 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3C200C001DC for ; Sun, 30 Jul 2023 00:35:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229554AbjG3Af1 (ORCPT ); Sat, 29 Jul 2023 20:35:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50826 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229468AbjG3Af0 (ORCPT ); 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Sat, 29 Jul 2023 17:35:21 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar , Marijn Suijten Cc: Stephen Boyd , David Airlie , Daniel Vetter , Bjorn Andersson , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH v2 3/8] drm/msm/dpu: drop the DPU_PINGPONG_TE flag Date: Sun, 30 Jul 2023 03:35:13 +0300 Message-Id: <20230730003518.349197-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230730003518.349197-1-dmitry.baryshkov@linaro.org> References: <20230730003518.349197-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The DPU_PINGPONG_TE flag became unused, we can drop it now. Reviewed-by: Marijn Suijten Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 4 +--- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index 3ff07d7cbf4b..c19dc70d4456 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -79,7 +79,7 @@ (BIT(DPU_DIM_LAYER) | BIT(DPU_MIXER_COMBINED_ALPHA)) #define PINGPONG_SDM845_MASK \ - (BIT(DPU_PINGPONG_DITHER) | BIT(DPU_PINGPONG_TE) | BIT(DPU_PINGPONG_DSC)) + (BIT(DPU_PINGPONG_DITHER) | BIT(DPU_PINGPONG_DSC)) #define PINGPONG_SDM845_TE2_MASK \ (PINGPONG_SDM845_MASK | BIT(DPU_PINGPONG_TE2)) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index 945b88c5ab58..a6f8eee58b92 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -136,7 +136,6 @@ enum { /** * PINGPONG sub-blocks - * @DPU_PINGPONG_TE Tear check block * @DPU_PINGPONG_TE2 Additional tear check block for split pipes * @DPU_PINGPONG_SPLIT PP block supports split fifo * @DPU_PINGPONG_SLAVE PP block is a suitable slave for split fifo @@ -145,8 +144,7 @@ enum { * @DPU_PINGPONG_MAX */ enum { - DPU_PINGPONG_TE = 0x1, - DPU_PINGPONG_TE2, + DPU_PINGPONG_TE2 = 0x1, DPU_PINGPONG_SPLIT, DPU_PINGPONG_SLAVE, DPU_PINGPONG_DITHER, From patchwork Sun Jul 30 00:35:14 2023 Content-Type: text/plain; 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Reviewed-by: Marijn Suijten Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 48 ++++++++++----------- 1 file changed, 22 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c index 8ec6505d9e78..dd67686f5403 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c @@ -524,31 +524,6 @@ static void dpu_hw_intf_program_intf_cmd_cfg(struct dpu_hw_intf *ctx, DPU_REG_WRITE(&ctx->hw, INTF_CONFIG2, intf_cfg2); } -static void _setup_intf_ops(struct dpu_hw_intf_ops *ops, - unsigned long cap, const struct dpu_mdss_version *mdss_rev) -{ - ops->setup_timing_gen = dpu_hw_intf_setup_timing_engine; - ops->setup_prg_fetch = dpu_hw_intf_setup_prg_fetch; - ops->get_status = dpu_hw_intf_get_status; - ops->enable_timing = dpu_hw_intf_enable_timing_engine; - ops->get_line_count = dpu_hw_intf_get_line_count; - if (cap & BIT(DPU_INTF_INPUT_CTRL)) - ops->bind_pingpong_blk = dpu_hw_intf_bind_pingpong_blk; - ops->setup_misr = dpu_hw_intf_setup_misr; - ops->collect_misr = dpu_hw_intf_collect_misr; - - if (cap & BIT(DPU_INTF_TE)) { - ops->enable_tearcheck = dpu_hw_intf_enable_te; - ops->disable_tearcheck = dpu_hw_intf_disable_te; - ops->connect_external_te = dpu_hw_intf_connect_external_te; - ops->vsync_sel = dpu_hw_intf_vsync_sel; - ops->disable_autorefresh = dpu_hw_intf_disable_autorefresh; - } - - if (mdss_rev->core_major_ver >= 7) - ops->program_intf_cmd_cfg = dpu_hw_intf_program_intf_cmd_cfg; -} - struct dpu_hw_intf *dpu_hw_intf_init(const struct dpu_intf_cfg *cfg, void __iomem *addr, const struct dpu_mdss_version *mdss_rev) { @@ -571,7 +546,28 @@ struct dpu_hw_intf *dpu_hw_intf_init(const struct dpu_intf_cfg *cfg, */ c->idx = cfg->id; c->cap = cfg; - _setup_intf_ops(&c->ops, c->cap->features, mdss_rev); + + c->ops.setup_timing_gen = dpu_hw_intf_setup_timing_engine; + c->ops.setup_prg_fetch = dpu_hw_intf_setup_prg_fetch; + c->ops.get_status = dpu_hw_intf_get_status; + c->ops.enable_timing = dpu_hw_intf_enable_timing_engine; + c->ops.get_line_count = dpu_hw_intf_get_line_count; + c->ops.setup_misr = dpu_hw_intf_setup_misr; + c->ops.collect_misr = dpu_hw_intf_collect_misr; + + if (cfg->features & BIT(DPU_INTF_INPUT_CTRL)) + c->ops.bind_pingpong_blk = dpu_hw_intf_bind_pingpong_blk; + + if (cfg->features & BIT(DPU_INTF_TE)) { + c->ops.enable_tearcheck = dpu_hw_intf_enable_te; + c->ops.disable_tearcheck = dpu_hw_intf_disable_te; + c->ops.connect_external_te = dpu_hw_intf_connect_external_te; + c->ops.vsync_sel = dpu_hw_intf_vsync_sel; + c->ops.disable_autorefresh = dpu_hw_intf_disable_autorefresh; + } + + if (mdss_rev->core_major_ver >= 7) + c->ops.program_intf_cmd_cfg = dpu_hw_intf_program_intf_cmd_cfg; return c; } From patchwork Sun Jul 30 00:35:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 708328 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 294E0C04A6A for ; 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Sat, 29 Jul 2023 17:35:24 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id j22-20020a2e8016000000b002b6ffa50896sm1780482ljg.128.2023.07.29.17.35.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 29 Jul 2023 17:35:24 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar , Marijn Suijten Cc: Stephen Boyd , David Airlie , Daniel Vetter , Bjorn Andersson , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH v2 5/8] drm/msm/dpu: enable INTF TE operations only when supported by HW Date: Sun, 30 Jul 2023 03:35:15 +0300 Message-Id: <20230730003518.349197-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230730003518.349197-1-dmitry.baryshkov@linaro.org> References: <20230730003518.349197-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The DPU_INTF_TE bit is set for all INTF blocks on DPU >= 5.0, however only INTF_1 and INTF_2 actually support tearing control (both are INTF_DSI). Rather than trying to limit the DPU_INTF_TE feature bit to those two INTF instances, check for the major && INTF type. Reviewed-by: Marijn Suijten Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c index dd67686f5403..95ff2f5ebbaa 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c @@ -558,7 +558,10 @@ struct dpu_hw_intf *dpu_hw_intf_init(const struct dpu_intf_cfg *cfg, if (cfg->features & BIT(DPU_INTF_INPUT_CTRL)) c->ops.bind_pingpong_blk = dpu_hw_intf_bind_pingpong_blk; - if (cfg->features & BIT(DPU_INTF_TE)) { + /* INTF TE is only for DSI interfaces */ + if (mdss_rev->core_major_ver >= 5 && cfg->type == INTF_DSI) { + WARN_ON(!cfg->intr_tear_rd_ptr); + c->ops.enable_tearcheck = dpu_hw_intf_enable_te; c->ops.disable_tearcheck = dpu_hw_intf_disable_te; c->ops.connect_external_te = dpu_hw_intf_connect_external_te; From patchwork Sun Jul 30 00:35:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 708528 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EDBEFC04FE0 for ; Sun, 30 Jul 2023 00:35:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229613AbjG3Af3 (ORCPT ); Sat, 29 Jul 2023 20:35:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50840 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229493AbjG3Af2 (ORCPT ); Sat, 29 Jul 2023 20:35:28 -0400 Received: from mail-lf1-x134.google.com (mail-lf1-x134.google.com [IPv6:2a00:1450:4864:20::134]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 539B919B5 for ; Sat, 29 Jul 2023 17:35:27 -0700 (PDT) Received: by mail-lf1-x134.google.com with SMTP id 2adb3069b0e04-4fe216edaf7so2176426e87.0 for ; Sat, 29 Jul 2023 17:35:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1690677325; x=1691282125; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Ft+lcYPkOD2X5Cy6eIa14FthuLC+uz/Nzwlggwr4hDE=; b=eenDRTCNw9tcFwjxwb0nO3oaZl3JXWAXLTSSAP0a0pejWlcUfPTDIDtmPv1x796Q97 j/ANf+82FD8Byb/FlsRI9jVig3G0QysbBgz9HqRJb4FtB/iKBb2vF4+z9pJs4ay7owJo xSAtp/MSWfZHNW+RAY1xioTbjDFjEZmiStJinXaWbTtqKlMfsC8k08wXKVYdDWsZnbcO MUpnsjVDSCQvV88N/xZeTZiUKVjbHKG+tW3PEWHlTktlSFalCcUuXt9pVERb5q7bjdAU owoOJ5BQy72ZoYGBSXfOpWekK86TtBR9393TrhNkWznElXQRLZX/jAx6cHNgRKDO04ud LrcQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690677325; x=1691282125; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Ft+lcYPkOD2X5Cy6eIa14FthuLC+uz/Nzwlggwr4hDE=; b=MOBgtZFbeV5TeYOV/n4L7onZEgWufgQnlcVOqS/i6Zzj5t+3SkpHvrIDjPwUIpgHMZ 5fIqMzsRrEtG54Muliyx+FhG3DcvICoitOqL+3qzZp1rHhuzKl0y6BKtxbAeYe8+hEJh b8NKEQnGt21otFtNB0wadOuOAByd1XWe4f3fKQMz7hsY2JC9KwRSD+V/fusg7b+yGVeL 4bF5W7o1CaypUPJVUi1QjhPL9j8lD24dI7TKyXbyxFvw/YK0EqO2X8OMNJ5eG9o3ZfmZ 7Z12/ivuEmSa0cC3kNPTITO+vC2cSLUjH5YhbsDhYPzZfmS3xa+GQFQLMGAR/fYSD0bO /3HQ== X-Gm-Message-State: ABy/qLY9BT/c4MPhsJe5vioDhVO95LY5+CbAlTsB9C07lOW9dpnDkrjn dpgJSX4CuddQ/AHGQNrvGVRVkw== X-Google-Smtp-Source: APBJJlEYfgh+CNI4jN67nxwSyQTAdHekeCgdRvKPdgT3atYqVpm7UWXcS2p7/pBLpXjKZbYt1DfE6g== X-Received: by 2002:a05:6512:1112:b0:4fd:d254:edc6 with SMTP id l18-20020a056512111200b004fdd254edc6mr3258073lfg.26.1690677325620; Sat, 29 Jul 2023 17:35:25 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id j22-20020a2e8016000000b002b6ffa50896sm1780482ljg.128.2023.07.29.17.35.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 29 Jul 2023 17:35:25 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar , Marijn Suijten Cc: Stephen Boyd , David Airlie , Daniel Vetter , Bjorn Andersson , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH v2 6/8] drm/msm/dpu: drop DPU_INTF_TE feature flag Date: Sun, 30 Jul 2023 03:35:16 +0300 Message-Id: <20230730003518.349197-7-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230730003518.349197-1-dmitry.baryshkov@linaro.org> References: <20230730003518.349197-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Replace the only user of the DPU_INTF_TE feature flag with the direct DPU version comparison. Reviewed-by: Marijn Suijten Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 5 +++-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 -- 3 files changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c index 9589fe719452..d1f309f45fa1 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c @@ -776,8 +776,9 @@ struct dpu_encoder_phys *dpu_encoder_phys_cmd_init( phys_enc->intf_mode = INTF_MODE_CMD; cmd_enc->stream_sel = 0; - phys_enc->has_intf_te = test_bit(DPU_INTF_TE, - &phys_enc->hw_intf->cap->features); + /* DPU before 5.0 use PINGPONG for TE handling */ + if (phys_enc->dpu_kms->catalog->mdss_ver->core_major_ver >= 5) + phys_enc->has_intf_te = true; atomic_set(&cmd_enc->pending_vblank_cnt, 0); init_waitqueue_head(&cmd_enc->pending_vblank_wq); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index c19dc70d4456..17426f0f981e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -100,7 +100,6 @@ #define INTF_SC7180_MASK \ (BIT(DPU_INTF_INPUT_CTRL) | \ - BIT(DPU_INTF_TE) | \ BIT(DPU_INTF_STATUS_SUPPORTED) | \ BIT(DPU_DATA_HCTL_EN)) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index a6f8eee58b92..69c9099cf5a6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -175,7 +175,6 @@ enum { * INTF sub-blocks * @DPU_INTF_INPUT_CTRL Supports the setting of pp block from which * pixel data arrives to this INTF - * @DPU_INTF_TE INTF block has TE configuration support * @DPU_DATA_HCTL_EN Allows data to be transferred at different rate * than video timing * @DPU_INTF_STATUS_SUPPORTED INTF block has INTF_STATUS register @@ -183,7 +182,6 @@ enum { */ enum { DPU_INTF_INPUT_CTRL = 0x1, - DPU_INTF_TE, DPU_DATA_HCTL_EN, DPU_INTF_STATUS_SUPPORTED, DPU_INTF_MAX From patchwork Sun Jul 30 00:35:17 2023 Content-Type: text/plain; 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Reviewed-by: Marijn Suijten Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 8 -------- 1 file changed, 8 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c index d1f309f45fa1..012986cff38c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c @@ -108,14 +108,6 @@ static void dpu_encoder_phys_cmd_te_rd_ptr_irq(void *arg) struct dpu_encoder_phys *phys_enc = arg; struct dpu_encoder_phys_cmd *cmd_enc; - if (phys_enc->has_intf_te) { - if (!phys_enc->hw_intf) - return; - } else { - if (!phys_enc->hw_pp) - return; - } - DPU_ATRACE_BEGIN("rd_ptr_irq"); cmd_enc = to_dpu_encoder_phys_cmd(phys_enc); From patchwork Sun Jul 30 00:35:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 708527 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5413EC04E69 for ; Sun, 30 Jul 2023 00:35:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229493AbjG3Afa (ORCPT ); Sat, 29 Jul 2023 20:35:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50868 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229555AbjG3Afa (ORCPT ); Sat, 29 Jul 2023 20:35:30 -0400 Received: from mail-lj1-x229.google.com (mail-lj1-x229.google.com [IPv6:2a00:1450:4864:20::229]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CB99519B5 for ; Sat, 29 Jul 2023 17:35:28 -0700 (PDT) Received: by mail-lj1-x229.google.com with SMTP id 38308e7fff4ca-2b9338e4695so49591301fa.2 for ; Sat, 29 Jul 2023 17:35:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1690677327; x=1691282127; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=SmjGd6hQg5+KzT5ujuzMh2o3ciL+YNI2GkvXWKUqqAs=; b=ZgJVLnAfJAQUM4bSILyTLf+Im47B/dyNmIyjpw4oLc7ObYAql/7HIJvFcc5f5ihTYT i9Ln4Mx04ujT9NUQWmmTbnq2NPgsbno7+kUVJWslgHnU0kk+YrAXB2n6PnOZuPK3iu2q ZM1fOzodAF9BzogVBY/7FuouLzzYKpeMyBwCtX5hVxKNpG+FsQa5igVuW1CPKj96xrSq nZkom/2QU0nJ5vgVrMr3kiQjoD98jU6Gd8i7H2EimBllj+MmF3AKfI1A2lywH24Um7m/ NOsb38b5TXSVTAjkLyiqQxZOIR6rMROneXCiKZLru4YgDJWKPp3cK99x1iyGtdx5BAOl Ifag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690677327; x=1691282127; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SmjGd6hQg5+KzT5ujuzMh2o3ciL+YNI2GkvXWKUqqAs=; b=UG1ZB6cPA2dMSJ0hhHX5FZ3D5QF8kpQFtKtHkG1ENlRjTEZGIqMJRN1snBi5t5r7C/ nfcQXFXPGo4jxBMfUGk4nKRYV0hSWANdnfHXUflsj400QbfKL02BWkpQOqIW27OXCfyJ uYSmG30E3zXWlwVZJNkUZ0LbDPHgQ7mOxSx496ID/wqTzpM6F8Zb+ZoLqeJYIK6GysyO q6RUNHc9HD31aI6oA5qnlabBS/9yafZuH1ZX2vynafjCQBSZQToDEa2h2KHLzxSAS3aW 73VnRcrG4+cnGAzKtESzfOCsIyDxc4E/Mm4OodR9C33UU8BqU59olGEDMEoy3G3R9gdY XV2w== X-Gm-Message-State: ABy/qLaLMkajAnnOi/z87HMRZXZEU/4CMrhsJMei+CxgqaaxhE0oyvT/ KXoZoruVvNzYL7MKkROQ5C0wNg== X-Google-Smtp-Source: APBJJlE/Masgcy12zxqKZTm46aarOd7BSDmEN/SL2Jz+5EdmLFdorC+H60FSJfrmlnBy05dFeOevtg== X-Received: by 2002:a2e:c51:0:b0:2b9:e053:7a01 with SMTP id o17-20020a2e0c51000000b002b9e0537a01mr925423ljd.43.1690677327182; Sat, 29 Jul 2023 17:35:27 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id j22-20020a2e8016000000b002b6ffa50896sm1780482ljg.128.2023.07.29.17.35.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 29 Jul 2023 17:35:26 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar , Marijn Suijten Cc: Stephen Boyd , David Airlie , Daniel Vetter , Bjorn Andersson , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH v2 8/8] drm/msm/dpu: move INTF tearing checks to dpu_encoder_phys_cmd_init Date: Sun, 30 Jul 2023 03:35:18 +0300 Message-Id: <20230730003518.349197-9-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230730003518.349197-1-dmitry.baryshkov@linaro.org> References: <20230730003518.349197-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org As the INTF is fixed at the encoder creation time, we can move the check whether INTF supports tearchck to dpu_encoder_phys_cmd_init(). This function can return an error if INTF doesn't have required feature. Performing this check in dpu_encoder_phys_cmd_tearcheck_config() is less useful, as this function returns void. Signed-off-by: Dmitry Baryshkov --- .../drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 41 +++++++++++-------- 1 file changed, 25 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c index 012986cff38c..adbd559a5290 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c @@ -325,24 +325,21 @@ static void dpu_encoder_phys_cmd_tearcheck_config( unsigned long vsync_hz; struct dpu_kms *dpu_kms; - if (phys_enc->has_intf_te) { - if (!phys_enc->hw_intf || - !phys_enc->hw_intf->ops.enable_tearcheck) { - DPU_DEBUG_CMDENC(cmd_enc, "tearcheck not supported\n"); - return; - } - - DPU_DEBUG_CMDENC(cmd_enc, ""); - } else { - if (!phys_enc->hw_pp || - !phys_enc->hw_pp->ops.enable_tearcheck) { - DPU_DEBUG_CMDENC(cmd_enc, "tearcheck not supported\n"); - return; - } - - DPU_DEBUG_CMDENC(cmd_enc, "pp %d\n", phys_enc->hw_pp->idx - PINGPONG_0); + /* + * TODO: if/when resource allocation is refactored, move this to a + * place where the driver can actually return an error. + */ + if (!phys_enc->has_intf_te && + (!phys_enc->hw_pp || + !phys_enc->hw_pp->ops.enable_tearcheck)) { + DPU_DEBUG_CMDENC(cmd_enc, "tearcheck not supported\n"); + return; } + DPU_DEBUG_CMDENC(cmd_enc, "intf %d pp %d\n", + phys_enc->hw_intf->idx - INTF_0, + phys_enc->hw_pp->idx - PINGPONG_0); + mode = &phys_enc->cached_mode; dpu_kms = phys_enc->dpu_kms; @@ -768,10 +765,22 @@ struct dpu_encoder_phys *dpu_encoder_phys_cmd_init( phys_enc->intf_mode = INTF_MODE_CMD; cmd_enc->stream_sel = 0; + if (!phys_enc->hw_intf) { + DPU_ERROR_CMDENC(cmd_enc, "no INTF provided\n"); + + return ERR_PTR(-EINVAL); + } + /* DPU before 5.0 use PINGPONG for TE handling */ if (phys_enc->dpu_kms->catalog->mdss_ver->core_major_ver >= 5) phys_enc->has_intf_te = true; + if (phys_enc->has_intf_te && !phys_enc->hw_intf->ops.enable_tearcheck) { + DPU_ERROR_CMDENC(cmd_enc, "tearcheck not supported\n"); + + return ERR_PTR(-EINVAL); + } + atomic_set(&cmd_enc->pending_vblank_cnt, 0); init_waitqueue_head(&cmd_enc->pending_vblank_wq);