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a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Camera System (CamSys) incorporates an enhanced feature based image signal processor to connect a variety of image sensor components. This processor consists of timing generated unit (TG), lens/sensor compensation unit and image process unit. For more detail, ask Mediatek for the MT8365 AIoT application processor functional specification. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Alexandre Mergnat --- arch/arm64/boot/dts/mediatek/mt8365.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi index bcabc2b89a94..f9cddce5bd9d 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi @@ -609,6 +609,12 @@ mmsys: syscon@14000000 { reg = <0 0x14000000 0 0x1000>; #clock-cells = <1>; }; + + camsys: syscon@15000000 { + compatible = "mediatek,mt8365-imgsys", "syscon"; + reg = <0 0x15000000 0 0x1000>; + #clock-cells = <1>; + }; }; timer { From patchwork Thu Aug 3 09:40:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Mergnat X-Patchwork-Id: 709741 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 04446C04A6A for ; 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a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org AI Processor Unit System (APUSYS) is a highly efficient computing unit system which is most suitable for AI/CV algorithms. It includes one programmable AI processor (Cadence VP6) for both AI and CV algorithms, and an eDMA engine for data movement between external DRAM and VP6 internal memory. For more detail, ask Mediatek for the MT8365 AIoT application processor functional specification. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Alexandre Mergnat --- arch/arm64/boot/dts/mediatek/mt8365.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi index f9cddce5bd9d..c3ad7cbc89ab 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi @@ -615,6 +615,12 @@ camsys: syscon@15000000 { reg = <0 0x15000000 0 0x1000>; #clock-cells = <1>; }; + + apu: syscon@19020000 { + compatible = "mediatek,mt8365-apu", "syscon"; + reg = <0 0x19020000 0 0x1000>; + #clock-cells = <1>; + }; }; timer { From patchwork Thu Aug 3 09:40:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Mergnat X-Patchwork-Id: 709740 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 65E7AC00528 for ; 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a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Smart Multimedia Interface (SMI) local arbiter does the arbitration for memory requests from multi-media engines. Add SMI in the MT8365 DTS will allow to add local ARBiter (LARB), use by IOMMU. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Alexandre Mergnat --- arch/arm64/boot/dts/mediatek/mt8365.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi index c2f88d153dee..a03b8c0da68b 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi @@ -340,16 +340,19 @@ power-domain@MT8365_POWER_DOMAIN_CAM { "cam-4", "cam-5"; #power-domain-cells = <0>; mediatek,infracfg = <&infracfg>; + mediatek,smi = <&smi_common>; }; power-domain@MT8365_POWER_DOMAIN_VDEC { reg = ; #power-domain-cells = <0>; + mediatek,smi = <&smi_common>; }; power-domain@MT8365_POWER_DOMAIN_VENC { reg = ; #power-domain-cells = <0>; + mediatek,smi = <&smi_common>; }; power-domain@MT8365_POWER_DOMAIN_APU { @@ -367,6 +370,7 @@ power-domain@MT8365_POWER_DOMAIN_APU { "apu-5"; #power-domain-cells = <0>; mediatek,infracfg = <&infracfg>; + mediatek,smi = <&smi_common>; }; }; @@ -720,6 +724,17 @@ mmsys: syscon@14000000 { #clock-cells = <1>; }; + smi_common: smi@14002000 { + compatible = "mediatek,mt8365-smi-common"; + reg = <0 0x14002000 0 0x1000>; + clocks = <&mmsys CLK_MM_MM_SMI_COMMON>, + <&mmsys CLK_MM_MM_SMI_COMMON>, + <&mmsys CLK_MM_MM_SMI_COMM0>, + <&mmsys CLK_MM_MM_SMI_COMM1>; + clock-names = "apb", "smi", "gals0", "gals1"; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + }; + camsys: syscon@15000000 { compatible = "mediatek,mt8365-imgsys", "syscon"; reg = <0 0x15000000 0 0x1000>; From patchwork Thu Aug 3 09:40:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Mergnat X-Patchwork-Id: 709739 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 77F62C00528 for ; Thu, 3 Aug 2023 09:41:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235123AbjHCJlh (ORCPT ); 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Thu, 03 Aug 2023 02:41:12 -0700 (PDT) From: Alexandre Mergnat Date: Thu, 03 Aug 2023 11:40:59 +0200 Subject: [PATCH v4 7/7] arm64: dts: mediatek: add iommu support for mt8365 SoC MIME-Version: 1.0 Message-Id: <20230207-iommu-support-v4-7-84798657c410@baylibre.com> References: <20230207-iommu-support-v4-0-84798657c410@baylibre.com> In-Reply-To: <20230207-iommu-support-v4-0-84798657c410@baylibre.com> To: Yong Wu , Krzysztof Kozlowski , Rob Herring , Matthias Brugger , AngeloGioacchino Del Regno , Krzysztof Kozlowski , Conor Dooley Cc: linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Alexandre Mergnat X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1094; i=amergnat@baylibre.com; h=from:subject:message-id; bh=9vmrSAYQ/OJGejgymOj9rq18l0jyb8olHnhsKnJiPYw=; b=owEBbAKT/ZANAwAKAStGSZ1+MdRFAcsmYgBky3YuJx6x4dzDhkJEC8For4LCR2hLUkAQ+++WgYvK LGwc6IyJAjIEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCZMt2LgAKCRArRkmdfjHURedSD/ i0CM6VH7TYVqNFUOU3Vvvj9lj3yLia/HYD5uuz2nC0zGYQeLx0mOPVnS7DEF8TBRwRXc8PLyiuWeIk faqvsYAXVImDAominB2/0DREyXWQ8YIBcnKzi92enu/y+pwFo/aS4WblRnwc4TzN4cFjFeS4/4O6gW 89KNusCnwqg20iHE/bTxOjaAHz598/azpJ/eawPEydC+Wd7GUudVnkXiIbsQzvYJ83I8UHMXH8kZQi pKg4StMsGHCS3mewVMRZCtmgB2tGmMwo/X87RD77II0ZVIV7I1OI6amUzBSNXB/nJHsMvIEYiapECo bxLrIHWMT2V9KcSxkgdp81B+ZbIRkro1vN2+M6fS5LTJMNAAd5YiIRyTxAWJ4Af5A986e6roNmUN3Y Om8RsQmDHwgKAQoDhsphdgKucuhPDEx897OX0Uk7SNgW/1qlGVM6nyBoi8kDGtyzBJZVACdT9vr01j Ijjc21Jm+h0tOits72Ao7oYZxXIdRL370X3vEn4yGPkTxK0lsei/mlY1DL7tQb1jMfCPSW+WLL1JcY gYvGxfzhdkyGXi2K59ZcwqOSYPg8N8SjTxg2HUgNd8c175WRL9tn9rZrY/c7K2ifAZCfJ2ZyVAB4M0 GNhxXJc3aVW+DycPFeL+AUfJvCrUMNclqlF24ClQJ6VRXjvTy096lXvt8W X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add iommu support in the SoC DTS using the 4 local arbiters (LARBs) Reviewed-by: Yong Wu Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Alexandre Mergnat --- arch/arm64/boot/dts/mediatek/mt8365.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi index afcfa1dd242e..24581f7410aa 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi @@ -471,6 +471,14 @@ sysirq: interrupt-controller@10200a80 { reg = <0 0x10200a80 0 0x20>; }; + iommu: iommu@10205000 { + compatible = "mediatek,mt8365-m4u"; + reg = <0 0x10205000 0 0x1000>; + interrupts = ; + mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, <&larb3>; + #iommu-cells = <1>; + }; + infracfg_nao: infracfg@1020e000 { compatible = "mediatek,mt8365-infracfg", "syscon"; reg = <0 0x1020e000 0 0x1000>;