From patchwork Wed Aug 9 17:39:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Apurva Nandan X-Patchwork-Id: 712215 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 25CBAC41513 for ; Wed, 9 Aug 2023 17:39:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232367AbjHIRj1 (ORCPT ); Wed, 9 Aug 2023 13:39:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33922 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229829AbjHIRj0 (ORCPT ); Wed, 9 Aug 2023 13:39:26 -0400 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 28DF210D8; Wed, 9 Aug 2023 10:39:26 -0700 (PDT) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 379HdGjt115763; Wed, 9 Aug 2023 12:39:16 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1691602756; bh=CdF+/PF0GuX8AeEA9MTivaI6srcXKpUQaw6iQUoPB6k=; h=From:To:Subject:Date:In-Reply-To:References; b=gBoZwkl2fqyLfcCZrTTfTTbh0FkFUWfFsY0akeAjjF0NU/CKtJhZdrSXwD+0WgZml DXd5J1U1o7OuFNqSE+rPlsu1W/gjOFPu69F+fwayP+chDgEPbxsMWiNnlbVtdwrRz0 btfTc6LXywCdO1uyA9reVfoA1oAufRQ8r1rtp2Nk= Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 379HdG9N097137 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 9 Aug 2023 12:39:16 -0500 Received: from DFLE102.ent.ti.com (10.64.6.23) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 9 Aug 2023 12:39:15 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 9 Aug 2023 12:39:15 -0500 Received: from TI.dhcp.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 379Hd6gb077353; Wed, 9 Aug 2023 12:39:11 -0500 From: Apurva Nandan To: Apurva Nandan , Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Rafael J Wysocki , Daniel Lezcano , Amit Kucheria , Zhang Rui , , , , , Udit Kumar , Keerthy J Subject: [PATCH 1/3] thermal: k3_j72xx_bandgap: Add cooling device support Date: Wed, 9 Aug 2023 23:09:03 +0530 Message-ID: <20230809173905.1844132-2-a-nandan@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230809173905.1844132-1-a-nandan@ti.com> References: <20230809173905.1844132-1-a-nandan@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Keerthy Add cpufreq as a cooling device, based on the inputs from the thermal sensors. Signed-off-by: Keerthy Signed-off-by: Apurva Nandan --- drivers/thermal/k3_j72xx_bandgap.c | 121 +++++++++++++++++++++++++++++ 1 file changed, 121 insertions(+) diff --git a/drivers/thermal/k3_j72xx_bandgap.c b/drivers/thermal/k3_j72xx_bandgap.c index a5a0fc9b9356..c844cb527761 100644 --- a/drivers/thermal/k3_j72xx_bandgap.c +++ b/drivers/thermal/k3_j72xx_bandgap.c @@ -19,6 +19,9 @@ #include #include #include +#include +#include +#include #define K3_VTM_DEVINFO_PWR0_OFFSET 0x4 #define K3_VTM_DEVINFO_PWR0_TEMPSENS_CT_MASK 0xf0 @@ -183,10 +186,28 @@ struct k3_j72xx_bandgap { /* common data structures */ struct k3_thermal_data { struct k3_j72xx_bandgap *bgp; + struct cpufreq_policy *policy; + struct thermal_zone_device *ti_thermal; + struct thermal_cooling_device *cool_dev; + struct work_struct thermal_wq; u32 ctrl_offset; u32 stat_offset; + enum thermal_device_mode mode; + int prev_temp; + int sensor_id; }; +static void k3_thermal_work(struct work_struct *work) +{ + struct k3_thermal_data *data = container_of(work, + struct k3_thermal_data, thermal_wq); + + thermal_zone_device_update(data->ti_thermal, THERMAL_EVENT_UNSPECIFIED); + + dev_info(&data->ti_thermal->device, "updated thermal zone %s\n", + data->ti_thermal->type); +} + static int two_cmp(int tmp, int mask) { tmp = ~(tmp); @@ -251,8 +272,40 @@ static int k3_thermal_get_temp(struct thermal_zone_device *tz, int *temp) return k3_bgp_read_temp(thermal_zone_device_priv(tz), temp); } +static int k3_thermal_get_trend(struct thermal_zone_device *tz, int trip, enum thermal_trend *trend) +{ + struct k3_thermal_data *data = tz->devdata; + struct k3_j72xx_bandgap *bgp; + u32 temp1, temp2; + int tr, ret = 0; + + bgp = data->bgp; + + ret = k3_thermal_get_temp(tz, &temp1); + if (ret) + return ret; + temp2 = data->prev_temp; + + tr = temp1 - temp2; + + data->prev_temp = temp1; + + if (tr > 0) + *trend = THERMAL_TREND_RAISING; + else if (tr < 0) + *trend = THERMAL_TREND_DROPPING; + else + *trend = THERMAL_TREND_STABLE; + + dev_dbg(bgp->dev, "The temperatures are t1 = %d and t2 = %d and trend =%d\n", + temp1, temp2, *trend); + + return ret; +} + static const struct thermal_zone_device_ops k3_of_thermal_ops = { .get_temp = k3_thermal_get_temp, + .get_trend = k3_thermal_get_trend, }; static int k3_j72xx_bandgap_temp_to_adc_code(int temp) @@ -342,6 +395,63 @@ struct k3_j72xx_bandgap_data { const bool has_errata_i2128; }; +static int k3_thermal_register_cpu_cooling(struct k3_j72xx_bandgap *bgp, int id) +{ + struct k3_thermal_data *data; + struct device_node *np = bgp->dev->of_node; + + /* + * We are assuming here that if one deploys the zone + * using DT, then it must be aware that the cooling device + * loading has to happen via cpufreq driver. + */ + if (of_find_property(np, "#thermal-sensor-cells", NULL)) + return 0; + + data = bgp->ts_data[id]; + if (!data) + return -EINVAL; + + data->policy = cpufreq_cpu_get(0); + if (!data->policy) { + pr_debug("%s: CPUFreq policy not found\n", __func__); + return -EPROBE_DEFER; + } + + /* Register cooling device */ + data->cool_dev = cpufreq_cooling_register(data->policy); + if (IS_ERR(data->cool_dev)) { + int ret = PTR_ERR(data->cool_dev); + + dev_err(bgp->dev, "Failed to register cpu cooling device %d\n", + ret); + cpufreq_cpu_put(data->policy); + + return ret; + } + + data->mode = THERMAL_DEVICE_ENABLED; + + INIT_WORK(&data->thermal_wq, k3_thermal_work); + + return 0; +} + +static int k3_thermal_unregister_cpu_cooling(struct k3_j72xx_bandgap *bgp, int id) +{ + struct k3_thermal_data *data; + + data = bgp->ts_data[id]; + + if (!IS_ERR_OR_NULL(data)) { + cpufreq_cooling_unregister(data->cool_dev); + if (data->policy) + cpufreq_cpu_put(data->policy); + } + + return 0; +} + static int k3_j72xx_bandgap_probe(struct platform_device *pdev) { int ret = 0, cnt, val, id; @@ -452,6 +562,7 @@ static int k3_j72xx_bandgap_probe(struct platform_device *pdev) /* Register the thermal sensors */ for (id = 0; id < cnt; id++) { data[id].bgp = bgp; + data[id].sensor_id = id; data[id].ctrl_offset = K3_VTM_TMPSENS0_CTRL_OFFSET + id * 0x20; data[id].stat_offset = data[id].ctrl_offset + K3_VTM_TMPSENS_STAT_OFFSET; @@ -477,6 +588,12 @@ static int k3_j72xx_bandgap_probe(struct platform_device *pdev) writel(val, data[id].bgp->cfg2_base + data[id].ctrl_offset); bgp->ts_data[id] = &data[id]; + + if (id == 1) + ret = k3_thermal_register_cpu_cooling(bgp, 1); + if (ret) + goto err_alloc; + ti_thermal = devm_thermal_of_zone_register(bgp->dev, id, &data[id], &k3_of_thermal_ops); if (IS_ERR(ti_thermal)) { @@ -514,6 +631,7 @@ static int k3_j72xx_bandgap_probe(struct platform_device *pdev) return 0; err_free_ref_table: + k3_thermal_unregister_cpu_cooling(bgp, 1); kfree(ref_table); err_alloc: @@ -525,6 +643,9 @@ static int k3_j72xx_bandgap_probe(struct platform_device *pdev) static int k3_j72xx_bandgap_remove(struct platform_device *pdev) { + struct k3_j72xx_bandgap *bgp = platform_get_drvdata(pdev); + + k3_thermal_unregister_cpu_cooling(bgp, 1); pm_runtime_put_sync(&pdev->dev); pm_runtime_disable(&pdev->dev); From patchwork Wed Aug 9 17:39:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Apurva Nandan X-Patchwork-Id: 712214 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 02E87C04A94 for ; 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Wed, 9 Aug 2023 12:39:20 -0500 Received: from DFLE108.ent.ti.com (10.64.6.29) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 9 Aug 2023 12:39:20 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 9 Aug 2023 12:39:20 -0500 Received: from TI.dhcp.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 379Hd6gc077353; Wed, 9 Aug 2023 12:39:15 -0500 From: Apurva Nandan To: Apurva Nandan , Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Rafael J Wysocki , Daniel Lezcano , Amit Kucheria , Zhang Rui , , , , , Udit Kumar , Keerthy J Subject: [PATCH 2/3] arm64: dts: ti: k3-j7200: Add the supported frequencies for A72 Date: Wed, 9 Aug 2023 23:09:04 +0530 Message-ID: <20230809173905.1844132-3-a-nandan@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230809173905.1844132-1-a-nandan@ti.com> References: <20230809173905.1844132-1-a-nandan@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Keerthy Add 750M, 1G, 1.5G & 2G as the supported frequencies for A72. This enables support for Dynamic Frequency Scaling(DFS) Signed-off-by: Keerthy Signed-off-by: Apurva Nandan --- arch/arm64/boot/dts/ti/k3-j7200.dtsi | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200.dtsi b/arch/arm64/boot/dts/ti/k3-j7200.dtsi index ef73e6d7e858..7222c453096f 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200.dtsi @@ -48,6 +48,10 @@ cpu0: cpu@0 { d-cache-line-size = <64>; d-cache-sets = <256>; next-level-cache = <&L2_0>; + clocks = <&k3_clks 202 2>; + clock-names = "cpu"; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; /* min followed by max */ }; cpu1: cpu@1 { @@ -62,6 +66,30 @@ cpu1: cpu@1 { d-cache-line-size = <64>; d-cache-sets = <256>; next-level-cache = <&L2_0>; + clocks = <&k3_clks 203 0>; + clock-names = "cpu"; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + }; + }; + + cpu0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp4-2000000000 { + opp-hz = /bits/ 64 <2000000000>; + }; + + opp3-1500000000 { + opp-hz = /bits/ 64 <1500000000>; + }; + + opp2-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + }; + + opp1-750000000 { + opp-hz = /bits/ 64 <750000000>; }; }; From patchwork Wed Aug 9 17:39:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Apurva Nandan X-Patchwork-Id: 712515 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EA6FAC41513 for ; Wed, 9 Aug 2023 17:39:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233004AbjHIRjm (ORCPT ); Wed, 9 Aug 2023 13:39:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59478 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232762AbjHIRjg (ORCPT ); Wed, 9 Aug 2023 13:39:36 -0400 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0E7D610DE; Wed, 9 Aug 2023 10:39:35 -0700 (PDT) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 379HdP6o044737; Wed, 9 Aug 2023 12:39:25 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1691602765; bh=bPJNJeQUgy0aF+J1sZlxi9L3YvHWdEofe+SYa/mf4fk=; h=From:To:Subject:Date:In-Reply-To:References; b=pdzmApGr09OPwlRMQLcIl9ulvvIu8/BxJ0MF0yZ7rLMKHF8YUM4i/7c9e0w7X+iN2 VkZUtLFwSUqxsOKjnWgP8nz0QXWsKEjloB791GjECYHPdpOQ8P+jEpvyEOBczPHIx2 r9Ul9nR0XiBrir7Bl0XUjolwyRIAWVwC5dtcOkxc= Received: from DLEE107.ent.ti.com (dlee107.ent.ti.com [157.170.170.37]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 379HdPAB097175 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 9 Aug 2023 12:39:25 -0500 Received: from DLEE107.ent.ti.com (157.170.170.37) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 9 Aug 2023 12:39:24 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 9 Aug 2023 12:39:24 -0500 Received: from TI.dhcp.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 379Hd6gd077353; Wed, 9 Aug 2023 12:39:20 -0500 From: Apurva Nandan To: Apurva Nandan , Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Rafael J Wysocki , Daniel Lezcano , Amit Kucheria , Zhang Rui , , , , , Udit Kumar , Keerthy J Subject: [PATCH 3/3] arm64: dts: ti: k3-j7200-thermal: Add cooling maps and cpu_alert trip at 75C Date: Wed, 9 Aug 2023 23:09:05 +0530 Message-ID: <20230809173905.1844132-4-a-nandan@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230809173905.1844132-1-a-nandan@ti.com> References: <20230809173905.1844132-1-a-nandan@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Keerthy Add cooling maps and mpu_alert trip at 75C Note: mpu_alert trip value should adjusted based on the system load and performance needs. Signed-off-by: Keerthy Signed-off-by: Apurva Nandan --- arch/arm64/boot/dts/ti/k3-j7200-thermal.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-thermal.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-thermal.dtsi index e7e3a643a6f0..eeb596727d48 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-thermal.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-thermal.dtsi @@ -28,6 +28,20 @@ mpu_crit: mpu-crit { hysteresis = <2000>; /* milliCelsius */ type = "critical"; }; + + mpu_alert0: mpu_alert { + temperature = <75000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "passive"; + }; + }; + + cpu_cooling_maps: cooling-maps { + map0 { + trip = <&mpu_alert0>; + cooling-device = + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; }; };