From patchwork Thu Aug 10 08:29:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yang Yingliang X-Patchwork-Id: 712577 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9B7B1C001DB for ; Thu, 10 Aug 2023 08:33:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233728AbjHJIdI (ORCPT ); Thu, 10 Aug 2023 04:33:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41576 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234202AbjHJIdI (ORCPT ); Thu, 10 Aug 2023 04:33:08 -0400 Received: from szxga01-in.huawei.com (szxga01-in.huawei.com [45.249.212.187]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8AF87E56 for ; Thu, 10 Aug 2023 01:33:07 -0700 (PDT) Received: from dggpemm100005.china.huawei.com (unknown [172.30.72.57]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4RM0TW0t5mztSGG; Thu, 10 Aug 2023 16:29:35 +0800 (CST) Received: from dggpemm500007.china.huawei.com (7.185.36.183) by dggpemm100005.china.huawei.com (7.185.36.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 10 Aug 2023 16:33:05 +0800 Received: from huawei.com (10.175.103.91) by dggpemm500007.china.huawei.com (7.185.36.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 10 Aug 2023 16:33:04 +0800 From: Yang Yingliang To: CC: , , , Subject: [PATCH -next 01/21] spi: lm70llp: switch to use modern name Date: Thu, 10 Aug 2023 16:29:44 +0800 Message-ID: <20230810083004.3988597-2-yangyingliang@huawei.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230810083004.3988597-1-yangyingliang@huawei.com> References: <20230810083004.3988597-1-yangyingliang@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.175.103.91] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To dggpemm500007.china.huawei.com (7.185.36.183) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Change legacy name master to modern name host or controller. No functional changed. Signed-off-by: Yang Yingliang --- drivers/spi/spi-lm70llp.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/spi/spi-lm70llp.c b/drivers/spi/spi-lm70llp.c index ead0507c63be..e6a65b5c8c31 100644 --- a/drivers/spi/spi-lm70llp.c +++ b/drivers/spi/spi-lm70llp.c @@ -24,7 +24,7 @@ * the SPI/Microwire bus interface. This driver specifically supports an * NS LM70 LLP Evaluation Board, interfacing to a PC using its parallel * port to bitbang an SPI-parport bridge. Accordingly, this is an SPI - * master controller driver. The hwmon/lm70 driver is a "SPI protocol + * host controller driver. The hwmon/lm70 driver is a "SPI protocol * driver", layered on top of this one and usable without the lm70llp. * * Datasheet and Schematic: @@ -189,7 +189,7 @@ static void spi_lm70llp_attach(struct parport *p) { struct pardevice *pd; struct spi_lm70llp *pp; - struct spi_master *master; + struct spi_controller *host; int status; struct pardev_cb lm70llp_cb; @@ -202,17 +202,17 @@ static void spi_lm70llp_attach(struct parport *p) * the lm70 driver could verify it, reading the manf ID. */ - master = spi_alloc_master(p->physport->dev, sizeof(*pp)); - if (!master) { + host = spi_alloc_host(p->physport->dev, sizeof(*pp)); + if (!host) { status = -ENOMEM; goto out_fail; } - pp = spi_master_get_devdata(master); + pp = spi_controller_get_devdata(host); /* * SPI and bitbang hookup. */ - pp->bitbang.master = master; + pp->bitbang.master = host; pp->bitbang.chipselect = lm70_chipselect; pp->bitbang.txrx_word[SPI_MODE_0] = lm70_txrx; pp->bitbang.flags = SPI_3WIRE; @@ -228,7 +228,7 @@ static void spi_lm70llp_attach(struct parport *p) if (!pd) { status = -ENOMEM; - goto out_free_master; + goto out_free_host; } pp->pd = pd; @@ -287,8 +287,8 @@ static void spi_lm70llp_attach(struct parport *p) parport_release(pp->pd); out_parport_unreg: parport_unregister_device(pd); -out_free_master: - spi_master_put(master); +out_free_host: + spi_controller_put(host); out_fail: pr_info("spi_lm70llp probe fail, status %d\n", status); } @@ -309,7 +309,7 @@ static void spi_lm70llp_detach(struct parport *p) parport_release(pp->pd); parport_unregister_device(pp->pd); - spi_master_put(pp->bitbang.master); + spi_controller_put(pp->bitbang.master); lm70llp = NULL; } From patchwork Thu Aug 10 08:29:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yang Yingliang X-Patchwork-Id: 712568 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B4E73C07E8A for ; Thu, 10 Aug 2023 08:33:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234229AbjHJIdR (ORCPT ); Thu, 10 Aug 2023 04:33:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34902 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234231AbjHJIdQ (ORCPT ); Thu, 10 Aug 2023 04:33:16 -0400 Received: from szxga03-in.huawei.com (szxga03-in.huawei.com [45.249.212.189]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 405C4E64 for ; Thu, 10 Aug 2023 01:33:15 -0700 (PDT) Received: from dggpemm100003.china.huawei.com (unknown [172.30.72.54]) by szxga03-in.huawei.com (SkyGuard) with ESMTP id 4RM0VQ3hBJzqSrC; Thu, 10 Aug 2023 16:30:22 +0800 (CST) Received: from dggpemm500007.china.huawei.com (7.185.36.183) by dggpemm100003.china.huawei.com (7.185.36.68) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 10 Aug 2023 16:33:05 +0800 Received: from huawei.com (10.175.103.91) by dggpemm500007.china.huawei.com (7.185.36.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 10 Aug 2023 16:33:05 +0800 From: Yang Yingliang To: CC: , , , Subject: [PATCH -next 02/21] spi: lp-8841: switch to use modern name Date: Thu, 10 Aug 2023 16:29:45 +0800 Message-ID: <20230810083004.3988597-3-yangyingliang@huawei.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230810083004.3988597-1-yangyingliang@huawei.com> References: <20230810083004.3988597-1-yangyingliang@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.175.103.91] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To dggpemm500007.china.huawei.com (7.185.36.183) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Change legacy name master/slave to modern name host/target or controller. No functional changed. Signed-off-by: Yang Yingliang --- drivers/spi/spi-lp8841-rtc.c | 56 ++++++++++++++++++------------------ 1 file changed, 28 insertions(+), 28 deletions(-) diff --git a/drivers/spi/spi-lp8841-rtc.c b/drivers/spi/spi-lp8841-rtc.c index b357461f1b8b..382e2a69f7a7 100644 --- a/drivers/spi/spi-lp8841-rtc.c +++ b/drivers/spi/spi-lp8841-rtc.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-or-later /* - * SPI master driver for ICP DAS LP-8841 RTC + * SPI host driver for ICP DAS LP-8841 RTC * * Copyright (C) 2016 Sergei Ianovich * @@ -73,13 +73,13 @@ bitbang_txrx_be_cpha0_lsb(struct spi_lp8841_rtc *data, /* clock starts at inactive polarity */ for (; likely(bits); bits--) { - /* setup LSB (to slave) on leading edge */ + /* setup LSB (to target) on leading edge */ if ((flags & SPI_CONTROLLER_NO_TX) == 0) setmosi(data, (word & 1)); usleep_range(usecs, usecs + 1); /* T(setup) */ - /* sample LSB (from slave) on trailing edge */ + /* sample LSB (from target) on trailing edge */ word >>= 1; if ((flags & SPI_CONTROLLER_NO_RX) == 0) word |= (getmiso(data) << 31); @@ -95,11 +95,11 @@ bitbang_txrx_be_cpha0_lsb(struct spi_lp8841_rtc *data, } static int -spi_lp8841_rtc_transfer_one(struct spi_master *master, +spi_lp8841_rtc_transfer_one(struct spi_controller *host, struct spi_device *spi, struct spi_transfer *t) { - struct spi_lp8841_rtc *data = spi_master_get_devdata(master); + struct spi_lp8841_rtc *data = spi_controller_get_devdata(host); unsigned count = t->len; const u8 *tx = t->tx_buf; u8 *rx = t->rx_buf; @@ -128,7 +128,7 @@ spi_lp8841_rtc_transfer_one(struct spi_master *master, ret = -EINVAL; } - spi_finalize_current_transfer(master); + spi_finalize_current_transfer(host); return ret; } @@ -136,7 +136,7 @@ spi_lp8841_rtc_transfer_one(struct spi_master *master, static void spi_lp8841_rtc_set_cs(struct spi_device *spi, bool enable) { - struct spi_lp8841_rtc *data = spi_master_get_devdata(spi->master); + struct spi_lp8841_rtc *data = spi_controller_get_devdata(spi->controller); data->state = 0; writeb(data->state, data->iomem); @@ -182,48 +182,48 @@ static int spi_lp8841_rtc_probe(struct platform_device *pdev) { int ret; - struct spi_master *master; + struct spi_controller *host; struct spi_lp8841_rtc *data; - master = spi_alloc_master(&pdev->dev, sizeof(*data)); - if (!master) + host = spi_alloc_host(&pdev->dev, sizeof(*data)); + if (!host) return -ENOMEM; - platform_set_drvdata(pdev, master); + platform_set_drvdata(pdev, host); - master->flags = SPI_CONTROLLER_HALF_DUPLEX; - master->mode_bits = SPI_CS_HIGH | SPI_3WIRE | SPI_LSB_FIRST; + host->flags = SPI_CONTROLLER_HALF_DUPLEX; + host->mode_bits = SPI_CS_HIGH | SPI_3WIRE | SPI_LSB_FIRST; - master->bus_num = pdev->id; - master->num_chipselect = 1; - master->setup = spi_lp8841_rtc_setup; - master->set_cs = spi_lp8841_rtc_set_cs; - master->transfer_one = spi_lp8841_rtc_transfer_one; - master->bits_per_word_mask = SPI_BPW_MASK(8); + host->bus_num = pdev->id; + host->num_chipselect = 1; + host->setup = spi_lp8841_rtc_setup; + host->set_cs = spi_lp8841_rtc_set_cs; + host->transfer_one = spi_lp8841_rtc_transfer_one; + host->bits_per_word_mask = SPI_BPW_MASK(8); #ifdef CONFIG_OF - master->dev.of_node = pdev->dev.of_node; + host->dev.of_node = pdev->dev.of_node; #endif - data = spi_master_get_devdata(master); + data = spi_controller_get_devdata(host); data->iomem = devm_platform_ioremap_resource(pdev, 0); ret = PTR_ERR_OR_ZERO(data->iomem); if (ret) { dev_err(&pdev->dev, "failed to get IO address\n"); - goto err_put_master; + goto err_put_host; } /* register with the SPI framework */ - ret = devm_spi_register_master(&pdev->dev, master); + ret = devm_spi_register_controller(&pdev->dev, host); if (ret) { - dev_err(&pdev->dev, "cannot register spi master\n"); - goto err_put_master; + dev_err(&pdev->dev, "cannot register spi host\n"); + goto err_put_host; } return ret; -err_put_master: - spi_master_put(master); +err_put_host: + spi_controller_put(host); return ret; } @@ -239,6 +239,6 @@ static struct platform_driver spi_lp8841_rtc_driver = { }; module_platform_driver(spi_lp8841_rtc_driver); -MODULE_DESCRIPTION("SPI master driver for ICP DAS LP-8841 RTC"); +MODULE_DESCRIPTION("SPI host driver for ICP DAS LP-8841 RTC"); MODULE_AUTHOR("Sergei Ianovich"); MODULE_LICENSE("GPL"); From patchwork Thu Aug 10 08:29:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yang Yingliang X-Patchwork-Id: 712576 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A1BF0C04FDF for ; Thu, 10 Aug 2023 08:33:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233216AbjHJIdL (ORCPT ); Thu, 10 Aug 2023 04:33:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34732 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234202AbjHJIdK (ORCPT ); Thu, 10 Aug 2023 04:33:10 -0400 Received: from szxga01-in.huawei.com (szxga01-in.huawei.com [45.249.212.187]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AD501E40 for ; Thu, 10 Aug 2023 01:33:08 -0700 (PDT) Received: from dggpemm100004.china.huawei.com (unknown [172.30.72.53]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4RM0TW6c7VztSFH; Thu, 10 Aug 2023 16:29:35 +0800 (CST) Received: from dggpemm500007.china.huawei.com (7.185.36.183) by dggpemm100004.china.huawei.com (7.185.36.189) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 10 Aug 2023 16:33:06 +0800 Received: from huawei.com (10.175.103.91) by dggpemm500007.china.huawei.com (7.185.36.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 10 Aug 2023 16:33:05 +0800 From: Yang Yingliang To: CC: , , , Subject: [PATCH -next 03/21] spi: meson-spicc: switch to use modern name Date: Thu, 10 Aug 2023 16:29:46 +0800 Message-ID: <20230810083004.3988597-4-yangyingliang@huawei.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230810083004.3988597-1-yangyingliang@huawei.com> References: <20230810083004.3988597-1-yangyingliang@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.175.103.91] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To dggpemm500007.china.huawei.com (7.185.36.183) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Change legacy name master to modern name host or controller. No functional changed. Signed-off-by: Yang Yingliang --- drivers/spi/spi-meson-spicc.c | 106 +++++++++++++++++----------------- 1 file changed, 53 insertions(+), 53 deletions(-) diff --git a/drivers/spi/spi-meson-spicc.c b/drivers/spi/spi-meson-spicc.c index 43d134f4b42b..d0790d2ef1b5 100644 --- a/drivers/spi/spi-meson-spicc.c +++ b/drivers/spi/spi-meson-spicc.c @@ -44,7 +44,7 @@ #define SPICC_CONREG 0x08 #define SPICC_ENABLE BIT(0) -#define SPICC_MODE_MASTER BIT(1) +#define SPICC_MODE_HOST BIT(1) #define SPICC_XCH BIT(2) #define SPICC_SMC BIT(3) #define SPICC_POL BIT(4) @@ -106,17 +106,17 @@ #define SPICC_SWAP_RO BIT(14) /* RX FIFO Data Swap Read-Only */ #define SPICC_SWAP_W1 BIT(15) /* RX FIFO Data Swap Write-Only */ #define SPICC_DLYCTL_RO_MASK GENMASK(20, 15) /* Delay Control Read-Only */ -#define SPICC_MO_DELAY_MASK GENMASK(17, 16) /* Master Output Delay */ +#define SPICC_MO_DELAY_MASK GENMASK(17, 16) /* Host Output Delay */ #define SPICC_MO_NO_DELAY 0 #define SPICC_MO_DELAY_1_CYCLE 1 #define SPICC_MO_DELAY_2_CYCLE 2 #define SPICC_MO_DELAY_3_CYCLE 3 -#define SPICC_MI_DELAY_MASK GENMASK(19, 18) /* Master Input Delay */ +#define SPICC_MI_DELAY_MASK GENMASK(19, 18) /* Host Input Delay */ #define SPICC_MI_NO_DELAY 0 #define SPICC_MI_DELAY_1_CYCLE 1 #define SPICC_MI_DELAY_2_CYCLE 2 #define SPICC_MI_DELAY_3_CYCLE 3 -#define SPICC_MI_CAP_DELAY_MASK GENMASK(21, 20) /* Master Capture Delay */ +#define SPICC_MI_CAP_DELAY_MASK GENMASK(21, 20) /* Host Capture Delay */ #define SPICC_CAP_AHEAD_2_CYCLE 0 #define SPICC_CAP_AHEAD_1_CYCLE 1 #define SPICC_CAP_NO_DELAY 2 @@ -151,7 +151,7 @@ struct meson_spicc_data { }; struct meson_spicc_device { - struct spi_master *master; + struct spi_controller *host; struct platform_device *pdev; void __iomem *base; struct clk *core; @@ -399,11 +399,11 @@ static void meson_spicc_reset_fifo(struct meson_spicc_device *spicc) spicc->base + SPICC_ENH_CTL0); } -static int meson_spicc_transfer_one(struct spi_master *master, +static int meson_spicc_transfer_one(struct spi_controller *host, struct spi_device *spi, struct spi_transfer *xfer) { - struct meson_spicc_device *spicc = spi_master_get_devdata(master); + struct meson_spicc_device *spicc = spi_controller_get_devdata(host); uint64_t timeout; /* Store current transfer */ @@ -454,19 +454,19 @@ static int meson_spicc_transfer_one(struct spi_master *master, return 0; } -static int meson_spicc_prepare_message(struct spi_master *master, +static int meson_spicc_prepare_message(struct spi_controller *host, struct spi_message *message) { - struct meson_spicc_device *spicc = spi_master_get_devdata(master); + struct meson_spicc_device *spicc = spi_controller_get_devdata(host); struct spi_device *spi = message->spi; u32 conf = readl_relaxed(spicc->base + SPICC_CONREG) & SPICC_DATARATE_MASK; /* Store current message */ spicc->message = message; - /* Enable Master */ + /* Enable Host */ conf |= SPICC_ENABLE; - conf |= SPICC_MODE_MASTER; + conf |= SPICC_MODE_HOST; /* SMC = 0 */ @@ -519,9 +519,9 @@ static int meson_spicc_prepare_message(struct spi_master *master, return 0; } -static int meson_spicc_unprepare_transfer(struct spi_master *master) +static int meson_spicc_unprepare_transfer(struct spi_controller *host) { - struct meson_spicc_device *spicc = spi_master_get_devdata(master); + struct meson_spicc_device *spicc = spi_controller_get_devdata(host); u32 conf = readl_relaxed(spicc->base + SPICC_CONREG) & SPICC_DATARATE_MASK; /* Disable all IRQs */ @@ -541,7 +541,7 @@ static int meson_spicc_unprepare_transfer(struct spi_master *master) static int meson_spicc_setup(struct spi_device *spi) { if (!spi->controller_state) - spi->controller_state = spi_master_get_devdata(spi->master); + spi->controller_state = spi_controller_get_devdata(spi->controller); return 0; } @@ -585,7 +585,7 @@ static unsigned long meson_spicc_pow2_recalc_rate(struct clk_hw *hw, struct clk_divider *divider = to_clk_divider(hw); struct meson_spicc_device *spicc = pow2_clk_to_spicc(divider); - if (!spicc->master->cur_msg) + if (!spicc->host->cur_msg) return 0; return clk_divider_ops.recalc_rate(hw, parent_rate); @@ -597,7 +597,7 @@ static int meson_spicc_pow2_determine_rate(struct clk_hw *hw, struct clk_divider *divider = to_clk_divider(hw); struct meson_spicc_device *spicc = pow2_clk_to_spicc(divider); - if (!spicc->master->cur_msg) + if (!spicc->host->cur_msg) return -EINVAL; return clk_divider_ops.determine_rate(hw, req); @@ -609,7 +609,7 @@ static int meson_spicc_pow2_set_rate(struct clk_hw *hw, unsigned long rate, struct clk_divider *divider = to_clk_divider(hw); struct meson_spicc_device *spicc = pow2_clk_to_spicc(divider); - if (!spicc->master->cur_msg) + if (!spicc->host->cur_msg) return -EINVAL; return clk_divider_ops.set_rate(hw, rate, parent_rate); @@ -769,23 +769,23 @@ static int meson_spicc_enh_clk_init(struct meson_spicc_device *spicc) static int meson_spicc_probe(struct platform_device *pdev) { - struct spi_master *master; + struct spi_controller *host; struct meson_spicc_device *spicc; int ret, irq; - master = spi_alloc_master(&pdev->dev, sizeof(*spicc)); - if (!master) { - dev_err(&pdev->dev, "master allocation failed\n"); + host = spi_alloc_host(&pdev->dev, sizeof(*spicc)); + if (!host) { + dev_err(&pdev->dev, "host allocation failed\n"); return -ENOMEM; } - spicc = spi_master_get_devdata(master); - spicc->master = master; + spicc = spi_controller_get_devdata(host); + spicc->host = host; spicc->data = of_device_get_match_data(&pdev->dev); if (!spicc->data) { dev_err(&pdev->dev, "failed to get match data\n"); ret = -EINVAL; - goto out_master; + goto out_host; } spicc->pdev = pdev; @@ -797,11 +797,11 @@ static int meson_spicc_probe(struct platform_device *pdev) if (IS_ERR(spicc->base)) { dev_err(&pdev->dev, "io resource mapping failed\n"); ret = PTR_ERR(spicc->base); - goto out_master; + goto out_host; } - /* Set master mode and enable controller */ - writel_relaxed(SPICC_ENABLE | SPICC_MODE_MASTER, + /* Set host mode and enable controller */ + writel_relaxed(SPICC_ENABLE | SPICC_MODE_HOST, spicc->base + SPICC_CONREG); /* Disable all IRQs */ @@ -810,21 +810,21 @@ static int meson_spicc_probe(struct platform_device *pdev) irq = platform_get_irq(pdev, 0); if (irq < 0) { ret = irq; - goto out_master; + goto out_host; } ret = devm_request_irq(&pdev->dev, irq, meson_spicc_irq, 0, NULL, spicc); if (ret) { dev_err(&pdev->dev, "irq request failed\n"); - goto out_master; + goto out_host; } spicc->core = devm_clk_get(&pdev->dev, "core"); if (IS_ERR(spicc->core)) { dev_err(&pdev->dev, "core clock request failed\n"); ret = PTR_ERR(spicc->core); - goto out_master; + goto out_host; } if (spicc->data->has_pclk) { @@ -832,14 +832,14 @@ static int meson_spicc_probe(struct platform_device *pdev) if (IS_ERR(spicc->pclk)) { dev_err(&pdev->dev, "pclk clock request failed\n"); ret = PTR_ERR(spicc->pclk); - goto out_master; + goto out_host; } } ret = clk_prepare_enable(spicc->core); if (ret) { dev_err(&pdev->dev, "core clock enable failed\n"); - goto out_master; + goto out_host; } ret = clk_prepare_enable(spicc->pclk); @@ -856,22 +856,22 @@ static int meson_spicc_probe(struct platform_device *pdev) device_reset_optional(&pdev->dev); - master->num_chipselect = 4; - master->dev.of_node = pdev->dev.of_node; - master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH; - master->bits_per_word_mask = SPI_BPW_MASK(32) | - SPI_BPW_MASK(24) | - SPI_BPW_MASK(16) | - SPI_BPW_MASK(8); - master->flags = (SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX); - master->min_speed_hz = spicc->data->min_speed_hz; - master->max_speed_hz = spicc->data->max_speed_hz; - master->setup = meson_spicc_setup; - master->cleanup = meson_spicc_cleanup; - master->prepare_message = meson_spicc_prepare_message; - master->unprepare_transfer_hardware = meson_spicc_unprepare_transfer; - master->transfer_one = meson_spicc_transfer_one; - master->use_gpio_descriptors = true; + host->num_chipselect = 4; + host->dev.of_node = pdev->dev.of_node; + host->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH; + host->bits_per_word_mask = SPI_BPW_MASK(32) | + SPI_BPW_MASK(24) | + SPI_BPW_MASK(16) | + SPI_BPW_MASK(8); + host->flags = (SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX); + host->min_speed_hz = spicc->data->min_speed_hz; + host->max_speed_hz = spicc->data->max_speed_hz; + host->setup = meson_spicc_setup; + host->cleanup = meson_spicc_cleanup; + host->prepare_message = meson_spicc_prepare_message; + host->unprepare_transfer_hardware = meson_spicc_unprepare_transfer; + host->transfer_one = meson_spicc_transfer_one; + host->use_gpio_descriptors = true; meson_spicc_oen_enable(spicc); @@ -889,9 +889,9 @@ static int meson_spicc_probe(struct platform_device *pdev) } } - ret = devm_spi_register_master(&pdev->dev, master); + ret = devm_spi_register_controller(&pdev->dev, host); if (ret) { - dev_err(&pdev->dev, "spi master registration failed\n"); + dev_err(&pdev->dev, "spi host registration failed\n"); goto out_clk; } @@ -903,8 +903,8 @@ static int meson_spicc_probe(struct platform_device *pdev) out_core_clk: clk_disable_unprepare(spicc->core); -out_master: - spi_master_put(master); +out_host: + spi_controller_put(host); return ret; } @@ -919,7 +919,7 @@ static void meson_spicc_remove(struct platform_device *pdev) clk_disable_unprepare(spicc->core); clk_disable_unprepare(spicc->pclk); - spi_master_put(spicc->master); + spi_controller_put(spicc->host); } static const struct meson_spicc_data meson_spicc_gx_data = { From patchwork Thu Aug 10 08:29:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yang Yingliang X-Patchwork-Id: 713168 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 14BA6C04E69 for ; Thu, 10 Aug 2023 08:33:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234205AbjHJIdK (ORCPT ); Thu, 10 Aug 2023 04:33:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41598 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233216AbjHJIdJ (ORCPT ); Thu, 10 Aug 2023 04:33:09 -0400 Received: from szxga08-in.huawei.com (szxga08-in.huawei.com [45.249.212.255]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 49E53ED for ; Thu, 10 Aug 2023 01:33:08 -0700 (PDT) Received: from dggpemm100001.china.huawei.com (unknown [172.30.72.56]) by szxga08-in.huawei.com (SkyGuard) with ESMTP id 4RM0XB1mnYz1L9kG; Thu, 10 Aug 2023 16:31:54 +0800 (CST) Received: from dggpemm500007.china.huawei.com (7.185.36.183) by dggpemm100001.china.huawei.com (7.185.36.93) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 10 Aug 2023 16:33:06 +0800 Received: from huawei.com (10.175.103.91) by dggpemm500007.china.huawei.com (7.185.36.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 10 Aug 2023 16:33:05 +0800 From: Yang Yingliang To: CC: , , , Subject: [PATCH -next 04/21] spi: meson-spifc: switch to use modern name Date: Thu, 10 Aug 2023 16:29:47 +0800 Message-ID: <20230810083004.3988597-5-yangyingliang@huawei.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230810083004.3988597-1-yangyingliang@huawei.com> References: <20230810083004.3988597-1-yangyingliang@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.175.103.91] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To dggpemm500007.china.huawei.com (7.185.36.183) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Change legacy name master/slave to modern name host/target or controller. No functional changed. Signed-off-by: Yang Yingliang --- drivers/spi/spi-meson-spifc.c | 94 +++++++++++++++++------------------ 1 file changed, 47 insertions(+), 47 deletions(-) diff --git a/drivers/spi/spi-meson-spifc.c b/drivers/spi/spi-meson-spifc.c index 06626f406f68..ec571856be1e 100644 --- a/drivers/spi/spi-meson-spifc.c +++ b/drivers/spi/spi-meson-spifc.c @@ -31,10 +31,10 @@ #define REG_USER2 0x24 #define REG_USER3 0x28 #define REG_USER4 0x2c -#define REG_SLAVE 0x30 -#define REG_SLAVE1 0x34 -#define REG_SLAVE2 0x38 -#define REG_SLAVE3 0x3c +#define REG_TARGET 0x30 +#define REG_TARGET1 0x34 +#define REG_TARGET2 0x38 +#define REG_TARGET3 0x3c #define REG_C0 0x40 #define REG_B8 0x60 #define REG_MAX 0x7c @@ -59,21 +59,21 @@ #define USER1_BN_UC_DIN_SHIFT 8 #define USER1_BN_UC_DIN_MASK (0xff << 8) #define USER4_CS_ACT BIT(30) -#define SLAVE_TRST_DONE BIT(4) -#define SLAVE_OP_MODE BIT(30) -#define SLAVE_SW_RST BIT(31) +#define TARGET_TRST_DONE BIT(4) +#define TARGET_OP_MODE BIT(30) +#define TARGET_SW_RST BIT(31) #define SPIFC_BUFFER_SIZE 64 /** * struct meson_spifc - * @master: the SPI master + * @host: the SPI host * @regmap: regmap for device registers * @clk: input clock of the built-in baud rate generator * @dev: the device structure */ struct meson_spifc { - struct spi_master *master; + struct spi_controller *host; struct regmap *regmap; struct clk *clk; struct device *dev; @@ -97,8 +97,8 @@ static int meson_spifc_wait_ready(struct meson_spifc *spifc) u32 data; do { - regmap_read(spifc->regmap, REG_SLAVE, &data); - if (data & SLAVE_TRST_DONE) + regmap_read(spifc->regmap, REG_TARGET, &data); + if (data & TARGET_TRST_DONE) return 0; cond_resched(); } while (!time_after(jiffies, deadline)); @@ -223,7 +223,7 @@ static int meson_spifc_txrx(struct meson_spifc *spifc, keep_cs ? USER4_CS_ACT : 0); /* clear transition done bit */ - regmap_update_bits(spifc->regmap, REG_SLAVE, SLAVE_TRST_DONE, 0); + regmap_update_bits(spifc->regmap, REG_TARGET, TARGET_TRST_DONE, 0); /* start transfer */ regmap_update_bits(spifc->regmap, REG_CMD, CMD_USER, CMD_USER); @@ -237,16 +237,16 @@ static int meson_spifc_txrx(struct meson_spifc *spifc, /** * meson_spifc_transfer_one() - perform a single transfer - * @master: the SPI master + * @host: the SPI host * @spi: the SPI device * @xfer: the current SPI transfer * Return: 0 on success, a negative value on error */ -static int meson_spifc_transfer_one(struct spi_master *master, +static int meson_spifc_transfer_one(struct spi_controller *host, struct spi_device *spi, struct spi_transfer *xfer) { - struct meson_spifc *spifc = spi_master_get_devdata(master); + struct meson_spifc *spifc = spi_controller_get_devdata(host); int len, done = 0, ret = 0; meson_spifc_setup_speed(spifc, xfer->speed_hz); @@ -256,7 +256,7 @@ static int meson_spifc_transfer_one(struct spi_master *master, while (done < xfer->len && !ret) { len = min_t(int, xfer->len - done, SPIFC_BUFFER_SIZE); ret = meson_spifc_txrx(spifc, xfer, done, len, - spi_transfer_is_last(master, xfer), + spi_transfer_is_last(host, xfer), done + len >= xfer->len); done += len; } @@ -274,29 +274,29 @@ static int meson_spifc_transfer_one(struct spi_master *master, static void meson_spifc_hw_init(struct meson_spifc *spifc) { /* reset device */ - regmap_update_bits(spifc->regmap, REG_SLAVE, SLAVE_SW_RST, - SLAVE_SW_RST); + regmap_update_bits(spifc->regmap, REG_TARGET, TARGET_SW_RST, + TARGET_SW_RST); /* disable compatible mode */ regmap_update_bits(spifc->regmap, REG_USER, USER_CMP_MODE, 0); - /* set master mode */ - regmap_update_bits(spifc->regmap, REG_SLAVE, SLAVE_OP_MODE, 0); + /* set host mode */ + regmap_update_bits(spifc->regmap, REG_TARGET, TARGET_OP_MODE, 0); } static int meson_spifc_probe(struct platform_device *pdev) { - struct spi_master *master; + struct spi_controller *host; struct meson_spifc *spifc; void __iomem *base; unsigned int rate; int ret = 0; - master = spi_alloc_master(&pdev->dev, sizeof(struct meson_spifc)); - if (!master) + host = spi_alloc_host(&pdev->dev, sizeof(struct meson_spifc)); + if (!host) return -ENOMEM; - platform_set_drvdata(pdev, master); + platform_set_drvdata(pdev, host); - spifc = spi_master_get_devdata(master); + spifc = spi_controller_get_devdata(host); spifc->dev = &pdev->dev; base = devm_platform_ioremap_resource(pdev, 0); @@ -327,22 +327,22 @@ static int meson_spifc_probe(struct platform_device *pdev) rate = clk_get_rate(spifc->clk); - master->num_chipselect = 1; - master->dev.of_node = pdev->dev.of_node; - master->bits_per_word_mask = SPI_BPW_MASK(8); - master->auto_runtime_pm = true; - master->transfer_one = meson_spifc_transfer_one; - master->min_speed_hz = rate >> 6; - master->max_speed_hz = rate >> 1; + host->num_chipselect = 1; + host->dev.of_node = pdev->dev.of_node; + host->bits_per_word_mask = SPI_BPW_MASK(8); + host->auto_runtime_pm = true; + host->transfer_one = meson_spifc_transfer_one; + host->min_speed_hz = rate >> 6; + host->max_speed_hz = rate >> 1; meson_spifc_hw_init(spifc); pm_runtime_set_active(spifc->dev); pm_runtime_enable(spifc->dev); - ret = devm_spi_register_master(spifc->dev, master); + ret = devm_spi_register_controller(spifc->dev, host); if (ret) { - dev_err(spifc->dev, "failed to register spi master\n"); + dev_err(spifc->dev, "failed to register spi host\n"); goto out_clk; } @@ -351,14 +351,14 @@ static int meson_spifc_probe(struct platform_device *pdev) clk_disable_unprepare(spifc->clk); pm_runtime_disable(spifc->dev); out_err: - spi_master_put(master); + spi_controller_put(host); return ret; } static void meson_spifc_remove(struct platform_device *pdev) { - struct spi_master *master = platform_get_drvdata(pdev); - struct meson_spifc *spifc = spi_master_get_devdata(master); + struct spi_controller *host = platform_get_drvdata(pdev); + struct meson_spifc *spifc = spi_controller_get_devdata(host); pm_runtime_get_sync(&pdev->dev); clk_disable_unprepare(spifc->clk); @@ -368,11 +368,11 @@ static void meson_spifc_remove(struct platform_device *pdev) #ifdef CONFIG_PM_SLEEP static int meson_spifc_suspend(struct device *dev) { - struct spi_master *master = dev_get_drvdata(dev); - struct meson_spifc *spifc = spi_master_get_devdata(master); + struct spi_controller *host = dev_get_drvdata(dev); + struct meson_spifc *spifc = spi_controller_get_devdata(host); int ret; - ret = spi_master_suspend(master); + ret = spi_controller_suspend(host); if (ret) return ret; @@ -384,8 +384,8 @@ static int meson_spifc_suspend(struct device *dev) static int meson_spifc_resume(struct device *dev) { - struct spi_master *master = dev_get_drvdata(dev); - struct meson_spifc *spifc = spi_master_get_devdata(master); + struct spi_controller *host = dev_get_drvdata(dev); + struct meson_spifc *spifc = spi_controller_get_devdata(host); int ret; if (!pm_runtime_suspended(dev)) { @@ -396,7 +396,7 @@ static int meson_spifc_resume(struct device *dev) meson_spifc_hw_init(spifc); - ret = spi_master_resume(master); + ret = spi_controller_resume(host); if (ret) clk_disable_unprepare(spifc->clk); @@ -407,8 +407,8 @@ static int meson_spifc_resume(struct device *dev) #ifdef CONFIG_PM static int meson_spifc_runtime_suspend(struct device *dev) { - struct spi_master *master = dev_get_drvdata(dev); - struct meson_spifc *spifc = spi_master_get_devdata(master); + struct spi_controller *host = dev_get_drvdata(dev); + struct meson_spifc *spifc = spi_controller_get_devdata(host); clk_disable_unprepare(spifc->clk); @@ -417,8 +417,8 @@ static int meson_spifc_runtime_suspend(struct device *dev) static int meson_spifc_runtime_resume(struct device *dev) { - struct spi_master *master = dev_get_drvdata(dev); - struct meson_spifc *spifc = spi_master_get_devdata(master); + struct spi_controller *host = dev_get_drvdata(dev); + struct meson_spifc *spifc = spi_controller_get_devdata(host); return clk_prepare_enable(spifc->clk); } From patchwork Thu Aug 10 08:29:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yang Yingliang X-Patchwork-Id: 713167 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0FA9FC001DE for ; Thu, 10 Aug 2023 08:33:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234202AbjHJIdL (ORCPT ); Thu, 10 Aug 2023 04:33:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34716 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234206AbjHJIdK (ORCPT ); Thu, 10 Aug 2023 04:33:10 -0400 Received: from szxga01-in.huawei.com (szxga01-in.huawei.com [45.249.212.187]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 01D2CED for ; Thu, 10 Aug 2023 01:33:10 -0700 (PDT) Received: from dggpemm100002.china.huawei.com (unknown [172.30.72.55]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4RM0TX4qVYztSGR; Thu, 10 Aug 2023 16:29:36 +0800 (CST) Received: from dggpemm500007.china.huawei.com (7.185.36.183) by dggpemm100002.china.huawei.com (7.185.36.179) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 10 Aug 2023 16:33:06 +0800 Received: from huawei.com (10.175.103.91) by dggpemm500007.china.huawei.com (7.185.36.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 10 Aug 2023 16:33:06 +0800 From: Yang Yingliang To: CC: , , , Subject: [PATCH -next 05/21] spi: microchip-core-qspi: switch to use modern name Date: Thu, 10 Aug 2023 16:29:48 +0800 Message-ID: <20230810083004.3988597-6-yangyingliang@huawei.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230810083004.3988597-1-yangyingliang@huawei.com> References: <20230810083004.3988597-1-yangyingliang@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.175.103.91] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To dggpemm500007.china.huawei.com (7.185.36.183) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Change legacy name master to modern name host or controller. No functional changed. Signed-off-by: Yang Yingliang --- drivers/spi/spi-microchip-core-qspi.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/spi/spi-microchip-core-qspi.c b/drivers/spi/spi-microchip-core-qspi.c index 4f76ddf97b10..512542457dcc 100644 --- a/drivers/spi/spi-microchip-core-qspi.c +++ b/drivers/spi/spi-microchip-core-qspi.c @@ -25,7 +25,7 @@ * QSPI Control register mask defines */ #define CONTROL_ENABLE BIT(0) -#define CONTROL_MASTER BIT(1) +#define CONTROL_HOST BIT(1) #define CONTROL_XIP BIT(2) #define CONTROL_XIPADDR BIT(3) #define CONTROL_CLKIDLE BIT(10) @@ -299,11 +299,11 @@ static int mchp_coreqspi_setup_clock(struct mchp_coreqspi *qspi, struct spi_devi static int mchp_coreqspi_setup_op(struct spi_device *spi_dev) { - struct spi_controller *ctlr = spi_dev->master; + struct spi_controller *ctlr = spi_dev->controller; struct mchp_coreqspi *qspi = spi_controller_get_devdata(ctlr); u32 control = readl_relaxed(qspi->regs + REG_CONTROL); - control |= (CONTROL_MASTER | CONTROL_ENABLE); + control |= (CONTROL_HOST | CONTROL_ENABLE); control &= ~CONTROL_CLKIDLE; writel_relaxed(control, qspi->regs + REG_CONTROL); @@ -368,7 +368,7 @@ static inline void mchp_coreqspi_config_op(struct mchp_coreqspi *qspi, const str static int mchp_qspi_wait_for_ready(struct spi_mem *mem) { struct mchp_coreqspi *qspi = spi_controller_get_devdata - (mem->spi->master); + (mem->spi->controller); u32 status; int ret; @@ -387,7 +387,7 @@ static int mchp_qspi_wait_for_ready(struct spi_mem *mem) static int mchp_coreqspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) { struct mchp_coreqspi *qspi = spi_controller_get_devdata - (mem->spi->master); + (mem->spi->controller); u32 address = op->addr.val; u8 opcode = op->cmd.opcode; u8 opaddr[5]; @@ -505,10 +505,10 @@ static int mchp_coreqspi_probe(struct platform_device *pdev) struct device_node *np = dev->of_node; int ret; - ctlr = devm_spi_alloc_master(&pdev->dev, sizeof(*qspi)); + ctlr = devm_spi_alloc_host(&pdev->dev, sizeof(*qspi)); if (!ctlr) return dev_err_probe(&pdev->dev, -ENOMEM, - "unable to allocate master for QSPI controller\n"); + "unable to allocate host for QSPI controller\n"); qspi = spi_controller_get_devdata(ctlr); platform_set_drvdata(pdev, qspi); From patchwork Thu Aug 10 08:29:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yang Yingliang X-Patchwork-Id: 713165 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 75D36C04FE2 for ; Thu, 10 Aug 2023 08:33:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234213AbjHJIdN (ORCPT ); Thu, 10 Aug 2023 04:33:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34800 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234216AbjHJIdM (ORCPT ); Thu, 10 Aug 2023 04:33:12 -0400 Received: from szxga02-in.huawei.com (szxga02-in.huawei.com [45.249.212.188]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 64D0EED for ; Thu, 10 Aug 2023 01:33:11 -0700 (PDT) Received: from dggpemm500002.china.huawei.com (unknown [172.30.72.54]) by szxga02-in.huawei.com (SkyGuard) with ESMTP id 4RM0WL6FrVzTmWb; Thu, 10 Aug 2023 16:31:10 +0800 (CST) Received: from dggpemm500007.china.huawei.com (7.185.36.183) by dggpemm500002.china.huawei.com (7.185.36.229) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 10 Aug 2023 16:33:07 +0800 Received: from huawei.com (10.175.103.91) by dggpemm500007.china.huawei.com (7.185.36.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 10 Aug 2023 16:33:06 +0800 From: Yang Yingliang To: CC: , , , Subject: [PATCH -next 06/21] spi: microchip-core: switch to use modern name Date: Thu, 10 Aug 2023 16:29:49 +0800 Message-ID: <20230810083004.3988597-7-yangyingliang@huawei.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230810083004.3988597-1-yangyingliang@huawei.com> References: <20230810083004.3988597-1-yangyingliang@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.175.103.91] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To dggpemm500007.china.huawei.com (7.185.36.183) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Change legacy name master/slave to modern name host/target or controller. No functional changed. Signed-off-by: Yang Yingliang --- drivers/spi/spi-microchip-core.c | 90 ++++++++++++++++---------------- 1 file changed, 45 insertions(+), 45 deletions(-) diff --git a/drivers/spi/spi-microchip-core.c b/drivers/spi/spi-microchip-core.c index b451cd4860ec..dfdb1daad9da 100644 --- a/drivers/spi/spi-microchip-core.c +++ b/drivers/spi/spi-microchip-core.c @@ -30,7 +30,7 @@ #define MODE_X_MASK_SHIFT (24) #define CONTROL_ENABLE BIT(0) -#define CONTROL_MASTER BIT(1) +#define CONTROL_HOST BIT(1) #define CONTROL_RX_DATA_INT BIT(4) #define CONTROL_TX_DATA_INT BIT(5) #define CONTROL_RX_OVER_INT BIT(6) @@ -80,7 +80,7 @@ #define REG_RX_DATA (0x10) #define REG_TX_DATA (0x14) #define REG_CLK_GEN (0x18) -#define REG_SLAVE_SELECT (0x1c) +#define REG_TARGET_SELECT (0x1c) #define SSEL_MASK GENMASK(7, 0) #define SSEL_DIRECT BIT(8) #define SSELOUT_SHIFT 9 @@ -244,39 +244,39 @@ static inline void mchp_corespi_set_framesize(struct mchp_corespi *spi, int bt) static void mchp_corespi_set_cs(struct spi_device *spi, bool disable) { u32 reg; - struct mchp_corespi *corespi = spi_master_get_devdata(spi->master); + struct mchp_corespi *corespi = spi_controller_get_devdata(spi->controller); - reg = mchp_corespi_read(corespi, REG_SLAVE_SELECT); + reg = mchp_corespi_read(corespi, REG_TARGET_SELECT); reg &= ~BIT(spi_get_chipselect(spi, 0)); reg |= !disable << spi_get_chipselect(spi, 0); - mchp_corespi_write(corespi, REG_SLAVE_SELECT, reg); + mchp_corespi_write(corespi, REG_TARGET_SELECT, reg); } static int mchp_corespi_setup(struct spi_device *spi) { - struct mchp_corespi *corespi = spi_master_get_devdata(spi->master); + struct mchp_corespi *corespi = spi_controller_get_devdata(spi->controller); u32 reg; /* - * Active high slaves need to be specifically set to their inactive + * Active high targets need to be specifically set to their inactive * states during probe by adding them to the "control group" & thus * driving their select line low. */ if (spi->mode & SPI_CS_HIGH) { - reg = mchp_corespi_read(corespi, REG_SLAVE_SELECT); + reg = mchp_corespi_read(corespi, REG_TARGET_SELECT); reg |= BIT(spi_get_chipselect(spi, 0)); - mchp_corespi_write(corespi, REG_SLAVE_SELECT, reg); + mchp_corespi_write(corespi, REG_TARGET_SELECT, reg); } return 0; } -static void mchp_corespi_init(struct spi_master *master, struct mchp_corespi *spi) +static void mchp_corespi_init(struct spi_controller *host, struct mchp_corespi *spi) { unsigned long clk_hz; u32 control = mchp_corespi_read(spi, REG_CONTROL); - control |= CONTROL_MASTER; + control |= CONTROL_HOST; control &= ~CONTROL_MODE_MASK; control |= MOTOROLA_MODE; @@ -285,7 +285,7 @@ static void mchp_corespi_init(struct spi_master *master, struct mchp_corespi *sp /* max. possible spi clock rate is the apb clock rate */ clk_hz = clk_get_rate(spi->clk); - master->max_speed_hz = clk_hz; + host->max_speed_hz = clk_hz; /* * The controller must be configured so that it doesn't remove Chip @@ -305,9 +305,9 @@ static void mchp_corespi_init(struct spi_master *master, struct mchp_corespi *sp /* * It is required to enable direct mode, otherwise control over the chip * select is relinquished to the hardware. SSELOUT is enabled too so we - * can deal with active high slaves. + * can deal with active high targets. */ - mchp_corespi_write(spi, REG_SLAVE_SELECT, SSELOUT | SSEL_DIRECT); + mchp_corespi_write(spi, REG_TARGET_SELECT, SSELOUT | SSEL_DIRECT); control = mchp_corespi_read(spi, REG_CONTROL); @@ -371,8 +371,8 @@ static inline void mchp_corespi_set_mode(struct mchp_corespi *spi, unsigned int static irqreturn_t mchp_corespi_interrupt(int irq, void *dev_id) { - struct spi_master *master = dev_id; - struct mchp_corespi *spi = spi_master_get_devdata(master); + struct spi_controller *host = dev_id; + struct mchp_corespi *spi = spi_controller_get_devdata(host); u32 intfield = mchp_corespi_read(spi, REG_MIS) & 0xf; bool finalise = false; @@ -399,7 +399,7 @@ static irqreturn_t mchp_corespi_interrupt(int irq, void *dev_id) if (intfield & INT_RX_CHANNEL_OVERFLOW) { mchp_corespi_write(spi, REG_INT_CLEAR, INT_RX_CHANNEL_OVERFLOW); finalise = true; - dev_err(&master->dev, + dev_err(&host->dev, "%s: RX OVERFLOW: rxlen: %d, txlen: %d\n", __func__, spi->rx_len, spi->tx_len); } @@ -407,13 +407,13 @@ static irqreturn_t mchp_corespi_interrupt(int irq, void *dev_id) if (intfield & INT_TX_CHANNEL_UNDERRUN) { mchp_corespi_write(spi, REG_INT_CLEAR, INT_TX_CHANNEL_UNDERRUN); finalise = true; - dev_err(&master->dev, + dev_err(&host->dev, "%s: TX UNDERFLOW: rxlen: %d, txlen: %d\n", __func__, spi->rx_len, spi->tx_len); } if (finalise) - spi_finalize_current_transfer(master); + spi_finalize_current_transfer(host); return IRQ_HANDLED; } @@ -455,16 +455,16 @@ static int mchp_corespi_calculate_clkgen(struct mchp_corespi *spi, return 0; } -static int mchp_corespi_transfer_one(struct spi_master *master, +static int mchp_corespi_transfer_one(struct spi_controller *host, struct spi_device *spi_dev, struct spi_transfer *xfer) { - struct mchp_corespi *spi = spi_master_get_devdata(master); + struct mchp_corespi *spi = spi_controller_get_devdata(host); int ret; ret = mchp_corespi_calculate_clkgen(spi, (unsigned long)xfer->speed_hz); if (ret) { - dev_err(&master->dev, "failed to set clk_gen for target %u Hz\n", xfer->speed_hz); + dev_err(&host->dev, "failed to set clk_gen for target %u Hz\n", xfer->speed_hz); return ret; } @@ -484,11 +484,11 @@ static int mchp_corespi_transfer_one(struct spi_master *master, return 1; } -static int mchp_corespi_prepare_message(struct spi_master *master, +static int mchp_corespi_prepare_message(struct spi_controller *host, struct spi_message *msg) { struct spi_device *spi_dev = msg->spi; - struct mchp_corespi *spi = spi_master_get_devdata(master); + struct mchp_corespi *spi = spi_controller_get_devdata(host); mchp_corespi_set_framesize(spi, DEFAULT_FRAMESIZE); mchp_corespi_set_mode(spi, spi_dev->mode); @@ -498,32 +498,32 @@ static int mchp_corespi_prepare_message(struct spi_master *master, static int mchp_corespi_probe(struct platform_device *pdev) { - struct spi_master *master; + struct spi_controller *host; struct mchp_corespi *spi; struct resource *res; u32 num_cs; int ret = 0; - master = devm_spi_alloc_master(&pdev->dev, sizeof(*spi)); - if (!master) + host = devm_spi_alloc_host(&pdev->dev, sizeof(*spi)); + if (!host) return dev_err_probe(&pdev->dev, -ENOMEM, - "unable to allocate master for SPI controller\n"); + "unable to allocate host for SPI controller\n"); - platform_set_drvdata(pdev, master); + platform_set_drvdata(pdev, host); if (of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs)) num_cs = MAX_CS; - master->num_chipselect = num_cs; - master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; - master->setup = mchp_corespi_setup; - master->bits_per_word_mask = SPI_BPW_MASK(8); - master->transfer_one = mchp_corespi_transfer_one; - master->prepare_message = mchp_corespi_prepare_message; - master->set_cs = mchp_corespi_set_cs; - master->dev.of_node = pdev->dev.of_node; + host->num_chipselect = num_cs; + host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; + host->setup = mchp_corespi_setup; + host->bits_per_word_mask = SPI_BPW_MASK(8); + host->transfer_one = mchp_corespi_transfer_one; + host->prepare_message = mchp_corespi_prepare_message; + host->set_cs = mchp_corespi_set_cs; + host->dev.of_node = pdev->dev.of_node; - spi = spi_master_get_devdata(master); + spi = spi_controller_get_devdata(host); spi->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res); if (IS_ERR(spi->regs)) @@ -534,7 +534,7 @@ static int mchp_corespi_probe(struct platform_device *pdev) return spi->irq; ret = devm_request_irq(&pdev->dev, spi->irq, mchp_corespi_interrupt, - IRQF_SHARED, dev_name(&pdev->dev), master); + IRQF_SHARED, dev_name(&pdev->dev), host); if (ret) return dev_err_probe(&pdev->dev, ret, "could not request irq\n"); @@ -549,25 +549,25 @@ static int mchp_corespi_probe(struct platform_device *pdev) return dev_err_probe(&pdev->dev, ret, "failed to enable clock\n"); - mchp_corespi_init(master, spi); + mchp_corespi_init(host, spi); - ret = devm_spi_register_master(&pdev->dev, master); + ret = devm_spi_register_controller(&pdev->dev, host); if (ret) { mchp_corespi_disable(spi); clk_disable_unprepare(spi->clk); return dev_err_probe(&pdev->dev, ret, - "unable to register master for SPI controller\n"); + "unable to register host for SPI controller\n"); } - dev_info(&pdev->dev, "Registered SPI controller %d\n", master->bus_num); + dev_info(&pdev->dev, "Registered SPI controller %d\n", host->bus_num); return 0; } static void mchp_corespi_remove(struct platform_device *pdev) { - struct spi_master *master = platform_get_drvdata(pdev); - struct mchp_corespi *spi = spi_master_get_devdata(master); + struct spi_controller *host = platform_get_drvdata(pdev); + struct mchp_corespi *spi = spi_controller_get_devdata(host); mchp_corespi_disable_ints(spi); clk_disable_unprepare(spi->clk); From patchwork Thu Aug 10 08:29:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yang Yingliang X-Patchwork-Id: 712575 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 58AB8C001DB for ; Thu, 10 Aug 2023 08:33:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234206AbjHJIdL (ORCPT ); Thu, 10 Aug 2023 04:33:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34746 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234208AbjHJIdL (ORCPT ); Thu, 10 Aug 2023 04:33:11 -0400 Received: from szxga01-in.huawei.com (szxga01-in.huawei.com [45.249.212.187]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 33F70E56 for ; Thu, 10 Aug 2023 01:33:10 -0700 (PDT) Received: from dggpemm500006.china.huawei.com (unknown [172.30.72.54]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4RM0XB4SV5zkX9K; Thu, 10 Aug 2023 16:31:54 +0800 (CST) Received: from dggpemm500007.china.huawei.com (7.185.36.183) by dggpemm500006.china.huawei.com (7.185.36.236) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 10 Aug 2023 16:33:07 +0800 Received: from huawei.com (10.175.103.91) by dggpemm500007.china.huawei.com (7.185.36.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 10 Aug 2023 16:33:07 +0800 From: Yang Yingliang To: CC: , , , Subject: [PATCH -next 07/21] spi: mpc512x-psc: switch to use modern name Date: Thu, 10 Aug 2023 16:29:50 +0800 Message-ID: <20230810083004.3988597-8-yangyingliang@huawei.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230810083004.3988597-1-yangyingliang@huawei.com> References: <20230810083004.3988597-1-yangyingliang@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.175.103.91] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To dggpemm500007.china.huawei.com (7.185.36.183) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Change legacy name master to modern name host or controller. No functional changed. Signed-off-by: Yang Yingliang --- drivers/spi/spi-mpc512x-psc.c | 54 +++++++++++++++++------------------ 1 file changed, 27 insertions(+), 27 deletions(-) diff --git a/drivers/spi/spi-mpc512x-psc.c b/drivers/spi/spi-mpc512x-psc.c index 5cecca1bef02..7b4150f68165 100644 --- a/drivers/spi/spi-mpc512x-psc.c +++ b/drivers/spi/spi-mpc512x-psc.c @@ -85,7 +85,7 @@ static int mpc512x_psc_spi_transfer_setup(struct spi_device *spi, static void mpc512x_psc_spi_activate_cs(struct spi_device *spi) { struct mpc512x_psc_spi_cs *cs = spi->controller_state; - struct mpc512x_psc_spi *mps = spi_master_get_devdata(spi->master); + struct mpc512x_psc_spi *mps = spi_controller_get_devdata(spi->controller); u32 sicr; u32 ccr; int speed; @@ -143,7 +143,7 @@ static void mpc512x_psc_spi_deactivate_cs(struct spi_device *spi) static int mpc512x_psc_spi_transfer_rxtx(struct spi_device *spi, struct spi_transfer *t) { - struct mpc512x_psc_spi *mps = spi_master_get_devdata(spi->master); + struct mpc512x_psc_spi *mps = spi_controller_get_devdata(spi->controller); struct mpc512x_psc_fifo __iomem *fifo = mps->fifo; size_t tx_len = t->len; size_t rx_len = t->len; @@ -280,7 +280,7 @@ static int mpc512x_psc_spi_transfer_rxtx(struct spi_device *spi, return 0; } -static int mpc512x_psc_spi_msg_xfer(struct spi_master *master, +static int mpc512x_psc_spi_msg_xfer(struct spi_controller *host, struct spi_message *m) { struct spi_device *spi; @@ -320,15 +320,15 @@ static int mpc512x_psc_spi_msg_xfer(struct spi_master *master, mpc512x_psc_spi_transfer_setup(spi, NULL); - spi_finalize_current_message(master); + spi_finalize_current_message(host); return status; } -static int mpc512x_psc_spi_prep_xfer_hw(struct spi_master *master) +static int mpc512x_psc_spi_prep_xfer_hw(struct spi_controller *host) { - struct mpc512x_psc_spi *mps = spi_master_get_devdata(master); + struct mpc512x_psc_spi *mps = spi_controller_get_devdata(host); - dev_dbg(&master->dev, "%s()\n", __func__); + dev_dbg(&host->dev, "%s()\n", __func__); /* Zero MR2 */ in_8(psc_addr(mps, mr2)); @@ -340,12 +340,12 @@ static int mpc512x_psc_spi_prep_xfer_hw(struct spi_master *master) return 0; } -static int mpc512x_psc_spi_unprep_xfer_hw(struct spi_master *master) +static int mpc512x_psc_spi_unprep_xfer_hw(struct spi_controller *host) { - struct mpc512x_psc_spi *mps = spi_master_get_devdata(master); + struct mpc512x_psc_spi *mps = spi_controller_get_devdata(host); struct mpc512x_psc_fifo __iomem *fifo = mps->fifo; - dev_dbg(&master->dev, "%s()\n", __func__); + dev_dbg(&host->dev, "%s()\n", __func__); /* disable transmitter/receiver and fifo interrupt */ out_8(psc_addr(mps, command), MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE); @@ -380,7 +380,7 @@ static void mpc512x_psc_spi_cleanup(struct spi_device *spi) kfree(spi->controller_state); } -static int mpc512x_psc_spi_port_config(struct spi_master *master, +static int mpc512x_psc_spi_port_config(struct spi_controller *host, struct mpc512x_psc_spi *mps) { struct mpc512x_psc_fifo __iomem *fifo = mps->fifo; @@ -408,7 +408,7 @@ static int mpc512x_psc_spi_port_config(struct spi_master *master, sicr = 0x01000000 | /* SIM = 0001 -- 8 bit */ 0x00800000 | /* GenClk = 1 -- internal clk */ 0x00008000 | /* SPI = 1 */ - 0x00004000 | /* MSTR = 1 -- SPI master */ + 0x00004000 | /* HST = 1 -- SPI host */ 0x00000800; /* UseEOF = 1 -- SS low until EOF */ out_be32(psc_addr(mps, sicr), sicr); @@ -459,28 +459,28 @@ static int mpc512x_psc_spi_of_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct mpc512x_psc_spi *mps; - struct spi_master *master; + struct spi_controller *host; int ret; void *tempp; struct clk *clk; - master = devm_spi_alloc_master(dev, sizeof(*mps)); - if (master == NULL) + host = devm_spi_alloc_host(dev, sizeof(*mps)); + if (host == NULL) return -ENOMEM; - dev_set_drvdata(dev, master); - mps = spi_master_get_devdata(master); + dev_set_drvdata(dev, host); + mps = spi_controller_get_devdata(host); mps->type = (int)device_get_match_data(dev); - master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST; - master->setup = mpc512x_psc_spi_setup; - master->prepare_transfer_hardware = mpc512x_psc_spi_prep_xfer_hw; - master->transfer_one_message = mpc512x_psc_spi_msg_xfer; - master->unprepare_transfer_hardware = mpc512x_psc_spi_unprep_xfer_hw; - master->use_gpio_descriptors = true; - master->cleanup = mpc512x_psc_spi_cleanup; + host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST; + host->setup = mpc512x_psc_spi_setup; + host->prepare_transfer_hardware = mpc512x_psc_spi_prep_xfer_hw; + host->transfer_one_message = mpc512x_psc_spi_msg_xfer; + host->unprepare_transfer_hardware = mpc512x_psc_spi_unprep_xfer_hw; + host->use_gpio_descriptors = true; + host->cleanup = mpc512x_psc_spi_cleanup; - device_set_node(&master->dev, dev_fwnode(dev)); + device_set_node(&host->dev, dev_fwnode(dev)); tempp = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); if (IS_ERR(tempp)) @@ -509,11 +509,11 @@ static int mpc512x_psc_spi_of_probe(struct platform_device *pdev) if (IS_ERR(clk)) return PTR_ERR(clk); - ret = mpc512x_psc_spi_port_config(master, mps); + ret = mpc512x_psc_spi_port_config(host, mps); if (ret < 0) return ret; - return devm_spi_register_master(dev, master); + return devm_spi_register_controller(dev, host); } static const struct of_device_id mpc512x_psc_spi_of_match[] = { From patchwork Thu Aug 10 08:29:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yang Yingliang X-Patchwork-Id: 712574 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EC6E4C04FE1 for ; Thu, 10 Aug 2023 08:33:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234220AbjHJIdN (ORCPT ); Thu, 10 Aug 2023 04:33:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34758 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234208AbjHJIdM (ORCPT ); Thu, 10 Aug 2023 04:33:12 -0400 Received: from szxga02-in.huawei.com (szxga02-in.huawei.com [45.249.212.188]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C1EB5E7E for ; Thu, 10 Aug 2023 01:33:10 -0700 (PDT) Received: from dggpemm500001.china.huawei.com (unknown [172.30.72.54]) by szxga02-in.huawei.com (SkyGuard) with ESMTP id 4RM0TZ6szyzJskT; Thu, 10 Aug 2023 16:29:38 +0800 (CST) Received: from dggpemm500007.china.huawei.com (7.185.36.183) by dggpemm500001.china.huawei.com (7.185.36.107) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 10 Aug 2023 16:33:07 +0800 Received: from huawei.com (10.175.103.91) by dggpemm500007.china.huawei.com (7.185.36.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 10 Aug 2023 16:33:07 +0800 From: Yang Yingliang To: CC: , , , Subject: [PATCH -next 08/21] spi: mpc52xx-psc: switch to use modern name Date: Thu, 10 Aug 2023 16:29:51 +0800 Message-ID: <20230810083004.3988597-9-yangyingliang@huawei.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230810083004.3988597-1-yangyingliang@huawei.com> References: <20230810083004.3988597-1-yangyingliang@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.175.103.91] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To dggpemm500007.china.huawei.com (7.185.36.183) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Change legacy name master to modern name host or controller. No functional changed. Signed-off-by: Yang Yingliang --- drivers/spi/spi-mpc52xx-psc.c | 34 +++++++++++++++++----------------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/drivers/spi/spi-mpc52xx-psc.c b/drivers/spi/spi-mpc52xx-psc.c index 795c08594a4d..78405cb45c96 100644 --- a/drivers/spi/spi-mpc52xx-psc.c +++ b/drivers/spi/spi-mpc52xx-psc.c @@ -60,7 +60,7 @@ static int mpc52xx_psc_spi_transfer_setup(struct spi_device *spi, static void mpc52xx_psc_spi_activate_cs(struct spi_device *spi) { struct mpc52xx_psc_spi_cs *cs = spi->controller_state; - struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master); + struct mpc52xx_psc_spi *mps = spi_controller_get_devdata(spi->controller); struct mpc52xx_psc __iomem *psc = mps->psc; u32 sicr; u16 ccr; @@ -104,7 +104,7 @@ static void mpc52xx_psc_spi_activate_cs(struct spi_device *spi) static int mpc52xx_psc_spi_transfer_rxtx(struct spi_device *spi, struct spi_transfer *t) { - struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master); + struct mpc52xx_psc_spi *mps = spi_controller_get_devdata(spi->controller); struct mpc52xx_psc __iomem *psc = mps->psc; struct mpc52xx_psc_fifo __iomem *fifo = mps->fifo; unsigned rb = 0; /* number of bytes receieved */ @@ -263,7 +263,7 @@ static int mpc52xx_psc_spi_port_config(int psc_id, struct mpc52xx_psc_spi *mps) out_8(&fifo->rfcntl, 0); out_8(&psc->mode, MPC52xx_PSC_MODE_FFULL); - /* Configure 8bit codec mode as a SPI master and use EOF flags */ + /* Configure 8bit codec mode as a SPI host and use EOF flags */ /* SICR_SIM_CODEC8|SICR_GENCLK|SICR_SPI|SICR_MSTR|SICR_USEEOF */ out_be32(&psc->sicr, 0x0180C800); out_be16((u16 __iomem *)&psc->ccr, 0x070F); /* default SPI Clk 1MHz */ @@ -295,31 +295,31 @@ static int mpc52xx_psc_spi_of_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct mpc52xx_psc_spi *mps; - struct spi_master *master; + struct spi_controller *host; u32 bus_num; int ret; - master = devm_spi_alloc_master(dev, sizeof(*mps)); - if (master == NULL) + host = devm_spi_alloc_host(dev, sizeof(*mps)); + if (host == NULL) return -ENOMEM; - dev_set_drvdata(dev, master); - mps = spi_master_get_devdata(master); + dev_set_drvdata(dev, host); + mps = spi_controller_get_devdata(host); /* the spi->mode bits understood by this driver: */ - master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST; + host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST; ret = device_property_read_u32(dev, "cell-index", &bus_num); if (ret || bus_num > 5) return dev_err_probe(dev, ret ? : -EINVAL, "Invalid cell-index property\n"); - master->bus_num = bus_num + 1; + host->bus_num = bus_num + 1; - master->num_chipselect = 255; - master->setup = mpc52xx_psc_spi_setup; - master->transfer_one_message = mpc52xx_psc_spi_transfer_one_message; - master->cleanup = mpc52xx_psc_spi_cleanup; + host->num_chipselect = 255; + host->setup = mpc52xx_psc_spi_setup; + host->transfer_one_message = mpc52xx_psc_spi_transfer_one_message; + host->cleanup = mpc52xx_psc_spi_cleanup; - device_set_node(&master->dev, dev_fwnode(dev)); + device_set_node(&host->dev, dev_fwnode(dev)); mps->psc = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); if (IS_ERR(mps->psc)) @@ -337,13 +337,13 @@ static int mpc52xx_psc_spi_of_probe(struct platform_device *pdev) if (ret) return ret; - ret = mpc52xx_psc_spi_port_config(master->bus_num, mps); + ret = mpc52xx_psc_spi_port_config(host->bus_num, mps); if (ret < 0) return dev_err_probe(dev, ret, "can't configure PSC! Is it capable of SPI?\n"); init_completion(&mps->done); - return devm_spi_register_master(dev, master); + return devm_spi_register_controller(dev, host); } static const struct of_device_id mpc52xx_psc_spi_of_match[] = { From patchwork Thu Aug 10 08:29:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yang Yingliang X-Patchwork-Id: 712567 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0E62CC001DB for ; Thu, 10 Aug 2023 08:33:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234233AbjHJIdU (ORCPT ); Thu, 10 Aug 2023 04:33:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42060 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234232AbjHJIdU (ORCPT ); Thu, 10 Aug 2023 04:33:20 -0400 Received: from szxga01-in.huawei.com (szxga01-in.huawei.com [45.249.212.187]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1D77FED for ; Thu, 10 Aug 2023 01:33:19 -0700 (PDT) Received: from dggpemm500004.china.huawei.com (unknown [172.30.72.56]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4RM0XN27SGzkX9y; Thu, 10 Aug 2023 16:32:04 +0800 (CST) Received: from dggpemm500007.china.huawei.com (7.185.36.183) by dggpemm500004.china.huawei.com (7.185.36.219) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 10 Aug 2023 16:33:08 +0800 Received: from huawei.com (10.175.103.91) by dggpemm500007.china.huawei.com (7.185.36.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 10 Aug 2023 16:33:07 +0800 From: Yang Yingliang To: CC: , , , Subject: [PATCH -next 09/21] spi: mpc52xx: switch to use modern name Date: Thu, 10 Aug 2023 16:29:52 +0800 Message-ID: <20230810083004.3988597-10-yangyingliang@huawei.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230810083004.3988597-1-yangyingliang@huawei.com> References: <20230810083004.3988597-1-yangyingliang@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.175.103.91] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To dggpemm500007.china.huawei.com (7.185.36.183) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Change legacy name master to modern name host or controller. No functional changed. Signed-off-by: Yang Yingliang --- drivers/spi/spi-mpc52xx.c | 56 +++++++++++++++++++-------------------- 1 file changed, 28 insertions(+), 28 deletions(-) diff --git a/drivers/spi/spi-mpc52xx.c b/drivers/spi/spi-mpc52xx.c index ab7df5f64342..4a6c984b6bff 100644 --- a/drivers/spi/spi-mpc52xx.c +++ b/drivers/spi/spi-mpc52xx.c @@ -62,7 +62,7 @@ MODULE_LICENSE("GPL"); /* Driver internal data */ struct mpc52xx_spi { - struct spi_master *master; + struct spi_controller *host; void __iomem *regs; int irq0; /* MODF irq */ int irq1; /* SPIF irq */ @@ -152,7 +152,7 @@ mpc52xx_spi_fsmstate_idle(int irq, struct mpc52xx_spi *ms, u8 status, u8 data) u8 ctrl1; if (status && irq) - dev_err(&ms->master->dev, "spurious irq, status=0x%.2x\n", + dev_err(&ms->host->dev, "spurious irq, status=0x%.2x\n", status); /* Check if there is another transfer waiting. */ @@ -235,7 +235,7 @@ static int mpc52xx_spi_fsmstate_transfer(int irq, struct mpc52xx_spi *ms, return FSM_CONTINUE; } else if (status & SPI_STATUS_MODF) { ms->modf_count++; - dev_err(&ms->master->dev, "mode fault\n"); + dev_err(&ms->host->dev, "mode fault\n"); mpc52xx_spi_chipsel(ms, 0); ms->message->status = -EIO; if (ms->message->complete) @@ -280,7 +280,7 @@ static int mpc52xx_spi_fsmstate_wait(int irq, struct mpc52xx_spi *ms, u8 status, u8 data) { if (status && irq) - dev_err(&ms->master->dev, "spurious irq, status=0x%.2x\n", + dev_err(&ms->host->dev, "spurious irq, status=0x%.2x\n", status); if (((int)mftb()) - ms->timestamp < 0) @@ -361,12 +361,12 @@ static void mpc52xx_spi_wq(struct work_struct *work) } /* - * spi_master ops + * spi_controller ops */ static int mpc52xx_spi_transfer(struct spi_device *spi, struct spi_message *m) { - struct mpc52xx_spi *ms = spi_master_get_devdata(spi->master); + struct mpc52xx_spi *ms = spi_controller_get_devdata(spi->controller); unsigned long flags; m->actual_length = 0; @@ -385,7 +385,7 @@ static int mpc52xx_spi_transfer(struct spi_device *spi, struct spi_message *m) */ static int mpc52xx_spi_probe(struct platform_device *op) { - struct spi_master *master; + struct spi_controller *host; struct mpc52xx_spi *ms; struct gpio_desc *gpio_cs; void __iomem *regs; @@ -406,7 +406,7 @@ static int mpc52xx_spi_probe(struct platform_device *op) out_8(regs + SPI_PORTDATA, 0x8); /* Deassert /SS signal */ /* Clear the status register and re-read it to check for a MODF - * failure. This driver cannot currently handle multiple masters + * failure. This driver cannot currently handle multiple hosts * on the SPI bus. This fault will also occur if the SPI signals * are not connected to any pins (port_config setting) */ in_8(regs + SPI_STATUS); @@ -419,22 +419,22 @@ static int mpc52xx_spi_probe(struct platform_device *op) goto err_init; } - dev_dbg(&op->dev, "allocating spi_master struct\n"); - master = spi_alloc_master(&op->dev, sizeof(*ms)); - if (!master) { + dev_dbg(&op->dev, "allocating spi_controller struct\n"); + host = spi_alloc_host(&op->dev, sizeof(*ms)); + if (!host) { rc = -ENOMEM; goto err_alloc; } - master->transfer = mpc52xx_spi_transfer; - master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST; - master->bits_per_word_mask = SPI_BPW_MASK(8); - master->dev.of_node = op->dev.of_node; + host->transfer = mpc52xx_spi_transfer; + host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST; + host->bits_per_word_mask = SPI_BPW_MASK(8); + host->dev.of_node = op->dev.of_node; - platform_set_drvdata(op, master); + platform_set_drvdata(op, host); - ms = spi_master_get_devdata(master); - ms->master = master; + ms = spi_controller_get_devdata(host); + ms->host = host; ms->regs = regs; ms->irq0 = irq_of_parse_and_map(op->dev.of_node, 0); ms->irq1 = irq_of_parse_and_map(op->dev.of_node, 1); @@ -442,7 +442,7 @@ static int mpc52xx_spi_probe(struct platform_device *op) ms->ipb_freq = mpc5xxx_get_bus_frequency(&op->dev); ms->gpio_cs_count = gpiod_count(&op->dev, NULL); if (ms->gpio_cs_count > 0) { - master->num_chipselect = ms->gpio_cs_count; + host->num_chipselect = ms->gpio_cs_count; ms->gpio_cs = kmalloc_array(ms->gpio_cs_count, sizeof(*ms->gpio_cs), GFP_KERNEL); @@ -489,24 +489,24 @@ static int mpc52xx_spi_probe(struct platform_device *op) if (!ms->irq0) dev_info(&op->dev, "using polled mode\n"); - dev_dbg(&op->dev, "registering spi_master struct\n"); - rc = spi_register_master(master); + dev_dbg(&op->dev, "registering spi_controller struct\n"); + rc = spi_register_controller(host); if (rc) goto err_register; - dev_info(&ms->master->dev, "registered MPC5200 SPI bus\n"); + dev_info(&ms->host->dev, "registered MPC5200 SPI bus\n"); return rc; err_register: - dev_err(&ms->master->dev, "initialization failed\n"); + dev_err(&ms->host->dev, "initialization failed\n"); err_gpio: while (i-- > 0) gpiod_put(ms->gpio_cs[i]); kfree(ms->gpio_cs); err_alloc_gpio: - spi_master_put(master); + spi_controller_put(host); err_alloc: err_init: iounmap(regs); @@ -515,8 +515,8 @@ static int mpc52xx_spi_probe(struct platform_device *op) static void mpc52xx_spi_remove(struct platform_device *op) { - struct spi_master *master = spi_master_get(platform_get_drvdata(op)); - struct mpc52xx_spi *ms = spi_master_get_devdata(master); + struct spi_controller *host = spi_controller_get(platform_get_drvdata(op)); + struct mpc52xx_spi *ms = spi_controller_get_devdata(host); int i; free_irq(ms->irq0, ms); @@ -526,9 +526,9 @@ static void mpc52xx_spi_remove(struct platform_device *op) gpiod_put(ms->gpio_cs[i]); kfree(ms->gpio_cs); - spi_unregister_master(master); + spi_unregister_controller(host); iounmap(ms->regs); - spi_master_put(master); + spi_controller_put(host); } static const struct of_device_id mpc52xx_spi_match[] = { From patchwork Thu Aug 10 08:29:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yang Yingliang X-Patchwork-Id: 713164 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 35D96C04FE0 for ; Thu, 10 Aug 2023 08:33:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234208AbjHJIdN (ORCPT ); Thu, 10 Aug 2023 04:33:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34782 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234213AbjHJIdM (ORCPT ); Thu, 10 Aug 2023 04:33:12 -0400 Received: from szxga02-in.huawei.com (szxga02-in.huawei.com [45.249.212.188]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B9EF8E64 for ; Thu, 10 Aug 2023 01:33:10 -0700 (PDT) Received: from dggpemm500008.china.huawei.com (unknown [172.30.72.55]) by szxga02-in.huawei.com (SkyGuard) with ESMTP id 4RM0Tb5B0lzJsf2; Thu, 10 Aug 2023 16:29:39 +0800 (CST) Received: from dggpemm500007.china.huawei.com (7.185.36.183) by dggpemm500008.china.huawei.com (7.185.36.136) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 10 Aug 2023 16:33:08 +0800 Received: from huawei.com (10.175.103.91) by dggpemm500007.china.huawei.com (7.185.36.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 10 Aug 2023 16:33:08 +0800 From: Yang Yingliang To: CC: , , , Subject: [PATCH -next 10/21] spi: mt65xx: switch to use modern name Date: Thu, 10 Aug 2023 16:29:53 +0800 Message-ID: <20230810083004.3988597-11-yangyingliang@huawei.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230810083004.3988597-1-yangyingliang@huawei.com> References: <20230810083004.3988597-1-yangyingliang@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.175.103.91] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To dggpemm500007.china.huawei.com (7.185.36.183) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Change legacy name master to modern name host or controller. No functional changed. Signed-off-by: Yang Yingliang --- drivers/spi/spi-mt65xx.c | 190 +++++++++++++++++++-------------------- 1 file changed, 95 insertions(+), 95 deletions(-) diff --git a/drivers/spi/spi-mt65xx.c b/drivers/spi/spi-mt65xx.c index 0757985947dd..8d5d170d49cc 100644 --- a/drivers/spi/spi-mt65xx.c +++ b/drivers/spi/spi-mt65xx.c @@ -135,7 +135,7 @@ struct mtk_spi_compatible { * @pad_num: Number of pad_sel entries * @pad_sel: Groups of pins to select * @parent_clk: Parent of sel_clk - * @sel_clk: SPI master mux clock + * @sel_clk: SPI host mux clock * @spi_clk: Peripheral clock * @spi_hclk: AHB bus clock * @cur_transfer: Currently processed SPI transfer @@ -282,7 +282,7 @@ static void mtk_spi_reset(struct mtk_spi *mdata) static int mtk_spi_set_hw_cs_timing(struct spi_device *spi) { - struct mtk_spi *mdata = spi_master_get_devdata(spi->master); + struct mtk_spi *mdata = spi_controller_get_devdata(spi->controller); struct spi_delay *cs_setup = &spi->cs_setup; struct spi_delay *cs_hold = &spi->cs_hold; struct spi_delay *cs_inactive = &spi->cs_inactive; @@ -347,13 +347,13 @@ static int mtk_spi_set_hw_cs_timing(struct spi_device *spi) return 0; } -static int mtk_spi_hw_init(struct spi_master *master, +static int mtk_spi_hw_init(struct spi_controller *host, struct spi_device *spi) { u16 cpha, cpol; u32 reg_val; struct mtk_chip_config *chip_config = spi->controller_data; - struct mtk_spi *mdata = spi_master_get_devdata(master); + struct mtk_spi *mdata = spi_controller_get_devdata(host); cpha = spi->mode & SPI_CPHA ? 1 : 0; cpol = spi->mode & SPI_CPOL ? 1 : 0; @@ -452,16 +452,16 @@ static int mtk_spi_hw_init(struct spi_master *master, return 0; } -static int mtk_spi_prepare_message(struct spi_master *master, +static int mtk_spi_prepare_message(struct spi_controller *host, struct spi_message *msg) { - return mtk_spi_hw_init(master, msg->spi); + return mtk_spi_hw_init(host, msg->spi); } static void mtk_spi_set_cs(struct spi_device *spi, bool enable) { u32 reg_val; - struct mtk_spi *mdata = spi_master_get_devdata(spi->master); + struct mtk_spi *mdata = spi_controller_get_devdata(spi->controller); if (spi->mode & SPI_CS_HIGH) enable = !enable; @@ -478,11 +478,11 @@ static void mtk_spi_set_cs(struct spi_device *spi, bool enable) } } -static void mtk_spi_prepare_transfer(struct spi_master *master, +static void mtk_spi_prepare_transfer(struct spi_controller *host, u32 speed_hz) { u32 div, sck_time, reg_val; - struct mtk_spi *mdata = spi_master_get_devdata(master); + struct mtk_spi *mdata = spi_controller_get_devdata(host); if (speed_hz < mdata->spi_clk_hz / 2) div = DIV_ROUND_UP(mdata->spi_clk_hz, speed_hz); @@ -511,10 +511,10 @@ static void mtk_spi_prepare_transfer(struct spi_master *master, } } -static void mtk_spi_setup_packet(struct spi_master *master) +static void mtk_spi_setup_packet(struct spi_controller *host) { u32 packet_size, packet_loop, reg_val; - struct mtk_spi *mdata = spi_master_get_devdata(master); + struct mtk_spi *mdata = spi_controller_get_devdata(host); if (mdata->dev_comp->ipm_design) packet_size = min_t(u32, @@ -538,10 +538,10 @@ static void mtk_spi_setup_packet(struct spi_master *master) writel(reg_val, mdata->base + SPI_CFG1_REG); } -static void mtk_spi_enable_transfer(struct spi_master *master) +static void mtk_spi_enable_transfer(struct spi_controller *host) { u32 cmd; - struct mtk_spi *mdata = spi_master_get_devdata(master); + struct mtk_spi *mdata = spi_controller_get_devdata(host); cmd = readl(mdata->base + SPI_CMD_REG); if (mdata->state == MTK_SPI_IDLE) @@ -566,10 +566,10 @@ static int mtk_spi_get_mult_delta(struct mtk_spi *mdata, u32 xfer_len) return mult_delta; } -static void mtk_spi_update_mdata_len(struct spi_master *master) +static void mtk_spi_update_mdata_len(struct spi_controller *host) { int mult_delta; - struct mtk_spi *mdata = spi_master_get_devdata(master); + struct mtk_spi *mdata = spi_controller_get_devdata(host); if (mdata->tx_sgl_len && mdata->rx_sgl_len) { if (mdata->tx_sgl_len > mdata->rx_sgl_len) { @@ -594,10 +594,10 @@ static void mtk_spi_update_mdata_len(struct spi_master *master) } } -static void mtk_spi_setup_dma_addr(struct spi_master *master, +static void mtk_spi_setup_dma_addr(struct spi_controller *host, struct spi_transfer *xfer) { - struct mtk_spi *mdata = spi_master_get_devdata(master); + struct mtk_spi *mdata = spi_controller_get_devdata(host); if (mdata->tx_sgl) { writel((u32)(xfer->tx_dma & MTK_SPI_32BITS_MASK), @@ -620,19 +620,19 @@ static void mtk_spi_setup_dma_addr(struct spi_master *master, } } -static int mtk_spi_fifo_transfer(struct spi_master *master, +static int mtk_spi_fifo_transfer(struct spi_controller *host, struct spi_device *spi, struct spi_transfer *xfer) { int cnt, remainder; u32 reg_val; - struct mtk_spi *mdata = spi_master_get_devdata(master); + struct mtk_spi *mdata = spi_controller_get_devdata(host); mdata->cur_transfer = xfer; mdata->xfer_len = min(MTK_SPI_MAX_FIFO_SIZE, xfer->len); mdata->num_xfered = 0; - mtk_spi_prepare_transfer(master, xfer->speed_hz); - mtk_spi_setup_packet(master); + mtk_spi_prepare_transfer(host, xfer->speed_hz); + mtk_spi_setup_packet(host); if (xfer->tx_buf) { cnt = xfer->len / 4; @@ -645,17 +645,17 @@ static int mtk_spi_fifo_transfer(struct spi_master *master, } } - mtk_spi_enable_transfer(master); + mtk_spi_enable_transfer(host); return 1; } -static int mtk_spi_dma_transfer(struct spi_master *master, +static int mtk_spi_dma_transfer(struct spi_controller *host, struct spi_device *spi, struct spi_transfer *xfer) { int cmd; - struct mtk_spi *mdata = spi_master_get_devdata(master); + struct mtk_spi *mdata = spi_controller_get_devdata(host); mdata->tx_sgl = NULL; mdata->rx_sgl = NULL; @@ -664,7 +664,7 @@ static int mtk_spi_dma_transfer(struct spi_master *master, mdata->cur_transfer = xfer; mdata->num_xfered = 0; - mtk_spi_prepare_transfer(master, xfer->speed_hz); + mtk_spi_prepare_transfer(host, xfer->speed_hz); cmd = readl(mdata->base + SPI_CMD_REG); if (xfer->tx_buf) @@ -687,19 +687,19 @@ static int mtk_spi_dma_transfer(struct spi_master *master, mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl); } - mtk_spi_update_mdata_len(master); - mtk_spi_setup_packet(master); - mtk_spi_setup_dma_addr(master, xfer); - mtk_spi_enable_transfer(master); + mtk_spi_update_mdata_len(host); + mtk_spi_setup_packet(host); + mtk_spi_setup_dma_addr(host, xfer); + mtk_spi_enable_transfer(host); return 1; } -static int mtk_spi_transfer_one(struct spi_master *master, +static int mtk_spi_transfer_one(struct spi_controller *host, struct spi_device *spi, struct spi_transfer *xfer) { - struct mtk_spi *mdata = spi_master_get_devdata(spi->master); + struct mtk_spi *mdata = spi_controller_get_devdata(spi->controller); u32 reg_val = 0; /* prepare xfer direction and duplex mode */ @@ -712,13 +712,13 @@ static int mtk_spi_transfer_one(struct spi_master *master, writel(reg_val, mdata->base + SPI_CFG3_IPM_REG); } - if (master->can_dma(master, spi, xfer)) - return mtk_spi_dma_transfer(master, spi, xfer); + if (host->can_dma(host, spi, xfer)) + return mtk_spi_dma_transfer(host, spi, xfer); else - return mtk_spi_fifo_transfer(master, spi, xfer); + return mtk_spi_fifo_transfer(host, spi, xfer); } -static bool mtk_spi_can_dma(struct spi_master *master, +static bool mtk_spi_can_dma(struct spi_controller *host, struct spi_device *spi, struct spi_transfer *xfer) { @@ -730,7 +730,7 @@ static bool mtk_spi_can_dma(struct spi_master *master, static int mtk_spi_setup(struct spi_device *spi) { - struct mtk_spi *mdata = spi_master_get_devdata(spi->master); + struct mtk_spi *mdata = spi_controller_get_devdata(spi->controller); if (!spi->controller_data) spi->controller_data = (void *)&mtk_default_chip_info; @@ -745,8 +745,8 @@ static int mtk_spi_setup(struct spi_device *spi) static irqreturn_t mtk_spi_interrupt(int irq, void *dev_id) { u32 cmd, reg_val, cnt, remainder, len; - struct spi_master *master = dev_id; - struct mtk_spi *mdata = spi_master_get_devdata(master); + struct spi_controller *host = dev_id; + struct mtk_spi *mdata = spi_controller_get_devdata(host); struct spi_transfer *trans = mdata->cur_transfer; reg_val = readl(mdata->base + SPI_STATUS0_REG); @@ -761,7 +761,7 @@ static irqreturn_t mtk_spi_interrupt(int irq, void *dev_id) return IRQ_HANDLED; } - if (!master->can_dma(master, NULL, trans)) { + if (!host->can_dma(host, NULL, trans)) { if (trans->rx_buf) { cnt = mdata->xfer_len / 4; ioread32_rep(mdata->base + SPI_RX_DATA_REG, @@ -779,13 +779,13 @@ static irqreturn_t mtk_spi_interrupt(int irq, void *dev_id) mdata->num_xfered += mdata->xfer_len; if (mdata->num_xfered == trans->len) { - spi_finalize_current_transfer(master); + spi_finalize_current_transfer(host); return IRQ_HANDLED; } len = trans->len - mdata->num_xfered; mdata->xfer_len = min(MTK_SPI_MAX_FIFO_SIZE, len); - mtk_spi_setup_packet(master); + mtk_spi_setup_packet(host); cnt = mdata->xfer_len / 4; iowrite32_rep(mdata->base + SPI_TX_DATA_REG, @@ -800,7 +800,7 @@ static irqreturn_t mtk_spi_interrupt(int irq, void *dev_id) writel(reg_val, mdata->base + SPI_TX_DATA_REG); } - mtk_spi_enable_transfer(master); + mtk_spi_enable_transfer(host); return IRQ_HANDLED; } @@ -832,14 +832,14 @@ static irqreturn_t mtk_spi_interrupt(int irq, void *dev_id) cmd &= ~SPI_CMD_RX_DMA; writel(cmd, mdata->base + SPI_CMD_REG); - spi_finalize_current_transfer(master); + spi_finalize_current_transfer(host); return IRQ_HANDLED; } - mtk_spi_update_mdata_len(master); - mtk_spi_setup_packet(master); - mtk_spi_setup_dma_addr(master, trans); - mtk_spi_enable_transfer(master); + mtk_spi_update_mdata_len(host); + mtk_spi_setup_packet(host); + mtk_spi_setup_dma_addr(host, trans); + mtk_spi_enable_transfer(host); return IRQ_HANDLED; } @@ -884,10 +884,10 @@ static bool mtk_spi_mem_supports_op(struct spi_mem *mem, return true; } -static void mtk_spi_mem_setup_dma_xfer(struct spi_master *master, +static void mtk_spi_mem_setup_dma_xfer(struct spi_controller *host, const struct spi_mem_op *op) { - struct mtk_spi *mdata = spi_master_get_devdata(master); + struct mtk_spi *mdata = spi_controller_get_devdata(host); writel((u32)(mdata->tx_dma & MTK_SPI_32BITS_MASK), mdata->base + SPI_TX_SRC_REG); @@ -911,7 +911,7 @@ static void mtk_spi_mem_setup_dma_xfer(struct spi_master *master, static int mtk_spi_transfer_wait(struct spi_mem *mem, const struct spi_mem_op *op) { - struct mtk_spi *mdata = spi_master_get_devdata(mem->spi->master); + struct mtk_spi *mdata = spi_controller_get_devdata(mem->spi->controller); /* * For each byte we wait for 8 cycles of the SPI clock. * Since speed is defined in Hz and we want milliseconds, @@ -941,7 +941,7 @@ static int mtk_spi_transfer_wait(struct spi_mem *mem, static int mtk_spi_mem_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) { - struct mtk_spi *mdata = spi_master_get_devdata(mem->spi->master); + struct mtk_spi *mdata = spi_controller_get_devdata(mem->spi->controller); u32 reg_val, nio, tx_size; char *tx_tmp_buf, *rx_tmp_buf; int ret = 0; @@ -950,8 +950,8 @@ static int mtk_spi_mem_exec_op(struct spi_mem *mem, reinit_completion(&mdata->spimem_done); mtk_spi_reset(mdata); - mtk_spi_hw_init(mem->spi->master, mem->spi); - mtk_spi_prepare_transfer(mem->spi->master, mem->spi->max_speed_hz); + mtk_spi_hw_init(mem->spi->controller, mem->spi); + mtk_spi_prepare_transfer(mem->spi->controller, mem->spi->max_speed_hz); reg_val = readl(mdata->base + SPI_CFG3_IPM_REG); /* opcode byte len */ @@ -971,7 +971,7 @@ static int mtk_spi_mem_exec_op(struct spi_mem *mem, } else { reg_val &= ~SPI_CFG3_IPM_NODATA_FLAG; mdata->xfer_len = op->data.nbytes; - mtk_spi_setup_packet(mem->spi->master); + mtk_spi_setup_packet(mem->spi->controller); } if (op->addr.nbytes || op->dummy.nbytes) { @@ -1069,9 +1069,9 @@ static int mtk_spi_mem_exec_op(struct spi_mem *mem, reg_val |= SPI_CMD_RX_DMA; writel(reg_val, mdata->base + SPI_CMD_REG); - mtk_spi_mem_setup_dma_xfer(mem->spi->master, op); + mtk_spi_mem_setup_dma_xfer(mem->spi->controller, op); - mtk_spi_enable_transfer(mem->spi->master); + mtk_spi_enable_transfer(mem->spi->controller); /* Wait for the interrupt. */ ret = mtk_spi_transfer_wait(mem, op); @@ -1115,41 +1115,41 @@ static const struct spi_controller_mem_ops mtk_spi_mem_ops = { static int mtk_spi_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; - struct spi_master *master; + struct spi_controller *host; struct mtk_spi *mdata; int i, irq, ret, addr_bits; - master = devm_spi_alloc_master(dev, sizeof(*mdata)); - if (!master) - return dev_err_probe(dev, -ENOMEM, "failed to alloc spi master\n"); + host = devm_spi_alloc_host(dev, sizeof(*mdata)); + if (!host) + return dev_err_probe(dev, -ENOMEM, "failed to alloc spi host\n"); - master->auto_runtime_pm = true; - master->dev.of_node = dev->of_node; - master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST; + host->auto_runtime_pm = true; + host->dev.of_node = dev->of_node; + host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST; - master->set_cs = mtk_spi_set_cs; - master->prepare_message = mtk_spi_prepare_message; - master->transfer_one = mtk_spi_transfer_one; - master->can_dma = mtk_spi_can_dma; - master->setup = mtk_spi_setup; - master->set_cs_timing = mtk_spi_set_hw_cs_timing; - master->use_gpio_descriptors = true; + host->set_cs = mtk_spi_set_cs; + host->prepare_message = mtk_spi_prepare_message; + host->transfer_one = mtk_spi_transfer_one; + host->can_dma = mtk_spi_can_dma; + host->setup = mtk_spi_setup; + host->set_cs_timing = mtk_spi_set_hw_cs_timing; + host->use_gpio_descriptors = true; - mdata = spi_master_get_devdata(master); + mdata = spi_controller_get_devdata(host); mdata->dev_comp = device_get_match_data(dev); if (mdata->dev_comp->enhance_timing) - master->mode_bits |= SPI_CS_HIGH; + host->mode_bits |= SPI_CS_HIGH; if (mdata->dev_comp->must_tx) - master->flags = SPI_CONTROLLER_MUST_TX; + host->flags = SPI_CONTROLLER_MUST_TX; if (mdata->dev_comp->ipm_design) - master->mode_bits |= SPI_LOOP | SPI_RX_DUAL | SPI_TX_DUAL | - SPI_RX_QUAD | SPI_TX_QUAD; + host->mode_bits |= SPI_LOOP | SPI_RX_DUAL | SPI_TX_DUAL | + SPI_RX_QUAD | SPI_TX_QUAD; if (mdata->dev_comp->ipm_design) { mdata->dev = dev; - master->mem_ops = &mtk_spi_mem_ops; + host->mem_ops = &mtk_spi_mem_ops; init_completion(&mdata->spimem_done); } @@ -1176,7 +1176,7 @@ static int mtk_spi_probe(struct platform_device *pdev) } } - platform_set_drvdata(pdev, master); + platform_set_drvdata(pdev, host); mdata->base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(mdata->base)) return PTR_ERR(mdata->base); @@ -1235,12 +1235,12 @@ static int mtk_spi_probe(struct platform_device *pdev) } if (mdata->dev_comp->need_pad_sel) { - if (mdata->pad_num != master->num_chipselect) + if (mdata->pad_num != host->num_chipselect) return dev_err_probe(dev, -EINVAL, "pad_num does not match num_chipselect(%d != %d)\n", - mdata->pad_num, master->num_chipselect); + mdata->pad_num, host->num_chipselect); - if (!master->cs_gpiods && master->num_chipselect > 1) + if (!host->cs_gpiods && host->num_chipselect > 1) return dev_err_probe(dev, -EINVAL, "cs_gpios not specified and num_chipselect > 1\n"); } @@ -1255,16 +1255,16 @@ static int mtk_spi_probe(struct platform_device *pdev) addr_bits, ret); ret = devm_request_irq(dev, irq, mtk_spi_interrupt, - IRQF_TRIGGER_NONE, dev_name(dev), master); + IRQF_TRIGGER_NONE, dev_name(dev), host); if (ret) return dev_err_probe(dev, ret, "failed to register irq\n"); pm_runtime_enable(dev); - ret = devm_spi_register_master(dev, master); + ret = devm_spi_register_controller(dev, host); if (ret) { pm_runtime_disable(dev); - return dev_err_probe(dev, ret, "failed to register master\n"); + return dev_err_probe(dev, ret, "failed to register host\n"); } return 0; @@ -1272,8 +1272,8 @@ static int mtk_spi_probe(struct platform_device *pdev) static void mtk_spi_remove(struct platform_device *pdev) { - struct spi_master *master = platform_get_drvdata(pdev); - struct mtk_spi *mdata = spi_master_get_devdata(master); + struct spi_controller *host = platform_get_drvdata(pdev); + struct mtk_spi *mdata = spi_controller_get_devdata(host); int ret; if (mdata->use_spimem && !completion_done(&mdata->spimem_done)) @@ -1304,10 +1304,10 @@ static void mtk_spi_remove(struct platform_device *pdev) static int mtk_spi_suspend(struct device *dev) { int ret; - struct spi_master *master = dev_get_drvdata(dev); - struct mtk_spi *mdata = spi_master_get_devdata(master); + struct spi_controller *host = dev_get_drvdata(dev); + struct mtk_spi *mdata = spi_controller_get_devdata(host); - ret = spi_master_suspend(master); + ret = spi_controller_suspend(host); if (ret) return ret; @@ -1322,8 +1322,8 @@ static int mtk_spi_suspend(struct device *dev) static int mtk_spi_resume(struct device *dev) { int ret; - struct spi_master *master = dev_get_drvdata(dev); - struct mtk_spi *mdata = spi_master_get_devdata(master); + struct spi_controller *host = dev_get_drvdata(dev); + struct mtk_spi *mdata = spi_controller_get_devdata(host); if (!pm_runtime_suspended(dev)) { ret = clk_prepare_enable(mdata->spi_clk); @@ -1340,7 +1340,7 @@ static int mtk_spi_resume(struct device *dev) } } - ret = spi_master_resume(master); + ret = spi_controller_resume(host); if (ret < 0) { clk_disable_unprepare(mdata->spi_clk); clk_disable_unprepare(mdata->spi_hclk); @@ -1353,8 +1353,8 @@ static int mtk_spi_resume(struct device *dev) #ifdef CONFIG_PM static int mtk_spi_runtime_suspend(struct device *dev) { - struct spi_master *master = dev_get_drvdata(dev); - struct mtk_spi *mdata = spi_master_get_devdata(master); + struct spi_controller *host = dev_get_drvdata(dev); + struct mtk_spi *mdata = spi_controller_get_devdata(host); if (mdata->dev_comp->no_need_unprepare) { clk_disable(mdata->spi_clk); @@ -1369,8 +1369,8 @@ static int mtk_spi_runtime_suspend(struct device *dev) static int mtk_spi_runtime_resume(struct device *dev) { - struct spi_master *master = dev_get_drvdata(dev); - struct mtk_spi *mdata = spi_master_get_devdata(master); + struct spi_controller *host = dev_get_drvdata(dev); + struct mtk_spi *mdata = spi_controller_get_devdata(host); int ret; if (mdata->dev_comp->no_need_unprepare) { From patchwork Thu Aug 10 08:29:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yang Yingliang X-Patchwork-Id: 713163 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B31F1C05051 for ; Thu, 10 Aug 2023 08:33:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234223AbjHJIdO (ORCPT ); Thu, 10 Aug 2023 04:33:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34792 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234215AbjHJIdM (ORCPT ); Thu, 10 Aug 2023 04:33:12 -0400 Received: from szxga02-in.huawei.com (szxga02-in.huawei.com [45.249.212.188]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 80E5BE40 for ; Thu, 10 Aug 2023 01:33:11 -0700 (PDT) Received: from dggpemm500012.china.huawei.com (unknown [172.30.72.57]) by szxga02-in.huawei.com (SkyGuard) with ESMTP id 4RM0WN5WbLzTmWv; Thu, 10 Aug 2023 16:31:12 +0800 (CST) Received: from dggpemm500007.china.huawei.com (7.185.36.183) by dggpemm500012.china.huawei.com (7.185.36.89) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 10 Aug 2023 16:33:09 +0800 Received: from huawei.com (10.175.103.91) by dggpemm500007.china.huawei.com (7.185.36.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 10 Aug 2023 16:33:08 +0800 From: Yang Yingliang To: CC: , , , Subject: [PATCH -next 11/21] spi: mt7621: switch to use modern name Date: Thu, 10 Aug 2023 16:29:54 +0800 Message-ID: <20230810083004.3988597-12-yangyingliang@huawei.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230810083004.3988597-1-yangyingliang@huawei.com> References: <20230810083004.3988597-1-yangyingliang@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.175.103.91] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To dggpemm500007.china.huawei.com (7.185.36.183) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Change legacy name master/slave to modern name host/target or controller. No functional changed. Signed-off-by: Yang Yingliang --- drivers/spi/spi-mt7621.c | 70 ++++++++++++++++++++-------------------- 1 file changed, 35 insertions(+), 35 deletions(-) diff --git a/drivers/spi/spi-mt7621.c b/drivers/spi/spi-mt7621.c index 91600e5c22e4..099d5e119f0a 100644 --- a/drivers/spi/spi-mt7621.c +++ b/drivers/spi/spi-mt7621.c @@ -37,12 +37,12 @@ #define SPI_CTL_TX_RX_CNT_MASK 0xff #define SPI_CTL_START BIT(8) -#define MT7621_SPI_MASTER 0x28 -#define MASTER_MORE_BUFMODE BIT(2) -#define MASTER_FULL_DUPLEX BIT(10) -#define MASTER_RS_CLK_SEL GENMASK(27, 16) -#define MASTER_RS_CLK_SEL_SHIFT 16 -#define MASTER_RS_SLAVE_SEL GENMASK(31, 29) +#define MT7621_SPI_HOST 0x28 +#define HOST_MORE_BUFMODE BIT(2) +#define HOST_FULL_DUPLEX BIT(10) +#define HOST_RS_CLK_SEL GENMASK(27, 16) +#define HOST_RS_CLK_SEL_SHIFT 16 +#define HOST_RS_TARGET_SEL GENMASK(31, 29) #define MT7621_SPI_MOREBUF 0x2c #define MT7621_SPI_POLAR 0x38 @@ -53,7 +53,7 @@ #define MT7621_LSB_FIRST BIT(3) struct mt7621_spi { - struct spi_controller *master; + struct spi_controller *host; void __iomem *base; unsigned int sys_freq; unsigned int speed; @@ -62,7 +62,7 @@ struct mt7621_spi { static inline struct mt7621_spi *spidev_to_mt7621_spi(struct spi_device *spi) { - return spi_controller_get_devdata(spi->master); + return spi_controller_get_devdata(spi->controller); } static inline u32 mt7621_spi_read(struct mt7621_spi *rs, u32 reg) @@ -80,17 +80,17 @@ static void mt7621_spi_set_cs(struct spi_device *spi, int enable) struct mt7621_spi *rs = spidev_to_mt7621_spi(spi); int cs = spi_get_chipselect(spi, 0); u32 polar = 0; - u32 master; + u32 host; /* * Select SPI device 7, enable "more buffer mode" and disable * full-duplex (only half-duplex really works on this chip * reliably) */ - master = mt7621_spi_read(rs, MT7621_SPI_MASTER); - master |= MASTER_RS_SLAVE_SEL | MASTER_MORE_BUFMODE; - master &= ~MASTER_FULL_DUPLEX; - mt7621_spi_write(rs, MT7621_SPI_MASTER, master); + host = mt7621_spi_read(rs, MT7621_SPI_HOST); + host |= HOST_RS_TARGET_SEL | HOST_MORE_BUFMODE; + host &= ~HOST_FULL_DUPLEX; + mt7621_spi_write(rs, MT7621_SPI_HOST, host); rs->pending_write = 0; @@ -116,9 +116,9 @@ static int mt7621_spi_prepare(struct spi_device *spi, unsigned int speed) if (rate < 2) rate = 2; - reg = mt7621_spi_read(rs, MT7621_SPI_MASTER); - reg &= ~MASTER_RS_CLK_SEL; - reg |= (rate - 2) << MASTER_RS_CLK_SEL_SHIFT; + reg = mt7621_spi_read(rs, MT7621_SPI_HOST); + reg &= ~HOST_RS_CLK_SEL; + reg |= (rate - 2) << HOST_RS_CLK_SEL_SHIFT; rs->speed = speed; reg &= ~MT7621_LSB_FIRST; @@ -132,7 +132,7 @@ static int mt7621_spi_prepare(struct spi_device *spi, unsigned int speed) */ reg &= ~(MT7621_CPHA | MT7621_CPOL); - mt7621_spi_write(rs, MT7621_SPI_MASTER, reg); + mt7621_spi_write(rs, MT7621_SPI_HOST, reg); return 0; } @@ -245,10 +245,10 @@ static void mt7621_spi_write_half_duplex(struct mt7621_spi *rs, rs->pending_write = len; } -static int mt7621_spi_transfer_one_message(struct spi_controller *master, +static int mt7621_spi_transfer_one_message(struct spi_controller *host, struct spi_message *m) { - struct mt7621_spi *rs = spi_controller_get_devdata(master); + struct mt7621_spi *rs = spi_controller_get_devdata(host); struct spi_device *spi = m->spi; unsigned int speed = spi->max_speed_hz; struct spi_transfer *t = NULL; @@ -294,7 +294,7 @@ static int mt7621_spi_transfer_one_message(struct spi_controller *master, msg_done: m->status = status; - spi_finalize_current_message(master); + spi_finalize_current_message(host); return 0; } @@ -325,7 +325,7 @@ MODULE_DEVICE_TABLE(of, mt7621_spi_match); static int mt7621_spi_probe(struct platform_device *pdev) { const struct of_device_id *match; - struct spi_controller *master; + struct spi_controller *host; struct mt7621_spi *rs; void __iomem *base; struct clk *clk; @@ -344,25 +344,25 @@ static int mt7621_spi_probe(struct platform_device *pdev) return dev_err_probe(&pdev->dev, PTR_ERR(clk), "unable to get SYS clock\n"); - master = devm_spi_alloc_master(&pdev->dev, sizeof(*rs)); - if (!master) { - dev_info(&pdev->dev, "master allocation failed\n"); + host = devm_spi_alloc_host(&pdev->dev, sizeof(*rs)); + if (!host) { + dev_info(&pdev->dev, "host allocation failed\n"); return -ENOMEM; } - master->mode_bits = SPI_LSB_FIRST; - master->flags = SPI_CONTROLLER_HALF_DUPLEX; - master->setup = mt7621_spi_setup; - master->transfer_one_message = mt7621_spi_transfer_one_message; - master->bits_per_word_mask = SPI_BPW_MASK(8); - master->dev.of_node = pdev->dev.of_node; - master->num_chipselect = 2; + host->mode_bits = SPI_LSB_FIRST; + host->flags = SPI_CONTROLLER_HALF_DUPLEX; + host->setup = mt7621_spi_setup; + host->transfer_one_message = mt7621_spi_transfer_one_message; + host->bits_per_word_mask = SPI_BPW_MASK(8); + host->dev.of_node = pdev->dev.of_node; + host->num_chipselect = 2; - dev_set_drvdata(&pdev->dev, master); + dev_set_drvdata(&pdev->dev, host); - rs = spi_controller_get_devdata(master); + rs = spi_controller_get_devdata(host); rs->base = base; - rs->master = master; + rs->host = host; rs->sys_freq = clk_get_rate(clk); rs->pending_write = 0; dev_info(&pdev->dev, "sys_freq: %u\n", rs->sys_freq); @@ -373,7 +373,7 @@ static int mt7621_spi_probe(struct platform_device *pdev) return ret; } - return devm_spi_register_controller(&pdev->dev, master); + return devm_spi_register_controller(&pdev->dev, host); } MODULE_ALIAS("platform:" DRIVER_NAME); From patchwork Thu Aug 10 08:29:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yang Yingliang X-Patchwork-Id: 713166 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 83DB5C04A94 for ; Thu, 10 Aug 2023 08:33:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234219AbjHJIdN (ORCPT ); Thu, 10 Aug 2023 04:33:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34770 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234212AbjHJIdM (ORCPT ); Thu, 10 Aug 2023 04:33:12 -0400 Received: from szxga08-in.huawei.com (szxga08-in.huawei.com [45.249.212.255]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 97F7210CF for ; Thu, 10 Aug 2023 01:33:11 -0700 (PDT) Received: from dggpemm500009.china.huawei.com (unknown [172.30.72.57]) by szxga08-in.huawei.com (SkyGuard) with ESMTP id 4RM0XF1twlz1L9kL; Thu, 10 Aug 2023 16:31:57 +0800 (CST) Received: from dggpemm500007.china.huawei.com (7.185.36.183) by dggpemm500009.china.huawei.com (7.185.36.225) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 10 Aug 2023 16:33:09 +0800 Received: from huawei.com (10.175.103.91) by dggpemm500007.china.huawei.com (7.185.36.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 10 Aug 2023 16:33:09 +0800 From: Yang Yingliang To: CC: , , , Subject: [PATCH -next 12/21] spi: mtk-nor: switch to use modern name Date: Thu, 10 Aug 2023 16:29:55 +0800 Message-ID: <20230810083004.3988597-13-yangyingliang@huawei.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230810083004.3988597-1-yangyingliang@huawei.com> References: <20230810083004.3988597-1-yangyingliang@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.175.103.91] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To dggpemm500007.china.huawei.com (7.185.36.183) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Change legacy name master to modern name host or controller. No functional changed. Signed-off-by: Yang Yingliang --- drivers/spi/spi-mtk-nor.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/spi/spi-mtk-nor.c b/drivers/spi/spi-mtk-nor.c index cf4ee8b19e42..62b1c8995fa4 100644 --- a/drivers/spi/spi-mtk-nor.c +++ b/drivers/spi/spi-mtk-nor.c @@ -275,7 +275,7 @@ static void mtk_nor_adj_prg_size(struct spi_mem_op *op) static int mtk_nor_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op) { - struct mtk_nor *sp = spi_controller_get_devdata(mem->spi->master); + struct mtk_nor *sp = spi_controller_get_devdata(mem->spi->controller); if (!op->data.nbytes) return 0; @@ -598,7 +598,7 @@ static int mtk_nor_spi_mem_prg(struct mtk_nor *sp, const struct spi_mem_op *op) static int mtk_nor_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) { - struct mtk_nor *sp = spi_controller_get_devdata(mem->spi->master); + struct mtk_nor *sp = spi_controller_get_devdata(mem->spi->controller); int ret; if ((op->data.nbytes == 0) || @@ -639,7 +639,7 @@ static int mtk_nor_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) static int mtk_nor_setup(struct spi_device *spi) { - struct mtk_nor *sp = spi_controller_get_devdata(spi->master); + struct mtk_nor *sp = spi_controller_get_devdata(spi->controller); if (spi->max_speed_hz && (spi->max_speed_hz < sp->spi_freq)) { dev_err(&spi->dev, "spi clock should be %u Hz.\n", @@ -651,10 +651,10 @@ static int mtk_nor_setup(struct spi_device *spi) return 0; } -static int mtk_nor_transfer_one_message(struct spi_controller *master, +static int mtk_nor_transfer_one_message(struct spi_controller *host, struct spi_message *m) { - struct mtk_nor *sp = spi_controller_get_devdata(master); + struct mtk_nor *sp = spi_controller_get_devdata(host); struct spi_transfer *t = NULL; unsigned long trx_len = 0; int stat = 0; @@ -696,7 +696,7 @@ static int mtk_nor_transfer_one_message(struct spi_controller *master, m->actual_length = trx_len; msg_done: m->status = stat; - spi_finalize_current_message(master); + spi_finalize_current_message(host); return 0; } @@ -844,7 +844,7 @@ static int mtk_nor_probe(struct platform_device *pdev) return ret; } - ctlr = devm_spi_alloc_master(&pdev->dev, sizeof(*sp)); + ctlr = devm_spi_alloc_host(&pdev->dev, sizeof(*sp)); if (!ctlr) { dev_err(&pdev->dev, "failed to allocate spi controller\n"); return -ENOMEM; From patchwork Thu Aug 10 08:29:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yang Yingliang X-Patchwork-Id: 712573 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4B878C04E69 for ; Thu, 10 Aug 2023 08:33:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234225AbjHJIdO (ORCPT ); Thu, 10 Aug 2023 04:33:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34808 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234212AbjHJIdN (ORCPT ); Thu, 10 Aug 2023 04:33:13 -0400 Received: from szxga01-in.huawei.com (szxga01-in.huawei.com [45.249.212.187]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CCE8DE56 for ; Thu, 10 Aug 2023 01:33:11 -0700 (PDT) Received: from dggpemm500003.china.huawei.com (unknown [172.30.72.56]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4RM0XD6YzXzkX9R; Thu, 10 Aug 2023 16:31:56 +0800 (CST) Received: from dggpemm500007.china.huawei.com (7.185.36.183) by dggpemm500003.china.huawei.com (7.185.36.56) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 10 Aug 2023 16:33:09 +0800 Received: from huawei.com (10.175.103.91) by dggpemm500007.china.huawei.com (7.185.36.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 10 Aug 2023 16:33:09 +0800 From: Yang Yingliang To: CC: , , , Subject: [PATCH -next 13/21] spi: mtk-snfi: switch to use modern name Date: Thu, 10 Aug 2023 16:29:56 +0800 Message-ID: <20230810083004.3988597-14-yangyingliang@huawei.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230810083004.3988597-1-yangyingliang@huawei.com> References: <20230810083004.3988597-1-yangyingliang@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.175.103.91] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To dggpemm500007.china.huawei.com (7.185.36.183) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Change legacy name master to modern name host or controller. No functional changed. Signed-off-by: Yang Yingliang --- drivers/spi/spi-mtk-snfi.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/spi/spi-mtk-snfi.c b/drivers/spi/spi-mtk-snfi.c index 4433a8a9299f..43659014bef8 100644 --- a/drivers/spi/spi-mtk-snfi.c +++ b/drivers/spi/spi-mtk-snfi.c @@ -1255,7 +1255,7 @@ static bool mtk_snand_supports_op(struct spi_mem *mem, static int mtk_snand_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op) { - struct mtk_snand *ms = spi_controller_get_devdata(mem->spi->master); + struct mtk_snand *ms = spi_controller_get_devdata(mem->spi->controller); // page ops transfer size must be exactly ((sector_size + spare_size) * // nsectors). Limit the op size if the caller requests more than that. // exec_op will read more than needed and discard the leftover if the @@ -1282,7 +1282,7 @@ static int mtk_snand_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op) static int mtk_snand_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) { - struct mtk_snand *ms = spi_controller_get_devdata(mem->spi->master); + struct mtk_snand *ms = spi_controller_get_devdata(mem->spi->controller); dev_dbg(ms->dev, "OP %02x ADDR %08llX@%d:%u DATA %d:%u", op->cmd.opcode, op->addr.val, op->addr.buswidth, op->addr.nbytes, @@ -1382,7 +1382,7 @@ static int mtk_snand_probe(struct platform_device *pdev) if (!dev_id) return -EINVAL; - ctlr = devm_spi_alloc_master(&pdev->dev, sizeof(*ms)); + ctlr = devm_spi_alloc_host(&pdev->dev, sizeof(*ms)); if (!ctlr) return -ENOMEM; platform_set_drvdata(pdev, ctlr); From patchwork Thu Aug 10 08:29:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yang Yingliang X-Patchwork-Id: 712572 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 16D76C04FDF for ; Thu, 10 Aug 2023 08:33:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234224AbjHJIdO (ORCPT ); Thu, 10 Aug 2023 04:33:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34806 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234218AbjHJIdM (ORCPT ); Thu, 10 Aug 2023 04:33:12 -0400 Received: from szxga01-in.huawei.com (szxga01-in.huawei.com [45.249.212.187]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3D87710DE for ; Thu, 10 Aug 2023 01:33:12 -0700 (PDT) Received: from dggpemm500013.china.huawei.com (unknown [172.30.72.54]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4RM0Tc0sW2ztSG6; Thu, 10 Aug 2023 16:29:40 +0800 (CST) Received: from dggpemm500007.china.huawei.com (7.185.36.183) by dggpemm500013.china.huawei.com (7.185.36.172) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 10 Aug 2023 16:33:10 +0800 Received: from huawei.com (10.175.103.91) by dggpemm500007.china.huawei.com (7.185.36.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 10 Aug 2023 16:33:09 +0800 From: Yang Yingliang To: CC: , , , Subject: [PATCH -next 14/21] spi: mux: switch to use spi_alloc_host() Date: Thu, 10 Aug 2023 16:29:57 +0800 Message-ID: <20230810083004.3988597-15-yangyingliang@huawei.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230810083004.3988597-1-yangyingliang@huawei.com> References: <20230810083004.3988597-1-yangyingliang@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.175.103.91] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To dggpemm500007.china.huawei.com (7.185.36.183) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Switch to use modern name function spi_alloc_host(). No functional changed. Signed-off-by: Yang Yingliang --- drivers/spi/spi-mux.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/spi/spi-mux.c b/drivers/spi/spi-mux.c index fa8c1f740c70..bd988f53753e 100644 --- a/drivers/spi/spi-mux.c +++ b/drivers/spi/spi-mux.c @@ -129,7 +129,7 @@ static int spi_mux_probe(struct spi_device *spi) struct spi_mux_priv *priv; int ret; - ctlr = spi_alloc_master(&spi->dev, sizeof(*priv)); + ctlr = spi_alloc_host(&spi->dev, sizeof(*priv)); if (!ctlr) return -ENOMEM; From patchwork Thu Aug 10 08:29:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yang Yingliang X-Patchwork-Id: 712571 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 028A3C001DB for ; Thu, 10 Aug 2023 08:33:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234212AbjHJIdP (ORCPT ); Thu, 10 Aug 2023 04:33:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34824 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234222AbjHJIdN (ORCPT ); Thu, 10 Aug 2023 04:33:13 -0400 Received: from szxga02-in.huawei.com (szxga02-in.huawei.com [45.249.212.188]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AE08EE7E for ; Thu, 10 Aug 2023 01:33:12 -0700 (PDT) Received: from dggpemm500005.china.huawei.com (unknown [172.30.72.55]) by szxga02-in.huawei.com (SkyGuard) with ESMTP id 4RM0Td4kSfzJsg6; Thu, 10 Aug 2023 16:29:41 +0800 (CST) Received: from dggpemm500007.china.huawei.com (7.185.36.183) by dggpemm500005.china.huawei.com (7.185.36.74) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 10 Aug 2023 16:33:10 +0800 Received: from huawei.com (10.175.103.91) by dggpemm500007.china.huawei.com (7.185.36.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 10 Aug 2023 16:33:10 +0800 From: Yang Yingliang To: CC: , , , Subject: [PATCH -next 15/21] spi: mxic: switch to use modern name Date: Thu, 10 Aug 2023 16:29:58 +0800 Message-ID: <20230810083004.3988597-16-yangyingliang@huawei.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230810083004.3988597-1-yangyingliang@huawei.com> References: <20230810083004.3988597-1-yangyingliang@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.175.103.91] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To dggpemm500007.china.huawei.com (7.185.36.183) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Change legacy name master to modern name host or controller. No functional changed. Signed-off-by: Yang Yingliang --- drivers/spi/spi-mxic.c | 68 +++++++++++++++++++++--------------------- 1 file changed, 34 insertions(+), 34 deletions(-) diff --git a/drivers/spi/spi-mxic.c b/drivers/spi/spi-mxic.c index 00617fd4b2c3..60c9f3048ac9 100644 --- a/drivers/spi/spi-mxic.c +++ b/drivers/spi/spi-mxic.c @@ -390,7 +390,7 @@ static int mxic_spi_data_xfer(struct mxic_spi *mxic, const void *txbuf, static ssize_t mxic_spi_mem_dirmap_read(struct spi_mem_dirmap_desc *desc, u64 offs, size_t len, void *buf) { - struct mxic_spi *mxic = spi_master_get_devdata(desc->mem->spi->master); + struct mxic_spi *mxic = spi_controller_get_devdata(desc->mem->spi->controller); int ret; u32 sts; @@ -434,7 +434,7 @@ static ssize_t mxic_spi_mem_dirmap_write(struct spi_mem_dirmap_desc *desc, u64 offs, size_t len, const void *buf) { - struct mxic_spi *mxic = spi_master_get_devdata(desc->mem->spi->master); + struct mxic_spi *mxic = spi_controller_get_devdata(desc->mem->spi->controller); u32 sts; int ret; @@ -493,7 +493,7 @@ static bool mxic_spi_mem_supports_op(struct spi_mem *mem, static int mxic_spi_mem_dirmap_create(struct spi_mem_dirmap_desc *desc) { - struct mxic_spi *mxic = spi_master_get_devdata(desc->mem->spi->master); + struct mxic_spi *mxic = spi_controller_get_devdata(desc->mem->spi->controller); if (!mxic->linear.map) return -EINVAL; @@ -510,7 +510,7 @@ static int mxic_spi_mem_dirmap_create(struct spi_mem_dirmap_desc *desc) static int mxic_spi_mem_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) { - struct mxic_spi *mxic = spi_master_get_devdata(mem->spi->master); + struct mxic_spi *mxic = spi_controller_get_devdata(mem->spi->controller); int i, ret; u8 addr[8], cmd[2]; @@ -577,7 +577,7 @@ static const struct spi_controller_mem_caps mxic_spi_mem_caps = { static void mxic_spi_set_cs(struct spi_device *spi, bool lvl) { - struct mxic_spi *mxic = spi_master_get_devdata(spi->master); + struct mxic_spi *mxic = spi_controller_get_devdata(spi->controller); if (!lvl) { writel(readl(mxic->regs + HC_CFG) | HC_CFG_MAN_CS_EN, @@ -592,11 +592,11 @@ static void mxic_spi_set_cs(struct spi_device *spi, bool lvl) } } -static int mxic_spi_transfer_one(struct spi_master *master, +static int mxic_spi_transfer_one(struct spi_controller *host, struct spi_device *spi, struct spi_transfer *t) { - struct mxic_spi *mxic = spi_master_get_devdata(master); + struct mxic_spi *mxic = spi_controller_get_devdata(host); unsigned int busw = OP_BUSW_1; int ret; @@ -632,7 +632,7 @@ static int mxic_spi_transfer_one(struct spi_master *master, if (ret) return ret; - spi_finalize_current_transfer(master); + spi_finalize_current_transfer(host); return 0; } @@ -713,8 +713,8 @@ static int mxic_spi_mem_ecc_probe(struct platform_device *pdev, static int __maybe_unused mxic_spi_runtime_suspend(struct device *dev) { - struct spi_master *master = dev_get_drvdata(dev); - struct mxic_spi *mxic = spi_master_get_devdata(master); + struct spi_controller *host = dev_get_drvdata(dev); + struct mxic_spi *mxic = spi_controller_get_devdata(host); mxic_spi_clk_disable(mxic); clk_disable_unprepare(mxic->ps_clk); @@ -724,8 +724,8 @@ static int __maybe_unused mxic_spi_runtime_suspend(struct device *dev) static int __maybe_unused mxic_spi_runtime_resume(struct device *dev) { - struct spi_master *master = dev_get_drvdata(dev); - struct mxic_spi *mxic = spi_master_get_devdata(master); + struct spi_controller *host = dev_get_drvdata(dev); + struct mxic_spi *mxic = spi_controller_get_devdata(host); int ret; ret = clk_prepare_enable(mxic->ps_clk); @@ -744,21 +744,21 @@ static const struct dev_pm_ops mxic_spi_dev_pm_ops = { static int mxic_spi_probe(struct platform_device *pdev) { - struct spi_master *master; + struct spi_controller *host; struct resource *res; struct mxic_spi *mxic; int ret; - master = devm_spi_alloc_master(&pdev->dev, sizeof(struct mxic_spi)); - if (!master) + host = devm_spi_alloc_host(&pdev->dev, sizeof(struct mxic_spi)); + if (!host) return -ENOMEM; - platform_set_drvdata(pdev, master); + platform_set_drvdata(pdev, host); - mxic = spi_master_get_devdata(master); + mxic = spi_controller_get_devdata(host); mxic->dev = &pdev->dev; - master->dev.of_node = pdev->dev.of_node; + host->dev.of_node = pdev->dev.of_node; mxic->ps_clk = devm_clk_get(&pdev->dev, "ps_clk"); if (IS_ERR(mxic->ps_clk)) @@ -786,19 +786,19 @@ static int mxic_spi_probe(struct platform_device *pdev) } pm_runtime_enable(&pdev->dev); - master->auto_runtime_pm = true; + host->auto_runtime_pm = true; - master->num_chipselect = 1; - master->mem_ops = &mxic_spi_mem_ops; - master->mem_caps = &mxic_spi_mem_caps; + host->num_chipselect = 1; + host->mem_ops = &mxic_spi_mem_ops; + host->mem_caps = &mxic_spi_mem_caps; - master->set_cs = mxic_spi_set_cs; - master->transfer_one = mxic_spi_transfer_one; - master->bits_per_word_mask = SPI_BPW_MASK(8); - master->mode_bits = SPI_CPOL | SPI_CPHA | - SPI_RX_DUAL | SPI_TX_DUAL | - SPI_RX_QUAD | SPI_TX_QUAD | - SPI_RX_OCTAL | SPI_TX_OCTAL; + host->set_cs = mxic_spi_set_cs; + host->transfer_one = mxic_spi_transfer_one; + host->bits_per_word_mask = SPI_BPW_MASK(8); + host->mode_bits = SPI_CPOL | SPI_CPHA | + SPI_RX_DUAL | SPI_TX_DUAL | + SPI_RX_QUAD | SPI_TX_QUAD | + SPI_RX_OCTAL | SPI_TX_OCTAL; mxic_spi_hw_init(mxic); @@ -808,9 +808,9 @@ static int mxic_spi_probe(struct platform_device *pdev) return ret; } - ret = spi_register_master(master); + ret = spi_register_controller(host); if (ret) { - dev_err(&pdev->dev, "spi_register_master failed\n"); + dev_err(&pdev->dev, "spi_register_controller failed\n"); pm_runtime_disable(&pdev->dev); mxic_spi_mem_ecc_remove(mxic); } @@ -820,12 +820,12 @@ static int mxic_spi_probe(struct platform_device *pdev) static void mxic_spi_remove(struct platform_device *pdev) { - struct spi_master *master = platform_get_drvdata(pdev); - struct mxic_spi *mxic = spi_master_get_devdata(master); + struct spi_controller *host = platform_get_drvdata(pdev); + struct mxic_spi *mxic = spi_controller_get_devdata(host); pm_runtime_disable(&pdev->dev); mxic_spi_mem_ecc_remove(mxic); - spi_unregister_master(master); + spi_unregister_controller(host); } static const struct of_device_id mxic_spi_of_ids[] = { From patchwork Thu Aug 10 08:29:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yang Yingliang X-Patchwork-Id: 713162 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 40900C04A94 for ; Thu, 10 Aug 2023 08:33:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234230AbjHJIdP (ORCPT ); Thu, 10 Aug 2023 04:33:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34838 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234216AbjHJIdO (ORCPT ); Thu, 10 Aug 2023 04:33:14 -0400 Received: from szxga03-in.huawei.com (szxga03-in.huawei.com [45.249.212.189]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 343F8E40 for ; Thu, 10 Aug 2023 01:33:13 -0700 (PDT) Received: from dggpemm500010.china.huawei.com (unknown [172.30.72.55]) by szxga03-in.huawei.com (SkyGuard) with ESMTP id 4RM0VN0tzNzqSr6; Thu, 10 Aug 2023 16:30:20 +0800 (CST) Received: from dggpemm500007.china.huawei.com (7.185.36.183) by dggpemm500010.china.huawei.com (7.185.36.134) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 10 Aug 2023 16:33:11 +0800 Received: from huawei.com (10.175.103.91) by dggpemm500007.china.huawei.com (7.185.36.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 10 Aug 2023 16:33:10 +0800 From: Yang Yingliang To: CC: , , , Subject: [PATCH -next 16/21] spi: mxs: switch to use modern name Date: Thu, 10 Aug 2023 16:29:59 +0800 Message-ID: <20230810083004.3988597-17-yangyingliang@huawei.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230810083004.3988597-1-yangyingliang@huawei.com> References: <20230810083004.3988597-1-yangyingliang@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.175.103.91] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To dggpemm500007.china.huawei.com (7.185.36.183) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Change legacy name master to modern name host or controller. No functional changed. Signed-off-by: Yang Yingliang --- drivers/spi/spi-mxs.c | 70 +++++++++++++++++++++---------------------- 1 file changed, 35 insertions(+), 35 deletions(-) diff --git a/drivers/spi/spi-mxs.c b/drivers/spi/spi-mxs.c index cd0e7ae07162..1bf080339b5a 100644 --- a/drivers/spi/spi-mxs.c +++ b/drivers/spi/spi-mxs.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ // -// Freescale MXS SPI master driver +// Freescale MXS SPI host driver // // Copyright 2012 DENX Software Engineering, GmbH. // Copyright 2012 Freescale Semiconductor, Inc. @@ -63,7 +63,7 @@ struct mxs_spi { static int mxs_spi_setup_transfer(struct spi_device *dev, const struct spi_transfer *t) { - struct mxs_spi *spi = spi_master_get_devdata(dev->master); + struct mxs_spi *spi = spi_controller_get_devdata(dev->controller); struct mxs_ssp *ssp = &spi->ssp; const unsigned int hz = min(dev->max_speed_hz, t->speed_hz); @@ -357,10 +357,10 @@ static int mxs_spi_txrx_pio(struct mxs_spi *spi, return -ETIMEDOUT; } -static int mxs_spi_transfer_one(struct spi_master *master, +static int mxs_spi_transfer_one(struct spi_controller *host, struct spi_message *m) { - struct mxs_spi *spi = spi_master_get_devdata(master); + struct mxs_spi *spi = spi_controller_get_devdata(host); struct mxs_ssp *ssp = &spi->ssp; struct spi_transfer *t; unsigned int flag; @@ -432,15 +432,15 @@ static int mxs_spi_transfer_one(struct spi_master *master, } m->status = status; - spi_finalize_current_message(master); + spi_finalize_current_message(host); return status; } static int mxs_spi_runtime_suspend(struct device *dev) { - struct spi_master *master = dev_get_drvdata(dev); - struct mxs_spi *spi = spi_master_get_devdata(master); + struct spi_controller *host = dev_get_drvdata(dev); + struct mxs_spi *spi = spi_controller_get_devdata(host); struct mxs_ssp *ssp = &spi->ssp; int ret; @@ -460,8 +460,8 @@ static int mxs_spi_runtime_suspend(struct device *dev) static int mxs_spi_runtime_resume(struct device *dev) { - struct spi_master *master = dev_get_drvdata(dev); - struct mxs_spi *spi = spi_master_get_devdata(master); + struct spi_controller *host = dev_get_drvdata(dev); + struct mxs_spi *spi = spi_controller_get_devdata(host); struct mxs_ssp *ssp = &spi->ssp; int ret; @@ -478,10 +478,10 @@ static int mxs_spi_runtime_resume(struct device *dev) static int __maybe_unused mxs_spi_suspend(struct device *dev) { - struct spi_master *master = dev_get_drvdata(dev); + struct spi_controller *host = dev_get_drvdata(dev); int ret; - ret = spi_master_suspend(master); + ret = spi_controller_suspend(host); if (ret) return ret; @@ -493,7 +493,7 @@ static int __maybe_unused mxs_spi_suspend(struct device *dev) static int __maybe_unused mxs_spi_resume(struct device *dev) { - struct spi_master *master = dev_get_drvdata(dev); + struct spi_controller *host = dev_get_drvdata(dev); int ret; if (!pm_runtime_suspended(dev)) @@ -503,7 +503,7 @@ static int __maybe_unused mxs_spi_resume(struct device *dev) if (ret) return ret; - ret = spi_master_resume(master); + ret = spi_controller_resume(host); if (ret < 0 && !pm_runtime_suspended(dev)) mxs_spi_runtime_suspend(dev); @@ -528,7 +528,7 @@ static int mxs_spi_probe(struct platform_device *pdev) const struct of_device_id *of_id = of_match_device(mxs_spi_dt_ids, &pdev->dev); struct device_node *np = pdev->dev.of_node; - struct spi_master *master; + struct spi_controller *host; struct mxs_spi *spi; struct mxs_ssp *ssp; struct clk *clk; @@ -561,21 +561,21 @@ static int mxs_spi_probe(struct platform_device *pdev) if (ret) clk_freq = clk_freq_default; - master = spi_alloc_master(&pdev->dev, sizeof(*spi)); - if (!master) + host = spi_alloc_host(&pdev->dev, sizeof(*spi)); + if (!host) return -ENOMEM; - platform_set_drvdata(pdev, master); + platform_set_drvdata(pdev, host); - master->transfer_one_message = mxs_spi_transfer_one; - master->bits_per_word_mask = SPI_BPW_MASK(8); - master->mode_bits = SPI_CPOL | SPI_CPHA; - master->num_chipselect = 3; - master->dev.of_node = np; - master->flags = SPI_CONTROLLER_HALF_DUPLEX; - master->auto_runtime_pm = true; + host->transfer_one_message = mxs_spi_transfer_one; + host->bits_per_word_mask = SPI_BPW_MASK(8); + host->mode_bits = SPI_CPOL | SPI_CPHA; + host->num_chipselect = 3; + host->dev.of_node = np; + host->flags = SPI_CONTROLLER_HALF_DUPLEX; + host->auto_runtime_pm = true; - spi = spi_master_get_devdata(master); + spi = spi_controller_get_devdata(host); ssp = &spi->ssp; ssp->dev = &pdev->dev; ssp->clk = clk; @@ -587,13 +587,13 @@ static int mxs_spi_probe(struct platform_device *pdev) ret = devm_request_irq(&pdev->dev, irq_err, mxs_ssp_irq_handler, 0, dev_name(&pdev->dev), ssp); if (ret) - goto out_master_free; + goto out_host_free; ssp->dmach = dma_request_chan(&pdev->dev, "rx-tx"); if (IS_ERR(ssp->dmach)) { dev_err(ssp->dev, "Failed to request DMA\n"); ret = PTR_ERR(ssp->dmach); - goto out_master_free; + goto out_host_free; } pm_runtime_enable(ssp->dev); @@ -617,9 +617,9 @@ static int mxs_spi_probe(struct platform_device *pdev) if (ret) goto out_pm_runtime_put; - ret = devm_spi_register_master(&pdev->dev, master); + ret = devm_spi_register_controller(&pdev->dev, host); if (ret) { - dev_err(&pdev->dev, "Cannot register SPI master, %d\n", ret); + dev_err(&pdev->dev, "Cannot register SPI host, %d\n", ret); goto out_pm_runtime_put; } @@ -633,19 +633,19 @@ static int mxs_spi_probe(struct platform_device *pdev) pm_runtime_disable(ssp->dev); out_dma_release: dma_release_channel(ssp->dmach); -out_master_free: - spi_master_put(master); +out_host_free: + spi_controller_put(host); return ret; } static void mxs_spi_remove(struct platform_device *pdev) { - struct spi_master *master; + struct spi_controller *host; struct mxs_spi *spi; struct mxs_ssp *ssp; - master = platform_get_drvdata(pdev); - spi = spi_master_get_devdata(master); + host = platform_get_drvdata(pdev); + spi = spi_controller_get_devdata(host); ssp = &spi->ssp; pm_runtime_disable(&pdev->dev); @@ -668,6 +668,6 @@ static struct platform_driver mxs_spi_driver = { module_platform_driver(mxs_spi_driver); MODULE_AUTHOR("Marek Vasut "); -MODULE_DESCRIPTION("MXS SPI master driver"); +MODULE_DESCRIPTION("MXS SPI host driver"); MODULE_LICENSE("GPL"); MODULE_ALIAS("platform:mxs-spi"); From patchwork Thu Aug 10 08:30:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yang Yingliang X-Patchwork-Id: 713160 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 75568C001DE for ; Thu, 10 Aug 2023 08:33:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234216AbjHJIdQ (ORCPT ); Thu, 10 Aug 2023 04:33:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34872 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234218AbjHJIdO (ORCPT ); Thu, 10 Aug 2023 04:33:14 -0400 Received: from szxga01-in.huawei.com (szxga01-in.huawei.com [45.249.212.187]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 78CA3E64 for ; Thu, 10 Aug 2023 01:33:13 -0700 (PDT) Received: from dggpemm500011.china.huawei.com (unknown [172.30.72.55]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4RM0Td24X7ztSGZ; Thu, 10 Aug 2023 16:29:41 +0800 (CST) Received: from dggpemm500007.china.huawei.com (7.185.36.183) by dggpemm500011.china.huawei.com (7.185.36.110) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 10 Aug 2023 16:33:11 +0800 Received: from huawei.com (10.175.103.91) by dggpemm500007.china.huawei.com (7.185.36.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 10 Aug 2023 16:33:10 +0800 From: Yang Yingliang To: CC: , , , Subject: [PATCH -next 17/21] spi: npcm-pspi: switch to use modern name Date: Thu, 10 Aug 2023 16:30:00 +0800 Message-ID: <20230810083004.3988597-18-yangyingliang@huawei.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230810083004.3988597-1-yangyingliang@huawei.com> References: <20230810083004.3988597-1-yangyingliang@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.175.103.91] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To dggpemm500007.china.huawei.com (7.185.36.183) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Change legacy name master to modern name host or controller. No functional changed. Signed-off-by: Yang Yingliang --- drivers/spi/spi-npcm-pspi.c | 68 ++++++++++++++++++------------------- 1 file changed, 34 insertions(+), 34 deletions(-) diff --git a/drivers/spi/spi-npcm-pspi.c b/drivers/spi/spi-npcm-pspi.c index 64585c2a25c5..a7feb20b06ee 100644 --- a/drivers/spi/spi-npcm-pspi.c +++ b/drivers/spi/spi-npcm-pspi.c @@ -20,7 +20,7 @@ struct npcm_pspi { struct completion xfer_done; struct reset_control *reset; - struct spi_master *master; + struct spi_controller *host; unsigned int tx_bytes; unsigned int rx_bytes; void __iomem *base; @@ -101,7 +101,7 @@ static inline void npcm_pspi_disable(struct npcm_pspi *priv) static void npcm_pspi_set_mode(struct spi_device *spi) { - struct npcm_pspi *priv = spi_master_get_devdata(spi->master); + struct npcm_pspi *priv = spi_controller_get_devdata(spi->controller); u16 regtemp; u16 mode_val; @@ -159,7 +159,7 @@ static void npcm_pspi_set_baudrate(struct npcm_pspi *priv, unsigned int speed) static void npcm_pspi_setup_transfer(struct spi_device *spi, struct spi_transfer *t) { - struct npcm_pspi *priv = spi_master_get_devdata(spi->master); + struct npcm_pspi *priv = spi_controller_get_devdata(spi->controller); priv->tx_buf = t->tx_buf; priv->rx_buf = t->rx_buf; @@ -245,11 +245,11 @@ static void npcm_pspi_recv(struct npcm_pspi *priv) } } -static int npcm_pspi_transfer_one(struct spi_master *master, +static int npcm_pspi_transfer_one(struct spi_controller *host, struct spi_device *spi, struct spi_transfer *t) { - struct npcm_pspi *priv = spi_master_get_devdata(master); + struct npcm_pspi *priv = spi_controller_get_devdata(host); int status; npcm_pspi_setup_transfer(spi, t); @@ -266,18 +266,18 @@ static int npcm_pspi_transfer_one(struct spi_master *master, return 0; } -static int npcm_pspi_prepare_transfer_hardware(struct spi_master *master) +static int npcm_pspi_prepare_transfer_hardware(struct spi_controller *host) { - struct npcm_pspi *priv = spi_master_get_devdata(master); + struct npcm_pspi *priv = spi_controller_get_devdata(host); npcm_pspi_irq_enable(priv, NPCM_PSPI_CTL1_EIR | NPCM_PSPI_CTL1_EIW); return 0; } -static int npcm_pspi_unprepare_transfer_hardware(struct spi_master *master) +static int npcm_pspi_unprepare_transfer_hardware(struct spi_controller *host) { - struct npcm_pspi *priv = spi_master_get_devdata(master); + struct npcm_pspi *priv = spi_controller_get_devdata(host); npcm_pspi_irq_disable(priv, NPCM_PSPI_CTL1_EIR | NPCM_PSPI_CTL1_EIW); @@ -340,37 +340,37 @@ static irqreturn_t npcm_pspi_handler(int irq, void *dev_id) static int npcm_pspi_probe(struct platform_device *pdev) { struct npcm_pspi *priv; - struct spi_master *master; + struct spi_controller *host; unsigned long clk_hz; int irq; int ret; - master = spi_alloc_master(&pdev->dev, sizeof(*priv)); - if (!master) + host = spi_alloc_host(&pdev->dev, sizeof(*priv)); + if (!host) return -ENOMEM; - platform_set_drvdata(pdev, master); + platform_set_drvdata(pdev, host); - priv = spi_master_get_devdata(master); - priv->master = master; + priv = spi_controller_get_devdata(host); + priv->host = host; priv->is_save_param = false; priv->base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(priv->base)) { ret = PTR_ERR(priv->base); - goto out_master_put; + goto out_host_put; } priv->clk = devm_clk_get(&pdev->dev, NULL); if (IS_ERR(priv->clk)) { dev_err(&pdev->dev, "failed to get clock\n"); ret = PTR_ERR(priv->clk); - goto out_master_put; + goto out_host_put; } ret = clk_prepare_enable(priv->clk); if (ret) - goto out_master_put; + goto out_host_put; irq = platform_get_irq(pdev, 0); if (irq < 0) { @@ -398,42 +398,42 @@ static int npcm_pspi_probe(struct platform_device *pdev) clk_hz = clk_get_rate(priv->clk); - master->max_speed_hz = DIV_ROUND_UP(clk_hz, NPCM_PSPI_MIN_CLK_DIVIDER); - master->min_speed_hz = DIV_ROUND_UP(clk_hz, NPCM_PSPI_MAX_CLK_DIVIDER); - master->mode_bits = SPI_CPHA | SPI_CPOL; - master->dev.of_node = pdev->dev.of_node; - master->bus_num = -1; - master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16); - master->transfer_one = npcm_pspi_transfer_one; - master->prepare_transfer_hardware = + host->max_speed_hz = DIV_ROUND_UP(clk_hz, NPCM_PSPI_MIN_CLK_DIVIDER); + host->min_speed_hz = DIV_ROUND_UP(clk_hz, NPCM_PSPI_MAX_CLK_DIVIDER); + host->mode_bits = SPI_CPHA | SPI_CPOL; + host->dev.of_node = pdev->dev.of_node; + host->bus_num = -1; + host->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16); + host->transfer_one = npcm_pspi_transfer_one; + host->prepare_transfer_hardware = npcm_pspi_prepare_transfer_hardware; - master->unprepare_transfer_hardware = + host->unprepare_transfer_hardware = npcm_pspi_unprepare_transfer_hardware; - master->use_gpio_descriptors = true; + host->use_gpio_descriptors = true; /* set to default clock rate */ npcm_pspi_set_baudrate(priv, NPCM_PSPI_DEFAULT_CLK); - ret = devm_spi_register_master(&pdev->dev, master); + ret = devm_spi_register_controller(&pdev->dev, host); if (ret) goto out_disable_clk; - pr_info("NPCM Peripheral SPI %d probed\n", master->bus_num); + pr_info("NPCM Peripheral SPI %d probed\n", host->bus_num); return 0; out_disable_clk: clk_disable_unprepare(priv->clk); -out_master_put: - spi_master_put(master); +out_host_put: + spi_controller_put(host); return ret; } static void npcm_pspi_remove(struct platform_device *pdev) { - struct spi_master *master = platform_get_drvdata(pdev); - struct npcm_pspi *priv = spi_master_get_devdata(master); + struct spi_controller *host = platform_get_drvdata(pdev); + struct npcm_pspi *priv = spi_controller_get_devdata(host); npcm_pspi_reset_hw(priv); clk_disable_unprepare(priv->clk); From patchwork Thu Aug 10 08:30:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yang Yingliang X-Patchwork-Id: 712569 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EE69DC0729B for ; Thu, 10 Aug 2023 08:33:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234222AbjHJIdQ (ORCPT ); Thu, 10 Aug 2023 04:33:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34894 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234215AbjHJIdP (ORCPT ); Thu, 10 Aug 2023 04:33:15 -0400 Received: from szxga02-in.huawei.com (szxga02-in.huawei.com [45.249.212.188]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9F1D0E56 for ; Thu, 10 Aug 2023 01:33:14 -0700 (PDT) Received: from dggpemm500016.china.huawei.com (unknown [172.30.72.53]) by szxga02-in.huawei.com (SkyGuard) with ESMTP id 4RM0WR3yjDzTmWy; Thu, 10 Aug 2023 16:31:15 +0800 (CST) Received: from dggpemm500007.china.huawei.com (7.185.36.183) by dggpemm500016.china.huawei.com (7.185.36.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 10 Aug 2023 16:33:11 +0800 Received: from huawei.com (10.175.103.91) by dggpemm500007.china.huawei.com (7.185.36.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 10 Aug 2023 16:33:11 +0800 From: Yang Yingliang To: CC: , , , Subject: [PATCH -next 18/21] spi: nxp-fspi: switch to use modern name Date: Thu, 10 Aug 2023 16:30:01 +0800 Message-ID: <20230810083004.3988597-19-yangyingliang@huawei.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230810083004.3988597-1-yangyingliang@huawei.com> References: <20230810083004.3988597-1-yangyingliang@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.175.103.91] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To dggpemm500007.china.huawei.com (7.185.36.183) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Change legacy name master/slave to modern name host/target or controller. No functional changed. Signed-off-by: Yang Yingliang --- drivers/spi/spi-nxp-fspi.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/drivers/spi/spi-nxp-fspi.c b/drivers/spi/spi-nxp-fspi.c index 45a4acc95661..5dc950c87fe1 100644 --- a/drivers/spi/spi-nxp-fspi.c +++ b/drivers/spi/spi-nxp-fspi.c @@ -451,7 +451,7 @@ static int nxp_fspi_check_buswidth(struct nxp_fspi *f, u8 width) static bool nxp_fspi_supports_op(struct spi_mem *mem, const struct spi_mem_op *op) { - struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->master); + struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->controller); int ret; ret = nxp_fspi_check_buswidth(f, op->cmd.buswidth); @@ -520,7 +520,7 @@ static int fspi_readl_poll_tout(struct nxp_fspi *f, void __iomem *base, } /* - * If the slave device content being changed by Write/Erase, need to + * If the target device content being changed by Write/Erase, need to * invalidate the AHB buffer. This can be achieved by doing the reset * of controller after setting MCR0[SWRESET] bit. */ @@ -661,7 +661,7 @@ static void nxp_fspi_dll_calibration(struct nxp_fspi *f) /* * In FlexSPI controller, flash access is based on value of FSPI_FLSHXXCR0 - * register and start base address of the slave device. + * register and start base address of the target device. * * (Higher address) * -------- <-- FLSHB2CR0 @@ -680,15 +680,15 @@ static void nxp_fspi_dll_calibration(struct nxp_fspi *f) * * * Start base address defines the starting address range for given CS and - * FSPI_FLSHXXCR0 defines the size of the slave device connected at given CS. + * FSPI_FLSHXXCR0 defines the size of the target device connected at given CS. * * But, different targets are having different combinations of number of CS, * some targets only have single CS or two CS covering controller's full * memory mapped space area. * Thus, implementation is being done as independent of the size and number - * of the connected slave device. + * of the connected target device. * Assign controller memory mapped space size as the size to the connected - * slave device. + * target device. * Mark FLSHxxCR0 as zero initially and then assign value only to the selected * chip-select Flash configuration register. * @@ -704,8 +704,8 @@ static void nxp_fspi_select_mem(struct nxp_fspi *f, struct spi_device *spi) uint64_t size_kb; /* - * Return, if previously selected slave device is same as current - * requested slave device. + * Return, if previously selected target device is same as current + * requested target device. */ if (f->selected == spi_get_chipselect(spi, 0)) return; @@ -722,7 +722,7 @@ static void nxp_fspi_select_mem(struct nxp_fspi *f, struct spi_device *spi) fspi_writel(f, size_kb, f->iobase + FSPI_FLSHA1CR0 + 4 * spi_get_chipselect(spi, 0)); - dev_dbg(f->dev, "Slave device [CS:%x] selected\n", spi_get_chipselect(spi, 0)); + dev_dbg(f->dev, "Target device [CS:%x] selected\n", spi_get_chipselect(spi, 0)); nxp_fspi_clk_disable_unprep(f); @@ -912,7 +912,7 @@ static int nxp_fspi_do_op(struct nxp_fspi *f, const struct spi_mem_op *op) static int nxp_fspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) { - struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->master); + struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->controller); int err = 0; mutex_lock(&f->lock); @@ -952,7 +952,7 @@ static int nxp_fspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) static int nxp_fspi_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op) { - struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->master); + struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->controller); if (op->data.dir == SPI_MEM_DATA_OUT) { if (op->data.nbytes > f->devtype_data->txfifo) @@ -1049,7 +1049,7 @@ static int nxp_fspi_default_setup(struct nxp_fspi *f) fspi_writel(f, FSPI_MCR0_MDIS, base + FSPI_MCR0); /* - * Config the DLL register to default value, enable the slave clock delay + * Config the DLL register to default value, enable the target clock delay * line delay cell override mode, and use 1 fixed delay cell in DLL delay * chain, this is the suggested setting when clock rate < 100MHz. */ @@ -1062,7 +1062,7 @@ static int nxp_fspi_default_setup(struct nxp_fspi *f) base + FSPI_MCR0); /* - * Disable same device enable bit and configure all slave devices + * Disable same device enable bit and configure all target devices * independently. */ reg = fspi_readl(f, f->iobase + FSPI_MCR2); @@ -1100,7 +1100,7 @@ static int nxp_fspi_default_setup(struct nxp_fspi *f) static const char *nxp_fspi_get_name(struct spi_mem *mem) { - struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->master); + struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->controller); struct device *dev = &mem->spi->dev; const char *name; @@ -1137,7 +1137,7 @@ static int nxp_fspi_probe(struct platform_device *pdev) int ret; u32 reg; - ctlr = spi_alloc_master(&pdev->dev, sizeof(*f)); + ctlr = spi_alloc_host(&pdev->dev, sizeof(*f)); if (!ctlr) return -ENOMEM; From patchwork Thu Aug 10 08:30:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yang Yingliang X-Patchwork-Id: 713161 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7EAACC41513 for ; Thu, 10 Aug 2023 08:33:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234215AbjHJIdQ (ORCPT ); Thu, 10 Aug 2023 04:33:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34900 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234229AbjHJIdP (ORCPT ); Thu, 10 Aug 2023 04:33:15 -0400 Received: from szxga08-in.huawei.com (szxga08-in.huawei.com [45.249.212.255]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E2B7710CF for ; Thu, 10 Aug 2023 01:33:13 -0700 (PDT) Received: from dggpemm500014.china.huawei.com (unknown [172.30.72.57]) by szxga08-in.huawei.com (SkyGuard) with ESMTP id 4RM0XJ05Syz1L9k9; Thu, 10 Aug 2023 16:32:00 +0800 (CST) Received: from dggpemm500007.china.huawei.com (7.185.36.183) by dggpemm500014.china.huawei.com (7.185.36.153) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 10 Aug 2023 16:33:12 +0800 Received: from huawei.com (10.175.103.91) by dggpemm500007.china.huawei.com (7.185.36.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 10 Aug 2023 16:33:11 +0800 From: Yang Yingliang To: CC: , , , Subject: [PATCH -next 19/21] spi: oc-tiny: switch to use modern name Date: Thu, 10 Aug 2023 16:30:02 +0800 Message-ID: <20230810083004.3988597-20-yangyingliang@huawei.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230810083004.3988597-1-yangyingliang@huawei.com> References: <20230810083004.3988597-1-yangyingliang@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.175.103.91] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To dggpemm500007.china.huawei.com (7.185.36.183) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Change legacy name master to modern name host or controller. No functional changed. Signed-off-by: Yang Yingliang --- drivers/spi/spi-oc-tiny.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/drivers/spi/spi-oc-tiny.c b/drivers/spi/spi-oc-tiny.c index 3af499838e84..cf7c111088a6 100644 --- a/drivers/spi/spi-oc-tiny.c +++ b/drivers/spi/spi-oc-tiny.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * OpenCores tiny SPI master driver + * OpenCores tiny SPI host driver * * https://opencores.org/project,tiny_spi * @@ -53,7 +53,7 @@ struct tiny_spi { static inline struct tiny_spi *tiny_spi_to_hw(struct spi_device *sdev) { - return spi_master_get_devdata(sdev->master); + return spi_controller_get_devdata(sdev->controller); } static unsigned int tiny_spi_baud(struct spi_device *spi, unsigned int hz) @@ -212,24 +212,24 @@ static int tiny_spi_probe(struct platform_device *pdev) { struct tiny_spi_platform_data *platp = dev_get_platdata(&pdev->dev); struct tiny_spi *hw; - struct spi_master *master; + struct spi_controller *host; int err = -ENODEV; - master = spi_alloc_master(&pdev->dev, sizeof(struct tiny_spi)); - if (!master) + host = spi_alloc_host(&pdev->dev, sizeof(struct tiny_spi)); + if (!host) return err; - /* setup the master state. */ - master->bus_num = pdev->id; - master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; - master->setup = tiny_spi_setup; - master->use_gpio_descriptors = true; + /* setup the host state. */ + host->bus_num = pdev->id; + host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; + host->setup = tiny_spi_setup; + host->use_gpio_descriptors = true; - hw = spi_master_get_devdata(master); + hw = spi_controller_get_devdata(host); platform_set_drvdata(pdev, hw); /* setup the state for the bitbang driver */ - hw->bitbang.master = master; + hw->bitbang.master = host; hw->bitbang.setup_transfer = tiny_spi_setup_transfer; hw->bitbang.txrx_bufs = tiny_spi_txrx_bufs; @@ -267,17 +267,17 @@ static int tiny_spi_probe(struct platform_device *pdev) return 0; exit: - spi_master_put(master); + spi_controller_put(host); return err; } static void tiny_spi_remove(struct platform_device *pdev) { struct tiny_spi *hw = platform_get_drvdata(pdev); - struct spi_master *master = hw->bitbang.master; + struct spi_controller *host = hw->bitbang.master; spi_bitbang_stop(&hw->bitbang); - spi_master_put(master); + spi_controller_put(host); } #ifdef CONFIG_OF From patchwork Thu Aug 10 08:30:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yang Yingliang X-Patchwork-Id: 712570 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B0520C05052 for ; Thu, 10 Aug 2023 08:33:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234218AbjHJIdQ (ORCPT ); Thu, 10 Aug 2023 04:33:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34884 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234222AbjHJIdP (ORCPT ); Thu, 10 Aug 2023 04:33:15 -0400 Received: from szxga02-in.huawei.com (szxga02-in.huawei.com [45.249.212.188]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7E629E40 for ; Thu, 10 Aug 2023 01:33:14 -0700 (PDT) Received: from dggpemm500018.china.huawei.com (unknown [172.30.72.54]) by szxga02-in.huawei.com (SkyGuard) with ESMTP id 4RM0Tg4JM9zJsgT; Thu, 10 Aug 2023 16:29:43 +0800 (CST) Received: from dggpemm500007.china.huawei.com (7.185.36.183) by dggpemm500018.china.huawei.com (7.185.36.111) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 10 Aug 2023 16:33:12 +0800 Received: from huawei.com (10.175.103.91) by dggpemm500007.china.huawei.com (7.185.36.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 10 Aug 2023 16:33:12 +0800 From: Yang Yingliang To: CC: , , , Subject: [PATCH -next 20/21] spi: omap-uwire: switch to use modern name Date: Thu, 10 Aug 2023 16:30:03 +0800 Message-ID: <20230810083004.3988597-21-yangyingliang@huawei.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230810083004.3988597-1-yangyingliang@huawei.com> References: <20230810083004.3988597-1-yangyingliang@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.175.103.91] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To dggpemm500007.china.huawei.com (7.185.36.183) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Change legacy name master to modern name host or controller. No functional changed. Signed-off-by: Yang Yingliang --- drivers/spi/spi-omap-uwire.c | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/drivers/spi/spi-omap-uwire.c b/drivers/spi/spi-omap-uwire.c index f89aa9e52c23..2dd1c1bcf4bf 100644 --- a/drivers/spi/spi-omap-uwire.c +++ b/drivers/spi/spi-omap-uwire.c @@ -315,7 +315,7 @@ static int uwire_setup_transfer(struct spi_device *spi, struct spi_transfer *t) int div2; int status; - uwire = spi_master_get_devdata(spi->master); + uwire = spi_controller_get_devdata(spi->controller); /* mode 0..3, clock inverted separately; * standard nCS signaling; @@ -448,25 +448,25 @@ static void uwire_off(struct uwire_spi *uwire) { uwire_write_reg(UWIRE_SR3, 0); clk_disable_unprepare(uwire->ck); - spi_master_put(uwire->bitbang.master); + spi_controller_put(uwire->bitbang.master); } static int uwire_probe(struct platform_device *pdev) { - struct spi_master *master; + struct spi_controller *host; struct uwire_spi *uwire; int status; - master = spi_alloc_master(&pdev->dev, sizeof(*uwire)); - if (!master) + host = spi_alloc_host(&pdev->dev, sizeof(*uwire)); + if (!host) return -ENODEV; - uwire = spi_master_get_devdata(master); + uwire = spi_controller_get_devdata(host); uwire_base = devm_ioremap(&pdev->dev, UWIRE_BASE_PHYS, UWIRE_IO_SIZE); if (!uwire_base) { dev_dbg(&pdev->dev, "can't ioremap UWIRE\n"); - spi_master_put(master); + spi_controller_put(host); return -ENOMEM; } @@ -476,7 +476,7 @@ static int uwire_probe(struct platform_device *pdev) if (IS_ERR(uwire->ck)) { status = PTR_ERR(uwire->ck); dev_dbg(&pdev->dev, "no functional clock?\n"); - spi_master_put(master); + spi_controller_put(host); return status; } clk_prepare_enable(uwire->ck); @@ -484,16 +484,16 @@ static int uwire_probe(struct platform_device *pdev) uwire_write_reg(UWIRE_SR3, 1); /* the spi->mode bits understood by this driver: */ - master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; - master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 16); - master->flags = SPI_CONTROLLER_HALF_DUPLEX; + host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; + host->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 16); + host->flags = SPI_CONTROLLER_HALF_DUPLEX; - master->bus_num = 2; /* "official" */ - master->num_chipselect = 4; - master->setup = uwire_setup; - master->cleanup = uwire_cleanup; + host->bus_num = 2; /* "official" */ + host->num_chipselect = 4; + host->setup = uwire_setup; + host->cleanup = uwire_cleanup; - uwire->bitbang.master = master; + uwire->bitbang.master = host; uwire->bitbang.chipselect = uwire_chipselect; uwire->bitbang.setup_transfer = uwire_setup_transfer; uwire->bitbang.txrx_bufs = uwire_txrx; From patchwork Thu Aug 10 08:30:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yang Yingliang X-Patchwork-Id: 713159 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 29BB6C04FE1 for ; Thu, 10 Aug 2023 08:33:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234231AbjHJIdR (ORCPT ); Thu, 10 Aug 2023 04:33:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34914 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234232AbjHJIdR (ORCPT ); Thu, 10 Aug 2023 04:33:17 -0400 Received: from szxga01-in.huawei.com (szxga01-in.huawei.com [45.249.212.187]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 23950ED for ; Thu, 10 Aug 2023 01:33:15 -0700 (PDT) Received: from dggpemm500015.china.huawei.com (unknown [172.30.72.53]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4RM0Tf6Bj6ztSGR; Thu, 10 Aug 2023 16:29:42 +0800 (CST) Received: from dggpemm500007.china.huawei.com (7.185.36.183) by dggpemm500015.china.huawei.com (7.185.36.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 10 Aug 2023 16:33:12 +0800 Received: from huawei.com (10.175.103.91) by dggpemm500007.china.huawei.com (7.185.36.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 10 Aug 2023 16:33:12 +0800 From: Yang Yingliang To: CC: , , , Subject: [PATCH -next 21/21] spi: omap2-mcspi: switch to use modern name Date: Thu, 10 Aug 2023 16:30:04 +0800 Message-ID: <20230810083004.3988597-22-yangyingliang@huawei.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230810083004.3988597-1-yangyingliang@huawei.com> References: <20230810083004.3988597-1-yangyingliang@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.175.103.91] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To dggpemm500007.china.huawei.com (7.185.36.183) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Change legacy name master/slave to modern name host/target or controller. No functional changed. Signed-off-by: Yang Yingliang --- drivers/spi/spi-omap2-mcspi.c | 236 +++++++++++++++++----------------- 1 file changed, 118 insertions(+), 118 deletions(-) diff --git a/drivers/spi/spi-omap2-mcspi.c b/drivers/spi/spi-omap2-mcspi.c index e5cd82eb9e54..79888e6c54c2 100644 --- a/drivers/spi/spi-omap2-mcspi.c +++ b/drivers/spi/spi-omap2-mcspi.c @@ -117,7 +117,7 @@ struct omap2_mcspi_regs { struct omap2_mcspi { struct completion txdone; - struct spi_master *master; + struct spi_controller *ctlr; /* Virtual base address of the controller */ void __iomem *base; unsigned long phys; @@ -126,7 +126,7 @@ struct omap2_mcspi { struct device *dev; struct omap2_mcspi_regs ctx; int fifo_depth; - bool slave_aborted; + bool target_aborted; unsigned int pin_dir:1; size_t max_xfer_len; }; @@ -141,17 +141,17 @@ struct omap2_mcspi_cs { u32 chconf0, chctrl0; }; -static inline void mcspi_write_reg(struct spi_master *master, +static inline void mcspi_write_reg(struct spi_controller *ctlr, int idx, u32 val) { - struct omap2_mcspi *mcspi = spi_master_get_devdata(master); + struct omap2_mcspi *mcspi = spi_controller_get_devdata(ctlr); writel_relaxed(val, mcspi->base + idx); } -static inline u32 mcspi_read_reg(struct spi_master *master, int idx) +static inline u32 mcspi_read_reg(struct spi_controller *ctlr, int idx) { - struct omap2_mcspi *mcspi = spi_master_get_devdata(master); + struct omap2_mcspi *mcspi = spi_controller_get_devdata(ctlr); return readl_relaxed(mcspi->base + idx); } @@ -235,7 +235,7 @@ static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable) static void omap2_mcspi_set_cs(struct spi_device *spi, bool enable) { - struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); + struct omap2_mcspi *mcspi = spi_controller_get_devdata(spi->controller); u32 l; /* The controller handles the inverted chip selects @@ -266,24 +266,24 @@ static void omap2_mcspi_set_cs(struct spi_device *spi, bool enable) } } -static void omap2_mcspi_set_mode(struct spi_master *master) +static void omap2_mcspi_set_mode(struct spi_controller *ctlr) { - struct omap2_mcspi *mcspi = spi_master_get_devdata(master); + struct omap2_mcspi *mcspi = spi_controller_get_devdata(ctlr); struct omap2_mcspi_regs *ctx = &mcspi->ctx; u32 l; /* - * Choose master or slave mode + * Choose host or target mode */ - l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL); + l = mcspi_read_reg(ctlr, OMAP2_MCSPI_MODULCTRL); l &= ~(OMAP2_MCSPI_MODULCTRL_STEST); - if (spi_controller_is_slave(master)) { + if (spi_controller_is_target(ctlr)) { l |= (OMAP2_MCSPI_MODULCTRL_MS); } else { l &= ~(OMAP2_MCSPI_MODULCTRL_MS); l |= OMAP2_MCSPI_MODULCTRL_SINGLE; } - mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l); + mcspi_write_reg(ctlr, OMAP2_MCSPI_MODULCTRL, l); ctx->modulctrl = l; } @@ -291,14 +291,14 @@ static void omap2_mcspi_set_mode(struct spi_master *master) static void omap2_mcspi_set_fifo(const struct spi_device *spi, struct spi_transfer *t, int enable) { - struct spi_master *master = spi->master; + struct spi_controller *ctlr = spi->controller; struct omap2_mcspi_cs *cs = spi->controller_state; struct omap2_mcspi *mcspi; unsigned int wcnt; int max_fifo_depth, bytes_per_word; u32 chconf, xferlevel; - mcspi = spi_master_get_devdata(master); + mcspi = spi_controller_get_devdata(ctlr); chconf = mcspi_cached_chconf0(spi); if (enable) { @@ -326,7 +326,7 @@ static void omap2_mcspi_set_fifo(const struct spi_device *spi, xferlevel |= bytes_per_word - 1; } - mcspi_write_reg(master, OMAP2_MCSPI_XFERLEVEL, xferlevel); + mcspi_write_reg(ctlr, OMAP2_MCSPI_XFERLEVEL, xferlevel); mcspi_write_chconf0(spi, chconf); mcspi->fifo_depth = max_fifo_depth; @@ -364,9 +364,9 @@ static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit) static int mcspi_wait_for_completion(struct omap2_mcspi *mcspi, struct completion *x) { - if (spi_controller_is_slave(mcspi->master)) { + if (spi_controller_is_target(mcspi->ctlr)) { if (wait_for_completion_interruptible(x) || - mcspi->slave_aborted) + mcspi->target_aborted) return -EINTR; } else { wait_for_completion(x); @@ -378,7 +378,7 @@ static int mcspi_wait_for_completion(struct omap2_mcspi *mcspi, static void omap2_mcspi_rx_callback(void *data) { struct spi_device *spi = data; - struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); + struct omap2_mcspi *mcspi = spi_controller_get_devdata(spi->controller); struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi_get_chipselect(spi, 0)]; /* We must disable the DMA RX request */ @@ -390,7 +390,7 @@ static void omap2_mcspi_rx_callback(void *data) static void omap2_mcspi_tx_callback(void *data) { struct spi_device *spi = data; - struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); + struct omap2_mcspi *mcspi = spi_controller_get_devdata(spi->controller); struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi_get_chipselect(spi, 0)]; /* We must disable the DMA TX request */ @@ -407,7 +407,7 @@ static void omap2_mcspi_tx_dma(struct spi_device *spi, struct omap2_mcspi_dma *mcspi_dma; struct dma_async_tx_descriptor *tx; - mcspi = spi_master_get_devdata(spi->master); + mcspi = spi_controller_get_devdata(spi->controller); mcspi_dma = &mcspi->dma_channels[spi_get_chipselect(spi, 0)]; dmaengine_slave_config(mcspi_dma->dma_tx, &cfg); @@ -445,13 +445,13 @@ omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer, void __iomem *chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0; struct dma_async_tx_descriptor *tx; - mcspi = spi_master_get_devdata(spi->master); + mcspi = spi_controller_get_devdata(spi->controller); mcspi_dma = &mcspi->dma_channels[spi_get_chipselect(spi, 0)]; count = xfer->len; /* * In the "End-of-Transfer Procedure" section for DMA RX in OMAP35x TRM - * it mentions reducing DMA transfer length by one element in master + * it mentions reducing DMA transfer length by one element in host * normal mode. */ if (mcspi->fifo_depth == 0) @@ -514,7 +514,7 @@ omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer, omap2_mcspi_set_dma_req(spi, 1, 1); ret = mcspi_wait_for_completion(mcspi, &mcspi_dma->dma_rx_completion); - if (ret || mcspi->slave_aborted) { + if (ret || mcspi->target_aborted) { dmaengine_terminate_sync(mcspi_dma->dma_rx); omap2_mcspi_set_dma_req(spi, 1, 0); return 0; @@ -590,7 +590,7 @@ omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer) void __iomem *irqstat_reg; int wait_res; - mcspi = spi_master_get_devdata(spi->master); + mcspi = spi_controller_get_devdata(spi->controller); mcspi_dma = &mcspi->dma_channels[spi_get_chipselect(spi, 0)]; if (cs->word_len <= 8) { @@ -617,14 +617,14 @@ omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer) rx = xfer->rx_buf; tx = xfer->tx_buf; - mcspi->slave_aborted = false; + mcspi->target_aborted = false; reinit_completion(&mcspi_dma->dma_tx_completion); reinit_completion(&mcspi_dma->dma_rx_completion); reinit_completion(&mcspi->txdone); if (tx) { - /* Enable EOW IRQ to know end of tx in slave mode */ - if (spi_controller_is_slave(spi->master)) - mcspi_write_reg(spi->master, + /* Enable EOW IRQ to know end of tx in target mode */ + if (spi_controller_is_target(spi->controller)) + mcspi_write_reg(spi->controller, OMAP2_MCSPI_IRQENABLE, OMAP2_MCSPI_IRQSTATUS_EOW); omap2_mcspi_tx_dma(spi, xfer, cfg); @@ -637,15 +637,15 @@ omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer) int ret; ret = mcspi_wait_for_completion(mcspi, &mcspi_dma->dma_tx_completion); - if (ret || mcspi->slave_aborted) { + if (ret || mcspi->target_aborted) { dmaengine_terminate_sync(mcspi_dma->dma_tx); omap2_mcspi_set_dma_req(spi, 0, 0); return 0; } - if (spi_controller_is_slave(mcspi->master)) { + if (spi_controller_is_target(mcspi->ctlr)) { ret = mcspi_wait_for_completion(mcspi, &mcspi->txdone); - if (ret || mcspi->slave_aborted) + if (ret || mcspi->target_aborted) return 0; } @@ -656,7 +656,7 @@ omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer) OMAP2_MCSPI_IRQSTATUS_EOW) < 0) dev_err(&spi->dev, "EOW timed out\n"); - mcspi_write_reg(mcspi->master, OMAP2_MCSPI_IRQSTATUS, + mcspi_write_reg(mcspi->ctlr, OMAP2_MCSPI_IRQSTATUS, OMAP2_MCSPI_IRQSTATUS_EOW); } @@ -901,7 +901,7 @@ static int omap2_mcspi_setup_transfer(struct spi_device *spi, u8 word_len = spi->bits_per_word; u32 speed_hz = spi->max_speed_hz; - mcspi = spi_master_get_devdata(spi->master); + mcspi = spi_controller_get_devdata(spi->controller); if (t != NULL && t->bits_per_word) word_len = t->bits_per_word; @@ -926,7 +926,7 @@ static int omap2_mcspi_setup_transfer(struct spi_device *spi, l = mcspi_cached_chconf0(spi); - /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS + /* standard 4-wire host mode: SCK, MOSI/out, MISO/in, nCS * REVISIT: this controller could support SPI_3WIRE mode. */ if (mcspi->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) { @@ -1017,13 +1017,13 @@ static int omap2_mcspi_request_dma(struct omap2_mcspi *mcspi, return ret; } -static void omap2_mcspi_release_dma(struct spi_master *master) +static void omap2_mcspi_release_dma(struct spi_controller *ctlr) { - struct omap2_mcspi *mcspi = spi_master_get_devdata(master); + struct omap2_mcspi *mcspi = spi_controller_get_devdata(ctlr); struct omap2_mcspi_dma *mcspi_dma; int i; - for (i = 0; i < master->num_chipselect; i++) { + for (i = 0; i < ctlr->num_chipselect; i++) { mcspi_dma = &mcspi->dma_channels[i]; if (mcspi_dma->dma_rx) { @@ -1054,7 +1054,7 @@ static int omap2_mcspi_setup(struct spi_device *spi) { bool initial_setup = false; int ret; - struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); + struct omap2_mcspi *mcspi = spi_controller_get_devdata(spi->controller); struct omap2_mcspi_regs *ctx = &mcspi->ctx; struct omap2_mcspi_cs *cs = spi->controller_state; @@ -1096,24 +1096,24 @@ static irqreturn_t omap2_mcspi_irq_handler(int irq, void *data) struct omap2_mcspi *mcspi = data; u32 irqstat; - irqstat = mcspi_read_reg(mcspi->master, OMAP2_MCSPI_IRQSTATUS); + irqstat = mcspi_read_reg(mcspi->ctlr, OMAP2_MCSPI_IRQSTATUS); if (!irqstat) return IRQ_NONE; - /* Disable IRQ and wakeup slave xfer task */ - mcspi_write_reg(mcspi->master, OMAP2_MCSPI_IRQENABLE, 0); + /* Disable IRQ and wakeup target xfer task */ + mcspi_write_reg(mcspi->ctlr, OMAP2_MCSPI_IRQENABLE, 0); if (irqstat & OMAP2_MCSPI_IRQSTATUS_EOW) complete(&mcspi->txdone); return IRQ_HANDLED; } -static int omap2_mcspi_slave_abort(struct spi_master *master) +static int omap2_mcspi_target_abort(struct spi_controller *ctlr) { - struct omap2_mcspi *mcspi = spi_master_get_devdata(master); + struct omap2_mcspi *mcspi = spi_controller_get_devdata(ctlr); struct omap2_mcspi_dma *mcspi_dma = mcspi->dma_channels; - mcspi->slave_aborted = true; + mcspi->target_aborted = true; complete(&mcspi_dma->dma_rx_completion); complete(&mcspi_dma->dma_tx_completion); complete(&mcspi->txdone); @@ -1121,7 +1121,7 @@ static int omap2_mcspi_slave_abort(struct spi_master *master) return 0; } -static int omap2_mcspi_transfer_one(struct spi_master *master, +static int omap2_mcspi_transfer_one(struct spi_controller *ctlr, struct spi_device *spi, struct spi_transfer *t) { @@ -1129,7 +1129,7 @@ static int omap2_mcspi_transfer_one(struct spi_master *master, /* We only enable one channel at a time -- the one whose message is * -- although this controller would gladly * arbitrate among multiple channels. This corresponds to "single - * channel" master mode. As a side effect, we need to manage the + * channel" host mode. As a side effect, we need to manage the * chipselect with the FORCE bit ... CS != channel enable. */ @@ -1141,13 +1141,13 @@ static int omap2_mcspi_transfer_one(struct spi_master *master, int status = 0; u32 chconf; - mcspi = spi_master_get_devdata(master); + mcspi = spi_controller_get_devdata(ctlr); mcspi_dma = mcspi->dma_channels + spi_get_chipselect(spi, 0); cs = spi->controller_state; cd = spi->controller_data; /* - * The slave driver could have changed spi->mode in which case + * The target driver could have changed spi->mode in which case * it will be different from cs->mode (the current hardware setup). * If so, set par_override (even though its not a parity issue) so * omap2_mcspi_setup_transfer will be called to configure the hardware @@ -1175,7 +1175,7 @@ static int omap2_mcspi_transfer_one(struct spi_master *master, if (cd && cd->cs_per_word) { chconf = mcspi->ctx.modulctrl; chconf &= ~OMAP2_MCSPI_MODULCTRL_SINGLE; - mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf); + mcspi_write_reg(ctlr, OMAP2_MCSPI_MODULCTRL, chconf); mcspi->ctx.modulctrl = mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL); } @@ -1201,8 +1201,8 @@ static int omap2_mcspi_transfer_one(struct spi_master *master, unsigned count; if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) && - master->cur_msg_mapped && - master->can_dma(master, spi, t)) + ctlr->cur_msg_mapped && + ctlr->can_dma(ctlr, spi, t)) omap2_mcspi_set_fifo(spi, t, 1); omap2_mcspi_set_enable(spi, 1); @@ -1213,8 +1213,8 @@ static int omap2_mcspi_transfer_one(struct spi_master *master, + OMAP2_MCSPI_TX0); if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) && - master->cur_msg_mapped && - master->can_dma(master, spi, t)) + ctlr->cur_msg_mapped && + ctlr->can_dma(ctlr, spi, t)) count = omap2_mcspi_txrx_dma(spi, t); else count = omap2_mcspi_txrx_pio(spi, t); @@ -1240,7 +1240,7 @@ static int omap2_mcspi_transfer_one(struct spi_master *master, if (cd && cd->cs_per_word) { chconf = mcspi->ctx.modulctrl; chconf |= OMAP2_MCSPI_MODULCTRL_SINGLE; - mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf); + mcspi_write_reg(ctlr, OMAP2_MCSPI_MODULCTRL, chconf); mcspi->ctx.modulctrl = mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL); } @@ -1256,10 +1256,10 @@ static int omap2_mcspi_transfer_one(struct spi_master *master, return status; } -static int omap2_mcspi_prepare_message(struct spi_master *master, +static int omap2_mcspi_prepare_message(struct spi_controller *ctlr, struct spi_message *msg) { - struct omap2_mcspi *mcspi = spi_master_get_devdata(master); + struct omap2_mcspi *mcspi = spi_controller_get_devdata(ctlr); struct omap2_mcspi_regs *ctx = &mcspi->ctx; struct omap2_mcspi_cs *cs; @@ -1283,29 +1283,29 @@ static int omap2_mcspi_prepare_message(struct spi_master *master, return 0; } -static bool omap2_mcspi_can_dma(struct spi_master *master, +static bool omap2_mcspi_can_dma(struct spi_controller *ctlr, struct spi_device *spi, struct spi_transfer *xfer) { - struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); + struct omap2_mcspi *mcspi = spi_controller_get_devdata(spi->controller); struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi_get_chipselect(spi, 0)]; if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx) return false; - if (spi_controller_is_slave(master)) + if (spi_controller_is_target(ctlr)) return true; - master->dma_rx = mcspi_dma->dma_rx; - master->dma_tx = mcspi_dma->dma_tx; + ctlr->dma_rx = mcspi_dma->dma_rx; + ctlr->dma_tx = mcspi_dma->dma_tx; return (xfer->len >= DMA_MIN_BYTES); } static size_t omap2_mcspi_max_xfer_size(struct spi_device *spi) { - struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); + struct omap2_mcspi *mcspi = spi_controller_get_devdata(spi->controller); struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi_get_chipselect(spi, 0)]; @@ -1317,7 +1317,7 @@ static size_t omap2_mcspi_max_xfer_size(struct spi_device *spi) static int omap2_mcspi_controller_setup(struct omap2_mcspi *mcspi) { - struct spi_master *master = mcspi->master; + struct spi_controller *ctlr = mcspi->ctlr; struct omap2_mcspi_regs *ctx = &mcspi->ctx; int ret = 0; @@ -1325,11 +1325,11 @@ static int omap2_mcspi_controller_setup(struct omap2_mcspi *mcspi) if (ret < 0) return ret; - mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, + mcspi_write_reg(ctlr, OMAP2_MCSPI_WAKEUPENABLE, OMAP2_MCSPI_WAKEUPENABLE_WKEN); ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN; - omap2_mcspi_set_mode(master); + omap2_mcspi_set_mode(ctlr); pm_runtime_mark_last_busy(mcspi->dev); pm_runtime_put_autosuspend(mcspi->dev); return 0; @@ -1353,8 +1353,8 @@ static int omap_mcspi_runtime_suspend(struct device *dev) */ static int omap_mcspi_runtime_resume(struct device *dev) { - struct spi_master *master = dev_get_drvdata(dev); - struct omap2_mcspi *mcspi = spi_master_get_devdata(master); + struct spi_controller *ctlr = dev_get_drvdata(dev); + struct omap2_mcspi *mcspi = spi_controller_get_devdata(ctlr); struct omap2_mcspi_regs *ctx = &mcspi->ctx; struct omap2_mcspi_cs *cs; int error; @@ -1364,8 +1364,8 @@ static int omap_mcspi_runtime_resume(struct device *dev) dev_warn(dev, "%s: failed to set pins: %i\n", __func__, error); /* McSPI: context restore */ - mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl); - mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable); + mcspi_write_reg(ctlr, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl); + mcspi_write_reg(ctlr, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable); list_for_each_entry(cs, &ctx->cs, node) { /* @@ -1420,7 +1420,7 @@ MODULE_DEVICE_TABLE(of, omap_mcspi_of_match); static int omap2_mcspi_probe(struct platform_device *pdev) { - struct spi_master *master; + struct spi_controller *ctlr; const struct omap2_mcspi_platform_config *pdata; struct omap2_mcspi *mcspi; struct resource *r; @@ -1430,32 +1430,32 @@ static int omap2_mcspi_probe(struct platform_device *pdev) const struct of_device_id *match; if (of_property_read_bool(node, "spi-slave")) - master = spi_alloc_slave(&pdev->dev, sizeof(*mcspi)); + ctlr = spi_alloc_target(&pdev->dev, sizeof(*mcspi)); else - master = spi_alloc_master(&pdev->dev, sizeof(*mcspi)); - if (!master) + ctlr = spi_alloc_host(&pdev->dev, sizeof(*mcspi)); + if (!ctlr) return -ENOMEM; /* the spi->mode bits understood by this driver: */ - master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; - master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); - master->setup = omap2_mcspi_setup; - master->auto_runtime_pm = true; - master->prepare_message = omap2_mcspi_prepare_message; - master->can_dma = omap2_mcspi_can_dma; - master->transfer_one = omap2_mcspi_transfer_one; - master->set_cs = omap2_mcspi_set_cs; - master->cleanup = omap2_mcspi_cleanup; - master->slave_abort = omap2_mcspi_slave_abort; - master->dev.of_node = node; - master->max_speed_hz = OMAP2_MCSPI_MAX_FREQ; - master->min_speed_hz = OMAP2_MCSPI_MAX_FREQ >> 15; - master->use_gpio_descriptors = true; - - platform_set_drvdata(pdev, master); - - mcspi = spi_master_get_devdata(master); - mcspi->master = master; + ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; + ctlr->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); + ctlr->setup = omap2_mcspi_setup; + ctlr->auto_runtime_pm = true; + ctlr->prepare_message = omap2_mcspi_prepare_message; + ctlr->can_dma = omap2_mcspi_can_dma; + ctlr->transfer_one = omap2_mcspi_transfer_one; + ctlr->set_cs = omap2_mcspi_set_cs; + ctlr->cleanup = omap2_mcspi_cleanup; + ctlr->target_abort = omap2_mcspi_target_abort; + ctlr->dev.of_node = node; + ctlr->max_speed_hz = OMAP2_MCSPI_MAX_FREQ; + ctlr->min_speed_hz = OMAP2_MCSPI_MAX_FREQ >> 15; + ctlr->use_gpio_descriptors = true; + + platform_set_drvdata(pdev, ctlr); + + mcspi = spi_controller_get_devdata(ctlr); + mcspi->ctlr = ctlr; match = of_match_device(omap_mcspi_of_match, &pdev->dev); if (match) { @@ -1463,24 +1463,24 @@ static int omap2_mcspi_probe(struct platform_device *pdev) pdata = match->data; of_property_read_u32(node, "ti,spi-num-cs", &num_cs); - master->num_chipselect = num_cs; + ctlr->num_chipselect = num_cs; if (of_property_read_bool(node, "ti,pindir-d0-out-d1-in")) mcspi->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN; } else { pdata = dev_get_platdata(&pdev->dev); - master->num_chipselect = pdata->num_cs; + ctlr->num_chipselect = pdata->num_cs; mcspi->pin_dir = pdata->pin_dir; } regs_offset = pdata->regs_offset; if (pdata->max_xfer_len) { mcspi->max_xfer_len = pdata->max_xfer_len; - master->max_transfer_size = omap2_mcspi_max_xfer_size; + ctlr->max_transfer_size = omap2_mcspi_max_xfer_size; } mcspi->base = devm_platform_get_and_ioremap_resource(pdev, 0, &r); if (IS_ERR(mcspi->base)) { status = PTR_ERR(mcspi->base); - goto free_master; + goto free_ctlr; } mcspi->phys = r->start + regs_offset; mcspi->base += regs_offset; @@ -1489,34 +1489,34 @@ static int omap2_mcspi_probe(struct platform_device *pdev) INIT_LIST_HEAD(&mcspi->ctx.cs); - mcspi->dma_channels = devm_kcalloc(&pdev->dev, master->num_chipselect, + mcspi->dma_channels = devm_kcalloc(&pdev->dev, ctlr->num_chipselect, sizeof(struct omap2_mcspi_dma), GFP_KERNEL); if (mcspi->dma_channels == NULL) { status = -ENOMEM; - goto free_master; + goto free_ctlr; } - for (i = 0; i < master->num_chipselect; i++) { + for (i = 0; i < ctlr->num_chipselect; i++) { sprintf(mcspi->dma_channels[i].dma_rx_ch_name, "rx%d", i); sprintf(mcspi->dma_channels[i].dma_tx_ch_name, "tx%d", i); status = omap2_mcspi_request_dma(mcspi, &mcspi->dma_channels[i]); if (status == -EPROBE_DEFER) - goto free_master; + goto free_ctlr; } status = platform_get_irq(pdev, 0); if (status < 0) - goto free_master; + goto free_ctlr; init_completion(&mcspi->txdone); status = devm_request_irq(&pdev->dev, status, omap2_mcspi_irq_handler, 0, pdev->name, mcspi); if (status) { dev_err(&pdev->dev, "Cannot request IRQ"); - goto free_master; + goto free_ctlr; } pm_runtime_use_autosuspend(&pdev->dev); @@ -1527,7 +1527,7 @@ static int omap2_mcspi_probe(struct platform_device *pdev) if (status < 0) goto disable_pm; - status = devm_spi_register_controller(&pdev->dev, master); + status = devm_spi_register_controller(&pdev->dev, ctlr); if (status < 0) goto disable_pm; @@ -1537,18 +1537,18 @@ static int omap2_mcspi_probe(struct platform_device *pdev) pm_runtime_dont_use_autosuspend(&pdev->dev); pm_runtime_put_sync(&pdev->dev); pm_runtime_disable(&pdev->dev); -free_master: - omap2_mcspi_release_dma(master); - spi_master_put(master); +free_ctlr: + omap2_mcspi_release_dma(ctlr); + spi_controller_put(ctlr); return status; } static void omap2_mcspi_remove(struct platform_device *pdev) { - struct spi_master *master = platform_get_drvdata(pdev); - struct omap2_mcspi *mcspi = spi_master_get_devdata(master); + struct spi_controller *ctlr = platform_get_drvdata(pdev); + struct omap2_mcspi *mcspi = spi_controller_get_devdata(ctlr); - omap2_mcspi_release_dma(master); + omap2_mcspi_release_dma(ctlr); pm_runtime_dont_use_autosuspend(mcspi->dev); pm_runtime_put_sync(mcspi->dev); @@ -1560,8 +1560,8 @@ MODULE_ALIAS("platform:omap2_mcspi"); static int __maybe_unused omap2_mcspi_suspend(struct device *dev) { - struct spi_master *master = dev_get_drvdata(dev); - struct omap2_mcspi *mcspi = spi_master_get_devdata(master); + struct spi_controller *ctlr = dev_get_drvdata(dev); + struct omap2_mcspi *mcspi = spi_controller_get_devdata(ctlr); int error; error = pinctrl_pm_select_sleep_state(dev); @@ -1569,9 +1569,9 @@ static int __maybe_unused omap2_mcspi_suspend(struct device *dev) dev_warn(mcspi->dev, "%s: failed to set pins: %i\n", __func__, error); - error = spi_master_suspend(master); + error = spi_controller_suspend(ctlr); if (error) - dev_warn(mcspi->dev, "%s: master suspend failed: %i\n", + dev_warn(mcspi->dev, "%s: controller suspend failed: %i\n", __func__, error); return pm_runtime_force_suspend(dev); @@ -1579,13 +1579,13 @@ static int __maybe_unused omap2_mcspi_suspend(struct device *dev) static int __maybe_unused omap2_mcspi_resume(struct device *dev) { - struct spi_master *master = dev_get_drvdata(dev); - struct omap2_mcspi *mcspi = spi_master_get_devdata(master); + struct spi_controller *ctlr = dev_get_drvdata(dev); + struct omap2_mcspi *mcspi = spi_controller_get_devdata(ctlr); int error; - error = spi_master_resume(master); + error = spi_controller_resume(ctlr); if (error) - dev_warn(mcspi->dev, "%s: master resume failed: %i\n", + dev_warn(mcspi->dev, "%s: controller resume failed: %i\n", __func__, error); return pm_runtime_force_resume(dev);