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Mon, 21 Aug 2023 02:30:40 -0700 Received: from xhdsgoud40.xilinx.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2507.27 via Frontend Transport; Mon, 21 Aug 2023 04:30:39 -0500 From: Srinivas Goud To: CC: , , , , Srinivas Goud Subject: [PATCH] spi: spi-cadence: Fix data corruption issues in slave mode Date: Mon, 21 Aug 2023 15:00:16 +0530 Message-ID: <1692610216-217644-1-git-send-email-srinivas.goud@amd.com> X-Mailer: git-send-email 2.1.1 MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000971E9:EE_|DM4PR12MB6136:EE_ X-MS-Office365-Filtering-Correlation-Id: e3f883ed-df37-408e-be34-08dba2294a1e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 8ftxRYXsq5IgK2qYyBI/AwrG5wyMLHZHCX2hYHfhrUM9AKckpZf+r7XrxiG92rtCBnq2629aAcoU6xXy/1qz6Mh16GO98ckpIrCGWQKnQxqeneaPbIsOxGJQvHVHId8MoSLvgwjqO53NCpu+uIGK28R8Chln0io5E+0cVPHMtKTvDEt4PNvsBLuqHIVWc3jhSAYBv2MXoYbs3VZUE3EaFBWbnAnQ6/QfYVNme5Ulom1ZEmTY1B5bwg+khOYMcf5OeywEEw5sTJVf6CiW27eVNwKyf5x1fOGM4w5lZkYT4kB4Tlr0LbN90yCwERbFmK4G4W4GKpwN7sagdfOQGEVYccHt2i0BZyPfyAlSDy4++MvcLFyi53H2/uLXEs5TbHiREaAlrnjqG6K6a8IdyTFMMnN4dgUqx2eSeI3BDGgbuvk1r6/93IJ2HFv4Cc3U1s5ed+X64D5uy3qCihAmofLQnQ14QyAFOX37/gvzlpeXLKs48m8wj+cak8FJE9VoASC8hRs8Hqn3cNpZfHf02wsqzpVT39y9HaU9eQROut9vFuy4s2SKbxR60TUvag2Fl5/x3KjPUmukufSCSoJybjWAhgYfBvQAOVx0rf5E/JeKVQUHwpD2xJJmXUvkOp0GFIKM4QmexqVOD8YU5xs2YiErT5nrEqUQu9H6jGpn2oZKllJi5j7fE2zlr0T5Gmus1kYyLzRE5iWxaE6Bp20jbLWm2AFx5E17YjgRwDS1h0QRrHcYiG2oOqJAy0KBKEDaNk+pG3PWOXJFD/ERFK3WIejjKw== X-Forefront-Antispam-Report: CIP:165.204.84.17; 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Add 10us delay before processing the RX FIFO as TX empty doesn't guarantee valid data in RX FIFO. Signed-off-by: Srinivas Goud Reviewed-by: Charles Keepax Tested-by: Charles Keepax --- drivers/spi/spi-cadence.c | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/drivers/spi/spi-cadence.c b/drivers/spi/spi-cadence.c index 42f101d..b21d125 100644 --- a/drivers/spi/spi-cadence.c +++ b/drivers/spi/spi-cadence.c @@ -317,12 +317,6 @@ static void cdns_spi_process_fifo(struct cdns_spi *xspi, int ntx, int nrx) xspi->rx_bytes -= nrx; while (ntx || nrx) { - /* When xspi in busy condition, bytes may send failed, - * then spi control did't work thoroughly, add one byte delay - */ - if (cdns_spi_read(xspi, CDNS_SPI_ISR) & CDNS_SPI_IXR_TXFULL) - udelay(10); - if (ntx) { if (xspi->txbuf) cdns_spi_write(xspi, CDNS_SPI_TXD, *xspi->txbuf++); @@ -392,6 +386,11 @@ static irqreturn_t cdns_spi_irq(int irq, void *dev_id) if (xspi->tx_bytes) { cdns_spi_process_fifo(xspi, trans_cnt, trans_cnt); } else { + /* Fixed delay due to controller limitation with + * RX_NEMPTY incorrect status + * Xilinx AR:65885 contains more details + */ + udelay(10); cdns_spi_process_fifo(xspi, 0, trans_cnt); cdns_spi_write(xspi, CDNS_SPI_IDR, CDNS_SPI_IXR_DEFAULT); @@ -439,12 +438,18 @@ static int cdns_transfer_one(struct spi_controller *ctlr, cdns_spi_setup_transfer(spi, transfer); } else { /* Set TX empty threshold to half of FIFO depth - * only if TX bytes are more than half FIFO depth. + * only if TX bytes are more than FIFO depth. */ if (xspi->tx_bytes > xspi->tx_fifo_depth) cdns_spi_write(xspi, CDNS_SPI_THLD, xspi->tx_fifo_depth >> 1); } + /* When xspi in busy condition, bytes may send failed, + * then spi control didn't work thoroughly, add one byte delay + */ + if (cdns_spi_read(xspi, CDNS_SPI_ISR) & CDNS_SPI_IXR_TXFULL) + udelay(10); + cdns_spi_process_fifo(xspi, xspi->tx_fifo_depth, 0); spi_transfer_delay_exec(transfer);