From patchwork Tue Aug 22 15:12:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Chaitanya Chundru X-Patchwork-Id: 716211 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 92628EE49AA for ; Tue, 22 Aug 2023 15:12:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236311AbjHVPMs (ORCPT ); Tue, 22 Aug 2023 11:12:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49628 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234167AbjHVPMs (ORCPT ); Tue, 22 Aug 2023 11:12:48 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C0168198; Tue, 22 Aug 2023 08:12:46 -0700 (PDT) Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 37MAtVvA019657; Tue, 22 Aug 2023 15:12:28 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references; s=qcppdkim1; bh=Ay7KPWNjOeMgB6BdqMOnzyDYADeHyVKMyY58vSYGbhE=; b=eOwDJOD7b/oPTsaPBQprMnufGri784quSD8jEb/3D2AEWjyhYbhEKETWfSR8aHd3macU d7R7khlr/IGqXXShxZWs9q+9thgpf1JzxEyChs/y9DO2cx6kZoVhr2amg0Ob9jKhv1va BUCt6TMYiDtGOZ/5Ifdzc83BBIbRxv4BrvizQn9tbBYVxXcVmXeWvR4VZQerIhYaxNIP TEXSRrCKuz0lQfPL5PIwWPGymj7VtRhaEcNZY1ezq4J0IxXXZY0LZJWac1e+6Qp5RUOJ wq6vxp0AQqvlF61FfDQpP06vjH+eXzXQdvxmTswMznx35WI+AO0171mrjZX1GmNGEngs 8A== Received: from apblrppmta01.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3sm6f9ucpg-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 22 Aug 2023 15:12:28 +0000 Received: from pps.filterd (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 37MFCNYf032354; Tue, 22 Aug 2023 15:12:23 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 3sjptkwbvm-1; Tue, 22 Aug 2023 15:12:23 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 37MFCNS3032343; Tue, 22 Aug 2023 15:12:23 GMT Received: from hu-sgudaval-hyd.qualcomm.com (hu-krichai-hyd.qualcomm.com [10.213.110.112]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 37MFCNWv032336; Tue, 22 Aug 2023 15:12:23 +0000 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 4058933) id D7AE04B7C; Tue, 22 Aug 2023 20:42:22 +0530 (+0530) From: Krishna chaitanya chundru To: manivannan.sadhasivam@linaro.org Cc: helgaas@kernel.org, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, quic_vbadigan@quicinc.com, quic_nitegupt@quicinc.com, quic_skananth@quicinc.com, quic_ramkri@quicinc.com, quic_parass@quicinc.com, krzysztof.kozlowski@linaro.org, Krishna chaitanya chundru , Andy Gross , Bjorn Andersson , Konrad Dybcio , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Manivannan Sadhasivam , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS) Subject: [PATCH v4 1/4] dt-bindings: pci: qcom: Add opp table Date: Tue, 22 Aug 2023 20:42:18 +0530 Message-Id: <1692717141-32743-2-git-send-email-quic_krichai@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1692717141-32743-1-git-send-email-quic_krichai@quicinc.com> References: <1692717141-32743-1-git-send-email-quic_krichai@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 5_Dv4z-OYHd7sqKDTLm0MKdNsUZv3kfj X-Proofpoint-ORIG-GUID: 5_Dv4z-OYHd7sqKDTLm0MKdNsUZv3kfj X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-08-22_13,2023-08-22_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 impostorscore=0 malwarescore=0 lowpriorityscore=0 phishscore=0 mlxscore=0 priorityscore=1501 mlxlogscore=880 adultscore=0 bulkscore=0 suspectscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2308220116 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org PCIe needs to choose the appropriate performance state of RPMH power domain based upon the PCIe gen speed. Adding the Operating Performance Points table allows to adjust power domain performance state, depending on the PCIe gen speed. Signed-off-by: Krishna chaitanya chundru Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index 81971be4..779339c 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -121,6 +121,10 @@ properties: description: GPIO controlled connection to WAKE# signal maxItems: 1 + operating-points-v2: true + opp-table: + type: object + required: - compatible - reg From patchwork Tue Aug 22 15:12:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Chaitanya Chundru X-Patchwork-Id: 716212 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EB297EE49AF for ; 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Tue, 22 Aug 2023 15:12:27 +0000 Received: from pps.filterd (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 37MFCO3N032361; Tue, 22 Aug 2023 15:12:24 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 3sjptkwbvr-1; Tue, 22 Aug 2023 15:12:24 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 37MFCN3m032349; Tue, 22 Aug 2023 15:12:23 GMT Received: from hu-sgudaval-hyd.qualcomm.com (hu-krichai-hyd.qualcomm.com [10.213.110.112]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 37MFCNqd032337; Tue, 22 Aug 2023 15:12:23 +0000 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 4058933) id 162A24B8A; Tue, 22 Aug 2023 20:42:23 +0530 (+0530) From: Krishna chaitanya chundru To: manivannan.sadhasivam@linaro.org Cc: helgaas@kernel.org, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, quic_vbadigan@quicinc.com, quic_nitegupt@quicinc.com, quic_skananth@quicinc.com, quic_ramkri@quicinc.com, quic_parass@quicinc.com, krzysztof.kozlowski@linaro.org, Krishna chaitanya chundru , Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS) Subject: [PATCH v4 2/4] arm64: dts: qcom: sm8450: Add opp table support to PCIe Date: Tue, 22 Aug 2023 20:42:19 +0530 Message-Id: <1692717141-32743-3-git-send-email-quic_krichai@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1692717141-32743-1-git-send-email-quic_krichai@quicinc.com> References: <1692717141-32743-1-git-send-email-quic_krichai@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 8dCBgGvIh6S8vjRQqfEYy24LgVg6hs3B X-Proofpoint-GUID: 8dCBgGvIh6S8vjRQqfEYy24LgVg6hs3B X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-08-22_13,2023-08-22_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxscore=0 bulkscore=0 phishscore=0 priorityscore=1501 impostorscore=0 malwarescore=0 mlxlogscore=748 suspectscore=0 spamscore=0 adultscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2308220116 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org PCIe needs to choose the appropriate performance state of RPMH power domain based up on the PCIe gen speed. So let's add the OPP table support to specify RPMH performance states. Use opp-level for the PCIe gen speed for easier use. Signed-off-by: Krishna chaitanya chundru --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 47 ++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 595533a..3af0cf9 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -1803,7 +1803,28 @@ pinctrl-names = "default"; pinctrl-0 = <&pcie0_default_state>; + operating-points-v2 = <&pcie0_opp_table>; + status = "disabled"; + + pcie0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-1 { + opp-level = <1>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-2 { + opp-level = <2>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-3 { + opp-level = <3>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; }; pcie0_phy: phy@1c06000 { @@ -1915,7 +1936,33 @@ pinctrl-names = "default"; pinctrl-0 = <&pcie1_default_state>; + operating-points-v2 = <&pcie1_opp_table>; + status = "disabled"; + + pcie1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-1 { + opp-level = <1>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-2 { + opp-level = <2>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-3 { + opp-level = <3>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-4 { + opp-level = <4>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; }; pcie1_phy: phy@1c0f000 { From patchwork Tue Aug 22 15:12:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Chaitanya Chundru X-Patchwork-Id: 715815 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C3830EE49AC for ; Tue, 22 Aug 2023 15:12:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235232AbjHVPMn (ORCPT ); Tue, 22 Aug 2023 11:12:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49558 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233820AbjHVPMn (ORCPT ); Tue, 22 Aug 2023 11:12:43 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EB0E11AD; Tue, 22 Aug 2023 08:12:40 -0700 (PDT) Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 37MDdqSv029573; Tue, 22 Aug 2023 15:12:28 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references; s=qcppdkim1; bh=dZHSkX/6fvtGnwlb+ZmmWJYhYROGXRBi2FALpqYADiE=; b=MtDaGCDy9e/eydqwdqq4HceMrgVFgQMHWK3ANbAPDI9NkNIndtZUFvqmg/3SVdUQlIQR ZxC/hwFz9ObARGUk9E7Tu9qpJ/wmtJlt7mTzv4PeF4P9WDGQNti5nmsdOd89Uhuua/KB 0nN8Ikmenc0NS1oyaClWMV+RRWiuijGI0vGd96XFn7CueI4JMU7pb7rgd2umyWdG4t9M QnkRpcuCzpdUNkO9fxrFskjJJNTpO6NyV5tHRquzZ6gPAbQ4NFMte5/wLeIi4UxekFOO XQwW7HGxwVt0SpYk9ZLgCyuSxuTQKPlLCiFwsJsyrT05gYK+zQGf9ojuoAO/g1zHASCm 1w== Received: from apblrppmta01.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3smx3009hq-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 22 Aug 2023 15:12:27 +0000 Received: from pps.filterd (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 37MFCOG5032377; Tue, 22 Aug 2023 15:12:24 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 3sjptkwbvy-1; Tue, 22 Aug 2023 15:12:24 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 37MFCOZG032369; Tue, 22 Aug 2023 15:12:24 GMT Received: from hu-sgudaval-hyd.qualcomm.com (hu-krichai-hyd.qualcomm.com [10.213.110.112]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 37MFCNTp032355; Tue, 22 Aug 2023 15:12:24 +0000 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 4058933) id 57BE94B98; Tue, 22 Aug 2023 20:42:23 +0530 (+0530) From: Krishna chaitanya chundru To: manivannan.sadhasivam@linaro.org Cc: helgaas@kernel.org, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, quic_vbadigan@quicinc.com, quic_nitegupt@quicinc.com, quic_skananth@quicinc.com, quic_ramkri@quicinc.com, quic_parass@quicinc.com, krzysztof.kozlowski@linaro.org, Krishna chaitanya chundru , Viresh Kumar , Nishanth Menon , Stephen Boyd , "Rafael J. Wysocki" , linux-pm@vger.kernel.org (open list:OPERATING PERFORMANCE POINTS (OPP)) Subject: [PATCH v4 3/4] OPP: Add api to retrieve opps which is at most the provided level Date: Tue, 22 Aug 2023 20:42:20 +0530 Message-Id: <1692717141-32743-4-git-send-email-quic_krichai@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1692717141-32743-1-git-send-email-quic_krichai@quicinc.com> References: <1692717141-32743-1-git-send-email-quic_krichai@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: ic0KUM2-GCoD2akHeDRwbBQ0rmyBIoVJ X-Proofpoint-GUID: ic0KUM2-GCoD2akHeDRwbBQ0rmyBIoVJ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-08-22_13,2023-08-22_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 clxscore=1011 adultscore=0 mlxlogscore=832 priorityscore=1501 impostorscore=0 mlxscore=0 phishscore=0 suspectscore=0 spamscore=0 bulkscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2308220116 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add dev_pm_opp_find_level_floor() for searching a lesser match or operating on OPP in the order of decreasing level. Signed-off-by: Krishna chaitanya chundru --- drivers/opp/core.c | 26 ++++++++++++++++++++++++++ include/linux/pm_opp.h | 4 ++++ 2 files changed, 30 insertions(+) diff --git a/drivers/opp/core.c b/drivers/opp/core.c index 954c948..e668cf2 100644 --- a/drivers/opp/core.c +++ b/drivers/opp/core.c @@ -727,6 +727,32 @@ struct dev_pm_opp *dev_pm_opp_find_level_ceil(struct device *dev, } EXPORT_SYMBOL_GPL(dev_pm_opp_find_level_ceil); + +/** + * dev_pm_opp_find_level_floor() - Search for a rounded floor freq + * @dev: device for which we do this operation + * @freq: Start level + * + * Search for the matching floor *available* OPP from a starting level + * for a device. + * + * Return: matching *opp and refreshes *level accordingly, else returns + * ERR_PTR in case of error and should be handled using IS_ERR. Error return + * values can be: + * EINVAL: for bad pointer + * ERANGE: no match found for search + * ENODEV: if device not found in list of registered devices + * + * The callers are required to call dev_pm_opp_put() for the returned OPP after + * use. + */ +struct dev_pm_opp *dev_pm_opp_find_level_floor(struct device *dev, + unsigned long *level) +{ + return _find_key_floor(dev, level, 0, true, _read_level, NULL); +} +EXPORT_SYMBOL_GPL(dev_pm_opp_find_level_floor); + /** * dev_pm_opp_find_bw_ceil() - Search for a rounded ceil bandwidth * @dev: device for which we do this operation diff --git a/include/linux/pm_opp.h b/include/linux/pm_opp.h index dc1fb58..a3bc386 100644 --- a/include/linux/pm_opp.h +++ b/include/linux/pm_opp.h @@ -128,6 +128,8 @@ struct dev_pm_opp *dev_pm_opp_find_level_exact(struct device *dev, unsigned int level); struct dev_pm_opp *dev_pm_opp_find_level_ceil(struct device *dev, unsigned int *level); +struct dev_pm_opp *dev_pm_opp_find_level_floor(struct device *dev, + unsigned long *level); struct dev_pm_opp *dev_pm_opp_find_freq_ceil(struct device *dev, unsigned long *freq); @@ -285,6 +287,8 @@ static inline struct dev_pm_opp *dev_pm_opp_find_bw_ceil(struct device *dev, static inline struct dev_pm_opp *dev_pm_opp_find_bw_floor(struct device *dev, unsigned int *bw, int index) +static inline struct dev_pm_opp *dev_pm_opp_find_level_floor(struct device *dev, + unsigned long *level) { return ERR_PTR(-EOPNOTSUPP); } From patchwork Tue Aug 22 15:12:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Chaitanya Chundru X-Patchwork-Id: 715814 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DD5A5EE49AE for ; Tue, 22 Aug 2023 15:12:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236351AbjHVPMu (ORCPT ); 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Tue, 22 Aug 2023 15:12:28 +0000 Received: from pps.filterd (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 37MFCNYg032354; Tue, 22 Aug 2023 15:12:24 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 3sjptkwbw3-1; Tue, 22 Aug 2023 15:12:24 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 37MFCNS5032343; Tue, 22 Aug 2023 15:12:24 GMT Received: from hu-sgudaval-hyd.qualcomm.com (hu-krichai-hyd.qualcomm.com [10.213.110.112]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 37MFCO7v032362; Tue, 22 Aug 2023 15:12:24 +0000 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 4058933) id 8C02E4BA7; Tue, 22 Aug 2023 20:42:23 +0530 (+0530) From: Krishna chaitanya chundru To: manivannan.sadhasivam@linaro.org Cc: helgaas@kernel.org, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, quic_vbadigan@quicinc.com, quic_nitegupt@quicinc.com, quic_skananth@quicinc.com, quic_ramkri@quicinc.com, quic_parass@quicinc.com, krzysztof.kozlowski@linaro.org, Krishna chaitanya chundru , Manivannan Sadhasivam , Andy Gross , Bjorn Andersson , Konrad Dybcio , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas Subject: [PATCH v4 4/4] PCI: qcom: Add OPP support for speed based performance state of RPMH Date: Tue, 22 Aug 2023 20:42:21 +0530 Message-Id: <1692717141-32743-5-git-send-email-quic_krichai@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1692717141-32743-1-git-send-email-quic_krichai@quicinc.com> References: <1692717141-32743-1-git-send-email-quic_krichai@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: t7TmZnONEiw-gg2h7DLdbrGk_qxUTZja X-Proofpoint-GUID: t7TmZnONEiw-gg2h7DLdbrGk_qxUTZja X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-08-22_13,2023-08-22_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 bulkscore=0 spamscore=0 clxscore=1015 malwarescore=0 adultscore=0 lowpriorityscore=0 suspectscore=0 mlxscore=0 priorityscore=1501 phishscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2308220116 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Before link training vote for the maximum performance state of RPMH and once link is up, vote for the performance state based upon the link speed. Signed-off-by: Krishna chaitanya chundru --- drivers/pci/controller/dwc/pcie-qcom.c | 52 ++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 7a87a47..161fdad 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -1357,6 +1358,33 @@ static int qcom_pcie_icc_init(struct qcom_pcie *pcie) return 0; } +static void qcom_pcie_opp_update(struct qcom_pcie *pcie) +{ + struct dw_pcie *pci = pcie->pci; + struct dev_pm_opp *opp; + u32 offset, status; + int speed, ret = 0; + + offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + status = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA); + + /* Only update constraints if link is up. */ + if (!(status & PCI_EXP_LNKSTA_DLLLA)) + return; + + speed = FIELD_GET(PCI_EXP_LNKSTA_CLS, status); + + opp = dev_pm_opp_find_level_exact(pci->dev, speed); + if (!IS_ERR(opp)) { + ret = dev_pm_opp_set_opp(pci->dev, opp); + if (ret) + dev_err(pci->dev, "Failed to set opp: level %d ret %d\n", + dev_pm_opp_get_level(opp), ret); + dev_pm_opp_put(opp); + } + +} + static void qcom_pcie_icc_update(struct qcom_pcie *pcie) { struct dw_pcie *pci = pcie->pci; @@ -1439,8 +1467,10 @@ static void qcom_pcie_init_debugfs(struct qcom_pcie *pcie) static int qcom_pcie_probe(struct platform_device *pdev) { const struct qcom_pcie_cfg *pcie_cfg; + unsigned long max_level = INT_MAX; struct device *dev = &pdev->dev; struct qcom_pcie *pcie; + struct dev_pm_opp *opp; struct dw_pcie_rp *pp; struct resource *res; struct dw_pcie *pci; @@ -1511,6 +1541,23 @@ static int qcom_pcie_probe(struct platform_device *pdev) if (ret) goto err_pm_runtime_put; + /* OPP table is optional */ + ret = devm_pm_opp_of_add_table(dev); + if (ret && ret != -ENODEV) { + dev_err(dev, "Invalid OPP table in Device tree\n"); + goto err_pm_runtime_put; + } + + /* vote for max level in the opp table */ + opp = dev_pm_opp_find_level_floor(dev, &max_level); + if (!IS_ERR(opp)) { + ret = dev_pm_opp_set_opp(dev, opp); + if (ret) + dev_err(pci->dev, "Failed to set opp: level %d ret %d\n", + dev_pm_opp_get_level(opp), ret); + dev_pm_opp_put(opp); + } + ret = pcie->cfg->ops->get_resources(pcie); if (ret) goto err_pm_runtime_put; @@ -1531,6 +1578,8 @@ static int qcom_pcie_probe(struct platform_device *pdev) qcom_pcie_icc_update(pcie); + qcom_pcie_opp_update(pcie); + if (pcie->mhi) qcom_pcie_init_debugfs(pcie); @@ -1577,6 +1626,7 @@ static int qcom_pcie_suspend_noirq(struct device *dev) */ if (!dw_pcie_link_up(pcie->pci)) { qcom_pcie_host_deinit(&pcie->pci->pp); + dev_pm_opp_set_opp(dev, NULL); pcie->suspended = true; } @@ -1593,6 +1643,8 @@ static int qcom_pcie_resume_noirq(struct device *dev) if (ret) return ret; + qcom_pcie_opp_update(pcie); + pcie->suspended = false; }