From patchwork Wed Aug 23 15:44:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nitin Rawat X-Patchwork-Id: 716165 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 04BCCEE4993 for ; Wed, 23 Aug 2023 15:44:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234214AbjHWPo2 (ORCPT ); Wed, 23 Aug 2023 11:44:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55474 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230245AbjHWPo1 (ORCPT ); Wed, 23 Aug 2023 11:44:27 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 17019E52; Wed, 23 Aug 2023 08:44:26 -0700 (PDT) Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 37NEOjcT016771; Wed, 23 Aug 2023 15:44:20 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references; s=qcppdkim1; bh=75OGKGZobLN86QE8S1Fo0Ia1BOGzr7bQSpO253BHSPs=; b=BTb924NduGGtIFoIPW28HWgs42y57fzPl5cS0brPAZdYc38PrRZvAWw0WTTBwxk7e6ST h/xzxAoHGDN0Vua+Kg5qsLUJaNEgRzp1Sdr4DeqWr5xPTWBDmRif2rXBU/QheUs1SHy4 0PS4o0TLWSe/OhPO8FEbPm0MjZciVYmkmPqOiFt6JrTJM9cmu2cyAKo206wOJz6glFnM Jmf/ndD+K3KAUB/enj2NKbrOjq+/jC1KGEI3gX98SSjNgYM+DIYHP6mtFs34a1ubFypJ xZ4wGExdOm+UGcKNsxmxtgvaAxJXRqXjk8hxfWeM+owr8BOeSWJwe7TnRgcjtmXys2jk Ew== Received: from apblrppmta01.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3snkumr7q7-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 23 Aug 2023 15:44:19 +0000 Received: from pps.filterd (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 37NFiGgV029192; Wed, 23 Aug 2023 15:44:16 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 3sjptm3qdj-1; Wed, 23 Aug 2023 15:44:16 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 37NFiG3I029185; Wed, 23 Aug 2023 15:44:16 GMT Received: from hu-maiyas-hyd.qualcomm.com (hu-nitirawa-hyd.qualcomm.com [10.213.109.152]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 37NFiGRJ029179; Wed, 23 Aug 2023 15:44:16 +0000 Received: by hu-maiyas-hyd.qualcomm.com (Postfix, from userid 2342877) id C2AA95000AB; Wed, 23 Aug 2023 21:14:15 +0530 (+0530) From: Nitin Rawat To: mani@kernel.org, agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, jejb@linux.ibm.com, martin.petersen@oracle.com Cc: quic_cang@quicinc.com, quic_nguyenb@quicinc.com, linux-scsi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Nitin Rawat , Naveen Kumar Goud Arepalli Subject: [PATCH V5 1/6] scsi: ufs: qcom: Update offset for core_clk_1us_cycles Date: Wed, 23 Aug 2023 21:14:08 +0530 Message-Id: <20230823154413.23788-2-quic_nitirawa@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230823154413.23788-1-quic_nitirawa@quicinc.com> References: <20230823154413.23788-1-quic_nitirawa@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: _bstBj6IkelJ-bSKnmj5RG9IYaWosgvD X-Proofpoint-ORIG-GUID: _bstBj6IkelJ-bSKnmj5RG9IYaWosgvD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-08-23_09,2023-08-22_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 mlxlogscore=978 spamscore=0 suspectscore=0 adultscore=0 clxscore=1015 priorityscore=1501 impostorscore=0 lowpriorityscore=0 phishscore=0 mlxscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2308100000 definitions=main-2308230142 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This Patch updates offset for core_clk_1us_cycles in DME_VS_CORE_CLK_CTRL register. Offset for core_clk_1us_cycles is changed from Qualcomm UFS Controller V4.0.0 onwards. Co-developed-by: Naveen Kumar Goud Arepalli Signed-off-by: Naveen Kumar Goud Arepalli Signed-off-by: Nitin Rawat --- drivers/ufs/host/ufs-qcom.c | 19 ++++++++++++++----- drivers/ufs/host/ufs-qcom.h | 2 ++ 2 files changed, 16 insertions(+), 5 deletions(-) -- 2.17.1 diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index f88febb23123..1108b0cd43b3 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -1297,12 +1297,21 @@ static void ufs_qcom_exit(struct ufs_hba *hba) } static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba, - u32 clk_cycles) + u32 clk_1us_cycles) { - int err; + struct ufs_qcom_host *host = ufshcd_get_variant(hba); + u32 mask = DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK; u32 core_clk_ctrl_reg; + u32 offset = 0; + int err; + + /* Bit mask and offset changed on UFS host controller V4.0.0 onwards */ + if (host->hw_ver.major >= 4) { + mask = MAX_CORE_CLK_1US_CYCLES_MASK_V4; + offset = MAX_CORE_CLK_1US_CYCLES_OFFSET_V4; + } - if (clk_cycles > DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK) + if (clk_1us_cycles > mask) return -EINVAL; err = ufshcd_dme_get(hba, @@ -1311,8 +1320,8 @@ static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba, if (err) return err; - core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK; - core_clk_ctrl_reg |= clk_cycles; + core_clk_ctrl_reg &= ~(mask << offset); + core_clk_ctrl_reg |= clk_1us_cycles << offset; /* Clear CORE_CLK_DIV_EN */ core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT; diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h index d6f8e74bd538..a829296e11bb 100644 --- a/drivers/ufs/host/ufs-qcom.h +++ b/drivers/ufs/host/ufs-qcom.h @@ -129,6 +129,8 @@ enum { #define PA_VS_CONFIG_REG1 0x9000 #define DME_VS_CORE_CLK_CTRL 0xD002 /* bit and mask definitions for DME_VS_CORE_CLK_CTRL attribute */ +#define MAX_CORE_CLK_1US_CYCLES_MASK_V4 0xFFF +#define MAX_CORE_CLK_1US_CYCLES_OFFSET_V4 0x10 #define DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT BIT(8) #define DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK 0xFF From patchwork Wed Aug 23 15:44:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nitin Rawat X-Patchwork-Id: 716163 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0B260EE4993 for ; Wed, 23 Aug 2023 15:44:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235757AbjHWPoa (ORCPT ); Wed, 23 Aug 2023 11:44:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55506 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235596AbjHWPo3 (ORCPT ); Wed, 23 Aug 2023 11:44:29 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 53BF5E52; Wed, 23 Aug 2023 08:44:27 -0700 (PDT) Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 37NEOjse016761; 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Wed, 23 Aug 2023 15:44:17 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 3sjptm3qdx-1; Wed, 23 Aug 2023 15:44:17 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 37NFiHTr029212; Wed, 23 Aug 2023 15:44:17 GMT Received: from hu-maiyas-hyd.qualcomm.com (hu-nitirawa-hyd.qualcomm.com [10.213.109.152]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 37NFiHDZ029207; Wed, 23 Aug 2023 15:44:17 +0000 Received: by hu-maiyas-hyd.qualcomm.com (Postfix, from userid 2342877) id B1D395000AA; Wed, 23 Aug 2023 21:14:16 +0530 (+0530) From: Nitin Rawat To: mani@kernel.org, agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, jejb@linux.ibm.com, martin.petersen@oracle.com Cc: quic_cang@quicinc.com, quic_nguyenb@quicinc.com, linux-scsi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Nitin Rawat , Naveen Kumar Goud Arepalli Subject: [PATCH V5 3/6] scsi: ufs: qcom: Add multiple frequency support for unipro clk attributes Date: Wed, 23 Aug 2023 21:14:10 +0530 Message-Id: <20230823154413.23788-4-quic_nitirawa@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230823154413.23788-1-quic_nitirawa@quicinc.com> References: <20230823154413.23788-1-quic_nitirawa@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 31zQ8KvvHaMF-48sso1a5lxFw0GbqHdH X-Proofpoint-ORIG-GUID: 31zQ8KvvHaMF-48sso1a5lxFw0GbqHdH X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-08-23_09,2023-08-22_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 mlxlogscore=999 spamscore=0 suspectscore=0 adultscore=0 clxscore=1015 priorityscore=1501 impostorscore=0 lowpriorityscore=0 phishscore=0 mlxscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2308100000 definitions=main-2308230142 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add Support to configure CORE_CLK_1US_CYCLES, PA_VS_CORE_CLK_40NS_CYCLES for multiple unipro clock frequencies. Currently this is handled only for only 150Mhz and 75MHz. Co-developed-by: Naveen Kumar Goud Arepalli Signed-off-by: Naveen Kumar Goud Arepalli Signed-off-by: Nitin Rawat --- drivers/ufs/host/ufs-qcom.c | 88 ++++++++++++++++++++++++++++++++----- drivers/ufs/host/ufs-qcom.h | 9 ++++ 2 files changed, 87 insertions(+), 10 deletions(-) -- 2.17.1 diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index abc0e7f7d1b0..8162b19191a9 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -671,6 +671,45 @@ static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear, return 0; } +static int ufs_qcom_cfg_core_clk_ctrl(struct ufs_hba *hba) +{ + struct list_head *head = &hba->clk_list_head; + struct ufs_clk_info *clki; + u32 max_freq = 0; + int err; + + list_for_each_entry(clki, head, list) { + if (!IS_ERR_OR_NULL(clki->clk) && + !strcmp(clki->name, "core_clk_unipro")) { + max_freq = clki->max_freq; + break; + } + } + + switch (max_freq) { + case MHZ_403: + err = ufs_qcom_set_core_clk_ctrl(hba, 403, 16); + break; + case MHZ_300: + err = ufs_qcom_set_core_clk_ctrl(hba, 300, 12); + break; + case MHZ_201_5: + err = ufs_qcom_set_core_clk_ctrl(hba, 202, 8); + break; + case MHZ_150: + err = ufs_qcom_set_core_clk_ctrl(hba, 150, 6); + break; + case MHZ_100: + err = ufs_qcom_set_core_clk_ctrl(hba, 100, 4); + break; + default: + dev_err(hba->dev, "unipro max_freq=%u entry missing\n", max_freq); + err = -EINVAL; + break; + } + + return err; +} static int ufs_qcom_link_startup_notify(struct ufs_hba *hba, enum ufs_notify_change_status status) { @@ -686,12 +725,15 @@ static int ufs_qcom_link_startup_notify(struct ufs_hba *hba, return -EINVAL; } - if (ufs_qcom_cap_qunipro(host)) - /* - * set unipro core clock cycles to 150 & clear clock - * divider - */ - err = ufs_qcom_set_core_clk_ctrl(hba, 150, 6); + if (ufs_qcom_cap_qunipro(host)) { + err = ufs_qcom_cfg_core_clk_ctrl(hba); + if (err) { + dev_err(hba->dev, + "%s cfg core clk ctrl failed\n", + __func__); + return err; + } + } /* * Some UFS devices (and may be host) have issues if LCC is @@ -1369,8 +1411,7 @@ static int ufs_qcom_clk_scale_up_post_change(struct ufs_hba *hba) if (!ufs_qcom_cap_qunipro(host)) return 0; - /* set unipro core clock cycles to 150 and clear clock divider */ - return ufs_qcom_set_core_clk_ctrl(hba, 150, 6); + return ufs_qcom_cfg_core_clk_ctrl(hba); } static int ufs_qcom_clk_scale_down_pre_change(struct ufs_hba *hba) @@ -1401,12 +1442,39 @@ static int ufs_qcom_clk_scale_down_pre_change(struct ufs_hba *hba) static int ufs_qcom_clk_scale_down_post_change(struct ufs_hba *hba) { struct ufs_qcom_host *host = ufshcd_get_variant(hba); + struct list_head *head = &hba->clk_list_head; + struct ufs_clk_info *clki; + u32 curr_freq = 0; + int err; if (!ufs_qcom_cap_qunipro(host)) return 0; - /* set unipro core clock cycles to 75 and clear clock divider */ - return ufs_qcom_set_core_clk_ctrl(hba, 75, 3); + + list_for_each_entry(clki, head, list) { + if (!IS_ERR_OR_NULL(clki->clk) && + !strcmp(clki->name, "core_clk_unipro")) { + curr_freq = clk_get_rate(clki->clk); + break; + } + } + switch (curr_freq) { + case MHZ_37_5: + err = ufs_qcom_set_core_clk_ctrl(hba, 38, 2); + break; + case MHZ_75: + err = ufs_qcom_set_core_clk_ctrl(hba, 75, 3); + break; + case MHZ_100: + err = ufs_qcom_set_core_clk_ctrl(hba, 100, 4); + break; + default: + err = -EINVAL; + dev_err(hba->dev, "unipro curr_freq=%u entry missing\n", curr_freq); + break; + } + + return err; } static int ufs_qcom_clk_scale_notify(struct ufs_hba *hba, diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h index 325f08aca260..56550fd36c4e 100644 --- a/drivers/ufs/host/ufs-qcom.h +++ b/drivers/ufs/host/ufs-qcom.h @@ -79,6 +79,15 @@ enum { UFS_MEM_CQIS_VS = 0x8, }; +/* QCOM UFS host controller core clk frequencies */ +#define MHZ_37_5 37500000 +#define MHZ_50 50000000 +#define MHZ_75 75000000 +#define MHZ_100 100000000 +#define MHZ_150 150000000 +#define MHZ_300 300000000 +#define MHZ_201_5 201500000 +#define MHZ_403 403000000 #define UFS_CNTLR_2_x_x_VEN_REGS_OFFSET(x) (0x000 + x) #define UFS_CNTLR_3_x_x_VEN_REGS_OFFSET(x) (0x400 + x) From patchwork Wed Aug 23 15:44:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nitin Rawat X-Patchwork-Id: 716162 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EE084EE49B8 for ; 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Date: Wed, 23 Aug 2023 21:14:13 +0530 Message-Id: <20230823154413.23788-7-quic_nitirawa@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230823154413.23788-1-quic_nitirawa@quicinc.com> References: <20230823154413.23788-1-quic_nitirawa@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: Kirj_zTWA4LwA0501zrxRg7O_SwvA2bC X-Proofpoint-ORIG-GUID: Kirj_zTWA4LwA0501zrxRg7O_SwvA2bC X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-08-23_09,2023-08-22_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 mlxlogscore=999 mlxscore=0 lowpriorityscore=0 priorityscore=1501 impostorscore=0 malwarescore=0 suspectscore=0 adultscore=0 phishscore=0 bulkscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2308100000 definitions=main-2308230142 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Configure internal HW division of unipro core_clk based on scale up and scale down condition. This bit should be cleared before entering any SVS mode as per hardware specification. Co-developed-by: Naveen Kumar Goud Arepalli Signed-off-by: Naveen Kumar Goud Arepalli Signed-off-by: Nitin Rawat --- drivers/ufs/host/ufs-qcom.c | 49 ++++++++++++++++++++----------------- drivers/ufs/host/ufs-qcom.h | 2 +- 2 files changed, 27 insertions(+), 24 deletions(-) -- 2.17.1 diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index 82cf3ac4193a..d886e28b8a2a 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -95,7 +95,8 @@ static struct ufs_qcom_host *ufs_qcom_hosts[MAX_UFS_QCOM_HOSTS]; static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host); static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, u32 clk_cycles, - u32 clk_40ns_cycles); + u32 clk_40ns_cycles, + bool scale_up); static struct ufs_qcom_host *rcdev_to_ufs_host(struct reset_controller_dev *rcd) { @@ -700,19 +701,19 @@ static int ufs_qcom_cfg_core_clk_ctrl(struct ufs_hba *hba) switch (max_freq) { case MHZ_403: - err = ufs_qcom_set_core_clk_ctrl(hba, 403, 16); + err = ufs_qcom_set_core_clk_ctrl(hba, 403, 16, true); break; case MHZ_300: - err = ufs_qcom_set_core_clk_ctrl(hba, 300, 12); + err = ufs_qcom_set_core_clk_ctrl(hba, 300, 12, true); break; case MHZ_201_5: - err = ufs_qcom_set_core_clk_ctrl(hba, 202, 8); + err = ufs_qcom_set_core_clk_ctrl(hba, 202, 8, true); break; case MHZ_150: - err = ufs_qcom_set_core_clk_ctrl(hba, 150, 6); + err = ufs_qcom_set_core_clk_ctrl(hba, 150, 6, true); break; case MHZ_100: - err = ufs_qcom_set_core_clk_ctrl(hba, 100, 4); + err = ufs_qcom_set_core_clk_ctrl(hba, 100, 4, true); break; default: dev_err(hba->dev, "unipro max_freq=%u entry missing\n", max_freq); @@ -1352,7 +1353,8 @@ static void ufs_qcom_exit(struct ufs_hba *hba) static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, u32 clk_1us_cycles, - u32 clk_40ns_cycles) + u32 clk_40ns_cycles, + bool scale_up) { struct ufs_qcom_host *host = ufshcd_get_variant(hba); u32 mask = DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK; @@ -1378,18 +1380,20 @@ static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, core_clk_ctrl_reg &= ~(mask << offset); core_clk_ctrl_reg |= clk_1us_cycles << offset; - /* Clear CORE_CLK_DIV_EN */ - core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT; + if (scale_up) + core_clk_ctrl_reg |= CORE_CLK_DIV_EN_BIT; err = ufshcd_dme_set(hba, - UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), - core_clk_ctrl_reg); + UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), + core_clk_ctrl_reg); + if (err) + return err; /* * UFS host controller V4.0.0 onwards needs to program * PA_VS_CORE_CLK_40NS_CYCLES attribute per programmed * frequency of unipro core clk of UFS host controller. */ - if (!err && (host->hw_ver.major >= 4)) { + if (host->hw_ver.major >= 4) { if (clk_40ns_cycles > PA_VS_CORE_CLK_40NS_CYCLES_MASK) return -EINVAL; @@ -1442,22 +1446,21 @@ static int ufs_qcom_clk_scale_down_pre_change(struct ufs_hba *hba) { struct ufs_qcom_host *host = ufshcd_get_variant(hba); int err; - u32 core_clk_ctrl_reg; + u32 reg; if (!ufs_qcom_cap_qunipro(host)) return 0; - err = ufshcd_dme_get(hba, - UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), - &core_clk_ctrl_reg); + err = ufshcd_dme_get(hba, UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), ®); + if (err) + return err; /* make sure CORE_CLK_DIV_EN is cleared */ - if (!err && - (core_clk_ctrl_reg & DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT)) { - core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT; + if (reg & CORE_CLK_DIV_EN_BIT) { + reg &= ~CORE_CLK_DIV_EN_BIT; err = ufshcd_dme_set(hba, UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), - core_clk_ctrl_reg); + reg); } return err; @@ -1488,13 +1491,13 @@ static int ufs_qcom_clk_scale_down_post_change(struct ufs_hba *hba) } switch (curr_freq) { case MHZ_37_5: - err = ufs_qcom_set_core_clk_ctrl(hba, 38, 2); + err = ufs_qcom_set_core_clk_ctrl(hba, 38, 2, false); break; case MHZ_75: - err = ufs_qcom_set_core_clk_ctrl(hba, 75, 3); + err = ufs_qcom_set_core_clk_ctrl(hba, 75, 3, false); break; case MHZ_100: - err = ufs_qcom_set_core_clk_ctrl(hba, 100, 4); + err = ufs_qcom_set_core_clk_ctrl(hba, 100, 4, false); break; default: err = -EINVAL; diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h index 56550fd36c4e..6e8eb4bb9247 100644 --- a/drivers/ufs/host/ufs-qcom.h +++ b/drivers/ufs/host/ufs-qcom.h @@ -140,7 +140,7 @@ enum { /* bit and mask definitions for DME_VS_CORE_CLK_CTRL attribute */ #define MAX_CORE_CLK_1US_CYCLES_MASK_V4 0xFFF #define MAX_CORE_CLK_1US_CYCLES_OFFSET_V4 0x10 -#define DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT BIT(8) +#define CORE_CLK_DIV_EN_BIT BIT(8) #define DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK 0xFF #define PA_VS_CORE_CLK_40NS_CYCLES 0x9007 #define PA_VS_CORE_CLK_40NS_CYCLES_MASK 0x3F