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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id s12-20020adfeccc000000b00317b5c8a4f1sm21844004wro.60.2023.08.24.02.28.37 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Aug 2023 02:28:37 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/35] hw/gpio/nrf51: implement DETECT signal Date: Thu, 24 Aug 2023 10:28:02 +0100 Message-Id: <20230824092836.2239644-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230824092836.2239644-1-peter.maydell@linaro.org> References: <20230824092836.2239644-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Chris Laplante Implement nRF51 DETECT signal in the GPIO peripheral. The reference manual makes mention of a per-pin DETECT signal, but these are not exposed to the user. See https://devzone.nordicsemi.com/f/nordic-q-a/39858/gpio-per-pin-detect-signal-available for more information. Currently, I don't see a reason to model these. Signed-off-by: Chris Laplante Reviewed-by: Peter Maydell Message-id: 20230728160324.1159090-2-chris@laplante.io Signed-off-by: Peter Maydell --- include/hw/gpio/nrf51_gpio.h | 1 + hw/gpio/nrf51_gpio.c | 14 +++++++++++++- 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/include/hw/gpio/nrf51_gpio.h b/include/hw/gpio/nrf51_gpio.h index 8f9c2f86da3..fcfa2bac173 100644 --- a/include/hw/gpio/nrf51_gpio.h +++ b/include/hw/gpio/nrf51_gpio.h @@ -64,6 +64,7 @@ struct NRF51GPIOState { uint32_t old_out_connected; qemu_irq output[NRF51_GPIO_PINS]; + qemu_irq detect; }; diff --git a/hw/gpio/nrf51_gpio.c b/hw/gpio/nrf51_gpio.c index b47fddf4ed6..08396c69a4b 100644 --- a/hw/gpio/nrf51_gpio.c +++ b/hw/gpio/nrf51_gpio.c @@ -78,6 +78,7 @@ static void update_state(NRF51GPIOState *s) int pull; size_t i; bool connected_out, dir, connected_in, out, in, input; + bool assert_detect = false; for (i = 0; i < NRF51_GPIO_PINS; i++) { pull = pull_value(s->cnf[i]); @@ -99,7 +100,15 @@ static void update_state(NRF51GPIOState *s) qemu_log_mask(LOG_GUEST_ERROR, "GPIO pin %zu short circuited\n", i); } - if (!connected_in) { + if (connected_in) { + uint32_t detect_config = extract32(s->cnf[i], 16, 2); + if ((detect_config == 2) && (in == 1)) { + assert_detect = true; + } + if ((detect_config == 3) && (in == 0)) { + assert_detect = true; + } + } else { /* * Floating input: the output stimulates IN if connected, * otherwise pull-up/pull-down resistors put a value on both @@ -116,6 +125,8 @@ static void update_state(NRF51GPIOState *s) } update_output_irq(s, i, connected_out, out); } + + qemu_set_irq(s->detect, assert_detect); } /* @@ -291,6 +302,7 @@ static void nrf51_gpio_init(Object *obj) qdev_init_gpio_in(DEVICE(s), nrf51_gpio_set, NRF51_GPIO_PINS); qdev_init_gpio_out(DEVICE(s), s->output, NRF51_GPIO_PINS); + qdev_init_gpio_out_named(DEVICE(s), &s->detect, "detect", 1); } static void nrf51_gpio_class_init(ObjectClass *klass, void *data) From patchwork Thu Aug 24 09:28:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 716537 Delivered-To: patch@linaro.org Received: by 2002:adf:f747:0:b0:317:ecd7:513f with SMTP id z7csp1237651wrp; Thu, 24 Aug 2023 02:34:38 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHbQaexJwy5fzAJBcAWPP0Pe6k4Zf0Vf2vslgz/rvBu7Fo16ZthbD0JnHZsrcnb0nw68Bs2 X-Received: by 2002:ac8:7f95:0:b0:403:a662:a3c1 with SMTP id z21-20020ac87f95000000b00403a662a3c1mr19673182qtj.29.1692869677940; Thu, 24 Aug 2023 02:34:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1692869677; cv=none; d=google.com; s=arc-20160816; b=u9bWQHCaLIbq6GcZuqkuGcfH8K9WfpZJd+1zaLTgN/SLxdx4CXd75Wstske5fbBbJc kzymkj+BJ+ycETKNeRbZNMs/zj7nykY5ow0Idn1g2dLLEgspbbysI8aRI0yQUDWAkqsV 0FsFTjJyQP9UanJ00x12uFna09a3P2aOVbmlTTI3wgtsq/8lXXZEJEWCXgVBgH4uf8u1 Xec2MYtiG45E0OUUWUMLDsQ5eeIQtj0C0Klqx5FXlizdZCL9u1tHwii64C2K3crOoSf+ BzyMPsV5jYM7QbZt27cqCIpQ3meMrf/lPJx6HT5sATHAYRVRMSQXA3qWEmUuoTRBf2fU OxxQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=tswNfDLVJW3+gP/uE8SUQjolW4HExHb2Af24QmhcctE=; fh=bFDrUYhlTVi/QyetgXx/byg2+yO/22Hp9SjwoefyKLk=; b=leMkJZzWQaOafTvMM1LqFrD+5k1x2YrI8qaQz53Uy3FazOyu4Jqt5d3wUsOAcwyjHj ZrGykQFKGTdIiSgZzYedEnsCTUnVaSQLKkarKkQ2xvKi3i4PO5GvI5ukbuux2vN3/PTd BU1NQTERP+DUlNgBFYziiwJJ0CS/BZHq/81V/HMMj5fHxwdW7/Xo8JdmNS5qIrR1boJV h6f7bIB9Tc+mUW7FijGirlMGyE1n8f8FLAN3Q6uDUpghu2D4xQNG+nnDCQvSPZS5pOMh MYTNLZcFI96OijrWagSPZ9ybQ+WZVZpm+q+jvI9iuJwR6YEa/Uz18eFcXfznIzDSRvWc 9JMQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=mTf67cUp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id s12-20020adfeccc000000b00317b5c8a4f1sm21844004wro.60.2023.08.24.02.28.38 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Aug 2023 02:28:38 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/35] qtest: factor out qtest_install_gpio_out_intercept Date: Thu, 24 Aug 2023 10:28:03 +0100 Message-Id: <20230824092836.2239644-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230824092836.2239644-1-peter.maydell@linaro.org> References: <20230824092836.2239644-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Chris Laplante Signed-off-by: Chris Laplante Reviewed-by: Peter Maydell Message-id: 20230728160324.1159090-3-chris@laplante.io Signed-off-by: Peter Maydell --- softmmu/qtest.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/softmmu/qtest.c b/softmmu/qtest.c index f8d764b7190..1b864891629 100644 --- a/softmmu/qtest.c +++ b/softmmu/qtest.c @@ -365,6 +365,15 @@ void qtest_set_command_cb(bool (*pc_cb)(CharBackend *chr, gchar **words)) process_command_cb = pc_cb; } +static void qtest_install_gpio_out_intercept(DeviceState *dev, const char *name, int n) +{ + qemu_irq *disconnected = g_new0(qemu_irq, 1); + qemu_irq icpt = qemu_allocate_irq(qtest_irq_handler, + disconnected, n); + + *disconnected = qdev_intercept_gpio_out(dev, icpt, name, n); +} + static void qtest_process_command(CharBackend *chr, gchar **words) { const gchar *command; @@ -415,12 +424,7 @@ static void qtest_process_command(CharBackend *chr, gchar **words) if (words[0][14] == 'o') { int i; for (i = 0; i < ngl->num_out; ++i) { - qemu_irq *disconnected = g_new0(qemu_irq, 1); - qemu_irq icpt = qemu_allocate_irq(qtest_irq_handler, - disconnected, i); - - *disconnected = qdev_intercept_gpio_out(dev, icpt, - ngl->name, i); + qtest_install_gpio_out_intercept(dev, ngl->name, i); } } else { qemu_irq_intercept_in(ngl->in, qtest_irq_handler, From patchwork Thu Aug 24 09:28:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 716510 Delivered-To: patch@linaro.org Received: by 2002:adf:f747:0:b0:317:ecd7:513f with SMTP id z7csp1235970wrp; Thu, 24 Aug 2023 02:29:48 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGlZcOFnpI9fGuaiu3rcJ3NKcMv7FENcfHJbBXcvEhoJkjLeC4566ED58MhKnkCH4v78Q/d X-Received: by 2002:a05:620a:1a06:b0:76d:b7fe:6b2e with SMTP id bk6-20020a05620a1a0600b0076db7fe6b2emr7155210qkb.29.1692869388379; Thu, 24 Aug 2023 02:29:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1692869388; cv=none; d=google.com; s=arc-20160816; b=jFTr2pnAzOF36gnnRneQ72AVQaIL1tlk8pFWRGjy9fAzMabxeq5KGMEcsnRhieS5or D4577Fd+1RWNO7b4aiX6rFRcCEaWXzmYU/HZuY6LH4T8eV/IcsGyvSxam46tNcYH8c2/ L6Q2TCK4Kts5yGuC0UHCkk9QjUAiKlyfQKTyU0f0ih3R8L8vYefCmiIelkaFdlMHxJqs OK4rwescPJKxuR8GCFizZ5+z2CX3J/pLG4v4LswTH6YQHa4ppDkDKhTt2gFQi1O0nltT GLE2DqCxevfNocQECgIeKW5mBhXtuFQ6TIFERWsZZMWSx1rdFBQCnukQPwS/fSAcQoYa tLHA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=UyC6pkxktpI+U9x2+x+ifLYzV9VlMFeTgo38T5/icxQ=; fh=bFDrUYhlTVi/QyetgXx/byg2+yO/22Hp9SjwoefyKLk=; b=V0ggyvP7v/Jc/814nl4ou7Ds5OGeUQdJ+Pr0FXRC95EaW1LXnSg16kQlMoX3kbvl6E NbdJL1xjwc1w1WSM5esd+FAbGsZbzdaXSjH/DUwdvpW6ePgZSH2M+Kq0IVTqrgV1oFue JnRf0NBD9Prik9uZGC6tm/CVEHBGdl7Dl/+II26oJpYkU8yAyP/4uTW735iv+94vyp2a ycWZE2JCpYPr/aPgMGMgxAhSXJa2Uh4OEOKeg/Ew8MYm592/PZz63gBi/O55iaClBIN6 dZN4ZMuAURtSngm1dNLkBmzy7aOwynkvpYnozXU0HVFtkE9S5kCANxecoqYsSkU2fDF3 qPqQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Wx8gdMfW; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id s12-20020adfeccc000000b00317b5c8a4f1sm21844004wro.60.2023.08.24.02.28.38 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Aug 2023 02:28:38 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/35] qtest: implement named interception of out-GPIO Date: Thu, 24 Aug 2023 10:28:04 +0100 Message-Id: <20230824092836.2239644-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230824092836.2239644-1-peter.maydell@linaro.org> References: <20230824092836.2239644-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Chris Laplante Adds qtest_irq_intercept_out_named method, which utilizes a new optional name parameter to the irq_intercept_out qtest command. Signed-off-by: Chris Laplante Message-id: 20230728160324.1159090-4-chris@laplante.io Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- tests/qtest/libqtest.h | 11 +++++++++++ softmmu/qtest.c | 18 ++++++++++-------- tests/qtest/libqtest.c | 6 ++++++ 3 files changed, 27 insertions(+), 8 deletions(-) diff --git a/tests/qtest/libqtest.h b/tests/qtest/libqtest.h index 3a71bc45fcf..e53e350e3a6 100644 --- a/tests/qtest/libqtest.h +++ b/tests/qtest/libqtest.h @@ -371,6 +371,17 @@ void qtest_irq_intercept_in(QTestState *s, const char *string); */ void qtest_irq_intercept_out(QTestState *s, const char *string); +/** + * qtest_irq_intercept_out_named: + * @s: #QTestState instance to operate on. + * @qom_path: QOM path of a device. + * @name: Name of the GPIO out pin + * + * Associate a qtest irq with the named GPIO-out pin of the device + * whose path is specified by @string and whose name is @name. + */ +void qtest_irq_intercept_out_named(QTestState *s, const char *qom_path, const char *name); + /** * qtest_set_irq_in: * @s: QTestState instance to operate on. diff --git a/softmmu/qtest.c b/softmmu/qtest.c index 1b864891629..0f1d478bda5 100644 --- a/softmmu/qtest.c +++ b/softmmu/qtest.c @@ -397,8 +397,10 @@ static void qtest_process_command(CharBackend *chr, gchar **words) || strcmp(words[0], "irq_intercept_in") == 0) { DeviceState *dev; NamedGPIOList *ngl; + bool is_outbound; g_assert(words[1]); + is_outbound = words[0][14] == 'o'; dev = DEVICE(object_resolve_path(words[1], NULL)); if (!dev) { qtest_send_prefix(chr); @@ -417,14 +419,14 @@ static void qtest_process_command(CharBackend *chr, gchar **words) } QLIST_FOREACH(ngl, &dev->gpios, node) { - /* We don't support intercept of named GPIOs yet */ - if (ngl->name) { - continue; - } - if (words[0][14] == 'o') { - int i; - for (i = 0; i < ngl->num_out; ++i) { - qtest_install_gpio_out_intercept(dev, ngl->name, i); + /* We don't support inbound interception of named GPIOs yet */ + if (is_outbound) { + /* NULL is valid and matchable, for "unnamed GPIO" */ + if (g_strcmp0(ngl->name, words[2]) == 0) { + int i; + for (i = 0; i < ngl->num_out; ++i) { + qtest_install_gpio_out_intercept(dev, ngl->name, i); + } } } else { qemu_irq_intercept_in(ngl->in, qtest_irq_handler, diff --git a/tests/qtest/libqtest.c b/tests/qtest/libqtest.c index c22dfc30d3d..471529e6cc3 100644 --- a/tests/qtest/libqtest.c +++ b/tests/qtest/libqtest.c @@ -993,6 +993,12 @@ void qtest_irq_intercept_out(QTestState *s, const char *qom_path) qtest_rsp(s); } +void qtest_irq_intercept_out_named(QTestState *s, const char *qom_path, const char *name) +{ + qtest_sendf(s, "irq_intercept_out %s %s\n", qom_path, name); + qtest_rsp(s); +} + void qtest_irq_intercept_in(QTestState *s, const char *qom_path) { qtest_sendf(s, "irq_intercept_in %s\n", qom_path); From patchwork Thu Aug 24 09:28:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 716538 Delivered-To: patch@linaro.org Received: by 2002:adf:f747:0:b0:317:ecd7:513f with SMTP id z7csp1237666wrp; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id s12-20020adfeccc000000b00317b5c8a4f1sm21844004wro.60.2023.08.24.02.28.39 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Aug 2023 02:28:39 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/35] qtest: bail from irq_intercept_in if name is specified Date: Thu, 24 Aug 2023 10:28:05 +0100 Message-Id: <20230824092836.2239644-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230824092836.2239644-1-peter.maydell@linaro.org> References: <20230824092836.2239644-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Chris Laplante Named interception of in-GPIOs is not supported yet. Signed-off-by: Chris Laplante Reviewed-by: Peter Maydell Message-id: 20230728160324.1159090-5-chris@laplante.io Signed-off-by: Peter Maydell --- softmmu/qtest.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/softmmu/qtest.c b/softmmu/qtest.c index 0f1d478bda5..66757ba2618 100644 --- a/softmmu/qtest.c +++ b/softmmu/qtest.c @@ -397,9 +397,11 @@ static void qtest_process_command(CharBackend *chr, gchar **words) || strcmp(words[0], "irq_intercept_in") == 0) { DeviceState *dev; NamedGPIOList *ngl; + bool is_named; bool is_outbound; g_assert(words[1]); + is_named = words[2] != NULL; is_outbound = words[0][14] == 'o'; dev = DEVICE(object_resolve_path(words[1], NULL)); if (!dev) { @@ -408,6 +410,12 @@ static void qtest_process_command(CharBackend *chr, gchar **words) return; } + if (is_named && !is_outbound) { + qtest_send_prefix(chr); + qtest_send(chr, "FAIL Interception of named in-GPIOs not yet supported\n"); + return; + } + if (irq_intercept_dev) { qtest_send_prefix(chr); if (irq_intercept_dev != dev) { From patchwork Thu Aug 24 09:28:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 716535 Delivered-To: patch@linaro.org Received: by 2002:adf:f747:0:b0:317:ecd7:513f with SMTP id z7csp1237491wrp; Thu, 24 Aug 2023 02:34:05 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHhFr3ftNchVnXxWfaJszAPx084i4A82W/kkRC3XBmUIHiPaJGd16rihnc7TkYrHHRlIYNE X-Received: by 2002:a05:622a:44c:b0:410:9626:f0bf with SMTP id o12-20020a05622a044c00b004109626f0bfmr12874492qtx.13.1692869644840; Thu, 24 Aug 2023 02:34:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1692869644; cv=none; d=google.com; s=arc-20160816; b=TcSVyCtskldmwEpYk/s+irG1sRy4z0yhj8lNm6L3i+SF6UzoPl1MHNc1AonsFlb2Zl HJbw/I/ZQIrg3+ZCtC85HlUZVp3Ez3gByxJ9oTVmKQSrdvJSc0B8n5IaOWVBcS90DONI EVNsSdBbvqZZXBR5vYdv5+5aTOfp7UUNhYdEqL6q6mptoLoZGNH5NP9ik01WBQxFcwCE 0QckpjK18JuREC2XzPLbDGmBkGVsXto65qtlpSQQu51vaX0Bj3LxzYnG9mbWCi2QILyw +SeIkAL78uH+LaR6p5hrzM6lJbIRwEpLFp2F++WoIq/Vfq4o/kgAKbKuaq0/wqVRsZgC c+hA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=yoGfh1IvGmJKIOpV0F76Srck7ySJzUuEK4yJEk7+R08=; fh=bFDrUYhlTVi/QyetgXx/byg2+yO/22Hp9SjwoefyKLk=; b=Cc33u3x/vExPVgPtIwehX9QbYovKiy87c7tXxikmCPTl9gBufh+tKWTvL2d40sArzy BxAzANbj/9GJ9tSCeaHfMogSA5yatSYR2a2sPqi7g57gLyVqwlSw9XWKniMW7IZZ/J2V g9IwgPkma/SVW0cdivYiUSttnLhVd0Ah1o3O50JGhUnfYGRaX0Jyz8ewZ4bP8K+ubJOo EDjIPJWS+RXTiHNKnkKGeTfmn43uhytTQS/Tg4TVj36Qg3OMKyKPH6gCADMqWtacVXN1 tnCB862DlEe1LlcDYng8ww1NV4ZX6ZxUaH8CPqVKrHJqhV7sIu4C2V+wS1PDpnuAIhso iw5g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=aodfqDNn; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id s12-20020adfeccc000000b00317b5c8a4f1sm21844004wro.60.2023.08.24.02.28.39 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Aug 2023 02:28:39 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/35] qtest: irq_intercept_[out/in]: return FAIL if no intercepts are installed Date: Thu, 24 Aug 2023 10:28:06 +0100 Message-Id: <20230824092836.2239644-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230824092836.2239644-1-peter.maydell@linaro.org> References: <20230824092836.2239644-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Chris Laplante This is much better than just silently failing with OK. Signed-off-by: Chris Laplante Message-id: 20230728160324.1159090-6-chris@laplante.io Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- softmmu/qtest.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/softmmu/qtest.c b/softmmu/qtest.c index 66757ba2618..35b643a274c 100644 --- a/softmmu/qtest.c +++ b/softmmu/qtest.c @@ -399,6 +399,7 @@ static void qtest_process_command(CharBackend *chr, gchar **words) NamedGPIOList *ngl; bool is_named; bool is_outbound; + bool interception_succeeded = false; g_assert(words[1]); is_named = words[2] != NULL; @@ -435,15 +436,22 @@ static void qtest_process_command(CharBackend *chr, gchar **words) for (i = 0; i < ngl->num_out; ++i) { qtest_install_gpio_out_intercept(dev, ngl->name, i); } + interception_succeeded = true; } } else { qemu_irq_intercept_in(ngl->in, qtest_irq_handler, ngl->num_in); + interception_succeeded = true; } } - irq_intercept_dev = dev; + qtest_send_prefix(chr); - qtest_send(chr, "OK\n"); + if (interception_succeeded) { + irq_intercept_dev = dev; + qtest_send(chr, "OK\n"); + } else { + qtest_send(chr, "FAIL No intercepts installed\n"); + } } else if (strcmp(words[0], "set_irq_in") == 0) { DeviceState *dev; qemu_irq irq; From patchwork Thu Aug 24 09:28:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 716540 Delivered-To: patch@linaro.org Received: by 2002:adf:f747:0:b0:317:ecd7:513f with SMTP id z7csp1237689wrp; Thu, 24 Aug 2023 02:34:46 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHssG9nwmCGdob0GGtMV+l/Itp98t47+v7gy0ze3FVMWRHL0wsjS+N1S7PDE33kG4oy7Ylb X-Received: by 2002:a05:622a:1894:b0:403:c687:bfb6 with SMTP id v20-20020a05622a189400b00403c687bfb6mr18263052qtc.1.1692869685930; Thu, 24 Aug 2023 02:34:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1692869685; cv=none; d=google.com; s=arc-20160816; b=jrDIZYnzmUwADIKiqS8R8MZdCutTJwi385F4ewicS7b4IVfKQqh30F32E6jz5rPvPn AFTy9zBMZsSQKf96rvpcdkOjk7Np47xIEKQBY5eG8rXRk+XRBNa0TMYmrsm6ki8DXBku i2IvrqCxGbeoWfT8O2I/ZSqeQieTvCM5n7VP5lF96IOqc9aAqkeD5ctXi4R1JBcFsf+z VtwMZB5naiKPh1uZrg2BCLkX9sn8OOSqjS09emK7Qotxmtpamg7CVAJtbzMuLIABdV4i DNcDEf5UN5N/rclX2nKV+AHlUkV2oOUQufEVJNREDHjcyKDSj4u9xEpyO3Z7XphByl5K p2mA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=maKnpTX0sEKhyGC+nkCmnNKwDO8LJpaRhDI6Hxo5ERE=; fh=bFDrUYhlTVi/QyetgXx/byg2+yO/22Hp9SjwoefyKLk=; b=mzMZ5bIfftEf0sNjmQGMEVoKDw1ToFg/fPPYjRm0NyfNNKJbCxuVt7X6Y8VgqbeeKK aIEKJxfCT17C62AQu0YlY/Not2mO78wIGRN5CDKzqGGiXvk+pSwDr6qezHcAVwlear/9 6uvJLIYw7keKppC/lHwsr6GbSM0InNEUzR96z8G/IoMbnjSWpuXtQInHcp97c5T+ldJ+ +AvIH2XwXhNizgfVajepN15+8qgB4mGaTCMNeoyZ5ATgDY/tZyEjXXpUH7G2kn5CQM9g UUx7uFz2F7umqzIWZEpyQegyckAAvfITCNapUJjsVv8CnYk+BatWivuWvUcTu04sbxDk Wb6A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vEJjrMCP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id s12-20020adfeccc000000b00317b5c8a4f1sm21844004wro.60.2023.08.24.02.28.40 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Aug 2023 02:28:40 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/35] qtest: microbit-test: add tests for nRF51 DETECT Date: Thu, 24 Aug 2023 10:28:07 +0100 Message-Id: <20230824092836.2239644-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230824092836.2239644-1-peter.maydell@linaro.org> References: <20230824092836.2239644-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Chris Laplante Exercise the DETECT mechanism of the GPIO peripheral. Signed-off-by: Chris Laplante Reviewed-by: Peter Maydell Message-id: 20230728160324.1159090-7-chris@laplante.io [PMM: fixed coding style nits] Signed-off-by: Peter Maydell --- tests/qtest/microbit-test.c | 44 +++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/tests/qtest/microbit-test.c b/tests/qtest/microbit-test.c index 6022a92b6a9..2abcad8e31c 100644 --- a/tests/qtest/microbit-test.c +++ b/tests/qtest/microbit-test.c @@ -393,6 +393,49 @@ static void test_nrf51_gpio(void) qtest_quit(qts); } +static void test_nrf51_gpio_detect(void) +{ + QTestState *qts = qtest_init("-M microbit"); + int i; + + /* Connect input buffer on pins 1-7, configure SENSE for high level */ + for (i = 1; i <= 7; i++) { + qtest_writel(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START + i * 4, + deposit32(0, 16, 2, 2)); + } + + qtest_irq_intercept_out_named(qts, "/machine/nrf51/gpio", "detect"); + + for (i = 1; i <= 7; i++) { + /* Set pin high */ + qtest_set_irq_in(qts, "/machine/nrf51", "unnamed-gpio-in", i, 1); + uint32_t actual = qtest_readl(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_IN); + g_assert_cmpuint(actual, ==, 1 << i); + + /* Check that DETECT is high */ + g_assert_true(qtest_get_irq(qts, 0)); + + /* Set pin low, check that DETECT goes low. */ + qtest_set_irq_in(qts, "/machine/nrf51", "unnamed-gpio-in", i, 0); + actual = qtest_readl(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_IN); + g_assert_cmpuint(actual, ==, 0x0); + g_assert_false(qtest_get_irq(qts, 0)); + } + + /* Set pin 0 high, check that DETECT doesn't fire */ + qtest_set_irq_in(qts, "/machine/nrf51", "unnamed-gpio-in", 0, 1); + g_assert_false(qtest_get_irq(qts, 0)); + qtest_set_irq_in(qts, "/machine/nrf51", "unnamed-gpio-in", 0, 0); + + /* Set pins 1, 2, and 3 high, then set 3 low. Check DETECT is still high */ + for (i = 1; i <= 3; i++) { + qtest_set_irq_in(qts, "/machine/nrf51", "unnamed-gpio-in", i, 1); + } + g_assert_true(qtest_get_irq(qts, 0)); + qtest_set_irq_in(qts, "/machine/nrf51", "unnamed-gpio-in", 3, 0); + g_assert_true(qtest_get_irq(qts, 0)); +} + static void timer_task(QTestState *qts, hwaddr task) { qtest_writel(qts, NRF51_TIMER_BASE + task, NRF51_TRIGGER_TASK); @@ -499,6 +542,7 @@ int main(int argc, char **argv) qtest_add_func("/microbit/nrf51/uart", test_nrf51_uart); qtest_add_func("/microbit/nrf51/gpio", test_nrf51_gpio); + qtest_add_func("/microbit/nrf51/gpio_detect", test_nrf51_gpio_detect); qtest_add_func("/microbit/nrf51/nvmc", test_nrf51_nvmc); qtest_add_func("/microbit/nrf51/timer", test_nrf51_timer); qtest_add_func("/microbit/microbit/i2c", test_microbit_i2c); From patchwork Thu Aug 24 09:28:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 716531 Delivered-To: patch@linaro.org Received: by 2002:adf:f747:0:b0:317:ecd7:513f with SMTP id z7csp1237365wrp; Thu, 24 Aug 2023 02:33:46 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGnI+aA0Hgzd5/jmZ9tv79unpT8M33HOscSrfWDAGP/OVsGtPG3ZI5uL1WQxjF2ODBJch/0 X-Received: by 2002:a0c:e484:0:b0:635:e4ed:b6c9 with SMTP id n4-20020a0ce484000000b00635e4edb6c9mr10826745qvl.24.1692869626593; Thu, 24 Aug 2023 02:33:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1692869626; cv=none; d=google.com; s=arc-20160816; b=GiKwDOyiJePTmHCM6PRD5jZH4gYOGXVsAq8vtjVa/YoEtazELqSDoOE/9nYHeHfrl5 FAY34RcbQ/58qs/JDiNXzNbSgjIFEusexF/RLH68H8AkuYwSOGebjCSkWfRhCM8eqiLU SMAElLvWJjBqrRuIAZduBhXlJ0cmdRgo9yD+ZHYPrZMKaDzsaO84Gkd4kNPF1APRz0n0 Tp2rzV2iRJlBc27bZUmP3N6Qdfb/wV39p93Qu9QRNG8BFAIeFvAJiUB3GUuBi2fIR+qr bTyGS7zuFYeAVfiTrbi8NERRLJnecP2kEg5wD2XjfD1hB/ap3XuuN7O78b1PAgLFIve7 9YCg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=aeZYZvq4ZfImxsLYgMAThvvPorW5jC9WKxbUYeQ9C3c=; fh=bFDrUYhlTVi/QyetgXx/byg2+yO/22Hp9SjwoefyKLk=; b=EY6Dw2C4Y3y/vCb+CaW/rijnuGET2jAkti2r9E3/S1Ju+ULDY+QAOCMcy8MrYV2voY ZTIK2EDbwVHk9zJouuNP76qaXGWSUwnlNH9wY/OTHCuw/uCDKfNfbaEKDFqU10B5sid+ LfcAbDroCGsI0WBFJbywb0cC1a6QC52ECoMLI1FRpHbmh96uSslPv0bHzivl+OnB4zlS +nQSwCwfAIF56WEHLrgoEyNgCSwjFvicrrwmMXN3Viy+qm9dUiVXyGhj96yPu1jCuP1S fi5qkReT3Iueinlrl6EZWrUHysc2ouFjD9CJMuZKN1UUr6ApzaOZYwnqVJeKPMLd7akB VlCA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=LCvQkh3x; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id s12-20020adfeccc000000b00317b5c8a4f1sm21844004wro.60.2023.08.24.02.28.40 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Aug 2023 02:28:40 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/35] kvm: Introduce kvm_arch_get_default_type hook Date: Thu, 24 Aug 2023 10:28:08 +0100 Message-Id: <20230824092836.2239644-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230824092836.2239644-1-peter.maydell@linaro.org> References: <20230824092836.2239644-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Akihiko Odaki kvm_arch_get_default_type() returns the default KVM type. This hook is particularly useful to derive a KVM type that is valid for "none" machine model, which is used by libvirt to probe the availability of KVM. For MIPS, the existing mips_kvm_type() is reused. This function ensures the availability of VZ which is mandatory to use KVM on the current QEMU. Cc: qemu-stable@nongnu.org Signed-off-by: Akihiko Odaki Message-id: 20230727073134.134102-2-akihiko.odaki@daynix.com Reviewed-by: Peter Maydell [PMM: added doc comment for new function] Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé --- include/sysemu/kvm.h | 2 ++ target/mips/kvm_mips.h | 9 --------- accel/kvm/kvm-all.c | 4 +++- hw/mips/loongson3_virt.c | 2 -- target/arm/kvm.c | 5 +++++ target/i386/kvm/kvm.c | 5 +++++ target/mips/kvm.c | 2 +- target/ppc/kvm.c | 5 +++++ target/riscv/kvm.c | 5 +++++ target/s390x/kvm/kvm.c | 5 +++++ 10 files changed, 31 insertions(+), 13 deletions(-) diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h index 115f0cca79d..ccaf55caf73 100644 --- a/include/sysemu/kvm.h +++ b/include/sysemu/kvm.h @@ -369,6 +369,8 @@ int kvm_arch_get_registers(CPUState *cpu); int kvm_arch_put_registers(CPUState *cpu, int level); +int kvm_arch_get_default_type(MachineState *ms); + int kvm_arch_init(MachineState *ms, KVMState *s); int kvm_arch_init_vcpu(CPUState *cpu); diff --git a/target/mips/kvm_mips.h b/target/mips/kvm_mips.h index 171d53dbe13..c711269d0af 100644 --- a/target/mips/kvm_mips.h +++ b/target/mips/kvm_mips.h @@ -25,13 +25,4 @@ void kvm_mips_reset_vcpu(MIPSCPU *cpu); int kvm_mips_set_interrupt(MIPSCPU *cpu, int irq, int level); int kvm_mips_set_ipi_interrupt(MIPSCPU *cpu, int irq, int level); -#ifdef CONFIG_KVM -int mips_kvm_type(MachineState *machine, const char *vm_type); -#else -static inline int mips_kvm_type(MachineState *machine, const char *vm_type) -{ - return 0; -} -#endif - #endif /* KVM_MIPS_H */ diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c index 7b3da8dc3ab..b4723016379 100644 --- a/accel/kvm/kvm-all.c +++ b/accel/kvm/kvm-all.c @@ -2458,7 +2458,7 @@ static int kvm_init(MachineState *ms) KVMState *s; const KVMCapabilityInfo *missing_cap; int ret; - int type = 0; + int type; uint64_t dirty_log_manual_caps; qemu_mutex_init(&kml_slots_lock); @@ -2523,6 +2523,8 @@ static int kvm_init(MachineState *ms) type = mc->kvm_type(ms, kvm_type); } else if (mc->kvm_type) { type = mc->kvm_type(ms, NULL); + } else { + type = kvm_arch_get_default_type(ms); } do { diff --git a/hw/mips/loongson3_virt.c b/hw/mips/loongson3_virt.c index 3ad0a223df7..b74b358874f 100644 --- a/hw/mips/loongson3_virt.c +++ b/hw/mips/loongson3_virt.c @@ -29,7 +29,6 @@ #include "qemu/datadir.h" #include "qapi/error.h" #include "elf.h" -#include "kvm_mips.h" #include "hw/char/serial.h" #include "hw/intc/loongson_liointc.h" #include "hw/mips/mips.h" @@ -612,7 +611,6 @@ static void loongson3v_machine_class_init(ObjectClass *oc, void *data) mc->max_cpus = LOONGSON_MAX_VCPUS; mc->default_ram_id = "loongson3.highram"; mc->default_ram_size = 1600 * MiB; - mc->kvm_type = mips_kvm_type; mc->minimum_page_bits = 14; mc->default_nic = "virtio-net-pci"; } diff --git a/target/arm/kvm.c b/target/arm/kvm.c index b4c7654f498..40f577bfd55 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -247,6 +247,11 @@ int kvm_arm_get_max_vm_ipa_size(MachineState *ms, bool *fixed_ipa) return ret > 0 ? ret : 40; } +int kvm_arch_get_default_type(MachineState *ms) +{ + return 0; +} + int kvm_arch_init(MachineState *ms, KVMState *s) { int ret = 0; diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index ebfaf3d24c7..b45ce20fd8d 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -2556,6 +2556,11 @@ static void register_smram_listener(Notifier *n, void *unused) &smram_address_space, 1, "kvm-smram"); } +int kvm_arch_get_default_type(MachineState *ms) +{ + return 0; +} + int kvm_arch_init(MachineState *ms, KVMState *s) { uint64_t identity_base = 0xfffbc000; diff --git a/target/mips/kvm.c b/target/mips/kvm.c index c14e8f550fc..e98aad01bd5 100644 --- a/target/mips/kvm.c +++ b/target/mips/kvm.c @@ -1266,7 +1266,7 @@ int kvm_arch_msi_data_to_gsi(uint32_t data) abort(); } -int mips_kvm_type(MachineState *machine, const char *vm_type) +int kvm_arch_get_default_type(MachineState *machine) { #if defined(KVM_CAP_MIPS_VZ) int r; diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c index a8a935e2672..dc1182cd37e 100644 --- a/target/ppc/kvm.c +++ b/target/ppc/kvm.c @@ -108,6 +108,11 @@ static int kvm_ppc_register_host_cpu_type(void); static void kvmppc_get_cpu_characteristics(KVMState *s); static int kvmppc_get_dec_bits(void); +int kvm_arch_get_default_type(MachineState *ms) +{ + return 0; +} + int kvm_arch_init(MachineState *ms, KVMState *s) { cap_interrupt_unset = kvm_check_extension(s, KVM_CAP_PPC_UNSET_IRQ); diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index b1fd2233c03..dbcf26f27d3 100644 --- a/target/riscv/kvm.c +++ b/target/riscv/kvm.c @@ -914,6 +914,11 @@ int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route, return 0; } +int kvm_arch_get_default_type(MachineState *ms) +{ + return 0; +} + int kvm_arch_init(MachineState *ms, KVMState *s) { return 0; diff --git a/target/s390x/kvm/kvm.c b/target/s390x/kvm/kvm.c index a9e5880349d..9117fab6e8e 100644 --- a/target/s390x/kvm/kvm.c +++ b/target/s390x/kvm/kvm.c @@ -340,6 +340,11 @@ static void ccw_machine_class_foreach(ObjectClass *oc, void *opaque) mc->default_cpu_type = S390_CPU_TYPE_NAME("host"); } +int kvm_arch_get_default_type(MachineState *ms) +{ + return 0; +} + int kvm_arch_init(MachineState *ms, KVMState *s) { object_class_foreach(ccw_machine_class_foreach, TYPE_S390_CCW_MACHINE, From patchwork Thu Aug 24 09:28:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 716520 Delivered-To: patch@linaro.org Received: by 2002:adf:f747:0:b0:317:ecd7:513f with SMTP id z7csp1236239wrp; Thu, 24 Aug 2023 02:30:31 -0700 (PDT) X-Google-Smtp-Source: AGHT+IElSZ21KLAXhZTRySIWSJog1+yx1Xq3l5k+7Q8XCEFwDNhkC0XGZQk3PFPj/0NMjaKZDnsr X-Received: by 2002:a0c:aa91:0:b0:64f:49dd:c5fa with SMTP id f17-20020a0caa91000000b0064f49ddc5famr7769160qvb.62.1692869431497; Thu, 24 Aug 2023 02:30:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1692869431; cv=none; d=google.com; s=arc-20160816; b=JqMRZC7so+xwSj9TWl9Em0jtDz1HZdI7kcrYw+vHJ+zv0ZDEb8dCP3OjjovvM83Nhf V1MlfoNnt9G0NGvt7E6tZPr89q6hEylTmmnavVCPgOj6DJyYU4+sUdXS4xBvGrUka+6J 6PB9tquQfhb1BUoxU2UlkRCPR8DVbCC+tim4pJs3163Igxhe9MrWgV7MaayNsJpr0PtN q84J15B6kzwCLcv8oC8sqH8JckYALKL++4wMVa9Es4ah86t1dmm9Idp14vlgrfNRI1V7 VQIA9zI2QlEFCmUPRcogJJMfG/y18MOYWjaDMSESib8F3BarTQL4O5zhkSchCUZU40o3 RG0A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=dRFY4MrPTXsRJTRRlqLG+Tta4bFNbY1bwdeVb1jh0sw=; fh=bFDrUYhlTVi/QyetgXx/byg2+yO/22Hp9SjwoefyKLk=; b=U5UwXOJWAO0VNTamKNcb/WFc7YdepJZE5mcN1z+q+HMu4BbWQbmXa0ZbrciRePEKix uVu6VXMRHYVz8GB2msIlkXgmus9d1OdP+Iq4LZcSMAP2in5jXDZKCzixc0KOgocrLIAm 9s+BEZjWlYKg+WkEi9fNRZB1DrRakvko3xX6v0Ryqt3DD9L7QrIaAxzcrCF6g+ih7A79 oBOpnae9zuIwi1AUsi1a+0wnzno24TY+93t5hdTQFyyHgRjLBpGEGEzzzCtVpnlnE5ua NQQQU6oQSyvxQCsaLelGZ3eTTzIbNk1PmDVw03YRqrSI9iKLsHMJ+5bMzIwsxaorWCb/ HhhQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=e+b2tYo0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id s12-20020adfeccc000000b00317b5c8a4f1sm21844004wro.60.2023.08.24.02.28.40 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Aug 2023 02:28:41 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/35] accel/kvm: Specify default IPA size for arm64 Date: Thu, 24 Aug 2023 10:28:09 +0100 Message-Id: <20230824092836.2239644-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230824092836.2239644-1-peter.maydell@linaro.org> References: <20230824092836.2239644-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Akihiko Odaki Before this change, the default KVM type, which is used for non-virt machine models, was 0. The kernel documentation says: > On arm64, the physical address size for a VM (IPA Size limit) is > limited to 40bits by default. The limit can be configured if the host > supports the extension KVM_CAP_ARM_VM_IPA_SIZE. When supported, use > KVM_VM_TYPE_ARM_IPA_SIZE(IPA_Bits) to set the size in the machine type > identifier, where IPA_Bits is the maximum width of any physical > address used by the VM. The IPA_Bits is encoded in bits[7-0] of the > machine type identifier. > > e.g, to configure a guest to use 48bit physical address size:: > > vm_fd = ioctl(dev_fd, KVM_CREATE_VM, KVM_VM_TYPE_ARM_IPA_SIZE(48)); > > The requested size (IPA_Bits) must be: > > == ========================================================= > 0 Implies default size, 40bits (for backward compatibility) > N Implies N bits, where N is a positive integer such that, > 32 <= N <= Host_IPA_Limit > == ========================================================= > Host_IPA_Limit is the maximum possible value for IPA_Bits on the host > and is dependent on the CPU capability and the kernel configuration. > The limit can be retrieved using KVM_CAP_ARM_VM_IPA_SIZE of the > KVM_CHECK_EXTENSION ioctl() at run-time. > > Creation of the VM will fail if the requested IPA size (whether it is > implicit or explicit) is unsupported on the host. https://docs.kernel.org/virt/kvm/api.html#kvm-create-vm So if Host_IPA_Limit < 40, specifying 0 as the type will fail. This actually confused libvirt, which uses "none" machine model to probe the KVM availability, on M2 MacBook Air. Fix this by using Host_IPA_Limit as the default type when KVM_CAP_ARM_VM_IPA_SIZE is available. Cc: qemu-stable@nongnu.org Signed-off-by: Akihiko Odaki Message-id: 20230727073134.134102-3-akihiko.odaki@daynix.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/kvm.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 40f577bfd55..23aeb099490 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -249,7 +249,9 @@ int kvm_arm_get_max_vm_ipa_size(MachineState *ms, bool *fixed_ipa) int kvm_arch_get_default_type(MachineState *ms) { - return 0; + bool fixed_ipa; + int size = kvm_arm_get_max_vm_ipa_size(ms, &fixed_ipa); + return fixed_ipa ? 0 : size; } int kvm_arch_init(MachineState *ms, KVMState *s) From patchwork Thu Aug 24 09:28:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 716511 Delivered-To: patch@linaro.org Received: by 2002:adf:f747:0:b0:317:ecd7:513f with SMTP id z7csp1235978wrp; Thu, 24 Aug 2023 02:29:49 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHz4xtrpkUhuQig0K51TirKxEhoYDX5UTieVVpE3N5ynSHrnebNwSA8yQo5kb41LOgLVX7N X-Received: by 2002:ac8:5dd0:0:b0:411:616a:4bde with SMTP id e16-20020ac85dd0000000b00411616a4bdemr4555983qtx.18.1692869389248; Thu, 24 Aug 2023 02:29:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1692869389; cv=none; d=google.com; s=arc-20160816; b=cs7H+RPwbpHz66Jg3jzhOw8BaEWGBXpbAFeJdzTpjPkzJ4DQxaf/bXMJCiEh06Kv7E 01aFH2j9gKuCiB0wDWH3qo3Z3mUkSnRHPS2Z1cs1SPM3o9OfT8km5EVvnkFomtFa0krn LNedPp9vjV9EaCLVEILopccjpFyyC1AEFW/G7uJqXf5vS0IYHFi1NW0jzQz7pFB9ohbT 7e+IF/enb3d0Ou2nMk/6cMr2o/xyx2X8ITnjb/0TJTVP4HXt+c3TEPCGc5HKfEGq5X9E 51vF0DqLgcgaZxubV/GiTEZSnvcpFGlD/BbJ9TCTQSACriEukuGKX2u/hd+yX3+9z4Cu Ijvg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=sqblpYqc+Ubm/oCI2PE0OOl/KVdBbV9qWryrUIWZBpI=; fh=bFDrUYhlTVi/QyetgXx/byg2+yO/22Hp9SjwoefyKLk=; b=1JyKzWglxSbL8R5SgE7h2qjkruDrgtno6k2+LDq+23SLzqx2hENFAwZGuLzSHx7VMS F+hCSL8XnQt31Q9mXLQwPR5TnwFaLYtGO73FC9dWTVIGz22HzWSIbyaAL2ACqyoOgHHv yVwDwwnPtKxiY0CaY+yaLGxL5N80Q4ff7jDpW6Cu+AAUtOhmBJJyDP6mBXa5S/pqKbC/ /YJzdGFZ5vhSS7bpmFYcHN/6Pen7vDz7Bd3VZDh6Uz33rbYjREW8oWvX80ee55jacKiK ZqA6HpAzgYaYiN6htqIUxcAPMOUAp9PGCWgDnsSGBsOdsW2+6PiRYUZSo7dRGeZm14Xk 1fsA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZXP43udI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id s12-20020adfeccc000000b00317b5c8a4f1sm21844004wro.60.2023.08.24.02.28.41 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Aug 2023 02:28:41 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/35] mips: Report an error when KVM_VM_MIPS_VZ is unavailable Date: Thu, 24 Aug 2023 10:28:10 +0100 Message-Id: <20230824092836.2239644-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230824092836.2239644-1-peter.maydell@linaro.org> References: <20230824092836.2239644-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Akihiko Odaki On MIPS, QEMU requires KVM_VM_MIPS_VZ type for KVM. Report an error in such a case as other architectures do when an error occurred during KVM type decision. Signed-off-by: Akihiko Odaki Message-id: 20230727073134.134102-4-akihiko.odaki@daynix.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé --- target/mips/kvm.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/mips/kvm.c b/target/mips/kvm.c index e98aad01bd5..e22e24ed974 100644 --- a/target/mips/kvm.c +++ b/target/mips/kvm.c @@ -1278,6 +1278,7 @@ int kvm_arch_get_default_type(MachineState *machine) } #endif + error_report("KVM_VM_MIPS_VZ type is not available"); return -1; } From patchwork Thu Aug 24 09:28:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 716524 Delivered-To: patch@linaro.org Received: by 2002:adf:f747:0:b0:317:ecd7:513f with SMTP id z7csp1236324wrp; Thu, 24 Aug 2023 02:30:45 -0700 (PDT) X-Google-Smtp-Source: AGHT+IF20TEHf5ekPRoMGnnVf1C6YzABzmXLjrGHv2l7wXneFwpFNAr2hWXG006/Gs5W15lxfT5S X-Received: by 2002:a05:620a:4103:b0:76d:af8d:a1cc with SMTP id j3-20020a05620a410300b0076daf8da1ccmr11376698qko.65.1692869445549; Thu, 24 Aug 2023 02:30:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1692869445; cv=none; d=google.com; s=arc-20160816; b=ASIa3ewuttv/IbKi1d1GHqaki6TdgxX13sEDMI73jVH/EzdoDtQL8weiB/A04Tnp3h ySc6Gt5PXl3Y2k70aKcYAE9FQG3jQM0oEShMsOrjC2jlCs3PUfjZK4snY74tO0BYITpj lHqQWCbi5+C/feTbbG1s6h7LNhNV76qW+BZ+mFicINX8CF5bBLkYRpXWSkdi3s8BlMIC gIyJxzaypNbdoXc/yBfp0eS3aqCCbcc8hpcqN/8pYlw3533hmJXtnRhO3X2r8nI7KbPt fmlyj+n1lbxMI4soSkFSTDF00NQ8k3E5cUGw7yW0tjvpo2Uw5J46Y6Gymvu3D7LEQMPL lzbg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Fvo37lHKSY4gbS092X7jXMhMWoKtNHO/9H2RjswZUW4=; fh=bFDrUYhlTVi/QyetgXx/byg2+yO/22Hp9SjwoefyKLk=; b=a2uNWJJ41s2hjB18CHY+9goEn5f/nQ7lO1yASUxm8aYmMbryVoLDKciHqPm4xRqnUN o51P4QQQUjxfLtRq+0x1qb6ou+bH+T2/O9hILYOFma5IwmiOGsJvrOQGzHsAGg6RaTq2 Ui1iR1W33OzyG4aYqerxP3G/gf2fQ8ewP7gscLqnuVWuLLooC7/lJFIPGJKz6hnH6ktc VeJhRtfFuboqsleRxyXLObDg+d68T0m3vENn1GlLEkJvDBV1uydl4YONKLinaLzVbCtl EHyYnItSLazWg4LjNwu6hlgoXyBBhZRNFQ9F0r5fSascdWxsdifAOaMwPRdcQbuWW23g gYug== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=V7P8LD+W; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id s12-20020adfeccc000000b00317b5c8a4f1sm21844004wro.60.2023.08.24.02.28.42 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Aug 2023 02:28:42 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/35] accel/kvm: Use negative KVM type for error propagation Date: Thu, 24 Aug 2023 10:28:11 +0100 Message-Id: <20230824092836.2239644-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230824092836.2239644-1-peter.maydell@linaro.org> References: <20230824092836.2239644-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Akihiko Odaki On MIPS, kvm_arch_get_default_type() returns a negative value when an error occurred so handle the case. Also, let other machines return negative values when errors occur and declare returning a negative value as the correct way to propagate an error that happened when determining KVM type. Signed-off-by: Akihiko Odaki Message-id: 20230727073134.134102-5-akihiko.odaki@daynix.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé --- accel/kvm/kvm-all.c | 5 +++++ hw/arm/virt.c | 2 +- hw/ppc/spapr.c | 2 +- 3 files changed, 7 insertions(+), 2 deletions(-) diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c index b4723016379..3bac5aa678b 100644 --- a/accel/kvm/kvm-all.c +++ b/accel/kvm/kvm-all.c @@ -2527,6 +2527,11 @@ static int kvm_init(MachineState *ms) type = kvm_arch_get_default_type(ms); } + if (type < 0) { + ret = -EINVAL; + goto err; + } + do { ret = kvm_ioctl(s, KVM_CREATE_VM, type); } while (ret == -EINTR); diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 7d9dbc26633..83c05f1b9f6 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -2913,7 +2913,7 @@ static int virt_kvm_type(MachineState *ms, const char *type_str) "require an IPA range (%d bits) larger than " "the one supported by the host (%d bits)", requested_pa_size, max_vm_pa_size); - exit(1); + return -1; } /* * We return the requested PA log size, unless KVM only supports diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 1c8b8d57a70..e851f609198 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -3105,7 +3105,7 @@ static int spapr_kvm_type(MachineState *machine, const char *vm_type) } error_report("Unknown kvm-type specified '%s'", vm_type); - exit(1); + return -1; } /* From patchwork Thu Aug 24 09:28:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 716533 Delivered-To: patch@linaro.org Received: by 2002:adf:f747:0:b0:317:ecd7:513f with SMTP id z7csp1237434wrp; Thu, 24 Aug 2023 02:33:55 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHYQFIuMBbFHvb4f/7Sy70F9kkOQQ9OZdd3IM2PQZjINOPqeuDfSkner7znRNXmmrAi+x/n X-Received: by 2002:a05:622a:1c5:b0:403:b088:5d3 with SMTP id t5-20020a05622a01c500b00403b08805d3mr19680896qtw.17.1692869634788; Thu, 24 Aug 2023 02:33:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1692869634; cv=none; d=google.com; s=arc-20160816; b=eUSBcMBurS8TlSC6bONL43L2Jdm92CZqOmns6+8KVUaog+vMY7f2ZwMhVS1tXlZgCL +8D9CU6d2dvOhKM4gOgjzDGdONHPGvSPj6Rm6H/U0il+cHeaFAB3MGm3pdYlgE1f2hb9 lSR0LsXse5j8cXgyQOtOQl/Xq1RNaTdegDw/cd8aopPz4lTDEFEttfSxzG9i5AfnbEHY DsHX/AE0FdRzsqTW6iuI0vSaUJ3y14TfyMcn/GAA56VUL7iQ+VClNveanEwrLO9zK3m6 nXnIlfwYoT3Yg/dt/Lkm9fb4JdIPOekKskTRjK7czgGDEG3r8DHzx76FGsKIKuCZN1XF lPTQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=rDBvn+8aP4FuM7R/tw2wMoRa69yeF0kW2DF1HQRjT0U=; fh=bFDrUYhlTVi/QyetgXx/byg2+yO/22Hp9SjwoefyKLk=; b=RtcSCwkNHoMyeK2vLFXMakIk1o1yrc/qGmmvOuGd5QvlegpFF5XezM7vnmGuIIhx1h JConPJ4mk8gxaJQSuTOlExZmcKCP8U7dG9hVDKYzo1QyX06EBsqSCqPZW1ClY9iRGKHE iSKw5dFkbaJ0ETHFF8bKhFrkNTgCZwF4gTK3TukXQH8F95SE3QAP64whwQUIq6dfs67m An5o8Nb4YsyObXw3dnf9Y7cVbVudu/Gz+/4OLK8wKIWhZ3H8ozXo2XyoTp7pgs+d4X/7 PRw8Ps8fDoD4Qqflxc1b7HBqHQxp8B2b3Cod4J++m3+Yxuq/z7k3fofHeQ9AbC5BOmvD wlzw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Uk3yZPrn; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id s12-20020adfeccc000000b00317b5c8a4f1sm21844004wro.60.2023.08.24.02.28.42 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Aug 2023 02:28:42 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/35] accel/kvm: Free as when an error occurred Date: Thu, 24 Aug 2023 10:28:12 +0100 Message-Id: <20230824092836.2239644-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230824092836.2239644-1-peter.maydell@linaro.org> References: <20230824092836.2239644-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::12f; envelope-from=peter.maydell@linaro.org; helo=mail-lf1-x12f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Akihiko Odaki An error may occur after s->as is allocated, for example if the KVM_CREATE_VM ioctl call fails. Signed-off-by: Akihiko Odaki Message-id: 20230727073134.134102-6-akihiko.odaki@daynix.com Reviewed-by: Peter Maydell [PMM: tweaked commit message] Signed-off-by: Peter Maydell --- accel/kvm/kvm-all.c | 1 + 1 file changed, 1 insertion(+) diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c index 3bac5aa678b..ed30f4135b5 100644 --- a/accel/kvm/kvm-all.c +++ b/accel/kvm/kvm-all.c @@ -2765,6 +2765,7 @@ err: if (s->fd != -1) { close(s->fd); } + g_free(s->as); g_free(s->memory_listener.slots); return ret; From patchwork Thu Aug 24 09:28:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 716519 Delivered-To: patch@linaro.org Received: by 2002:adf:f747:0:b0:317:ecd7:513f with SMTP id z7csp1236242wrp; Thu, 24 Aug 2023 02:30:31 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEEKwZRjI7i6nmOSXCKhEv1Sfcr4fUdrLY40NLoi70PXK/ySPzpDW4Xih24h+fQVP/mtuWU X-Received: by 2002:a05:622a:191:b0:410:443:221a with SMTP id s17-20020a05622a019100b004100443221amr19421611qtw.1.1692869431716; Thu, 24 Aug 2023 02:30:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1692869431; cv=none; d=google.com; s=arc-20160816; b=VUdL8+uvybUOrxkWdZdOrye5HHguHJOFB4hLptvtNeluVsReU99dlBHOWSY7Xu57jO EW+qitpKf1g7njlY25WnxbODmONG5d3wAOSfHmMPvu5Z2/F2999ReZ5JCAECBPuZmRrV Xf6MBH+gii42hkDPMSUAM4jl2r21Shp/PsHNWGio/lqW0yQfKsnGHlczyOWyrxz1G5np Sh8u4Fp9NGYYJPFGz1Gz8BNTq3IRHaMUaVR0Bk9XLZhs17cefv4L7v2qP3exzPDtLotW /stPRNdKZxe85pRWdVIAK7sLb4vzX/KjbJiuSleDu3scll3q28lEa63QL51CixH6SCB4 061A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=L6YrIHhc5tInaHtSG+IOeZ7cliNEkq/9K95ncf5G8bg=; fh=bFDrUYhlTVi/QyetgXx/byg2+yO/22Hp9SjwoefyKLk=; b=QXes1eSNqvEIXmi+GvQDyk2G/1SvpmEwysk8zzMlnjp5awjz6TcsqLhMAypnf9RNrL eZcwRRDmpeBe8KjhA5AyoKq+5wfidLl4WNNznB1k10+6askItevfqg5pOUKIk4toMxUf ikqHNt+bV93LI/USJPaSO3Os1hz7mSnEicOlmK+1dqOXbCx0FeHp92C+ivc9u3tpK/KO zWzJGZk5Q/HdBZeBpYqNf9qAGrqNEHbs0F1MCwrBYoCVTrCljmV7dvaYyPG86FVWeL4H bSm2ogcTdSWeHpWZAaWPpjCazs2v7FJpBadZotvKJH1TGKMHPhLaZSDQ5tSJHvEb9fEu prMw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Lk/K0HDf"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id s12-20020adfeccc000000b00317b5c8a4f1sm21844004wro.60.2023.08.24.02.28.43 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Aug 2023 02:28:43 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/35] accel/kvm: Make kvm_dirty_ring_reaper_init() void Date: Thu, 24 Aug 2023 10:28:13 +0100 Message-Id: <20230824092836.2239644-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230824092836.2239644-1-peter.maydell@linaro.org> References: <20230824092836.2239644-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Akihiko Odaki The returned value was always zero and had no meaning. Signed-off-by: Akihiko Odaki Message-id: 20230727073134.134102-7-akihiko.odaki@daynix.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé --- accel/kvm/kvm-all.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c index ed30f4135b5..d07f1ecbd38 100644 --- a/accel/kvm/kvm-all.c +++ b/accel/kvm/kvm-all.c @@ -1454,15 +1454,13 @@ static void *kvm_dirty_ring_reaper_thread(void *data) return NULL; } -static int kvm_dirty_ring_reaper_init(KVMState *s) +static void kvm_dirty_ring_reaper_init(KVMState *s) { struct KVMDirtyRingReaper *r = &s->reaper; qemu_thread_create(&r->reaper_thr, "kvm-reaper", kvm_dirty_ring_reaper_thread, s, QEMU_THREAD_JOINABLE); - - return 0; } static int kvm_dirty_ring_init(KVMState *s) @@ -2744,10 +2742,7 @@ static int kvm_init(MachineState *ms) } if (s->kvm_dirty_ring_size) { - ret = kvm_dirty_ring_reaper_init(s); - if (ret) { - goto err; - } + kvm_dirty_ring_reaper_init(s); } if (kvm_check_extension(kvm_state, KVM_CAP_BINARY_STATS_FD)) { From patchwork Thu Aug 24 09:28:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 716536 Delivered-To: patch@linaro.org Received: by 2002:adf:f747:0:b0:317:ecd7:513f with SMTP id z7csp1237568wrp; Thu, 24 Aug 2023 02:34:15 -0700 (PDT) X-Google-Smtp-Source: AGHT+IE+9g4EOUyPcZiQU97GwRHkP0OjHulpLZroUS5m5SADEJIB85o//53xCVY1Ylh6D2sKYkxo X-Received: by 2002:a05:620a:440e:b0:76c:b7f0:2b94 with SMTP id v14-20020a05620a440e00b0076cb7f02b94mr19441391qkp.7.1692869655673; Thu, 24 Aug 2023 02:34:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1692869655; cv=none; d=google.com; s=arc-20160816; b=FnaqwVeXN428M/i92J5Ir7qysMHORKO5SF9q1GBor6ald1FBhPr5BppvYA8TskkzJc 3+MCc5Ccc7MtupqUSaGfutX9GZ7jdFZSQKn8RWo+kz6Pfv94ZrIRiFUfDGc0sdFhLuif MShNlmVIrSCoRo8+mhW9ete8lBB3wbOT0kLwVQ9St40Wf2lRaJUoDsQcD08znXj0vRCP V/oml8Js3SyZcbS7AEeuWWKcV35mzL5ScVbMZQdLGjQxBec657Pg41+gRueuoP6oeIBX CVOjSNMn6ZW4zH2vbwA3V0QUd9gqoZo8F18dvA4QfJtHwvSnCXMR0kYFxkC/UJGUeG5B 9uSQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=cvOJMWgOIR1DH7YY1zi4TyROxQHSO4tBJ9shorpuc1Y=; fh=bFDrUYhlTVi/QyetgXx/byg2+yO/22Hp9SjwoefyKLk=; b=s7A2bciJlD5+lLEkk8wfFIacFOIkHkWN6h3376qTpDTz8WtASoVZBcUH2Afr9dHxVb xPJNcJ0f4dGYhEkNbh0qD/0AZdZtUPD98hpZ3XUGObTsnkjQE8iHmyRCDKASitpFpKyZ m2w9qj9AyKADcg9cLfUfCC3vMyb4LwZPsWlVMuqr8SpeZ/7a+f4xcIgXHM8t0wvuQJHq slMJC6lFt1cD5rbonqaJmyoYErm/NpQcp52CqZp+EEM6q0AAdoHxdKwliEtNDQbqoKv4 23IfeulOx/wwyyz2rSeNbACwbt2PXhtqp9cA0P0nffNrX6v+KUtLDEGMMimbHEh0ujAE 9iIg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=AJxoyxFy; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id s12-20020adfeccc000000b00317b5c8a4f1sm21844004wro.60.2023.08.24.02.28.43 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Aug 2023 02:28:43 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/35] target/arm/ptw: Don't set fi->s1ptw for UnsuppAtomicUpdate fault Date: Thu, 24 Aug 2023 10:28:14 +0100 Message-Id: <20230824092836.2239644-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230824092836.2239644-1-peter.maydell@linaro.org> References: <20230824092836.2239644-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::133; envelope-from=peter.maydell@linaro.org; helo=mail-lf1-x133.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org For an Unsupported Atomic Update fault where the stage 1 translation table descriptor update can't be done because it's to an unsupported memory type, this is a stage 1 abort (per the Arm ARM R_VSXXT). This means we should not set fi->s1ptw, because this will cause the code in the get_phys_addr_lpae() error-exit path to mark it as stage 2. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230807141514.19075-2-peter.maydell@linaro.org --- target/arm/ptw.c | 1 - 1 file changed, 1 deletion(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 8f94100c61f..bafeb876ad7 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -701,7 +701,6 @@ static uint64_t arm_casq_ptw(CPUARMState *env, uint64_t old_val, if (unlikely(!host)) { fi->type = ARMFault_UnsuppAtomicUpdate; - fi->s1ptw = true; return 0; } From patchwork Thu Aug 24 09:28:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 716523 Delivered-To: patch@linaro.org Received: by 2002:adf:f747:0:b0:317:ecd7:513f with SMTP id z7csp1236306wrp; Thu, 24 Aug 2023 02:30:43 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHtzru4l5n4oEQrwVxN9G/mp92mUsmVXmx3dNNv0C8IM3iJ/489z47tEXOqndjTO6XtJnjx X-Received: by 2002:a05:620a:1727:b0:76d:b33b:59cd with SMTP id az39-20020a05620a172700b0076db33b59cdmr8057526qkb.20.1692869442981; Thu, 24 Aug 2023 02:30:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1692869442; cv=none; d=google.com; s=arc-20160816; b=g9Skmd2nt9M1ZE5e4w4GOXvtoq+jhVl5zJeiiu8xJenKTKAohGLt6gdrjNs1TKqpvJ usPlEvw93Ox9Ze1lu2kFjbyP4UqPfef9Ja4Z32bWGBLpnv/PcnNVGYMq1OlrR5cIy7sn 1Fgx2UxJrKpBD5cc0sDlqS0l2mnKQWf48W1WwNPABitmWyTVW2ffiVSAxVYoKMc8A0Ly tp6SSiIFu4hLuq61gXiYuca5klSADt1i1e7EjN6ObWLdLh3ymYaMJUdGHPeXYZzbuWET bHHH42BVtFashgFbmU6PEk1r7eG7BspEPFD8FkokHBl8dOt6vg0teNQX3LB5qPRGbEtr G2sw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=UGCC5w0EUtVabhmBA26zktdGI7YbZzgKTjnOnP1lMsI=; fh=bFDrUYhlTVi/QyetgXx/byg2+yO/22Hp9SjwoefyKLk=; b=Dmj8R4jVKmgMhDMOlTvKu7lDUrtOH0rQPRSHjLX7b1OijTpuj/jDYYxORHaPKdIfI0 ihXd4dNvF17tappqw6OYAbTsDutYuWEfkIWJ0Ekd91N3zcLQ2E8mXYhPfligRDECnccz i++jsfes9WEhfS4Wf9Wk+NmkrnxtulAo3KRUNUF0j5Q3knXG7x5LAFmPMfdnQRmsql9t 0OZZpgIqFcR+6fd04BTSb7Jn+CogfPl6Wrsd/a+faqsXkxHDaxQnCyHV9FKUSTjDVDoE BZFJ+WntjxdMqRbs0ZSGJsnL1mxRd8tsGqHNwL9NiJ1TVIww+zLDT99I2RqMkXESc8Li CAsg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=AuKwooqU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id s12-20020adfeccc000000b00317b5c8a4f1sm21844004wro.60.2023.08.24.02.28.44 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Aug 2023 02:28:44 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/35] target/arm/ptw: Don't report GPC faults on stage 1 ptw as stage2 faults Date: Thu, 24 Aug 2023 10:28:15 +0100 Message-Id: <20230824092836.2239644-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230824092836.2239644-1-peter.maydell@linaro.org> References: <20230824092836.2239644-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In S1_ptw_translate() we set up the ARMMMUFaultInfo if the attempt to translate the page descriptor address into a physical address fails. This used to only be possible if we are doing a stage 2 ptw for that descriptor address, and so the code always sets fi->stage2 and fi->s1ptw to true. However, with FEAT_RME it is also possible for the lookup of the page descriptor address to fail because of a Granule Protection Check fault. These should not be reported as stage 2, otherwise arm_deliver_fault() will incorrectly set HPFAR_EL2. Similarly the s1ptw bit should only be set for stage 2 faults on stage 1 translation table walks, i.e. not for GPC faults. Add a comment to the the other place where we might detect a stage2-fault-on-stage-1-ptw, in arm_casq_ptw(), noting why we know in that case that it must really be a stage 2 fault and not a GPC fault. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230807141514.19075-3-peter.maydell@linaro.org --- target/arm/ptw.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index bafeb876ad7..eb57ebd897b 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -600,8 +600,8 @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, fi->type = ARMFault_GPCFOnWalk; } fi->s2addr = addr; - fi->stage2 = true; - fi->s1ptw = true; + fi->stage2 = regime_is_stage2(s2_mmu_idx); + fi->s1ptw = fi->stage2; fi->s1ns = !is_secure; return false; } @@ -719,6 +719,12 @@ static uint64_t arm_casq_ptw(CPUARMState *env, uint64_t old_val, env->tlb_fi = NULL; if (unlikely(flags & TLB_INVALID_MASK)) { + /* + * We know this must be a stage 2 fault because the granule + * protection table does not separately track read and write + * permission, so all GPC faults are caught in S1_ptw_translate(): + * we only get here for "readable but not writeable". + */ assert(fi->type != ARMFault_None); fi->s2addr = ptw->out_virt; fi->stage2 = true; From patchwork Thu Aug 24 09:28:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 716507 Delivered-To: patch@linaro.org Received: by 2002:adf:f747:0:b0:317:ecd7:513f with SMTP id z7csp1235950wrp; Thu, 24 Aug 2023 02:29:45 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEkhxFhdjuXozCq9AmLqt36Ox4YVtsgdNUlix++AxA65K2TWaAXuOFrked90NQmyWiInAgv X-Received: by 2002:a0c:b301:0:b0:647:303f:c6f3 with SMTP id s1-20020a0cb301000000b00647303fc6f3mr14407926qve.8.1692869385013; Thu, 24 Aug 2023 02:29:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1692869385; cv=none; d=google.com; s=arc-20160816; b=AOyGqUStQdbH35Y7qkHGXS38XUr9QdUzZjOHhNHRzkxqEOoIVUDfO6UMGUsOdg0c6y bA5Wq21thLL4jqqjVlu7aOtBgdYLm4dMrTh6acZuTUS92dv38TxpAcfHJbrM/cwOytr1 CduT+04aK28wOX94TNaDPL8EfyRKLUF3TEi6NLNKJf5TyeiGnescPa17EVQdrmRLc7JD 657iqhPD8Pc4ubeDxkIp3mCfnvB+htqa+YRM8sIbEMeGWtvYVeiSwtTbRN2OTnN0ycbE Gbi5r27FJX+WeNwdjVvlzAIivArMZ5K1tz4AO4Cng7ndVPQE78iPaPrpFm11aeJtDhAv 9t2Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=cKwApaEBM2Ue+okvX0YIaC5zH+tiObfh8zC3y9f1bVw=; fh=bFDrUYhlTVi/QyetgXx/byg2+yO/22Hp9SjwoefyKLk=; b=lrsqaSArweQ6N/2gNkPVbFXKS1Ceg36tQTJqouDW07Euxyh7+kZSQGwkzyUWYyvtHk htTgXCVPZ4lhinkXcABxAwwTiyKL8fsfgOcmHb2IBicyWg1++P39cRdOw6GjnivscYhS VOe21eQ3vYDpxe8UpQsaGAUJdYlwjNP4HgwWlMyVnvITOwIM3C4xBp9efVjRXusmrMXt pXEPDr8HNMGoFs+frLbA/qRiB7CCkaULnb66iMlN/KAxWbSGj9qJ2C2gzraLdzBLo2Ce 1mcnvES1TQRaUYI/iOeHiT1omQo97jSKbsmahTj4L7PHE9SCGaP3R2st44D8h/woC9KN 7qLg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZXeOvBzj; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id s12-20020adfeccc000000b00317b5c8a4f1sm21844004wro.60.2023.08.24.02.28.45 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Aug 2023 02:28:45 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 15/35] target/arm/ptw: Set s1ns bit in fault info more consistently Date: Thu, 24 Aug 2023 10:28:16 +0100 Message-Id: <20230824092836.2239644-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230824092836.2239644-1-peter.maydell@linaro.org> References: <20230824092836.2239644-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The s1ns bit in ARMMMUFaultInfo is documented as "true if we faulted on a non-secure IPA while in secure state". Both the places which look at this bit only do so after having confirmed that this is a stage 2 fault and we're dealing with Secure EL2, which leaves the ptw.c code free to set the bit to any random value in the other cases. Instead of taking advantage of that freedom, consistently make the bit be set to false for the "not a stage 2 fault for Secure EL2" cases. This removes some cases where we were using an 'is_secure' boolean and leaving the reader guessing about whether that was the right thing for Realm and Root cases. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230807141514.19075-4-peter.maydell@linaro.org --- target/arm/ptw.c | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index eb57ebd897b..67078ae3509 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -514,6 +514,17 @@ static ARMSecuritySpace S2_security_space(ARMSecuritySpace s1_space, } } +static bool fault_s1ns(ARMSecuritySpace space, ARMMMUIdx s2_mmu_idx) +{ + /* + * For stage 2 faults in Secure EL22, S1NS indicates + * whether the faulting IPA is in the Secure or NonSecure + * IPA space. For all other kinds of fault, it is false. + */ + return space == ARMSS_Secure && regime_is_stage2(s2_mmu_idx) + && s2_mmu_idx == ARMMMUIdx_Stage2_S; +} + /* Translate a S1 pagetable walk through S2 if needed. */ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, hwaddr addr, ARMMMUFaultInfo *fi) @@ -586,7 +597,7 @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, fi->s2addr = addr; fi->stage2 = true; fi->s1ptw = true; - fi->s1ns = !is_secure; + fi->s1ns = fault_s1ns(ptw->in_space, s2_mmu_idx); return false; } } @@ -602,7 +613,7 @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, fi->s2addr = addr; fi->stage2 = regime_is_stage2(s2_mmu_idx); fi->s1ptw = fi->stage2; - fi->s1ns = !is_secure; + fi->s1ns = fault_s1ns(ptw->in_space, s2_mmu_idx); return false; } @@ -729,7 +740,7 @@ static uint64_t arm_casq_ptw(CPUARMState *env, uint64_t old_val, fi->s2addr = ptw->out_virt; fi->stage2 = true; fi->s1ptw = true; - fi->s1ns = !ptw->in_secure; + fi->s1ns = fault_s1ns(ptw->in_space, ptw->in_ptw_idx); return 0; } @@ -2030,7 +2041,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, fi->level = level; /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */ fi->stage2 = fi->s1ptw || regime_is_stage2(mmu_idx); - fi->s1ns = mmu_idx == ARMMMUIdx_Stage2; + fi->s1ns = fault_s1ns(ptw->in_space, mmu_idx); return true; } From patchwork Thu Aug 24 09:28:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 716521 Delivered-To: patch@linaro.org Received: by 2002:adf:f747:0:b0:317:ecd7:513f with SMTP id z7csp1236278wrp; Thu, 24 Aug 2023 02:30:38 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEj5EEZgng2fS1M/1lLwyiX7XAyjHVYNQM7pYLh9OwDrhJ8ROY/MvCeViOFsniweo0LahQi X-Received: by 2002:a05:620a:440e:b0:76c:b7f0:2b94 with SMTP id v14-20020a05620a440e00b0076cb7f02b94mr19433027qkp.7.1692869438517; Thu, 24 Aug 2023 02:30:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1692869438; cv=none; d=google.com; s=arc-20160816; b=r8qUOx7/MI0EGtqHIrv+8CE5mqVVuNPVO0+2dc3y4gLCs+m9PMJiPW9DqiI/Cs0qUd Qafq+rCg7t2froMJCAqco8tI45uAuYax2JqD9NBv+ogUmrxRkQL4Ntw9cq13gUejfOZR ozxHfnPczTCPFI6zp680pL7U8A9F2Mv3q6jx3AaoiZGvGWExm6JZNQRnMnBlSsI7oTf/ Tph4UaMk8mxEC1nuQlDj8oE3pWdXh9OwIndapJ5CaeCqMSp2hU5NfP76126wJAoLEjrv 4cIuK9diasbPbeQCNui++nCI9sVlPpnXk1GVSxcYweqOUMBkBfxf8qM/P7NKLSO1/fWj DMxQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=wK9zE1Lifmm6/8IKHW10U8rTZ3FDJYtigwQOzAGgaWs=; fh=bFDrUYhlTVi/QyetgXx/byg2+yO/22Hp9SjwoefyKLk=; b=nZt2/p5XOHgVPINp6Sv1fYAeJqWF4Hqdztr0UX+EyFNsIs6lndvb8chTBmYQSVQ43Q 0gHIYgpdhb3m2uaxi0iEhsBRmko02EL6S9a141MAhzexY1WeGzzcfOx8iA+z28+0y3nV X0xQYqRhJb/dwQMt2dlYserp0sxzJGVwU6YyUX8w4tdIrbyy+JeIArL5hYYsdlC6AK6L gzZniBWCm7AUzcm9XCQU2u2yefVp6Jrd87y/J79epN+JTjsoOU7XJk4KG+ESIPePLxy/ MttNHP508SDMfP/rkzx6AlO7IvWHI82feUGwsEblMIdectv+fUR9ZnStnK9rz5J7yIx/ WM5w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WFqUOLsN; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id s12-20020adfeccc000000b00317b5c8a4f1sm21844004wro.60.2023.08.24.02.28.45 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Aug 2023 02:28:45 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 16/35] target/arm/ptw: Pass ptw into get_phys_addr_pmsa*() and get_phys_addr_disabled() Date: Thu, 24 Aug 2023 10:28:17 +0100 Message-Id: <20230824092836.2239644-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230824092836.2239644-1-peter.maydell@linaro.org> References: <20230824092836.2239644-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In commit 6d2654ffacea813916176 we created the S1Translate struct and used it to plumb through various arguments that we were previously passing one-at-a-time to get_phys_addr_v5(), get_phys_addr_v6(), and get_phys_addr_lpae(). Extend that pattern to get_phys_addr_pmsav5(), get_phys_addr_pmsav7(), get_phys_addr_pmsav8() and get_phys_addr_disabled(), so that all the get_phys_addr_* functions we call from get_phys_addr_nogpc() take the S1Translate struct rather than the mmu_idx and is_secure bool. (This refactoring is a prelude to having the called functions look at ptw->is_space rather than using an is_secure boolean.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230807141514.19075-5-peter.maydell@linaro.org --- target/arm/ptw.c | 57 ++++++++++++++++++++++++++++++------------------ 1 file changed, 36 insertions(+), 21 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 67078ae3509..a873fbe0239 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2045,15 +2045,19 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, return true; } -static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, - bool is_secure, GetPhysAddrResult *result, +static bool get_phys_addr_pmsav5(CPUARMState *env, + S1Translate *ptw, + uint32_t address, + MMUAccessType access_type, + GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { int n; uint32_t mask; uint32_t base; + ARMMMUIdx mmu_idx = ptw->in_mmu_idx; bool is_user = regime_is_user(env, mmu_idx); + bool is_secure = arm_space_is_secure(ptw->in_space); if (regime_translation_disabled(env, mmu_idx, is_secure)) { /* MPU disabled. */ @@ -2210,14 +2214,18 @@ static bool pmsav7_use_background_region(ARMCPU *cpu, ARMMMUIdx mmu_idx, return regime_sctlr(env, mmu_idx) & SCTLR_BR; } -static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, - bool secure, GetPhysAddrResult *result, +static bool get_phys_addr_pmsav7(CPUARMState *env, + S1Translate *ptw, + uint32_t address, + MMUAccessType access_type, + GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { ARMCPU *cpu = env_archcpu(env); int n; + ARMMMUIdx mmu_idx = ptw->in_mmu_idx; bool is_user = regime_is_user(env, mmu_idx); + bool secure = arm_space_is_secure(ptw->in_space); result->f.phys_addr = address; result->f.lg_page_size = TARGET_PAGE_BITS; @@ -2736,12 +2744,16 @@ void v8m_security_lookup(CPUARMState *env, uint32_t address, } } -static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, - bool secure, GetPhysAddrResult *result, +static bool get_phys_addr_pmsav8(CPUARMState *env, + S1Translate *ptw, + uint32_t address, + MMUAccessType access_type, + GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { V8M_SAttributes sattrs = {}; + ARMMMUIdx mmu_idx = ptw->in_mmu_idx; + bool secure = arm_space_is_secure(ptw->in_space); bool ret; if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { @@ -3045,12 +3057,15 @@ static ARMCacheAttrs combine_cacheattrs(uint64_t hcr, * MMU disabled. S1 addresses within aa64 translation regimes are * still checked for bounds -- see AArch64.S1DisabledOutput(). */ -static bool get_phys_addr_disabled(CPUARMState *env, target_ulong address, +static bool get_phys_addr_disabled(CPUARMState *env, + S1Translate *ptw, + target_ulong address, MMUAccessType access_type, - ARMMMUIdx mmu_idx, bool is_secure, GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { + ARMMMUIdx mmu_idx = ptw->in_mmu_idx; + bool is_secure = arm_space_is_secure(ptw->in_space); uint8_t memattr = 0x00; /* Device nGnRnE */ uint8_t shareability = 0; /* non-shareable */ int r_el; @@ -3252,8 +3267,8 @@ static bool get_phys_addr_nogpc(CPUARMState *env, S1Translate *ptw, case ARMMMUIdx_Phys_Root: case ARMMMUIdx_Phys_Realm: /* Checking Phys early avoids special casing later vs regime_el. */ - return get_phys_addr_disabled(env, address, access_type, mmu_idx, - is_secure, result, fi); + return get_phys_addr_disabled(env, ptw, address, access_type, + result, fi); case ARMMMUIdx_Stage1_E0: case ARMMMUIdx_Stage1_E1: @@ -3321,16 +3336,16 @@ static bool get_phys_addr_nogpc(CPUARMState *env, S1Translate *ptw, if (arm_feature(env, ARM_FEATURE_V8)) { /* PMSAv8 */ - ret = get_phys_addr_pmsav8(env, address, access_type, mmu_idx, - is_secure, result, fi); + ret = get_phys_addr_pmsav8(env, ptw, address, access_type, + result, fi); } else if (arm_feature(env, ARM_FEATURE_V7)) { /* PMSAv7 */ - ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx, - is_secure, result, fi); + ret = get_phys_addr_pmsav7(env, ptw, address, access_type, + result, fi); } else { /* Pre-v7 MPU */ - ret = get_phys_addr_pmsav5(env, address, access_type, mmu_idx, - is_secure, result, fi); + ret = get_phys_addr_pmsav5(env, ptw, address, access_type, + result, fi); } qemu_log_mask(CPU_LOG_MMU, "PMSA MPU lookup for %s at 0x%08" PRIx32 " mmu_idx %u -> %s (prot %c%c%c)\n", @@ -3348,8 +3363,8 @@ static bool get_phys_addr_nogpc(CPUARMState *env, S1Translate *ptw, /* Definitely a real MMU, not an MPU */ if (regime_translation_disabled(env, mmu_idx, is_secure)) { - return get_phys_addr_disabled(env, address, access_type, mmu_idx, - is_secure, result, fi); + return get_phys_addr_disabled(env, ptw, address, access_type, + result, fi); } if (regime_using_lpae_format(env, mmu_idx)) { From patchwork Thu Aug 24 09:28:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 716512 Delivered-To: patch@linaro.org Received: by 2002:adf:f747:0:b0:317:ecd7:513f with SMTP id z7csp1235992wrp; Thu, 24 Aug 2023 02:29:52 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFtTp2EHrmpOMuNCHYhKmFn2miiOqqiY5CU+VQDJv6x5U6uWD1HBrJVUujkQ7u3G5dMkN7k X-Received: by 2002:a05:622a:15cf:b0:3ff:2fae:b4bb with SMTP id d15-20020a05622a15cf00b003ff2faeb4bbmr17716647qty.37.1692869391860; Thu, 24 Aug 2023 02:29:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1692869391; cv=none; d=google.com; s=arc-20160816; b=BPrnqadbc9q8QuX3CZnL08MdiUhma+UfskTezd3eMj7ROJ5Ht9urbcHU32hsRDwO+6 HXloRCIljkriYBZBD/Bmg6/3Ff0yab8nhPbtoXxzdEtRHm6OFF2AIPbinBvG4J1Cr1q0 tUUvvLvRrWPmDuJPFHFoJIzSvag0PyjlZ6LBoxv6VvtJB57kewJW9/TI/y2jXTq9wwHp Ra1Ovvhfk6z6iXovUlOv6dLRiuMmBxTI5ENgikf6aIiL1tDZmvTZPNNh4CS/32kNcYHm JyVpUHcDbGOxgqw03lfta9IRNcD4NewuGvN/p0wVb1abj7X1CRAVFsrIybL6h6782I/E xaFA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=tytt/fOPhVvLsxVci+b5d34otV2ZT934LA/p/rF2PD4=; fh=bFDrUYhlTVi/QyetgXx/byg2+yO/22Hp9SjwoefyKLk=; b=yv/l3rOMe3Qe967LWIPZDZZk9GrgxpvnVZfoOj3FRS73nGsHGbq7fekvXLNMmhSG3G eagidVMGfkDzug+f9COzZCdevZzDPL2UebZe80oM/OnlJSwBIrkJk5BLYrEPVbXP6Tfq ZPyZ7+ywE0Q1bNtHRyWt/NzLseymbIk0cVgLhIxph+2fvGPqbuoovzjiwdXHf2mN0unR LpVm3ioPW0RRCf2jqqtKeqzBEws6xnUFnNoQYNHHqfRZOuECTId3eB3YhqX/1p3mc/Oe BrY9c679C2CqzSYc0WoVVEOpGMzg+lOnXKsa7fLFRyC+CsiDARGIsBMk+Ott3a2AwPsZ bSyw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SAnowIkp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id s12-20020adfeccc000000b00317b5c8a4f1sm21844004wro.60.2023.08.24.02.28.45 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Aug 2023 02:28:46 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 17/35] target/arm/ptw: Pass ARMSecurityState to regime_translation_disabled() Date: Thu, 24 Aug 2023 10:28:18 +0100 Message-Id: <20230824092836.2239644-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230824092836.2239644-1-peter.maydell@linaro.org> References: <20230824092836.2239644-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Plumb the ARMSecurityState through to regime_translation_disabled() rather than just a bool is_secure. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230807141514.19075-6-peter.maydell@linaro.org --- target/arm/ptw.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index a873fbe0239..63dd8e3cbe1 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -206,9 +206,10 @@ static uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx, int ttbrn) /* Return true if the specified stage of address translation is disabled */ static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx, - bool is_secure) + ARMSecuritySpace space) { uint64_t hcr_el2; + bool is_secure = arm_space_is_secure(space); if (arm_feature(env, ARM_FEATURE_M)) { switch (env->v7m.mpu_ctrl[is_secure] & @@ -2057,9 +2058,8 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t base; ARMMMUIdx mmu_idx = ptw->in_mmu_idx; bool is_user = regime_is_user(env, mmu_idx); - bool is_secure = arm_space_is_secure(ptw->in_space); - if (regime_translation_disabled(env, mmu_idx, is_secure)) { + if (regime_translation_disabled(env, mmu_idx, ptw->in_space)) { /* MPU disabled. */ result->f.phys_addr = address; result->f.prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; @@ -2231,7 +2231,7 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, result->f.lg_page_size = TARGET_PAGE_BITS; result->f.prot = 0; - if (regime_translation_disabled(env, mmu_idx, secure) || + if (regime_translation_disabled(env, mmu_idx, ptw->in_space) || m_is_ppb_region(env, address)) { /* * MPU disabled or M profile PPB access: use default memory map. @@ -2475,7 +2475,8 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, * are done in arm_v7m_load_vector(), which always does a direct * read using address_space_ldl(), rather than going via this function. */ - if (regime_translation_disabled(env, mmu_idx, secure)) { /* MPU disabled */ + if (regime_translation_disabled(env, mmu_idx, arm_secure_to_space(secure))) { + /* MPU disabled */ hit = true; } else if (m_is_ppb_region(env, address)) { hit = true; @@ -3303,7 +3304,7 @@ static bool get_phys_addr_nogpc(CPUARMState *env, S1Translate *ptw, */ ptw->in_mmu_idx = mmu_idx = s1_mmu_idx; if (arm_feature(env, ARM_FEATURE_EL2) && - !regime_translation_disabled(env, ARMMMUIdx_Stage2, is_secure)) { + !regime_translation_disabled(env, ARMMMUIdx_Stage2, ptw->in_space)) { return get_phys_addr_twostage(env, ptw, address, access_type, result, fi); } @@ -3362,7 +3363,7 @@ static bool get_phys_addr_nogpc(CPUARMState *env, S1Translate *ptw, /* Definitely a real MMU, not an MPU */ - if (regime_translation_disabled(env, mmu_idx, is_secure)) { + if (regime_translation_disabled(env, mmu_idx, ptw->in_space)) { return get_phys_addr_disabled(env, ptw, address, access_type, result, fi); } From patchwork Thu Aug 24 09:28:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 716541 Delivered-To: patch@linaro.org Received: by 2002:adf:f747:0:b0:317:ecd7:513f with SMTP id z7csp1237705wrp; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id s12-20020adfeccc000000b00317b5c8a4f1sm21844004wro.60.2023.08.24.02.28.46 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Aug 2023 02:28:46 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 18/35] target/arm/ptw: Pass an ARMSecuritySpace to arm_hcr_el2_eff_secstate() Date: Thu, 24 Aug 2023 10:28:19 +0100 Message-Id: <20230824092836.2239644-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230824092836.2239644-1-peter.maydell@linaro.org> References: <20230824092836.2239644-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org arm_hcr_el2_eff_secstate() takes a bool secure, which it uses to determine whether EL2 is enabled in the current security state. With the advent of FEAT_RME this is no longer sufficient, because EL2 can be enabled for Secure state but not for Root, and both of those will pass 'secure == true' in the callsites in ptw.c. As it happens in all of our callsites in ptw.c we either avoid making the call or else avoid using the returned value if we're doing a translation for Root, so this is not a behaviour change even if the experimental FEAT_RME is enabled. But it is less confusing in the ptw.c code if we avoid the use of a bool secure that duplicates some of the information in the ArmSecuritySpace argument. Make arm_hcr_el2_eff_secstate() take an ARMSecuritySpace argument instead. Because we always want to know the HCR_EL2 for the security state defined by the current effective value of SCR_EL3.{NSE,NS}, it makes no sense to pass ARMSS_Root here, and we assert that callers don't do that. To avoid the assert(), we thus push the call to arm_hcr_el2_eff_secstate() down into the cases in regime_translation_disabled() that need it, rather than calling the function and ignoring the result for the Root space translations. All other calls to this function in ptw.c are already in places where we have confirmed that the mmu_idx is a stage 2 translation or that the regime EL is not 3. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230807141514.19075-7-peter.maydell@linaro.org --- target/arm/cpu.h | 2 +- target/arm/helper.c | 8 +++++--- target/arm/ptw.c | 15 +++++++-------- 3 files changed, 13 insertions(+), 12 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 88e5accda69..bcd65a63ca0 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2555,7 +2555,7 @@ static inline bool arm_is_el2_enabled(CPUARMState *env) * "for all purposes other than a direct read or write access of HCR_EL2." * Not included here is HCR_RW. */ -uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, bool secure); +uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, ARMSecuritySpace space); uint64_t arm_hcr_el2_eff(CPUARMState *env); uint64_t arm_hcrx_el2_eff(CPUARMState *env); diff --git a/target/arm/helper.c b/target/arm/helper.c index 50f61e42ca8..9862bc73b52 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5772,11 +5772,13 @@ static void hcr_writelow(CPUARMState *env, const ARMCPRegInfo *ri, * Bits that are not included here: * RW (read from SCR_EL3.RW as needed) */ -uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, bool secure) +uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, ARMSecuritySpace space) { uint64_t ret = env->cp15.hcr_el2; - if (!arm_is_el2_enabled_secstate(env, secure)) { + assert(space != ARMSS_Root); + + if (!arm_is_el2_enabled_secstate(env, arm_space_is_secure(space))) { /* * "This register has no effect if EL2 is not enabled in the * current Security state". This is ARMv8.4-SecEL2 speak for @@ -5840,7 +5842,7 @@ uint64_t arm_hcr_el2_eff(CPUARMState *env) if (arm_feature(env, ARM_FEATURE_M)) { return 0; } - return arm_hcr_el2_eff_secstate(env, arm_is_secure_below_el3(env)); + return arm_hcr_el2_eff_secstate(env, arm_security_space_below_el3(env)); } /* diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 63dd8e3cbe1..4c60de753dd 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -209,9 +209,9 @@ static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx, ARMSecuritySpace space) { uint64_t hcr_el2; - bool is_secure = arm_space_is_secure(space); if (arm_feature(env, ARM_FEATURE_M)) { + bool is_secure = arm_space_is_secure(space); switch (env->v7m.mpu_ctrl[is_secure] & (R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK)) { case R_V7M_MPU_CTRL_ENABLE_MASK: @@ -230,18 +230,19 @@ static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx, } } - hcr_el2 = arm_hcr_el2_eff_secstate(env, is_secure); switch (mmu_idx) { case ARMMMUIdx_Stage2: case ARMMMUIdx_Stage2_S: /* HCR.DC means HCR.VM behaves as 1 */ + hcr_el2 = arm_hcr_el2_eff_secstate(env, space); return (hcr_el2 & (HCR_DC | HCR_VM)) == 0; case ARMMMUIdx_E10_0: case ARMMMUIdx_E10_1: case ARMMMUIdx_E10_1_PAN: /* TGE means that EL0/1 act as if SCTLR_EL1.M is zero */ + hcr_el2 = arm_hcr_el2_eff_secstate(env, space); if (hcr_el2 & HCR_TGE) { return true; } @@ -251,6 +252,7 @@ static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx, case ARMMMUIdx_Stage1_E1: case ARMMMUIdx_Stage1_E1_PAN: /* HCR.DC means SCTLR_EL1.M behaves as 0 */ + hcr_el2 = arm_hcr_el2_eff_secstate(env, space); if (hcr_el2 & HCR_DC) { return true; } @@ -530,7 +532,6 @@ static bool fault_s1ns(ARMSecuritySpace space, ARMMMUIdx s2_mmu_idx) static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, hwaddr addr, ARMMMUFaultInfo *fi) { - bool is_secure = ptw->in_secure; ARMMMUIdx mmu_idx = ptw->in_mmu_idx; ARMMMUIdx s2_mmu_idx = ptw->in_ptw_idx; uint8_t pte_attrs; @@ -587,7 +588,7 @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, } if (regime_is_stage2(s2_mmu_idx)) { - uint64_t hcr = arm_hcr_el2_eff_secstate(env, is_secure); + uint64_t hcr = arm_hcr_el2_eff_secstate(env, ptw->in_space); if ((hcr & HCR_PTW) && S2_attrs_are_device(hcr, pte_attrs)) { /* @@ -3066,7 +3067,6 @@ static bool get_phys_addr_disabled(CPUARMState *env, ARMMMUFaultInfo *fi) { ARMMMUIdx mmu_idx = ptw->in_mmu_idx; - bool is_secure = arm_space_is_secure(ptw->in_space); uint8_t memattr = 0x00; /* Device nGnRnE */ uint8_t shareability = 0; /* non-shareable */ int r_el; @@ -3112,7 +3112,7 @@ static bool get_phys_addr_disabled(CPUARMState *env, /* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */ if (r_el == 1) { - uint64_t hcr = arm_hcr_el2_eff_secstate(env, is_secure); + uint64_t hcr = arm_hcr_el2_eff_secstate(env, ptw->in_space); if (hcr & HCR_DC) { if (hcr & HCR_DCT) { memattr = 0xf0; /* Tagged, Normal, WB, RWA */ @@ -3149,7 +3149,6 @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, { hwaddr ipa; int s1_prot, s1_lgpgsz; - bool is_secure = ptw->in_secure; ARMSecuritySpace in_space = ptw->in_space; bool ret, ipa_secure; ARMCacheAttrs cacheattrs1; @@ -3212,7 +3211,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, } /* Combine the S1 and S2 cache attributes. */ - hcr = arm_hcr_el2_eff_secstate(env, is_secure); + hcr = arm_hcr_el2_eff_secstate(env, in_space); if (hcr & HCR_DC) { /* * HCR.DC forces the first stage attributes to From patchwork Thu Aug 24 09:28:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 716529 Delivered-To: patch@linaro.org Received: by 2002:adf:f747:0:b0:317:ecd7:513f with SMTP id z7csp1237321wrp; Thu, 24 Aug 2023 02:33:42 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGW0NOkOQbCkobuSbxTGc0osdV7OXfy9AX0r7iV+n2kPUwIiDSju1BEDJA9xT01mziPY+qX X-Received: by 2002:a0c:e3c4:0:b0:649:384f:ed9 with SMTP id e4-20020a0ce3c4000000b00649384f0ed9mr15492267qvl.32.1692869622094; Thu, 24 Aug 2023 02:33:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1692869622; cv=none; d=google.com; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id s12-20020adfeccc000000b00317b5c8a4f1sm21844004wro.60.2023.08.24.02.28.47 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Aug 2023 02:28:47 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 19/35] target/arm: Pass an ARMSecuritySpace to arm_is_el2_enabled_secstate() Date: Thu, 24 Aug 2023 10:28:20 +0100 Message-Id: <20230824092836.2239644-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230824092836.2239644-1-peter.maydell@linaro.org> References: <20230824092836.2239644-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Pass an ARMSecuritySpace instead of a bool secure to arm_is_el2_enabled_secstate(). This doesn't change behaviour. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230807141514.19075-8-peter.maydell@linaro.org --- target/arm/cpu.h | 13 ++++++++----- target/arm/helper.c | 2 +- 2 files changed, 9 insertions(+), 6 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index bcd65a63ca0..02bc8f0e8e0 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2504,17 +2504,19 @@ static inline bool arm_is_secure(CPUARMState *env) /* * Return true if the current security state has AArch64 EL2 or AArch32 Hyp. - * This corresponds to the pseudocode EL2Enabled() + * This corresponds to the pseudocode EL2Enabled(). */ -static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, bool secure) +static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, + ARMSecuritySpace space) { + assert(space != ARMSS_Root); return arm_feature(env, ARM_FEATURE_EL2) - && (!secure || (env->cp15.scr_el3 & SCR_EEL2)); + && (space != ARMSS_Secure || (env->cp15.scr_el3 & SCR_EEL2)); } static inline bool arm_is_el2_enabled(CPUARMState *env) { - return arm_is_el2_enabled_secstate(env, arm_is_secure_below_el3(env)); + return arm_is_el2_enabled_secstate(env, arm_security_space_below_el3(env)); } #else @@ -2538,7 +2540,8 @@ static inline bool arm_is_secure(CPUARMState *env) return false; } -static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, bool secure) +static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, + ARMSecuritySpace space) { return false; } diff --git a/target/arm/helper.c b/target/arm/helper.c index 9862bc73b52..8290ca0aaad 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5778,7 +5778,7 @@ uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, ARMSecuritySpace space) assert(space != ARMSS_Root); - if (!arm_is_el2_enabled_secstate(env, arm_space_is_secure(space))) { + if (!arm_is_el2_enabled_secstate(env, space)) { /* * "This register has no effect if EL2 is not enabled in the * current Security state". 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id s12-20020adfeccc000000b00317b5c8a4f1sm21844004wro.60.2023.08.24.02.28.47 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Aug 2023 02:28:47 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 20/35] target/arm/ptw: Only fold in NSTable bit effects in Secure state Date: Thu, 24 Aug 2023 10:28:21 +0100 Message-Id: <20230824092836.2239644-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230824092836.2239644-1-peter.maydell@linaro.org> References: <20230824092836.2239644-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org When we do a translation in Secure state, the NSTable bits in table descriptors may downgrade us to NonSecure; we update ptw->in_secure and ptw->in_space accordingly. We guard that check correctly with a conditional that means it's only applied for Secure stage 1 translations. However, later on in get_phys_addr_lpae() we fold the effects of the NSTable bits into the final descriptor attributes bits, and there we do it unconditionally regardless of the CPU state. That means that in Realm state (where in_secure is false) we will set bit 5 in attrs, and later use it to decide to output to non-secure space. We don't in fact need to do this folding in at all any more (since commit 2f1ff4e7b9f30c): if an NSTable bit was set then we have already set ptw->in_space to ARMSS_NonSecure, and in that situation we don't look at attrs bit 5. The only thing we still need to deal with is the real NS bit in the final descriptor word, so we can just drop the code that ORed in the NSTable bit. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230807141514.19075-9-peter.maydell@linaro.org --- target/arm/ptw.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 4c60de753dd..6e736bacd77 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1886,11 +1886,10 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, * Extract attributes from the (modified) descriptor, and apply * table descriptors. Stage 2 table descriptors do not include * any attribute fields. HPD disables all the table attributes - * except NSTable. + * except NSTable (which we have already handled). */ attrs = new_descriptor & (MAKE_64BIT_MASK(2, 10) | MAKE_64BIT_MASK(50, 14)); if (!regime_is_stage2(mmu_idx)) { - attrs |= !ptw->in_secure << 5; /* NS */ if (!param.hpd) { attrs |= extract64(tableattrs, 0, 2) << 53; /* XN, PXN */ /* From patchwork Thu Aug 24 09:28:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 716527 Delivered-To: patch@linaro.org Received: by 2002:adf:f747:0:b0:317:ecd7:513f with SMTP id z7csp1237044wrp; Thu, 24 Aug 2023 02:32:52 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHL53iU9fTdHzQrlXcRudp/DolJudCfwYhM4wUh6C7nuqhsfqlVsJK+96zJEJdq0VMl1J7F X-Received: by 2002:a05:620a:801:b0:76d:2817:5006 with SMTP id s1-20020a05620a080100b0076d28175006mr15143855qks.18.1692869572713; Thu, 24 Aug 2023 02:32:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1692869572; cv=none; d=google.com; s=arc-20160816; b=yb1YMq8CGdwQs+9D1YvNpf0OllM0FjxO0YKow74ESPvQ+9DA9s888zuSyGOrpXvd7i GH7RByY+Hhmc/hEfDWvkr9G51/8HFJDN9eF/yPjC2XRgOmUmcrjR4JpqqGBgaY3004KB coaP5kNpPTepwUzbKKvnT+/qrNyGRGGXUzb6AuwYJVOo6qvrGDSteIXAaJtKYKN0eGst sT53XrUqIsocs6sv2Nxe3dR5vQS/HxG2Fp1e1Omb7NXmy1HRkhbFxwES8jeon0DczjNi v4pJRXQHf0HaFt98OELNzhgAzNo3IVoHgwHJq1cltnbq3oAB5BoDwY9jsV3Azl9iD3+t b0Qg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=PcqjEcLAFKPxq5704Gj2dDNs6SkxXicqwmg10sRrS5w=; fh=bFDrUYhlTVi/QyetgXx/byg2+yO/22Hp9SjwoefyKLk=; b=iRx/MycfjZ1e6tgfzjL/WpW1MKWLcOMk/HBnAYnVgVVX8Si7tC8Lwchnm299LvxJW6 UYOgv57EUU99TjP86k1yzCvpXZ77HUsAf3aHnLK7lHUPzpEYwxIuhiBl2DoHUysYyPlQ OoKSGCKI3JJTWfSLz7NtHPy3wn98EhaC5cP9BoUF1fM2EW9Gr87mN+WAAUlqGjeXclt3 LHhXS6gcsn2uaxYUngIcjAgXHnr8vuXrmTkddojeX8d8Cn4dGb6tCaTZWtm5qNRmx3JP f7bIsqtvrIbgFPyNZcCrd33rIFEqW5qJcCXFNDSa0T212fSf7eBcjAs96ck+19x7cJ78 nvTw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=W7KikZRP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id s12-20020adfeccc000000b00317b5c8a4f1sm21844004wro.60.2023.08.24.02.28.47 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Aug 2023 02:28:48 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 21/35] target/arm/ptw: Remove last uses of ptw->in_secure Date: Thu, 24 Aug 2023 10:28:22 +0100 Message-Id: <20230824092836.2239644-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230824092836.2239644-1-peter.maydell@linaro.org> References: <20230824092836.2239644-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Replace the last uses of ptw->in_secure with appropriate checks on ptw->in_space. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230807141514.19075-10-peter.maydell@linaro.org --- target/arm/ptw.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 6e736bacd77..1ca25438c3c 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -3249,7 +3249,6 @@ static bool get_phys_addr_nogpc(CPUARMState *env, S1Translate *ptw, ARMMMUFaultInfo *fi) { ARMMMUIdx mmu_idx = ptw->in_mmu_idx; - bool is_secure = ptw->in_secure; ARMMMUIdx s1_mmu_idx; /* @@ -3257,8 +3256,8 @@ static bool get_phys_addr_nogpc(CPUARMState *env, S1Translate *ptw, * cannot upgrade a NonSecure translation regime's attributes * to Secure or Realm. */ - result->f.attrs.secure = is_secure; result->f.attrs.space = ptw->in_space; + result->f.attrs.secure = arm_space_is_secure(ptw->in_space); switch (mmu_idx) { case ARMMMUIdx_Phys_S: @@ -3272,8 +3271,12 @@ static bool get_phys_addr_nogpc(CPUARMState *env, S1Translate *ptw, case ARMMMUIdx_Stage1_E0: case ARMMMUIdx_Stage1_E1: case ARMMMUIdx_Stage1_E1_PAN: - /* First stage lookup uses second stage for ptw. */ - ptw->in_ptw_idx = is_secure ? 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id s12-20020adfeccc000000b00317b5c8a4f1sm21844004wro.60.2023.08.24.02.28.48 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Aug 2023 02:28:48 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 22/35] target/arm/ptw: Remove S1Translate::in_secure Date: Thu, 24 Aug 2023 10:28:23 +0100 Message-Id: <20230824092836.2239644-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230824092836.2239644-1-peter.maydell@linaro.org> References: <20230824092836.2239644-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org We no longer look at the in_secure field of the S1Translate struct anyway, so we can remove it and all the code which sets it. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230807141514.19075-11-peter.maydell@linaro.org --- target/arm/ptw.c | 13 ------------- 1 file changed, 13 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 1ca25438c3c..78bc679deef 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -51,13 +51,6 @@ typedef struct S1Translate { * value being Stage2 vs Stage2_S distinguishes those. */ ARMSecuritySpace in_space; - /* - * in_secure: whether the translation regime is a Secure one. - * This is always equal to arm_space_is_secure(in_space). - * If a Secure ptw is "downgraded" to NonSecure by an NSTable bit, - * this field is updated accordingly. - */ - bool in_secure; /* * in_debug: is this a QEMU debug access (gdbstub, etc)? Debug * accesses will not update the guest page table access flags @@ -547,7 +540,6 @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, S1Translate s2ptw = { .in_mmu_idx = s2_mmu_idx, .in_ptw_idx = ptw_idx_for_stage_2(env, s2_mmu_idx), - .in_secure = arm_space_is_secure(s2_space), .in_space = s2_space, .in_debug = true, }; @@ -1784,7 +1776,6 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_S + 1 != ARMMMUIdx_Phys_NS); QEMU_BUILD_BUG_ON(ARMMMUIdx_Stage2_S + 1 != ARMMMUIdx_Stage2); ptw->in_ptw_idx += 1; - ptw->in_secure = false; ptw->in_space = ARMSS_NonSecure; } @@ -3167,7 +3158,6 @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, ptw->in_s1_is_el0 = ptw->in_mmu_idx == ARMMMUIdx_Stage1_E0; ptw->in_mmu_idx = ipa_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2; - ptw->in_secure = ipa_secure; ptw->in_space = ipa_space; ptw->in_ptw_idx = ptw_idx_for_stage_2(env, ptw->in_mmu_idx); @@ -3403,7 +3393,6 @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address, { S1Translate ptw = { .in_mmu_idx = mmu_idx, - .in_secure = is_secure, .in_space = arm_secure_to_space(is_secure), }; return get_phys_addr_gpc(env, &ptw, address, access_type, result, fi); @@ -3475,7 +3464,6 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, } ptw.in_space = ss; - ptw.in_secure = arm_space_is_secure(ss); return get_phys_addr_gpc(env, &ptw, address, access_type, result, fi); } @@ -3489,7 +3477,6 @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, S1Translate ptw = { .in_mmu_idx = mmu_idx, .in_space = ss, - .in_secure = arm_space_is_secure(ss), .in_debug = true, }; GetPhysAddrResult res = {}; From patchwork Thu Aug 24 09:28:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 716509 Delivered-To: patch@linaro.org Received: by 2002:adf:f747:0:b0:317:ecd7:513f with SMTP id z7csp1235962wrp; Thu, 24 Aug 2023 02:29:47 -0700 (PDT) X-Google-Smtp-Source: AGHT+IF9nhnZEmcvzN85wcbcGWHiwWHPKPwlebpY2s9OF+X9/J6S8ExsUHSbPFB9kf81/bFB5cq3 X-Received: by 2002:a0c:f54b:0:b0:63f:5868:ae45 with SMTP id p11-20020a0cf54b000000b0063f5868ae45mr15181651qvm.11.1692869387400; Thu, 24 Aug 2023 02:29:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1692869387; cv=none; d=google.com; s=arc-20160816; b=iJEuCiwHY45Vyq8QLvVlxnL0NagP28GUbgvkFij3mWSik/2nFH5HaWCoWuqnJDWNTa I9cJ+LpsmkfhCcVPr4NCDZGt6w0RNvTpkf3lB9PY3bQ47gfl3b0LN/L3/gM08VGiInBZ +v3nQKfInvnFeGGmjbEBHRpObop3aBSnlJ2U2abaIz6kHOwB6c2nItp5iSueupcgFMC4 yoit5jmGsbE6HUwvTTwcKq4fcufYNjc1d/6gdJFd/tQXz+gpOZ1Dab7NwaIFvOBRFmP7 x01vTxJT57YtCFzKsTA3wVXHMOv5PExVI5WVetJwd6ibqh23/dCUjmCEo14pCSa/RTKI b1RQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=rLfi7iwoUxJ42LFstDjsa56QpNDGkJ2EfgGmjg+R5ng=; fh=bFDrUYhlTVi/QyetgXx/byg2+yO/22Hp9SjwoefyKLk=; b=aXyP6xeDZi+lFkqpYFJDMmMYR5wDS/c6r2IzcT6YkTVd1kk8JHFXpZPHwRFwYZN61b 6jXTHGD45rY0shfDhyrGTmVydJnPUuQEGfcUOUOaInZiOvMLEs/dTt+QRJLe7h6Fxvj9 U4nXRQjVYcSVAkvXMFPvqqCIrdiGF21PPu1ZAC1L5eR8i7LrcWgIwrO6bQbNsR6VKQ0S RZhvv9aVacGDywS6EWjOwpK6fDLX1t9hIvQVja6dYk1aupSDJiQFQmsQfUw7FxIMx6Lr FNScwSWr8fgTH9Yi9zc73YcvLnJvJvsC1y+mR4ZDpljch+Ew9264zrOmHU0iiUOSbws9 +/2g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="gp/+/ReP"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id s12-20020adfeccc000000b00317b5c8a4f1sm21844004wro.60.2023.08.24.02.28.48 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Aug 2023 02:28:48 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 23/35] target/arm/ptw: Drop S1Translate::out_secure Date: Thu, 24 Aug 2023 10:28:24 +0100 Message-Id: <20230824092836.2239644-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230824092836.2239644-1-peter.maydell@linaro.org> References: <20230824092836.2239644-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org We only use S1Translate::out_secure in two places, where we are setting up MemTxAttrs for a page table load. We can use arm_space_is_secure(ptw->out_space) instead, which guarantees that we're setting the MemTxAttrs secure and space fields consistently, and allows us to drop the out_secure field in S1Translate entirely. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230807141514.19075-12-peter.maydell@linaro.org --- target/arm/ptw.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 78bc679deef..312ccabe92e 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -63,7 +63,6 @@ typedef struct S1Translate { * Stage 2 is indicated by in_mmu_idx set to ARMMMUIdx_Stage2{,_S}. */ bool in_s1_is_el0; - bool out_secure; bool out_rw; bool out_be; ARMSecuritySpace out_space; @@ -553,7 +552,6 @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, pte_attrs = s2.cacheattrs.attrs; ptw->out_host = NULL; ptw->out_rw = false; - ptw->out_secure = s2.f.attrs.secure; ptw->out_space = s2.f.attrs.space; } else { #ifdef CONFIG_TCG @@ -572,7 +570,6 @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, ptw->out_phys = full->phys_addr | (addr & ~TARGET_PAGE_MASK); ptw->out_rw = full->prot & PAGE_WRITE; pte_attrs = full->pte_attrs; - ptw->out_secure = full->attrs.secure; ptw->out_space = full->attrs.space; #else g_assert_not_reached(); @@ -630,8 +627,8 @@ static uint32_t arm_ldl_ptw(CPUARMState *env, S1Translate *ptw, } else { /* Page tables are in MMIO. */ MemTxAttrs attrs = { - .secure = ptw->out_secure, .space = ptw->out_space, + .secure = arm_space_is_secure(ptw->out_space), }; AddressSpace *as = arm_addressspace(cs, attrs); MemTxResult result = MEMTX_OK; @@ -676,8 +673,8 @@ static uint64_t arm_ldq_ptw(CPUARMState *env, S1Translate *ptw, } else { /* Page tables are in MMIO. */ MemTxAttrs attrs = { - .secure = ptw->out_secure, .space = ptw->out_space, + .secure = arm_space_is_secure(ptw->out_space), }; AddressSpace *as = arm_addressspace(cs, attrs); MemTxResult result = MEMTX_OK; From patchwork Thu Aug 24 09:28:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 716530 Delivered-To: patch@linaro.org Received: by 2002:adf:f747:0:b0:317:ecd7:513f with SMTP id z7csp1237363wrp; Thu, 24 Aug 2023 02:33:46 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHJ/vXzv499R6TAJWat+jVO83jt8GJeZ8BGKTqyc1CU+0yCynU2qOJb6/6rJYV8fLBgKOTu X-Received: by 2002:ac8:5bcc:0:b0:408:1807:5408 with SMTP id b12-20020ac85bcc000000b0040818075408mr20976334qtb.11.1692869626504; Thu, 24 Aug 2023 02:33:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1692869626; cv=none; d=google.com; s=arc-20160816; b=l7hswuR0JIrmOKN5Bko0nS/2zU30uBi6KNByM/DewzdaImyBBy2DdC3boCGSeIzFx4 j/JWNDi4SKavzkHSfz8BbrjdPK40td7vZxx9UfGxOKmsDFuddMI5yCWb9p0d4qsbfn1Z pb2qqNyq3kWKeQSW8Rvx3dzD0bexXwYNw8lNovPDSM9IV5QoZNIJ48biS2Bvn/CSOoOb WQPMHsqJrlXs3XuDvzBS2HFHE9d7GheJBBoOOoCZGCGNJZ97SW1ihhyiKOTJjQ+lmUTw BJJ4aZ0SXOQaOYlVoxV7dtyCkLiaJOFr3t7KxVToY7zl70xciXQqOmUYJZp7TifCvSly O3dg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Nl4ZpUZkjwvYqdaFnAmzJsKgzFy+tbw4XNF5WJzIR8U=; fh=bFDrUYhlTVi/QyetgXx/byg2+yO/22Hp9SjwoefyKLk=; b=kHboqXM/qb1XjwD2K9scLnFBVZ5Vj3VK1fo3NQVMiusOZS/ivVjGHpklxD5s6+Iycg KoYhFrTIrq8BgNwAz5FbPPmhyNlGgv2HyewwlxQOahejA95rEreavlTN9KcOKXYOGai3 DCjr2M9NKZUUp7QVhbugRFcAWpPimpp6fkfl2ITPnfpKTTkjsc0jyt1wRo+Xes4v9N2Z xQLMflPMAj9wtvcCgdBjWisTpZdMe6dpaTjYDtcDkodmD0moUEGDTWJU+laDK8EvRSlz HxESXGZATLBoN+UsZNX65I1oV3gClrteUcvEwBLSUm+pu8oZOhQHrogSivmAOGnG+XNi H4HA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kdWzd7Dk; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id s12-20020adfeccc000000b00317b5c8a4f1sm21844004wro.60.2023.08.24.02.28.49 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Aug 2023 02:28:49 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 24/35] target/arm/ptw: Set attributes correctly for MMU disabled data accesses Date: Thu, 24 Aug 2023 10:28:25 +0100 Message-Id: <20230824092836.2239644-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230824092836.2239644-1-peter.maydell@linaro.org> References: <20230824092836.2239644-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org When the MMU is disabled, data accesses should be Device nGnRnE, Outer Shareable, Untagged. We handle the other cases from AArch64.S1DisabledOutput() correctly but missed this one. Device nGnRnE is memattr == 0, so the only part we were missing was that shareability should be set to 2 for both insn fetches and data accesses. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230807141514.19075-13-peter.maydell@linaro.org --- target/arm/ptw.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 312ccabe92e..7f217a31895 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -3108,11 +3108,13 @@ static bool get_phys_addr_disabled(CPUARMState *env, } } } - if (memattr == 0 && access_type == MMU_INST_FETCH) { - if (regime_sctlr(env, mmu_idx) & SCTLR_I) { - memattr = 0xee; /* Normal, WT, RA, NT */ - } else { - memattr = 0x44; /* Normal, NC, No */ + if (memattr == 0) { + if (access_type == MMU_INST_FETCH) { + if (regime_sctlr(env, mmu_idx) & SCTLR_I) { + memattr = 0xee; /* Normal, WT, RA, NT */ + } else { + memattr = 0x44; /* Normal, NC, No */ + } } shareability = 2; /* outer shareable */ } From patchwork Thu Aug 24 09:28:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 716508 Delivered-To: patch@linaro.org Received: by 2002:adf:f747:0:b0:317:ecd7:513f with SMTP id z7csp1235957wrp; Thu, 24 Aug 2023 02:29:46 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHUk56mWZtXZSoGEHCSC+Bw9gh0rCNiKVjnbWVwFoRDUYX9f7aSo+0QuGJABL3O49WHH5Cf X-Received: by 2002:a05:622a:193:b0:400:a6f4:7a1e with SMTP id s19-20020a05622a019300b00400a6f47a1emr17460464qtw.24.1692869386299; Thu, 24 Aug 2023 02:29:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1692869386; cv=none; d=google.com; s=arc-20160816; b=Tmycd0ujpIhvLap8Tq9HyGScun3fr8COX9S8K35836trk6rdBlSBiCCTicgghQebUC yeO6ibZV3mVT+8ErTI5tayU2qgBodgm8zG5CMB2F1dtZzZGbJ8RY6hG3A3V/xCFvZYiy cjGyDGmTouMUVsrOCXBwmBH9bi8Ac5XyDLm3JQW5QcNaIFsSGJLCpiMfUWucPII1AdKq uun5oB1knTKGznne4r8yKmobLphJXQMAjUWvSC7uwSISX3J30PtpJtMFgnpq+f9oAiPQ eMYRooM+XZnBxUlEjzOfDePocbqrIIZEjHUAUEOl7xK2qEhHxEkFAHmHGCsKK8W+uSYO ojpQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ul2FDB9YGpIRuxaGUK+qoMd3NhbINUDOFe0qhJJmN4E=; fh=bFDrUYhlTVi/QyetgXx/byg2+yO/22Hp9SjwoefyKLk=; b=gPpU7NGEMxQIYR0HW7vhPS/aHQcOxFUKVbXbiq+Aj548mWDu/EL+fkLfMUPy7uWHV1 40d12ScIUl/214wckvrdPLUbJW0mM8Fk5ppzkQrq6UiNpsMvnuMyWwxLEk48HtjIJUZC xx2xurQh1o2A/U1dCxFax8KzjSkzox4ZRhX3Gxaeqvql+prnb1Ov+bNwLA0i4rLJmnsK rlK7kOaJ9g/fJh79ckLdCHXBPqjuU5eJ8+8RrliWRo5s/3IVyPWk4SvlV9FV/1oGxo5I 0oXoI5GP7vWog4qs7mVBph5lZJkVZHpMfn/AyVL00ZGM4MDZpkX1207WKYXze4EXhIVh SRJQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=wdzK5mGk; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id s12-20020adfeccc000000b00317b5c8a4f1sm21844004wro.60.2023.08.24.02.28.49 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Aug 2023 02:28:49 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 25/35] target/arm/ptw: Check for block descriptors at invalid levels Date: Thu, 24 Aug 2023 10:28:26 +0100 Message-Id: <20230824092836.2239644-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230824092836.2239644-1-peter.maydell@linaro.org> References: <20230824092836.2239644-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The architecture doesn't permit block descriptors at any arbitrary level of the page table walk; it depends on the granule size which levels are permitted. We implemented only a partial version of this check which assumes that block descriptors are valid at all levels except level 3, which meant that we wouldn't deliver the Translation fault for all cases of this sort of guest page table error. Implement the logic corresponding to the pseudocode AArch64.DecodeDescriptorType() and AArch64.BlockDescSupported(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230807141514.19075-14-peter.maydell@linaro.org --- target/arm/ptw.c | 25 +++++++++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 7f217a31895..fbb0f8a0bf2 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1551,6 +1551,25 @@ static int check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, uint64_t tcr, return INT_MIN; } +static bool lpae_block_desc_valid(ARMCPU *cpu, bool ds, + ARMGranuleSize gran, int level) +{ + /* + * See pseudocode AArch46.BlockDescSupported(): block descriptors + * are not valid at all levels, depending on the page size. + */ + switch (gran) { + case Gran4K: + return (level == 0 && ds) || level == 1 || level == 2; + case Gran16K: + return (level == 1 && ds) || level == 2; + case Gran64K: + return (level == 1 && arm_pamax(cpu) == 52) || level == 2; + default: + g_assert_not_reached(); + } +} + /** * get_phys_addr_lpae: perform one stage of page table walk, LPAE format * @@ -1786,8 +1805,10 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, new_descriptor = descriptor; restart_atomic_update: - if (!(descriptor & 1) || (!(descriptor & 2) && (level == 3))) { - /* Invalid, or the Reserved level 3 encoding */ + if (!(descriptor & 1) || + (!(descriptor & 2) && + !lpae_block_desc_valid(cpu, param.ds, param.gran, level))) { + /* Invalid, or a block descriptor at an invalid level */ goto do_translation_fault; } From patchwork Thu Aug 24 09:28:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 716516 Delivered-To: patch@linaro.org Received: by 2002:adf:f747:0:b0:317:ecd7:513f with SMTP id z7csp1236081wrp; Thu, 24 Aug 2023 02:30:08 -0700 (PDT) X-Google-Smtp-Source: AGHT+IH11L4SFnmchsny8NW6Ck6ucaWkBLHydT8FmyHQfbm7naBEmaNqIcq7aC7hTgnf1o4Vp7q+ X-Received: by 2002:a05:622a:1813:b0:405:4ba8:a179 with SMTP id t19-20020a05622a181300b004054ba8a179mr17773513qtc.4.1692869408436; Thu, 24 Aug 2023 02:30:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1692869408; cv=none; d=google.com; s=arc-20160816; b=bybpl+XpAOrvy7rar3yAvkvjtHuJ8C3gCD5wR6xf0Q3+ZK3npl7ubSjUigtdq6uodD vmIsa2UiMUil2We4PmpGGq/lHL4CGvAdz0ZBZV2fyjM2Qpp2YgAS9exeToagFn+cDabs 0Yl41axCm8/qbVHaB7lvGaJSyVwB6ZyiH5gM3XVD7A9+UDOJxR5mleOB1fRy+5oFqsY7 bBjjkuLm5L45sR2q1B3dJrGiiULq5lj0hR558TDkZhnglZMm9pxbRr9iXqWvgmM/9MEW Yeagl+bYytvxY5RDgpfyKQsaJqkaH7onL5PvGcD7EZdhC53vJZSQ+LzIZ0kExAJnv/0e 3d1Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=y+S+NVN8xC+7Bg8xrjvp8JbWeFqO2fn6xwxI6G3BukE=; fh=bFDrUYhlTVi/QyetgXx/byg2+yO/22Hp9SjwoefyKLk=; b=AptoHif0ThJsxVvOStIn46fN77mDGhsxlztYkEqIfVMBSdYtuI0o/ZVJsbumsF/bws Qkryi9XqFzCTi6oxhkyRx+RxO0ik1CpNZXSIAJvDNCiZHsYWh1MCxGa2uwz2jXfkmQvk BLFGZs4zEg6c53D8DS3RCQ92HsmwmMzi3jQLG8PwnBKHLRHIDh7f1hsfs+hB8qzGVoB1 9z4R9xZ4N0AcS/pcgp03ZBKropcjCZ+6bTyw2rwPVc3qVVGPnuisd4dg3OxyQKmO4S5k 2LyIQLVwf8LMz6ptHACSM6wKAgROUukLvh36mLZk54NPYen7THp7eCytpTG7qu4EsD2X R11Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Qpc5Hgxd; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id s12-20020adfeccc000000b00317b5c8a4f1sm21844004wro.60.2023.08.24.02.28.50 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Aug 2023 02:28:50 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 26/35] target/arm/ptw: Report stage 2 fault level for stage 2 faults on stage 1 ptw Date: Thu, 24 Aug 2023 10:28:27 +0100 Message-Id: <20230824092836.2239644-27-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230824092836.2239644-1-peter.maydell@linaro.org> References: <20230824092836.2239644-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::129; envelope-from=peter.maydell@linaro.org; helo=mail-lf1-x129.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org When we report faults due to stage 2 faults during a stage 1 page table walk, the 'level' parameter should be the level of the walk in stage 2 that faulted, not the level of the walk in stage 1. Correct the reporting of these faults. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230807141514.19075-15-peter.maydell@linaro.org --- target/arm/ptw.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index fbb0f8a0bf2..07832eb8f76 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2048,9 +2048,13 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, do_translation_fault: fi->type = ARMFault_Translation; do_fault: - fi->level = level; - /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */ - fi->stage2 = fi->s1ptw || regime_is_stage2(mmu_idx); + if (fi->s1ptw) { + /* Retain the existing stage 2 fi->level */ + assert(fi->stage2); + } else { + fi->level = level; + fi->stage2 = regime_is_stage2(mmu_idx); + } fi->s1ns = fault_s1ns(ptw->in_space, mmu_idx); return true; } From patchwork Thu Aug 24 09:28:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 716532 Delivered-To: patch@linaro.org Received: by 2002:adf:f747:0:b0:317:ecd7:513f with SMTP id z7csp1237406wrp; Thu, 24 Aug 2023 02:33:51 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGhkgun6DGm/VRsRLad5HDANaTdvNqksPzY89reUw3+a/C+he4DkjnVO/6SOBX3b8YKNr2a X-Received: by 2002:a0c:f1ca:0:b0:635:f412:6a70 with SMTP id u10-20020a0cf1ca000000b00635f4126a70mr13593491qvl.47.1692869631547; Thu, 24 Aug 2023 02:33:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1692869631; cv=none; d=google.com; s=arc-20160816; b=XP3ha7W4ttnLUARdhI++JONfNzJ4p24pioTV+KvEvAe7MNTU53m389sQwWk1yemUTX 9VwOMJS64N3SmTc9Ge8Q0+vs+jAWSCdiH1VY7UnEamp80mmxdzeP1vw+tpPD4yfARlLv T/XxIwoNddu31IuzCisifGvGRX9D05h4pH7EMmh3xvJbSuBQxD/rCEqsMAx+Qcba9OtR aE8AlI8Hak+XP1brwKapTAeGt+e81o7TqqTURAyzDUgQSNnwSlCnIRp30pDKuxhxk/Yr irPVFuqag76ZMi43lRY37zFh5wtSZPO+9JXv+npdRIQlYTlzgV6L/nbVY8uULpK5kCCx RDQA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=x2CxREWJG7MgeLcSqs2FqHmGhWzoHCJcynkCy/gC8pQ=; fh=bFDrUYhlTVi/QyetgXx/byg2+yO/22Hp9SjwoefyKLk=; b=dhB9f1bBgxDRpz0D9B5HZvfXBIGhXsMYOio7/VgYsBuPANK+PCzdq3IJ/kbGMVC01c hv6fvlPfdH2bdVyMYYqWjk3cZ4g5OCfvnopqQxWCBV9JHjxAzyNmBa+uCuYfzsedD9T+ L69YExcEzeZqezFQOCabFbw34neV0x8jVro8wSDj5OCjDyJyt78rOttczUEiyIylxgfA n10hrdG4KOE+yy6yxE8rFIdRjqS4mJfVkx1ipYoY7e65+xH9OGBb+EDiFTN/dIjBrwtM fRIYPgNuWVN5HdS14fHwf6/nwkXKqINjeifDxzUJT5+SmoSvX85CXQVX7tDd1rMjNdv8 FaBQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UBcs5oKC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id s12-20020adfeccc000000b00317b5c8a4f1sm21844004wro.60.2023.08.24.02.28.50 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Aug 2023 02:28:50 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 27/35] target/arm: Adjust PAR_EL1.SH for Device and Normal-NC memory types Date: Thu, 24 Aug 2023 10:28:28 +0100 Message-Id: <20230824092836.2239644-28-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230824092836.2239644-1-peter.maydell@linaro.org> References: <20230824092836.2239644-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The PAR_EL1.SH field documents that for the cases of: * Device memory * Normal memory with both Inner and Outer Non-Cacheable the field should be 0b10 rather than whatever was in the translation table descriptor field. (In the pseudocode this is handled by PAREncodeShareability().) Perform this adjustment when assembling a PAR value. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230807141514.19075-16-peter.maydell@linaro.org --- target/arm/helper.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 8290ca0aaad..da5db6d3ff6 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3342,6 +3342,19 @@ static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri, } #ifdef CONFIG_TCG +static int par_el1_shareability(GetPhysAddrResult *res) +{ + /* + * The PAR_EL1.SH field must be 0b10 for Device or Normal-NC + * memory -- see pseudocode PAREncodeShareability(). + */ + if (((res->cacheattrs.attrs & 0xf0) == 0) || + res->cacheattrs.attrs == 0x44 || res->cacheattrs.attrs == 0x40) { + return 2; + } + return res->cacheattrs.shareability; +} + static uint64_t do_ats_write(CPUARMState *env, uint64_t value, MMUAccessType access_type, ARMMMUIdx mmu_idx, bool is_secure) @@ -3470,7 +3483,7 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value, par64 |= (1 << 9); /* NS */ } par64 |= (uint64_t)res.cacheattrs.attrs << 56; /* ATTR */ - par64 |= res.cacheattrs.shareability << 7; /* SH */ + par64 |= par_el1_shareability(&res) << 7; /* SH */ } else { uint32_t fsr = arm_fi_to_lfsc(&fi); From patchwork Thu Aug 24 09:28:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 716515 Delivered-To: patch@linaro.org Received: by 2002:adf:f747:0:b0:317:ecd7:513f with SMTP id z7csp1236045wrp; Thu, 24 Aug 2023 02:30:03 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFqZ4y/fwcDHO/bZgwzuGBDtnwpHs/TE7VcARWS8KqIv1s3OML1VrrUlARU1UKg6gVt4vVZ X-Received: by 2002:a05:620a:448e:b0:768:f02:532e with SMTP id x14-20020a05620a448e00b007680f02532emr19624204qkp.39.1692869402908; Thu, 24 Aug 2023 02:30:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1692869402; cv=none; d=google.com; s=arc-20160816; b=g28Bwf8MAmcMqq7kKcfoorl46Dnr8m5wFDmwbVIwhoER6SkvxQ57Fxor9MOHgp21Qx u+3BoyGMtsve4zRpzCcLAK054HzI1eqEKmHpJ7MjmYC3KKEwZaRxh6ZtIKdTDCERWckW n9a3hzvekjgNCT2dOHYKp8EErYYnRzcvj7473ZlNDg1+PgKv4QLv8SG1zsRkC3/QrOAw Ylb1dXH33QhupUNvgGDbzFcwvRj/Pwm8j12a+9dnEyJm/bmDmJWqrjDoiYv/5U3Xza7b /uap2IvhuqfaVr7xW+XaZHfxsSSENzcQO7RPtlGeGYvpF3/yFHkwjW/6jk0SL2+VrP12 eKLQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=m7ehu004RcOiLV/pfLKDXFZl8HCdJzWH0SUfnwSyxlE=; fh=bFDrUYhlTVi/QyetgXx/byg2+yO/22Hp9SjwoefyKLk=; b=Ee8HPky8NQ1KKQYo7x7z4Bx83LNwenWKVckbXLwlxumhTZJaZcL+kiOiI6nLu/yP06 UTQ3LcLlPvawlzu0yZjKtv3ovWOIILA+/DmLsATSaRehMNx+26X46X3r0lABd5VfVuiD c6ix06Zfx3eoV3QNYJ3gqbMlUoXWC92RxTpl2lb4+fQFLqw4sQGiSuG3YckM0NUN/2Wl 3lNvXdT1XA3mN58vFTNYs7NtKVN0rS6ZQDjdO4PDuJhgVIdehG9tOB3hlPta32jBENyZ oyF0w+zlWGLCE8CZeYAtstcZrHYQmBp/2bZR8JpchwNQL/4GdbHHHT2t0QeAGoxlHd6e 3kdw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SMtuFkUR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id s12-20020adfeccc000000b00317b5c8a4f1sm21844004wro.60.2023.08.24.02.28.51 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Aug 2023 02:28:51 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 28/35] target/arm/ptw: Load stage-2 tables from realm physical space Date: Thu, 24 Aug 2023 10:28:29 +0100 Message-Id: <20230824092836.2239644-29-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230824092836.2239644-1-peter.maydell@linaro.org> References: <20230824092836.2239644-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Jean-Philippe Brucker In realm state, stage-2 translation tables are fetched from the realm physical address space (R_PGRQD). Signed-off-by: Jean-Philippe Brucker Reviewed-by: Peter Maydell Message-id: 20230809123706.1842548-2-jean-philippe@linaro.org Signed-off-by: Peter Maydell --- target/arm/ptw.c | 26 ++++++++++++++++++-------- 1 file changed, 18 insertions(+), 8 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 07832eb8f76..7a69968dd76 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -157,22 +157,32 @@ static ARMMMUIdx ptw_idx_for_stage_2(CPUARMState *env, ARMMMUIdx stage2idx) /* * We're OK to check the current state of the CPU here because - * (1) we always invalidate all TLBs when the SCR_EL3.NS bit changes + * (1) we always invalidate all TLBs when the SCR_EL3.NS or SCR_EL3.NSE bit + * changes. * (2) there's no way to do a lookup that cares about Stage 2 for a * different security state to the current one for AArch64, and AArch32 * never has a secure EL2. (AArch32 ATS12NSO[UP][RW] allow EL3 to do * an NS stage 1+2 lookup while the NS bit is 0.) */ - if (!arm_is_secure_below_el3(env) || !arm_el_is_aa64(env, 3)) { + if (!arm_el_is_aa64(env, 3)) { return ARMMMUIdx_Phys_NS; } - if (stage2idx == ARMMMUIdx_Stage2_S) { - s2walk_secure = !(env->cp15.vstcr_el2 & VSTCR_SW); - } else { - s2walk_secure = !(env->cp15.vtcr_el2 & VTCR_NSW); - } - return s2walk_secure ? ARMMMUIdx_Phys_S : ARMMMUIdx_Phys_NS; + switch (arm_security_space_below_el3(env)) { + case ARMSS_NonSecure: + return ARMMMUIdx_Phys_NS; + case ARMSS_Realm: + return ARMMMUIdx_Phys_Realm; + case ARMSS_Secure: + if (stage2idx == ARMMMUIdx_Stage2_S) { + s2walk_secure = !(env->cp15.vstcr_el2 & VSTCR_SW); + } else { + s2walk_secure = !(env->cp15.vtcr_el2 & VTCR_NSW); + } + return s2walk_secure ? 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id s12-20020adfeccc000000b00317b5c8a4f1sm21844004wro.60.2023.08.24.02.28.51 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Aug 2023 02:28:51 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 29/35] target/arm/helper: Fix tlbmask and tlbbits for TLBI VAE2* Date: Thu, 24 Aug 2023 10:28:30 +0100 Message-Id: <20230824092836.2239644-30-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230824092836.2239644-1-peter.maydell@linaro.org> References: <20230824092836.2239644-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::231; envelope-from=peter.maydell@linaro.org; helo=mail-lj1-x231.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Jean-Philippe Brucker When HCR_EL2.E2H is enabled, TLB entries are formed using the EL2&0 translation regime, instead of the EL2 translation regime. The TLB VAE2* instructions invalidate the regime that corresponds to the current value of HCR_EL2.E2H. At the moment we only invalidate the EL2 translation regime. This causes problems with RMM, which issues TLBI VAE2IS instructions with HCR_EL2.E2H enabled. Update vae2_tlbmask() to take HCR_EL2.E2H into account. Add vae2_tlbbits() as well, since the top-byte-ignore configuration is different between the EL2&0 and EL2 regime. Signed-off-by: Jean-Philippe Brucker Reviewed-by: Peter Maydell Message-id: 20230809123706.1842548-3-jean-philippe@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 50 ++++++++++++++++++++++++++++++++++++--------- 1 file changed, 40 insertions(+), 10 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index da5db6d3ff6..808f35218a2 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4663,6 +4663,21 @@ static int vae1_tlbmask(CPUARMState *env) return mask; } +static int vae2_tlbmask(CPUARMState *env) +{ + uint64_t hcr = arm_hcr_el2_eff(env); + uint16_t mask; + + if (hcr & HCR_E2H) { + mask = ARMMMUIdxBit_E20_2 | + ARMMMUIdxBit_E20_2_PAN | + ARMMMUIdxBit_E20_0; + } else { + mask = ARMMMUIdxBit_E2; + } + return mask; +} + /* Return 56 if TBI is enabled, 64 otherwise. */ static int tlbbits_for_regime(CPUARMState *env, ARMMMUIdx mmu_idx, uint64_t addr) @@ -4689,6 +4704,25 @@ static int vae1_tlbbits(CPUARMState *env, uint64_t addr) return tlbbits_for_regime(env, mmu_idx, addr); } +static int vae2_tlbbits(CPUARMState *env, uint64_t addr) +{ + uint64_t hcr = arm_hcr_el2_eff(env); + ARMMMUIdx mmu_idx; + + /* + * Only the regime of the mmu_idx below is significant. + * Regime EL2&0 has two ranges with separate TBI configuration, while EL2 + * only has one. + */ + if (hcr & HCR_E2H) { + mmu_idx = ARMMMUIdx_E20_2; + } else { + mmu_idx = ARMMMUIdx_E2; + } + + return tlbbits_for_regime(env, mmu_idx, addr); +} + static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -4781,10 +4815,11 @@ static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri, * flush-last-level-only. */ CPUState *cs = env_cpu(env); - int mask = e2_tlbmask(env); + int mask = vae2_tlbmask(env); uint64_t pageaddr = sextract64(value << 12, 0, 56); + int bits = vae2_tlbbits(env, pageaddr); - tlb_flush_page_by_mmuidx(cs, pageaddr, mask); + tlb_flush_page_bits_by_mmuidx(cs, pageaddr, mask, bits); } static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -4838,11 +4873,11 @@ static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { CPUState *cs = env_cpu(env); + int mask = vae2_tlbmask(env); uint64_t pageaddr = sextract64(value << 12, 0, 56); - int bits = tlbbits_for_regime(env, ARMMMUIdx_E2, pageaddr); + int bits = vae2_tlbbits(env, pageaddr); - tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, - ARMMMUIdxBit_E2, bits); + tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, bits); } static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -5014,11 +5049,6 @@ static void tlbi_aa64_rvae1is_write(CPUARMState *env, do_rvae_write(env, value, vae1_tlbmask(env), true); } -static int vae2_tlbmask(CPUARMState *env) -{ - return ARMMMUIdxBit_E2; -} - static void tlbi_aa64_rvae2_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) From patchwork Thu Aug 24 09:28:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 716513 Delivered-To: patch@linaro.org Received: by 2002:adf:f747:0:b0:317:ecd7:513f with SMTP id z7csp1236015wrp; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id s12-20020adfeccc000000b00317b5c8a4f1sm21844004wro.60.2023.08.24.02.28.51 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Aug 2023 02:28:52 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 30/35] target/arm: Skip granule protection checks for AT instructions Date: Thu, 24 Aug 2023 10:28:31 +0100 Message-Id: <20230824092836.2239644-31-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230824092836.2239644-1-peter.maydell@linaro.org> References: <20230824092836.2239644-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Jean-Philippe Brucker GPC checks are not performed on the output address for AT instructions, as stated by ARM DDI 0487J in D8.12.2: When populating PAR_EL1 with the result of an address translation instruction, granule protection checks are not performed on the final output address of a successful translation. Rename get_phys_addr_with_secure(), since it's only used to handle AT instructions. Signed-off-by: Jean-Philippe Brucker Reviewed-by: Peter Maydell Message-id: 20230809123706.1842548-4-jean-philippe@linaro.org Signed-off-by: Peter Maydell --- target/arm/internals.h | 25 ++++++++++++++----------- target/arm/helper.c | 8 ++++++-- target/arm/ptw.c | 11 ++++++----- 3 files changed, 26 insertions(+), 18 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 0f01bc32a8a..fc90c364f77 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1190,12 +1190,11 @@ typedef struct GetPhysAddrResult { } GetPhysAddrResult; /** - * get_phys_addr_with_secure: get the physical address for a virtual address + * get_phys_addr: get the physical address for a virtual address * @env: CPUARMState * @address: virtual address to get physical address for * @access_type: 0 for read, 1 for write, 2 for execute * @mmu_idx: MMU index indicating required translation regime - * @is_secure: security state for the access * @result: set on translation success. * @fi: set to fault info if the translation fails * @@ -1212,26 +1211,30 @@ typedef struct GetPhysAddrResult { * * for PSMAv5 based systems we don't bother to return a full FSR format * value. */ -bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address, - MMUAccessType access_type, - ARMMMUIdx mmu_idx, bool is_secure, - GetPhysAddrResult *result, ARMMMUFaultInfo *fi) +bool get_phys_addr(CPUARMState *env, target_ulong address, + MMUAccessType access_type, ARMMMUIdx mmu_idx, + GetPhysAddrResult *result, ARMMMUFaultInfo *fi) __attribute__((nonnull)); /** - * get_phys_addr: get the physical address for a virtual address + * get_phys_addr_with_secure_nogpc: get the physical address for a virtual + * address * @env: CPUARMState * @address: virtual address to get physical address for * @access_type: 0 for read, 1 for write, 2 for execute * @mmu_idx: MMU index indicating required translation regime + * @is_secure: security state for the access * @result: set on translation success. * @fi: set to fault info if the translation fails * - * Similarly, but use the security regime of @mmu_idx. + * Similar to get_phys_addr, but use the given security regime and don't perform + * a Granule Protection Check on the resulting address. */ -bool get_phys_addr(CPUARMState *env, target_ulong address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, - GetPhysAddrResult *result, ARMMMUFaultInfo *fi) +bool get_phys_addr_with_secure_nogpc(CPUARMState *env, target_ulong address, + MMUAccessType access_type, + ARMMMUIdx mmu_idx, bool is_secure, + GetPhysAddrResult *result, + ARMMMUFaultInfo *fi) __attribute__((nonnull)); bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, diff --git a/target/arm/helper.c b/target/arm/helper.c index 808f35218a2..e8a232a1f89 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3365,8 +3365,12 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value, ARMMMUFaultInfo fi = {}; GetPhysAddrResult res = {}; - ret = get_phys_addr_with_secure(env, value, access_type, mmu_idx, - is_secure, &res, &fi); + /* + * I_MXTJT: Granule protection checks are not performed on the final address + * of a successful translation. + */ + ret = get_phys_addr_with_secure_nogpc(env, value, access_type, mmu_idx, + is_secure, &res, &fi); /* * ATS operations only do S1 or S1+S2 translations, so we never diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 7a69968dd76..ca4de6e3999 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -3420,16 +3420,17 @@ static bool get_phys_addr_gpc(CPUARMState *env, S1Translate *ptw, return false; } -bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, - bool is_secure, GetPhysAddrResult *result, - ARMMMUFaultInfo *fi) +bool get_phys_addr_with_secure_nogpc(CPUARMState *env, target_ulong address, + MMUAccessType access_type, + ARMMMUIdx mmu_idx, bool is_secure, + GetPhysAddrResult *result, + ARMMMUFaultInfo *fi) { S1Translate ptw = { .in_mmu_idx = mmu_idx, .in_space = arm_secure_to_space(is_secure), }; - return get_phys_addr_gpc(env, &ptw, address, access_type, result, fi); + return get_phys_addr_nogpc(env, &ptw, address, access_type, result, fi); } bool get_phys_addr(CPUARMState *env, target_ulong address, From patchwork Thu Aug 24 09:28:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 716525 Delivered-To: patch@linaro.org Received: by 2002:adf:f747:0:b0:317:ecd7:513f with SMTP id z7csp1236336wrp; Thu, 24 Aug 2023 02:30:47 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEL9OuWzYBvqjhUiJsJtv63i5U2aEXfqPjwKwCMgNyiT1N4W3BGF/YjwjREq/j8PrA0T8kZ X-Received: by 2002:a05:620a:394a:b0:76d:bc1b:c495 with SMTP id qs10-20020a05620a394a00b0076dbc1bc495mr5142791qkn.14.1692869447163; Thu, 24 Aug 2023 02:30:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1692869447; cv=none; d=google.com; s=arc-20160816; b=YAmJkh0+yFmwQQMnM6eYdhiWH0nVusWfVn15uE1FL2gZ6IRwBBRrvRWyCMAVBtK46j Tc78FexSnrDFbQoG+HtDc1MJOL1QMAMRLfKhboHY2OHp7fQ/nQSfTnyTOBqMqJpyXydZ g9MDr2YCYzFUe2JqDTJ/jMM4PycCkj/EcFRBPYAlbAl7n6JfzmQp+zsFJEgQqH0CoMU0 upg/mAwk5fTapAizP+rSIIbqq2U4qr18H1rufKbchoNv6rLLZY9AHyTMnvCcORDC2iZx X54HFM4cYUENkBzgsPswTBPHHA/WygjhqiFF+R0KRpZs75veNQ1c6rUEUKZhlbBA+Cdc +0Gg== ARC-Message-Signature: i=1; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id s12-20020adfeccc000000b00317b5c8a4f1sm21844004wro.60.2023.08.24.02.28.52 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Aug 2023 02:28:52 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 31/35] target/arm: Pass security space rather than flag for AT instructions Date: Thu, 24 Aug 2023 10:28:32 +0100 Message-Id: <20230824092836.2239644-32-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230824092836.2239644-1-peter.maydell@linaro.org> References: <20230824092836.2239644-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::131; envelope-from=peter.maydell@linaro.org; helo=mail-lf1-x131.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Jean-Philippe Brucker At the moment we only handle Secure and Nonsecure security spaces for the AT instructions. Add support for Realm and Root. For AArch64, arm_security_space() gives the desired space. ARM DDI0487J says (R_NYXTL): If EL3 is implemented, then when an address translation instruction that applies to an Exception level lower than EL3 is executed, the Effective value of SCR_EL3.{NSE, NS} determines the target Security state that the instruction applies to. For AArch32, some instructions can access NonSecure space from Secure, so we still need to pass the state explicitly to do_ats_write(). Signed-off-by: Jean-Philippe Brucker Reviewed-by: Peter Maydell Message-id: 20230809123706.1842548-5-jean-philippe@linaro.org Signed-off-by: Peter Maydell --- target/arm/internals.h | 18 +++++++++--------- target/arm/helper.c | 27 ++++++++++++--------------- target/arm/ptw.c | 12 ++++++------ 3 files changed, 27 insertions(+), 30 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index fc90c364f77..cf13bb94f59 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1217,24 +1217,24 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, __attribute__((nonnull)); /** - * get_phys_addr_with_secure_nogpc: get the physical address for a virtual - * address + * get_phys_addr_with_space_nogpc: get the physical address for a virtual + * address * @env: CPUARMState * @address: virtual address to get physical address for * @access_type: 0 for read, 1 for write, 2 for execute * @mmu_idx: MMU index indicating required translation regime - * @is_secure: security state for the access + * @space: security space for the access * @result: set on translation success. * @fi: set to fault info if the translation fails * - * Similar to get_phys_addr, but use the given security regime and don't perform + * Similar to get_phys_addr, but use the given security space and don't perform * a Granule Protection Check on the resulting address. */ -bool get_phys_addr_with_secure_nogpc(CPUARMState *env, target_ulong address, - MMUAccessType access_type, - ARMMMUIdx mmu_idx, bool is_secure, - GetPhysAddrResult *result, - ARMMMUFaultInfo *fi) +bool get_phys_addr_with_space_nogpc(CPUARMState *env, target_ulong address, + MMUAccessType access_type, + ARMMMUIdx mmu_idx, ARMSecuritySpace space, + GetPhysAddrResult *result, + ARMMMUFaultInfo *fi) __attribute__((nonnull)); bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, diff --git a/target/arm/helper.c b/target/arm/helper.c index e8a232a1f89..de639d40871 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3357,7 +3357,7 @@ static int par_el1_shareability(GetPhysAddrResult *res) static uint64_t do_ats_write(CPUARMState *env, uint64_t value, MMUAccessType access_type, ARMMMUIdx mmu_idx, - bool is_secure) + ARMSecuritySpace ss) { bool ret; uint64_t par64; @@ -3369,8 +3369,8 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value, * I_MXTJT: Granule protection checks are not performed on the final address * of a successful translation. */ - ret = get_phys_addr_with_secure_nogpc(env, value, access_type, mmu_idx, - is_secure, &res, &fi); + ret = get_phys_addr_with_space_nogpc(env, value, access_type, mmu_idx, ss, + &res, &fi); /* * ATS operations only do S1 or S1+S2 translations, so we never @@ -3535,7 +3535,7 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) uint64_t par64; ARMMMUIdx mmu_idx; int el = arm_current_el(env); - bool secure = arm_is_secure_below_el3(env); + ARMSecuritySpace ss = arm_security_space(env); switch (ri->opc2 & 6) { case 0: @@ -3543,10 +3543,9 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) switch (el) { case 3: mmu_idx = ARMMMUIdx_E3; - secure = true; break; case 2: - g_assert(!secure); /* ARMv8.4-SecEL2 is 64-bit only */ + g_assert(ss != ARMSS_Secure); /* ARMv8.4-SecEL2 is 64-bit only */ /* fall through */ case 1: if (ri->crm == 9 && (env->uncached_cpsr & CPSR_PAN)) { @@ -3564,10 +3563,9 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) switch (el) { case 3: mmu_idx = ARMMMUIdx_E10_0; - secure = true; break; case 2: - g_assert(!secure); /* ARMv8.4-SecEL2 is 64-bit only */ + g_assert(ss != ARMSS_Secure); /* ARMv8.4-SecEL2 is 64-bit only */ mmu_idx = ARMMMUIdx_Stage1_E0; break; case 1: @@ -3580,18 +3578,18 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) case 4: /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */ mmu_idx = ARMMMUIdx_E10_1; - secure = false; + ss = ARMSS_NonSecure; break; case 6: /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */ mmu_idx = ARMMMUIdx_E10_0; - secure = false; + ss = ARMSS_NonSecure; break; default: g_assert_not_reached(); } - par64 = do_ats_write(env, value, access_type, mmu_idx, secure); + par64 = do_ats_write(env, value, access_type, mmu_idx, ss); A32_BANKED_CURRENT_REG_SET(env, par, par64); #else @@ -3608,7 +3606,8 @@ static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t par64; /* There is no SecureEL2 for AArch32. */ - par64 = do_ats_write(env, value, access_type, ARMMMUIdx_E2, false); + par64 = do_ats_write(env, value, access_type, ARMMMUIdx_E2, + ARMSS_NonSecure); A32_BANKED_CURRENT_REG_SET(env, par, par64); #else @@ -3633,7 +3632,6 @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, #ifdef CONFIG_TCG MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD; ARMMMUIdx mmu_idx; - int secure = arm_is_secure_below_el3(env); uint64_t hcr_el2 = arm_hcr_el2_eff(env); bool regime_e20 = (hcr_el2 & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE); @@ -3653,7 +3651,6 @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, break; case 6: /* AT S1E3R, AT S1E3W */ mmu_idx = ARMMMUIdx_E3; - secure = true; break; default: g_assert_not_reached(); @@ -3673,7 +3670,7 @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, } env->cp15.par_el[1] = do_ats_write(env, value, access_type, - mmu_idx, secure); + mmu_idx, arm_security_space(env)); #else /* Handled by hardware accelerator. */ g_assert_not_reached(); diff --git a/target/arm/ptw.c b/target/arm/ptw.c index ca4de6e3999..bfbab26b9b4 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -3420,15 +3420,15 @@ static bool get_phys_addr_gpc(CPUARMState *env, S1Translate *ptw, return false; } -bool get_phys_addr_with_secure_nogpc(CPUARMState *env, target_ulong address, - MMUAccessType access_type, - ARMMMUIdx mmu_idx, bool is_secure, - GetPhysAddrResult *result, - ARMMMUFaultInfo *fi) +bool get_phys_addr_with_space_nogpc(CPUARMState *env, target_ulong address, + MMUAccessType access_type, + ARMMMUIdx mmu_idx, ARMSecuritySpace space, + GetPhysAddrResult *result, + ARMMMUFaultInfo *fi) { S1Translate ptw = { .in_mmu_idx = mmu_idx, - .in_space = arm_secure_to_space(is_secure), + .in_space = space, }; return get_phys_addr_nogpc(env, &ptw, address, access_type, result, fi); } From patchwork Thu Aug 24 09:28:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 716522 Delivered-To: patch@linaro.org Received: by 2002:adf:f747:0:b0:317:ecd7:513f with SMTP id z7csp1236305wrp; Thu, 24 Aug 2023 02:30:43 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEXpTKLVcMar15Vl7KiedK//j5pe0RSsZRqYthlNY2UgecInRPiMMU5OJa8/0x5WzuQiBAb X-Received: by 2002:a05:622a:1907:b0:3e4:e2ce:526f with SMTP id w7-20020a05622a190700b003e4e2ce526fmr20615590qtc.39.1692869442979; Thu, 24 Aug 2023 02:30:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1692869442; cv=none; d=google.com; s=arc-20160816; b=Ta300ePV474MRRkeiO/TGBpajYl0BBxeFHu3qEnEr136ng21UZWBqFQurCSke+j6Ds HE4G1LUH8ZwUUz3eRo6ZiXu8AW+1/YdVpjxP74sGK7RyEtDLBktO1hZdmbjD0t2SD6cq R4Khxv9yy+6mAubZqjgIn9a06H20ZgIefW3zNmpuR+WqpgxCzZwk92s9PTA3FaBp9Nx0 72fCpIfkALRNMTKi8lkSqgqsWXIbfpQjoeCcuTfrO/uyoTe+jIqWaVoPVg0/wrKpnL9W 8ClyNfTqN1yIYE1Ikr06o538bGcWiU3t4NEHFdw3hRtw+SNRIEMdBnFKpyZkvCStE2UU cAzA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=x4DDzWHFyDRlseI7znq+s9DyvjvZkarZQ2nXqeTK/2Q=; fh=bFDrUYhlTVi/QyetgXx/byg2+yO/22Hp9SjwoefyKLk=; b=M49Hz3J1RPZGYP4lbYnR9N/7PBzuOypBAxCJ3R+AsfCYMcosf1R7oXe3vWyuJTbTzh mwyA/n9wEWoy4nOMkEqkXb0BJ3OWYvKKHxGBZ4/v4xGvILmxdZvJFzFsRwAnJdBhC1QA cJLyNVhFOFfVzJJHaAY/lujQmU5ZjSQXZbd/hJhEeT27apvLik3uo0UQbJL01chFqIqc na1OUZ0iQrGrW2QHNqUASuBVQnJJgSPbLDmBgVnzufJp9cXgsRQv5I/3lvwhvTTkmahO /ZswHZWNEzBX8fwGBRX1TWDAH6ffvkaa6UPtH/DI7Wxj4hv4VsmO7VDOnBDrlL7Kxh/G jBVQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=at2qwn9C; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id s12-20020adfeccc000000b00317b5c8a4f1sm21844004wro.60.2023.08.24.02.28.53 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Aug 2023 02:28:53 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 32/35] target/arm/helper: Check SCR_EL3.{NSE, NS} encoding for AT instructions Date: Thu, 24 Aug 2023 10:28:33 +0100 Message-Id: <20230824092836.2239644-33-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230824092836.2239644-1-peter.maydell@linaro.org> References: <20230824092836.2239644-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Jean-Philippe Brucker The AT instruction is UNDEFINED if the {NSE,NS} configuration is invalid. Add a function to check this on all AT instructions that apply to an EL lower than 3. Suggested-by: Peter Maydell Signed-off-by: Jean-Philippe Brucker Message-id: 20230809123706.1842548-6-jean-philippe@linaro.org Signed-off-by: Peter Maydell Reviewed-by: Peter Maydell --- target/arm/helper.c | 38 +++++++++++++++++++++++++++----------- 1 file changed, 27 insertions(+), 11 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index de639d40871..b4618ee2b95 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3616,6 +3616,22 @@ static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri, #endif /* CONFIG_TCG */ } +static CPAccessResult at_e012_access(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + /* + * R_NYXTL: instruction is UNDEFINED if it applies to an Exception level + * lower than EL3 and the combination SCR_EL3.{NSE,NS} is reserved. This can + * only happen when executing at EL3 because that combination also causes an + * illegal exception return. We don't need to check FEAT_RME either, because + * scr_write() ensures that the NSE bit is not set otherwise. + */ + if ((env->cp15.scr_el3 & (SCR_NSE | SCR_NS)) == SCR_NSE) { + return CP_ACCESS_TRAP; + } + return CP_ACCESS_OK; +} + static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) { @@ -3623,7 +3639,7 @@ static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri, !(env->cp15.scr_el3 & (SCR_NS | SCR_EEL2))) { return CP_ACCESS_TRAP; } - return CP_ACCESS_OK; + return at_e012_access(env, ri, isread); } static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, @@ -5505,38 +5521,38 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0, .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .fgt = FGT_ATS1E1R, - .writefn = ats_write64 }, + .accessfn = at_e012_access, .writefn = ats_write64 }, { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 1, .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .fgt = FGT_ATS1E1W, - .writefn = ats_write64 }, + .accessfn = at_e012_access, .writefn = ats_write64 }, { .name = "AT_S1E0R", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 2, .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .fgt = FGT_ATS1E0R, - .writefn = ats_write64 }, + .accessfn = at_e012_access, .writefn = ats_write64 }, { .name = "AT_S1E0W", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3, .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .fgt = FGT_ATS1E0W, - .writefn = ats_write64 }, + .accessfn = at_e012_access, .writefn = ats_write64 }, { .name = "AT_S12E1R", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 4, .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, - .writefn = ats_write64 }, + .accessfn = at_e012_access, .writefn = ats_write64 }, { .name = "AT_S12E1W", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 5, .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, - .writefn = ats_write64 }, + .accessfn = at_e012_access, .writefn = ats_write64 }, { .name = "AT_S12E0R", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 6, .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, - .writefn = ats_write64 }, + .accessfn = at_e012_access, .writefn = ats_write64 }, { .name = "AT_S12E0W", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 7, .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, - .writefn = ats_write64 }, + .accessfn = at_e012_access, .writefn = ats_write64 }, /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */ { .name = "AT_S1E3R", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 0, @@ -8079,12 +8095,12 @@ static const ARMCPRegInfo ats1e1_reginfo[] = { .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 0, .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .fgt = FGT_ATS1E1RP, - .writefn = ats_write64 }, + .accessfn = at_e012_access, .writefn = ats_write64 }, { .name = "AT_S1E1WP", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 1, .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .fgt = FGT_ATS1E1WP, - .writefn = ats_write64 }, + .accessfn = at_e012_access, .writefn = ats_write64 }, }; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id s12-20020adfeccc000000b00317b5c8a4f1sm21844004wro.60.2023.08.24.02.28.53 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Aug 2023 02:28:53 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 33/35] target/arm/helper: Implement CNTHCTL_EL2.CNT[VP]MASK Date: Thu, 24 Aug 2023 10:28:34 +0100 Message-Id: <20230824092836.2239644-34-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230824092836.2239644-1-peter.maydell@linaro.org> References: <20230824092836.2239644-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Jean-Philippe Brucker When FEAT_RME is implemented, these bits override the value of CNT[VP]_CTL_EL0.IMASK in Realm and Root state. Move the IRQ state update into a new gt_update_irq() function and test those bits every time we recompute the IRQ state. Since we're removing the IRQ state from some trace events, add a new trace event for gt_update_irq(). Signed-off-by: Jean-Philippe Brucker Message-id: 20230809123706.1842548-7-jean-philippe@linaro.org [PMM: only register change hook if not USER_ONLY and if TCG] Signed-off-by: Peter Maydell Reviewed-by: Peter Maydell --- target/arm/cpu.h | 4 +++ target/arm/cpu.c | 6 ++++ target/arm/helper.c | 65 ++++++++++++++++++++++++++++++++++------- target/arm/trace-events | 7 +++-- 4 files changed, 68 insertions(+), 14 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 02bc8f0e8e0..cdf8600b96a 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1115,6 +1115,7 @@ struct ArchCPU { }; unsigned int gt_cntfrq_period_ns(ARMCPU *cpu); +void gt_rme_post_el_change(ARMCPU *cpu, void *opaque); void arm_cpu_post_init(Object *obj); @@ -1743,6 +1744,9 @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) #define HSTR_TTEE (1 << 16) #define HSTR_TJDBX (1 << 17) +#define CNTHCTL_CNTVMASK (1 << 18) +#define CNTHCTL_CNTPMASK (1 << 19) + /* Return the current FPSCR value. */ uint32_t vfp_get_fpscr(CPUARMState *env); void vfp_set_fpscr(CPUARMState *env, uint32_t val); diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 93c28d50e58..d906d2b1caa 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2169,6 +2169,12 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) set_feature(env, ARM_FEATURE_VBAR); } +#ifndef CONFIG_USER_ONLY + if (tcg_enabled() && cpu_isar_feature(aa64_rme, cpu)) { + arm_register_el_change_hook(cpu, >_rme_post_el_change, 0); + } +#endif + register_cp_regs_for_features(cpu); arm_cpu_register_gdb_regs_for_features(cpu); diff --git a/target/arm/helper.c b/target/arm/helper.c index b4618ee2b95..85291d5b8e2 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2608,6 +2608,39 @@ static uint64_t gt_get_countervalue(CPUARMState *env) return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / gt_cntfrq_period_ns(cpu); } +static void gt_update_irq(ARMCPU *cpu, int timeridx) +{ + CPUARMState *env = &cpu->env; + uint64_t cnthctl = env->cp15.cnthctl_el2; + ARMSecuritySpace ss = arm_security_space(env); + /* ISTATUS && !IMASK */ + int irqstate = (env->cp15.c14_timer[timeridx].ctl & 6) == 4; + + /* + * If bit CNTHCTL_EL2.CNT[VP]MASK is set, it overrides IMASK. + * It is RES0 in Secure and NonSecure state. + */ + if ((ss == ARMSS_Root || ss == ARMSS_Realm) && + ((timeridx == GTIMER_VIRT && (cnthctl & CNTHCTL_CNTVMASK)) || + (timeridx == GTIMER_PHYS && (cnthctl & CNTHCTL_CNTPMASK)))) { + irqstate = 0; + } + + qemu_set_irq(cpu->gt_timer_outputs[timeridx], irqstate); + trace_arm_gt_update_irq(timeridx, irqstate); +} + +void gt_rme_post_el_change(ARMCPU *cpu, void *ignored) +{ + /* + * Changing security state between Root and Secure/NonSecure, which may + * happen when switching EL, can change the effective value of CNTHCTL_EL2 + * mask bits. Update the IRQ state accordingly. + */ + gt_update_irq(cpu, GTIMER_VIRT); + gt_update_irq(cpu, GTIMER_PHYS); +} + static void gt_recalc_timer(ARMCPU *cpu, int timeridx) { ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx]; @@ -2623,13 +2656,9 @@ static void gt_recalc_timer(ARMCPU *cpu, int timeridx) /* Note that this must be unsigned 64 bit arithmetic: */ int istatus = count - offset >= gt->cval; uint64_t nexttick; - int irqstate; gt->ctl = deposit32(gt->ctl, 2, 1, istatus); - irqstate = (istatus && !(gt->ctl & 2)); - qemu_set_irq(cpu->gt_timer_outputs[timeridx], irqstate); - if (istatus) { /* Next transition is when count rolls back over to zero */ nexttick = UINT64_MAX; @@ -2648,14 +2677,14 @@ static void gt_recalc_timer(ARMCPU *cpu, int timeridx) } else { timer_mod(cpu->gt_timer[timeridx], nexttick); } - trace_arm_gt_recalc(timeridx, irqstate, nexttick); + trace_arm_gt_recalc(timeridx, nexttick); } else { /* Timer disabled: ISTATUS and timer output always clear */ gt->ctl &= ~4; - qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0); timer_del(cpu->gt_timer[timeridx]); trace_arm_gt_recalc_disabled(timeridx); } + gt_update_irq(cpu, timeridx); } static void gt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri, @@ -2759,10 +2788,8 @@ static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, * IMASK toggled: don't need to recalculate, * just set the interrupt line based on ISTATUS */ - int irqstate = (oldval & 4) && !(value & 2); - - trace_arm_gt_imask_toggle(timeridx, irqstate); - qemu_set_irq(cpu->gt_timer_outputs[timeridx], irqstate); + trace_arm_gt_imask_toggle(timeridx); + gt_update_irq(cpu, timeridx); } } @@ -2888,6 +2915,21 @@ static void gt_virt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, gt_ctl_write(env, ri, GTIMER_VIRT, value); } +static void gt_cnthctl_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + ARMCPU *cpu = env_archcpu(env); + uint32_t oldval = env->cp15.cnthctl_el2; + + raw_write(env, ri, value); + + if ((oldval ^ value) & CNTHCTL_CNTVMASK) { + gt_update_irq(cpu, GTIMER_VIRT); + } else if ((oldval ^ value) & CNTHCTL_CNTPMASK) { + gt_update_irq(cpu, GTIMER_PHYS); + } +} + static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -6203,7 +6245,8 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { * reset values as IMPDEF. We choose to reset to 3 to comply with * both ARMv7 and ARMv8. */ - .access = PL2_RW, .resetvalue = 3, + .access = PL2_RW, .type = ARM_CP_IO, .resetvalue = 3, + .writefn = gt_cnthctl_write, .raw_writefn = raw_write, .fieldoffset = offsetof(CPUARMState, cp15.cnthctl_el2) }, { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3, diff --git a/target/arm/trace-events b/target/arm/trace-events index 2a0ba7bffc1..48cc0512dbe 100644 --- a/target/arm/trace-events +++ b/target/arm/trace-events @@ -1,13 +1,14 @@ # See docs/devel/tracing.rst for syntax documentation. # helper.c -arm_gt_recalc(int timer, int irqstate, uint64_t nexttick) "gt recalc: timer %d irqstate %d next tick 0x%" PRIx64 -arm_gt_recalc_disabled(int timer) "gt recalc: timer %d irqstate 0 timer disabled" +arm_gt_recalc(int timer, uint64_t nexttick) "gt recalc: timer %d next tick 0x%" PRIx64 +arm_gt_recalc_disabled(int timer) "gt recalc: timer %d timer disabled" arm_gt_cval_write(int timer, uint64_t value) "gt_cval_write: timer %d value 0x%" PRIx64 arm_gt_tval_write(int timer, uint64_t value) "gt_tval_write: timer %d value 0x%" PRIx64 arm_gt_ctl_write(int timer, uint64_t value) "gt_ctl_write: timer %d value 0x%" PRIx64 -arm_gt_imask_toggle(int timer, int irqstate) "gt_ctl_write: timer %d IMASK toggle, new irqstate %d" +arm_gt_imask_toggle(int timer) "gt_ctl_write: timer %d IMASK toggle" arm_gt_cntvoff_write(uint64_t value) "gt_cntvoff_write: value 0x%" PRIx64 +arm_gt_update_irq(int timer, int irqstate) "gt_update_irq: timer %d irqstate %d" # kvm.c kvm_arm_fixup_msi_route(uint64_t iova, uint64_t gpa) "MSI iova = 0x%"PRIx64" is translated into 0x%"PRIx64 From patchwork Thu Aug 24 09:28:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 716539 Delivered-To: patch@linaro.org Received: by 2002:adf:f747:0:b0:317:ecd7:513f with SMTP id z7csp1237670wrp; Thu, 24 Aug 2023 02:34:43 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGlA6+CF+DYMjFDEyuxuoPi0Vcf6ghdplMh9UHvkq3udwn/9/gKXWZHhbDLi4thA6rlVJLZ X-Received: by 2002:a05:620a:2151:b0:76c:c101:fbf2 with SMTP id m17-20020a05620a215100b0076cc101fbf2mr15047562qkm.37.1692869682849; Thu, 24 Aug 2023 02:34:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1692869682; cv=none; d=google.com; s=arc-20160816; b=NLaN+KQdUD31tiZEDEYsUEBYeg4PrX/LDNWpQdn+FXduNbuuR/zLDKxPVJboY7I1z5 //3RukYKzbH5KqnF3I2gOfQkHugT6LvjafNytYnbabqkJwWugfmojGrhW3ZqZdWNm9Q9 OzCe0RqzLm79fVMDNsFkyuQB/oefNZoEyJ7jxFA33fm3aITQjw5x6guad0dR0LkjH15K SfSixhtIJyarSyZnTd5MVJlwcjNhQpnRUmI9nh6Nrs8eFPy5pbXIxMA2MKXOf6m+8bmc L0y80PE0Mt+s5jhHDi8MvKN0LyYF8AyypqQ7OYsczDbBtHmNASS6604e9owqz//CzfvR swMA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=jJcM1m2DqXyGCyWJeoR0m55Hp/YRlvKCbwqX7Yknn7U=; fh=bFDrUYhlTVi/QyetgXx/byg2+yO/22Hp9SjwoefyKLk=; b=N9nibOOfb+P0nlH/Lme0WyMK8ThuO/j8yUaBptsXroZHIeZZMEj8DEHNgSfzmlN5p7 xZWJi93X1cWtEWtIPxlPffCntBFi3sG68PQRFfqbQHgBzZkYqH2drCMtG2ROACp158WP aZiJjTkoarYwuAoN4GUiAEe2HaDKG3ych4bBBvd3xr8ymmSERe+kfwlmSSKdwx6O3dGz CnNeD3ssKzFdRA/NBXnRTy3d3221hHSueidMkTjK6roIadnjavA7jgndpftxhjHZKdU6 Ocl4BTYdW8uoXmNUyt6g6W4tB1A1Ar0pqACh2YVhN7PKHzvmrZroK8q+ecnGs6dLs2of na/g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=YwhzEcsM; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id s12-20020adfeccc000000b00317b5c8a4f1sm21844004wro.60.2023.08.24.02.28.54 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Aug 2023 02:28:54 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 34/35] target/arm: Fix SME ST1Q Date: Thu, 24 Aug 2023 10:28:35 +0100 Message-Id: <20230824092836.2239644-35-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230824092836.2239644-1-peter.maydell@linaro.org> References: <20230824092836.2239644-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson A typo, noted in the bug report, resulting in an incorrect write offset. Cc: qemu-stable@nongnu.org Fixes: 7390e0e9ab8 ("target/arm: Implement SME LD1, ST1") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1833 Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-id: 20230818214255.146905-1-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/sme_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/tcg/sme_helper.c b/target/arm/tcg/sme_helper.c index 1e67fcac308..296826ffe6a 100644 --- a/target/arm/tcg/sme_helper.c +++ b/target/arm/tcg/sme_helper.c @@ -379,7 +379,7 @@ static inline void HNAME##_host(void *za, intptr_t off, void *host) \ { \ uint64_t *ptr = za + off; \ HOST(host, ptr[BE]); \ - HOST(host + 1, ptr[!BE]); \ + HOST(host + 8, ptr[!BE]); \ } \ static inline void VNAME##_v_host(void *za, intptr_t off, void *host) \ { \ From patchwork Thu Aug 24 09:28:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 716514 Delivered-To: patch@linaro.org Received: by 2002:adf:f747:0:b0:317:ecd7:513f with SMTP id z7csp1236018wrp; Thu, 24 Aug 2023 02:29:57 -0700 (PDT) X-Google-Smtp-Source: AGHT+IE0sal2msXv6pIFmOAvE9h9SSxhvujnc3fX0U8C+VwwTKU76yGh8XYyhZzWj4WPqyIq+qnE X-Received: by 2002:a05:620a:17a6:b0:76e:e9b4:ff44 with SMTP id ay38-20020a05620a17a600b0076ee9b4ff44mr3546907qkb.67.1692869397301; Thu, 24 Aug 2023 02:29:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1692869397; cv=none; d=google.com; s=arc-20160816; b=UnRr61Wg9+QIOPiVHdgNmGWKPKTA3BSUduGLcrl1wGgMEgqFMBC6inX99aX1xZq14P ehAgIETDY0KDexungptGJeNHkp/V3T9ydmWVIfM2JemYkppLA+AI9m8pWI18dfJSaRJb R/i95MP3It13YfWW4BbRWPYXoEv3za5h6bXR1Lili8udWaQ8wnn0LdD6nT1Qn6PSfEAm 7/spOuSc0amdwn5KKj1H8aIXHB94WWaGioZXAiCbQIxjHvyOl5uT6SQIWgubDWPBwFRp mthbhKmyEpP4SHmiA7JpX6W8QKQTUBwiettAwRIjVlTTZKuUQy8enc+3sGReYhenDwa2 HWwg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Kf9yPg8uZfo9VqqhLVaMYdusDTk1ucSU7Tw3bTGKmGA=; fh=bFDrUYhlTVi/QyetgXx/byg2+yO/22Hp9SjwoefyKLk=; b=i3M5WDT/xe/QmGrTr6g5adA4EZiXeZlgj3s/vu2X5KSgWT335vttSr1+eO58bH+gEf gsQDm79ilQjFL2O2uJDJ/wiKeaiDaififE9DAq8pSPAoLYI6UPEua9S3uueUbYAIM0Up Or1yKbEG4pfm2nK0fq82R2AvBWLU5LhDw3oMRAuJQIj1QPamcoEs7K1QZq8vzQ8tZVKf p41iMPyNz43zttA74DxcqGRkvWfFO7qC6l40OrRm8RH/zyY4ewPaPKsV+q8vMyVEiVnu a++6hmd5cVX2sFxy0egwIS5naz0vvKnYajbp12VCTQh2/dBhnwHtf8VfawGolsyuVMzP kz0Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=uTn++Ink; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id s12-20020adfeccc000000b00317b5c8a4f1sm21844004wro.60.2023.08.24.02.28.54 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Aug 2023 02:28:54 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 35/35] target/arm: Fix 64-bit SSRA Date: Thu, 24 Aug 2023 10:28:36 +0100 Message-Id: <20230824092836.2239644-36-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230824092836.2239644-1-peter.maydell@linaro.org> References: <20230824092836.2239644-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson Typo applied byte-wise shift instead of double-word shift. Cc: qemu-stable@nongnu.org Fixes: 631e565450c ("target/arm: Create gen_gvec_[us]sra") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1737 Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-id: 20230821022025.397682-1-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index b71ac2d0d53..39541ecdf0a 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -3053,7 +3053,7 @@ void gen_gvec_ssra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, .vece = MO_32 }, { .fni8 = gen_ssra64_i64, .fniv = gen_ssra_vec, - .fno = gen_helper_gvec_ssra_b, + .fno = gen_helper_gvec_ssra_d, .prefer_i64 = TCG_TARGET_REG_BITS == 64, .opt_opc = vecop_list, .load_dest = true,