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Wysocki" , Huang Rui CC: , , , , Shuah Khan , , "Nathan Fontenot" , Deepak Sharma , Alex Deucher , Mario Limonciello , Shimmer Huang , "Perry Yuan" , Xiaojian Du , Viresh Kumar , Borislav Petkov , Meng Li Subject: [PATCH V4 3/7] cpufreq: amd-pstate: Enable AMD Pstate Preferred Core Supporting. Date: Tue, 29 Aug 2023 14:43:36 +0800 Message-ID: <20230829064340.1136448-4-li.meng@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230829064340.1136448-1-li.meng@amd.com> References: <20230829064340.1136448-1-li.meng@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044F5:EE_|SN7PR12MB7934:EE_ X-MS-Office365-Filtering-Correlation-Id: 2f7ee472-09bf-48bc-2cc6-08dba85b625c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: LGOTgxz8fmiMCNelQQlICo1rXMrD4kcf07/3Pxs/1cbWY+68nwD5QFGSlAWb5XACD6ff6T+b/QSplk5MUQQcthoxT3YLdimxMzN2vqu2GEtGcCEC8cRNhPBFyLpiUxQNHkmapkgrUpQqbGWmhqIdlq/6aiIsI7PTaFGHXs+OK5Bo6VYCPK8pULzpNDDS1MnuVk/8Y5F6fcJCp1XikfUpbL8hc6Ta64OgU9B8vGsoj/zmJrGi3Njdygj4gnrG1Bfab5igTqdHt6wSNyALl9oD+73SAhOiQO8Gm7s9PH3Vg4xInppI37Ul5f1LxAHiu0WcewPFGX7mTm+//iq2Zjsi/o/5SSmfIaTubMWwLq9EUIHRzc8meZf6Nm45fe8fMwqNBrQoyt//vWToL5jhCXoE837jXl8ekzOXjR4kqnmw9wtjERkl47UJdnF6kYNrexzNZphr7Ed7fYOy8uqyj+DALTE3pc8zeVCjNowLg8qmv54Bqlcg/wWrJ7jkbw+fr4JWrG3zthiOqrEu8O1Vp93ZFdwAWqdPPLl8l3RYabJw6o+B+1m8nV8P57eZPIMQnLlyFa7UmR4RLH7Pn3VhaOH1+xI6DifF1uFB5JFmB2fd2lOhvPYHDwIS7edamO9j0fvdHlgT5o1en1l5eqjOdj8QXzijAv3uUudmSARiWKlvSFSdBZ7VTqMXIQtItKef5mzPsQBYdAYp1bt26pJFUnv6QUhOyRrItKatieBYL5zDz/sBdwcRevhBktrsYiN9ZlTOm9vGaW9YqpNcC6rehyBrcg== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230031)(4636009)(136003)(396003)(346002)(376002)(39860400002)(1800799009)(82310400011)(186009)(451199024)(36840700001)(46966006)(40470700004)(478600001)(83380400001)(356005)(81166007)(82740400003)(26005)(16526019)(336012)(426003)(47076005)(36860700001)(1076003)(2616005)(40480700001)(7696005)(110136005)(6666004)(86362001)(6636002)(2906002)(316002)(8676002)(4326008)(5660300002)(70206006)(41300700001)(8936002)(36756003)(54906003)(70586007)(40460700003)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Aug 2023 06:44:24.7349 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2f7ee472-09bf-48bc-2cc6-08dba85b625c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044F5.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7934 Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org AMD Pstate driver utilizes the functions and data structures provided by the ITMT architecture to enable the scheduler to favor scheduling on cores which can be get a higher frequency with lower voltage. We call it AMD Pstate Preferrred Core. Here sched_set_itmt_core_prio() is called to set priorities and sched_set_itmt_support() is called to enable ITMT feature. AMD Pstate driver uses the highest performance value to indicate the priority of CPU. The higher value has a higher priority. The initial core rankings are set up by AMD Pstate when the system boots. Add device attribute for preferred core states. Add one new early parameter `enable` to allow user to enable the preferred core if the processor and power firmware can support preferred core feature. Signed-off-by: Perry Yuan Co-developed-by: Perry Yuan Signed-off-by: Meng Li Co-developed-by: Meng Li Reviewed-by: Mario Limonciello --- drivers/cpufreq/amd-pstate.c | 120 ++++++++++++++++++++++++++++++----- 1 file changed, 104 insertions(+), 16 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 9a1e194d5cf8..d02305675f66 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -37,6 +37,7 @@ #include #include #include +#include #include #include @@ -49,6 +50,8 @@ #define AMD_PSTATE_TRANSITION_LATENCY 20000 #define AMD_PSTATE_TRANSITION_DELAY 1000 +#define AMD_PSTATE_PREFCORE_THRESHOLD 166 +#define AMD_PSTATE_MAX_CPPC_PERF 255 /* * TODO: We need more time to fine tune processors with shared memory solution @@ -65,6 +68,9 @@ static struct cpufreq_driver amd_pstate_epp_driver; static int cppc_state = AMD_PSTATE_UNDEFINED; static bool cppc_enabled; +/*Preferred Core featue is supported*/ +static bool prefcore = true; + /* * AMD Energy Preference Performance (EPP) * The EPP is used in the CCLK DPM controller to drive @@ -290,23 +296,21 @@ static inline int amd_pstate_enable(bool enable) static int pstate_init_perf(struct amd_cpudata *cpudata) { u64 cap1; - u32 highest_perf; int ret = rdmsrl_safe_on_cpu(cpudata->cpu, MSR_AMD_CPPC_CAP1, &cap1); if (ret) return ret; - /* - * TODO: Introduce AMD specific power feature. - * - * CPPC entry doesn't indicate the highest performance in some ASICs. + /* For platforms that do not support the preferred core feature, the + * highest_pef may be configured with 166 or 255, to avoid max frequency + * calculated wrongly. we take the AMD_CPPC_HIGHEST_PERF(cap1) value as + * the default max perf. */ - highest_perf = amd_get_highest_perf(); - if (highest_perf > AMD_CPPC_HIGHEST_PERF(cap1)) - highest_perf = AMD_CPPC_HIGHEST_PERF(cap1); - - WRITE_ONCE(cpudata->highest_perf, highest_perf); + if (prefcore) + WRITE_ONCE(cpudata->highest_perf, AMD_PSTATE_PREFCORE_THRESHOLD); + else + WRITE_ONCE(cpudata->highest_perf, AMD_CPPC_HIGHEST_PERF(cap1)); WRITE_ONCE(cpudata->nominal_perf, AMD_CPPC_NOMINAL_PERF(cap1)); WRITE_ONCE(cpudata->lowest_nonlinear_perf, AMD_CPPC_LOWNONLIN_PERF(cap1)); @@ -318,17 +322,15 @@ static int pstate_init_perf(struct amd_cpudata *cpudata) static int cppc_init_perf(struct amd_cpudata *cpudata) { struct cppc_perf_caps cppc_perf; - u32 highest_perf; int ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf); if (ret) return ret; - highest_perf = amd_get_highest_perf(); - if (highest_perf > cppc_perf.highest_perf) - highest_perf = cppc_perf.highest_perf; - - WRITE_ONCE(cpudata->highest_perf, highest_perf); + if (prefcore) + WRITE_ONCE(cpudata->highest_perf, AMD_PSTATE_PREFCORE_THRESHOLD); + else + WRITE_ONCE(cpudata->highest_perf, cppc_perf.highest_perf); WRITE_ONCE(cpudata->nominal_perf, cppc_perf.nominal_perf); WRITE_ONCE(cpudata->lowest_nonlinear_perf, @@ -676,6 +678,72 @@ static void amd_perf_ctl_reset(unsigned int cpu) wrmsrl_on_cpu(cpu, MSR_AMD_PERF_CTL, 0); } +/* + * Set AMD Pstate Preferred Core enable can't be done directly from cpufreq callbacks + * due to locking, so queue the work for later. + */ +static void amd_pstste_sched_prefcore_workfn(struct work_struct *work) +{ + sched_set_itmt_support(); +} +static DECLARE_WORK(sched_prefcore_work, amd_pstste_sched_prefcore_workfn); + +/** + * Get the highest performance register value. + * @cpu: CPU from which to get highest performance. + * @highest_perf: Return address. + * + * Return: 0 for success, -EIO otherwise. + */ +static int amd_pstate_get_highest_perf(int cpu, u64 *highest_perf) +{ + int ret; + + if (boot_cpu_has(X86_FEATURE_CPPC)) { + u64 cap1; + + ret = rdmsrl_safe_on_cpu(cpu, MSR_AMD_CPPC_CAP1, &cap1); + if (ret) + return ret; + WRITE_ONCE(*highest_perf, AMD_CPPC_HIGHEST_PERF(cap1)); + } else { + ret = cppc_get_highest_perf(cpu, highest_perf); + } + + return (ret); +} + +static void amd_pstate_init_prefcore(void) +{ + int cpu, ret; + u64 highest_perf; + + if (!prefcore) + return; + + for_each_online_cpu(cpu) { + ret = amd_pstate_get_highest_perf(cpu, &highest_perf); + if (ret) + break; + + sched_set_itmt_core_prio(highest_perf, cpu); + + /* check if CPPC preferred core feature is enabled*/ + if (highest_perf == AMD_PSTATE_MAX_CPPC_PERF) { + prefcore = false; + return; + } + } + + /* + * This code can be run during CPU online under the + * CPU hotplug locks, so sched_set_amd_prefcore_support() + * cannot be called from here. Queue up a work item + * to invoke it. + */ + schedule_work(&sched_prefcore_work); +} + static int amd_pstate_cpu_init(struct cpufreq_policy *policy) { int min_freq, max_freq, nominal_freq, lowest_nonlinear_freq, ret; @@ -1037,6 +1105,12 @@ static ssize_t status_store(struct device *a, struct device_attribute *b, return ret < 0 ? ret : count; } +static ssize_t prefcore_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return sysfs_emit(buf, "%s\n", prefcore ? "enabled" : "disabled"); +} + cpufreq_freq_attr_ro(amd_pstate_max_freq); cpufreq_freq_attr_ro(amd_pstate_lowest_nonlinear_freq); @@ -1044,6 +1118,7 @@ cpufreq_freq_attr_ro(amd_pstate_highest_perf); cpufreq_freq_attr_rw(energy_performance_preference); cpufreq_freq_attr_ro(energy_performance_available_preferences); static DEVICE_ATTR_RW(status); +static DEVICE_ATTR_RO(prefcore); static struct freq_attr *amd_pstate_attr[] = { &amd_pstate_max_freq, @@ -1063,6 +1138,7 @@ static struct freq_attr *amd_pstate_epp_attr[] = { static struct attribute *pstate_global_attributes[] = { &dev_attr_status.attr, + &dev_attr_prefcore.attr, NULL }; @@ -1506,6 +1582,8 @@ static int __init amd_pstate_init(void) } } + amd_pstate_init_prefcore(); + return ret; global_attr_free: @@ -1527,7 +1605,17 @@ static int __init amd_pstate_param(char *str) return amd_pstate_set_driver(mode_idx); } + +static int __init amd_prefcore_param(char *str) +{ + if (!strcmp(str, "disable")) + prefcore = false; + + return 0; +} + early_param("amd_pstate", amd_pstate_param); +early_param("amd_prefcore", amd_prefcore_param); MODULE_AUTHOR("Huang Rui "); MODULE_DESCRIPTION("AMD Processor P-state Frequency Driver"); From patchwork Tue Aug 29 06:43:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Meng, Li \(Jassmine\)" X-Patchwork-Id: 718329 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7501DC83F1F for ; Tue, 29 Aug 2023 06:45:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233484AbjH2Gos (ORCPT ); Tue, 29 Aug 2023 02:44:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48914 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232785AbjH2Gog (ORCPT ); Tue, 29 Aug 2023 02:44:36 -0400 Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2045.outbound.protection.outlook.com [40.107.93.45]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EE54D19A; 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Wysocki" , Huang Rui CC: , , , , Shuah Khan , , "Nathan Fontenot" , Deepak Sharma , Alex Deucher , Mario Limonciello , Shimmer Huang , "Perry Yuan" , Xiaojian Du , Viresh Kumar , Borislav Petkov , Meng Li Subject: [PATCH V4 4/7] cpufreq: Add a notification message that the highest perf has changed Date: Tue, 29 Aug 2023 14:43:37 +0800 Message-ID: <20230829064340.1136448-5-li.meng@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230829064340.1136448-1-li.meng@amd.com> References: <20230829064340.1136448-1-li.meng@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044F5:EE_|LV3PR12MB9401:EE_ X-MS-Office365-Filtering-Correlation-Id: 9068fe20-67d6-4d2a-9a0b-08dba85b64d1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Kp4MfXwW5EySTHbAYcaJ8OLt7P3kmCgT/fo5JLvcns4p61mUs8tr3s3aHGbK89AH85bKntk1Y4kbKcclQABaTaS+/3Yw/oJ2Yw82hEsPWPAZHAxpw3Jdy0cjgdhxuI2gWF1Yc19Mv2G6HrFRS+gh9AQlAAh4pOWmpMJxTiPl1x7OtAZDhLJVsJtDuO5PxV2qAypD3h4cxJySW9w7f3fObIzvwSpMpJyM1xY3J0Q0/yS3fe12uvFqlN6Cq/JvyFn6qCEDTfIhD1UR9geM4CmJrJ2w/gFszyRG4RNDOcdX/pl1rlWWp2HAxwSs+DRl5HsvHYpvqZ19uU7A1a0TUbaYxhwebCu+uUGNka3sziQGw7fAIXvMnRGiXVFmnWY2b7HrK9jciEq19cjrDAyNZAj2cibCIgW5CleJLqWlZOffC0ILERAln3HdZcJYusDpi9PnQu7lt2heur5UjcBndoYQujUsbR4P+rB0cDfzhwGAii5v6iVqujDlqDNSOzza3OgEK2qjmngPbDtLr878kn4yVkd9wYGszUZ1K8EKCL4pI7309bCbmN3b/cQbdqmQEjwlXsGpluoqZ43v2vpqE2Rij/fyP2JOYkVcn0Asgkgi91iWA5JF1lsgjSXU139Vqq2O22U1IovwG5MVyD45boYTBV0sOTmgIXt7tirCBK/b1wsXS1+YAmwDt1F3KOH/jxH+TjCvSmtgPRzfeNfPpgLgIzb48rAy/Pkn4FKkN4vhbWEC9lh56MdzXMiW4gpVXVDIu+A5H0AhOq/EZa5E6f+dsDr/hxM/JBkQutInF6tHnMc= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230031)(4636009)(376002)(396003)(346002)(136003)(39860400002)(186009)(1800799009)(451199024)(82310400011)(40470700004)(36840700001)(46966006)(82740400003)(7696005)(70206006)(110136005)(6666004)(40480700001)(40460700003)(36756003)(86362001)(47076005)(81166007)(356005)(36860700001)(1076003)(2616005)(2906002)(336012)(426003)(16526019)(15650500001)(83380400001)(26005)(478600001)(70586007)(4326008)(5660300002)(966005)(8936002)(54906003)(41300700001)(6636002)(316002)(8676002)(226483002)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Aug 2023 06:44:28.8130 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9068fe20-67d6-4d2a-9a0b-08dba85b64d1 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044F5.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV3PR12MB9401 Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org ACPI 6.5 section 8.4.6.1.1.1 specifies that Notify event 0x85 can be emmitted to cause the the OSPM to re-evaluate the highest performance register. Add support for this event. Signed-off-by: Meng Li Link: https://uefi.org/specs/ACPI/6.5/08_Processor_Configuration_and_Control.html?highlight=cppc#cpc-continuous-performance-control --- drivers/acpi/processor_driver.c | 6 ++++++ drivers/cpufreq/cpufreq.c | 13 +++++++++++++ include/linux/cpufreq.h | 4 ++++ 3 files changed, 23 insertions(+) diff --git a/drivers/acpi/processor_driver.c b/drivers/acpi/processor_driver.c index 4bd16b3f0781..29b2fb68a35d 100644 --- a/drivers/acpi/processor_driver.c +++ b/drivers/acpi/processor_driver.c @@ -27,6 +27,7 @@ #define ACPI_PROCESSOR_NOTIFY_PERFORMANCE 0x80 #define ACPI_PROCESSOR_NOTIFY_POWER 0x81 #define ACPI_PROCESSOR_NOTIFY_THROTTLING 0x82 +#define ACPI_PROCESSOR_NOTIFY_HIGEST_PERF_CHANGED 0x85 MODULE_AUTHOR("Paul Diefenbaugh"); MODULE_DESCRIPTION("ACPI Processor Driver"); @@ -83,6 +84,11 @@ static void acpi_processor_notify(acpi_handle handle, u32 event, void *data) acpi_bus_generate_netlink_event(device->pnp.device_class, dev_name(&device->dev), event, 0); break; + case ACPI_PROCESSOR_NOTIFY_HIGEST_PERF_CHANGED: + cpufreq_update_highest_perf(pr->id); + acpi_bus_generate_netlink_event(device->pnp.device_class, + dev_name(&device->dev), event, 0); + break; default: acpi_handle_debug(handle, "Unsupported event [0x%x]\n", event); break; diff --git a/drivers/cpufreq/cpufreq.c b/drivers/cpufreq/cpufreq.c index 50bbc969ffe5..842357abfae6 100644 --- a/drivers/cpufreq/cpufreq.c +++ b/drivers/cpufreq/cpufreq.c @@ -2675,6 +2675,19 @@ void cpufreq_update_limits(unsigned int cpu) } EXPORT_SYMBOL_GPL(cpufreq_update_limits); +/** + * cpufreq_update_highest_perf - Update highest performance for a given CPU. + * @cpu: CPU to update the highest performance for. + * + * Invoke the driver's ->update_highest_perf callback if present + */ +void cpufreq_update_highest_perf(unsigned int cpu) +{ + if (cpufreq_driver->update_highest_perf) + cpufreq_driver->update_highest_perf(cpu); +} +EXPORT_SYMBOL_GPL(cpufreq_update_highest_perf); + /********************************************************************* * BOOST * *********************************************************************/ diff --git a/include/linux/cpufreq.h b/include/linux/cpufreq.h index 9bf94ae08158..58106b3d9183 100644 --- a/include/linux/cpufreq.h +++ b/include/linux/cpufreq.h @@ -232,6 +232,7 @@ int cpufreq_get_policy(struct cpufreq_policy *policy, unsigned int cpu); void refresh_frequency_limits(struct cpufreq_policy *policy); void cpufreq_update_policy(unsigned int cpu); void cpufreq_update_limits(unsigned int cpu); +void cpufreq_update_highest_perf(unsigned int cpu); bool have_governor_per_policy(void); bool cpufreq_supports_freq_invariance(void); struct kobject *get_governor_parent_kobj(struct cpufreq_policy *policy); @@ -377,6 +378,9 @@ struct cpufreq_driver { /* Called to update policy limits on firmware notifications. */ void (*update_limits)(unsigned int cpu); + /* Called to update highest performance on firmware notifications. */ + void (*update_highest_perf)(unsigned int cpu); + /* optional */ int (*bios_limit)(int cpu, unsigned int *limit); From patchwork Tue Aug 29 06:43:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Meng, Li \(Jassmine\)" X-Patchwork-Id: 718327 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8FE83C83F17 for ; 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Wysocki" , Huang Rui CC: , , , , Shuah Khan , , "Nathan Fontenot" , Deepak Sharma , Alex Deucher , Mario Limonciello , Shimmer Huang , "Perry Yuan" , Xiaojian Du , Viresh Kumar , Borislav Petkov , Meng Li Subject: [PATCH V4 6/7] Documentation: amd-pstate: introduce AMD Pstate Preferred Core Date: Tue, 29 Aug 2023 14:43:39 +0800 Message-ID: <20230829064340.1136448-7-li.meng@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230829064340.1136448-1-li.meng@amd.com> References: <20230829064340.1136448-1-li.meng@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044F2:EE_|IA1PR12MB6331:EE_ X-MS-Office365-Filtering-Correlation-Id: da167f23-97c8-4002-1e91-08dba85b7105 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: fDpil3JS0UL4C8MxXHbgm647nKXM89A53zWAmMd/mbryS2QvKVWGGXqJFy4hcgmcgWTTvlbv8XmU/uYRipO6Xs9WGlqfL71VrXJ8XAtLDMXrHxdd+foZnBgLh2On6I+YEVF0q1AuJbV8pBi+p5EYg5XOHjG7VTTx5F6lwJKmtzcM1G+7F3/0hjdX6JDCr6TxvQpGW6NULnrFYDtDLQWzN7nLM8SO8SU212o4QefT6ilb15kvemRScI8PcM5zsEk2JVoDfZjgg3HcOosDcXKwm0pwaFDgMUMRHQ5hzJZ1gfw9vgMee20/sJRuYW+O2j6HXLA3776MBUs5bilpctQEYa9/WOoiaVtPu/SXLs68vpd/MpPl7+ej1WAkBE1EMLznhSifpuqRedRZouU7XTeMpjZ/vJF/pEA0ktSUDXCqMjxQJMbgtmvRUqP7+jKeAUNEKMARtnAGt6O9xzT5pPmrBqsf1TabipD/iTscX3cu4H1NUA0i5GhyFSKILU5hfKgGp6fAXuP+yPN7obBvBsiVzw3iLnTTwy1X7ajrd1FKfbIWTxupLQNRizWCVOhxdk6d0DzxdwwbGbJNwtRX6EHemEHW2FophcUfU3ZxYEU8mLZMHCHqcxijWxJle2tOG22pE+nFz4RrxeBj73sdDDHy0zmqF7oysM19+9y2IF8PhVAX2dDhKaO1a1B9+g1++ryYyGmfK5gY3I5VLuzx8UmM7F0zrCf5EFzdt9tijkuk1r/GlxL0pJGB46ZQQI8e0EC9P695YMLcGlO0f86I93vC4g== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230031)(4636009)(136003)(376002)(396003)(346002)(39860400002)(451199024)(1800799009)(186009)(82310400011)(36840700001)(40470700004)(46966006)(356005)(81166007)(82740400003)(8936002)(6666004)(110136005)(70206006)(70586007)(478600001)(7696005)(54906003)(6636002)(316002)(41300700001)(40460700003)(36756003)(26005)(16526019)(8676002)(1076003)(5660300002)(83380400001)(2906002)(2616005)(86362001)(47076005)(36860700001)(40480700001)(426003)(336012)(4326008)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Aug 2023 06:44:49.2989 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: da167f23-97c8-4002-1e91-08dba85b7105 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044F2.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6331 Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org Introduce AMD Pstate Preferred Core. check preferred core state: $ cat /sys/devices/system/cpu/amd-pstate/prefcore Signed-off-by: Meng Li --- Documentation/admin-guide/pm/amd-pstate.rst | 54 +++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/Documentation/admin-guide/pm/amd-pstate.rst b/Documentation/admin-guide/pm/amd-pstate.rst index 1cf40f69278c..400264d52007 100644 --- a/Documentation/admin-guide/pm/amd-pstate.rst +++ b/Documentation/admin-guide/pm/amd-pstate.rst @@ -353,6 +353,48 @@ is activated. In this mode, driver requests minimum and maximum performance level and the platform autonomously selects a performance level in this range and appropriate to the current workload. +AMD Pstate Preferred Core +================================= + +The core frequency is subjected to the process variation in semiconductors. +Not all cores are able to reach the maximum frequency respecting the +infrastructure limits. Consequently, AMD has redefined the concept of +maximum frequency of a part. This means that a fraction of cores can reach +maximum frequency. To find the best process scheduling policy for a given +scenario, OS needs to know the core ordering informed by the platform through +highest performance capability register of the CPPC interface. + +``AMD Pstate Preferred Core`` enables the scheduler to prefer scheduling on +cores that can achieve a higher frequency with lower voltage. The preferred +core rankings can dynamically change based on the workload, platform conditions, +thermals and ageing. + +The priority metric will be initialized by the AMD Pstate driver. The AMD Pstate +driver will also determine whether or not ``AMD Pstate Preferred Core`` is +supported by the platform. + +AMD Pstate driver will provide an initial core ordering when the system boots. +The platform uses the CPPC interfaces to communicate the core ranking to the +operating system and scheduler to make sure that OS is choosing the cores +with highest performance firstly for scheduling the process. When AMD Pstate +driver receives a message with the highest performance change, it will +update the core ranking and set the cpu's priority. + +AMD Preferred Core Switch +================================= +Kernel Parameters +----------------- + +``AMD Pstate Preferred Core`` has two states: enable and disable. +Enable/disable states can be chosen by different kernel parameters. +Default enable ``AMD Pstate Preferred Core``. + +``amd_prefcore=disable`` + +for systems that support ``AMD Pstate Preferred Core``, the core rankings will +always be advertised by the platform. But OS can choose to ignore that via the +kernel parameter ``amd_prefcore=disable``. + User Space Interface in ``sysfs`` - General =========================================== @@ -385,6 +427,18 @@ control its functionality at the system level. They are located in the to the operation mode represented by that string - or to be unregistered in the "disable" case. +``prefcore`` + Preferred Core state of the driver: "enabled" or "disabled". + + "enabled" + Enable the AMD Preferred Core. + + "disabled" + Disable the AMD Preferred Core + + + This attribute is read-only to check the state of Preferred Core. + ``cpupower`` tool support for ``amd-pstate`` ===============================================