From patchwork Mon Sep 4 02:04:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 720028 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D0B35CA0FE3 for ; Mon, 4 Sep 2023 02:05:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350530AbjIDCFD (ORCPT ); Sun, 3 Sep 2023 22:05:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35524 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350360AbjIDCFC (ORCPT ); Sun, 3 Sep 2023 22:05:02 -0400 Received: from mail-lj1-x234.google.com (mail-lj1-x234.google.com [IPv6:2a00:1450:4864:20::234]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 845E810A for ; Sun, 3 Sep 2023 19:04:58 -0700 (PDT) Received: by mail-lj1-x234.google.com with SMTP id 38308e7fff4ca-2bcc4347d2dso12733611fa.0 for ; Sun, 03 Sep 2023 19:04:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1693793096; x=1694397896; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VHLsmawO8YJUbD7foYhvrS8ZuNZpxIJ9tps5XjxyA5M=; b=o4VCPj5YHi86+i+DCU+i99vF1sgdu4n3ZT5RtKPXCS2FLsQ6o5pcwRRtCX2MA2faX7 YGlTDQeg/mwac2V+60L7mZzrnfdfjSuPLL7rzhohWVC07wqeFZEzOBO2rMUxmMeY4xEQ bQv1jVJSsuIsN7vps/24SlLWpo0CAUMHPVvxuVF30SFLfHYNpvn02+du/CvYaOr4UYXW x7+Rcwxx1Tjb+5RGMXJIDS6wQDitxtO5PxEGgnFV60lCCV/xpIbVKXawHYkRSp7nwfNm wSE4BQlCRQ91eUSyHHN9BWrHg2ScA2zV9TUauzlpP/u+7ZBsmQcSZEj8rcXS1nO4/kTc 1noA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693793096; x=1694397896; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VHLsmawO8YJUbD7foYhvrS8ZuNZpxIJ9tps5XjxyA5M=; b=GY3wyzx1lDj9yWQL16U9ybSUZmjzJxPD5onxVXc+VV2H+D7tPySFB76GOAMCYDR9jg /D5QB9/24V5BQKWY4UHKgKxcI8uOvcY/gNGxb7syOMxiV6uJsXc/ptmkx2NgdypsJ27v 3aTPNZFHw0UUGG8zUQO1LcbsmqAulFNiFnEIBtCRbP4b/tu+ETehj1cQHFI1AMUIOUm3 etDihBJdVAqlwpWrAEC3GH5gh9muHjxfeDQFY5uugghObCbipoRg1HmJjVX7rcAJpYo0 mym049hG1nDJkUfNBMbiCWDRjtlYmMI7c+mrl1lf017R1t+BuNwtHk46uid3dnoQD5Aw n+8w== X-Gm-Message-State: AOJu0Yx3wlV6y9U6vLDW/Y3UTQnljqAh/dzFwkdr09H8K4KE7YAKCvls xyajsV86uwkxBvaQYxCyIEYYRg== X-Google-Smtp-Source: AGHT+IE+2Yfq4u0kqraestEWo6xIjCVBQAPimXZVSpTk8IG0P/wMEfJmC/oNd+wc9c9gApNKbSJjTg== X-Received: by 2002:a2e:888f:0:b0:2b6:de52:357 with SMTP id k15-20020a2e888f000000b002b6de520357mr6156564lji.40.1693793095982; Sun, 03 Sep 2023 19:04:55 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id t13-20020a2e9c4d000000b002bce0e9385asm1818237ljj.9.2023.09.03.19.04.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Sep 2023 19:04:55 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar , Marijn Suijten Cc: Stephen Boyd , David Airlie , Daniel Vetter , Bjorn Andersson , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH v3 1/8] drm/msm/dpu: inline _setup_pingpong_ops() Date: Mon, 4 Sep 2023 05:04:47 +0300 Message-Id: <20230904020454.2945667-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230904020454.2945667-1-dmitry.baryshkov@linaro.org> References: <20230904020454.2945667-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Inline the _setup_pingpong_ops() function, it makes it easier to handle different conditions involving PINGPONG configuration. Reviewed-by: Marijn Suijten Signed-off-by: Dmitry Baryshkov Reviewed-by: Stephen Boyd --- .../gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c | 39 ++++++++----------- 1 file changed, 17 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c index 437d9e62a841..9298c166b213 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c @@ -281,27 +281,6 @@ static int dpu_hw_pp_setup_dsc(struct dpu_hw_pingpong *pp) return 0; } -static void _setup_pingpong_ops(struct dpu_hw_pingpong *c, - unsigned long features) -{ - if (test_bit(DPU_PINGPONG_TE, &features)) { - c->ops.enable_tearcheck = dpu_hw_pp_enable_te; - c->ops.disable_tearcheck = dpu_hw_pp_disable_te; - c->ops.connect_external_te = dpu_hw_pp_connect_external_te; - c->ops.get_line_count = dpu_hw_pp_get_line_count; - c->ops.disable_autorefresh = dpu_hw_pp_disable_autorefresh; - } - - if (test_bit(DPU_PINGPONG_DSC, &features)) { - c->ops.setup_dsc = dpu_hw_pp_setup_dsc; - c->ops.enable_dsc = dpu_hw_pp_dsc_enable; - c->ops.disable_dsc = dpu_hw_pp_dsc_disable; - } - - if (test_bit(DPU_PINGPONG_DITHER, &features)) - c->ops.setup_dither = dpu_hw_pp_setup_dither; -}; - struct dpu_hw_pingpong *dpu_hw_pingpong_init(const struct dpu_pingpong_cfg *cfg, void __iomem *addr) { @@ -316,7 +295,23 @@ struct dpu_hw_pingpong *dpu_hw_pingpong_init(const struct dpu_pingpong_cfg *cfg, c->idx = cfg->id; c->caps = cfg; - _setup_pingpong_ops(c, c->caps->features); + + if (test_bit(DPU_PINGPONG_TE, &cfg->features)) { + c->ops.enable_tearcheck = dpu_hw_pp_enable_te; + c->ops.disable_tearcheck = dpu_hw_pp_disable_te; + c->ops.connect_external_te = dpu_hw_pp_connect_external_te; + c->ops.get_line_count = dpu_hw_pp_get_line_count; + c->ops.disable_autorefresh = dpu_hw_pp_disable_autorefresh; + } + + if (test_bit(DPU_PINGPONG_DSC, &cfg->features)) { + c->ops.setup_dsc = dpu_hw_pp_setup_dsc; + c->ops.enable_dsc = dpu_hw_pp_dsc_enable; + c->ops.disable_dsc = dpu_hw_pp_dsc_disable; + } + + if (test_bit(DPU_PINGPONG_DITHER, &cfg->features)) + c->ops.setup_dither = dpu_hw_pp_setup_dither; return c; } From patchwork Mon Sep 4 02:04:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 720029 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BF5B8C83F2D for ; Mon, 4 Sep 2023 02:05:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240586AbjIDCFC (ORCPT ); Sun, 3 Sep 2023 22:05:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33102 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350357AbjIDCFC (ORCPT ); Sun, 3 Sep 2023 22:05:02 -0400 Received: from mail-lj1-x233.google.com (mail-lj1-x233.google.com [IPv6:2a00:1450:4864:20::233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5BDE3106 for ; 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Rather than checking for the flag, check for the presense of the corresponding interrupt line. Reviewed-by: Marijn Suijten Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c | 6 ++++-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h | 3 ++- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 2 +- 3 files changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c index 9298c166b213..057cac7f5d93 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c @@ -282,7 +282,7 @@ static int dpu_hw_pp_setup_dsc(struct dpu_hw_pingpong *pp) } struct dpu_hw_pingpong *dpu_hw_pingpong_init(const struct dpu_pingpong_cfg *cfg, - void __iomem *addr) + void __iomem *addr, const struct dpu_mdss_version *mdss_rev) { struct dpu_hw_pingpong *c; @@ -296,7 +296,9 @@ struct dpu_hw_pingpong *dpu_hw_pingpong_init(const struct dpu_pingpong_cfg *cfg, c->idx = cfg->id; c->caps = cfg; - if (test_bit(DPU_PINGPONG_TE, &cfg->features)) { + if (mdss_rev->core_major_ver < 5) { + WARN_ON(!cfg->intr_rdptr); + c->ops.enable_tearcheck = dpu_hw_pp_enable_te; c->ops.disable_tearcheck = dpu_hw_pp_disable_te; c->ops.connect_external_te = dpu_hw_pp_connect_external_te; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h index d3246a9a5808..0d541ca5b056 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h @@ -123,10 +123,11 @@ static inline struct dpu_hw_pingpong *to_dpu_hw_pingpong(struct dpu_hw_blk *hw) * pingpong catalog entry. * @cfg: Pingpong catalog entry for which driver object is required * @addr: Mapped register io address of MDP + * @mdss_rev: dpu core's major and minor versions * Return: Error code or allocated dpu_hw_pingpong context */ struct dpu_hw_pingpong *dpu_hw_pingpong_init(const struct dpu_pingpong_cfg *cfg, - void __iomem *addr); + void __iomem *addr, const struct dpu_mdss_version *mdss_rev); /** * dpu_hw_pingpong_destroy - destroys pingpong driver context diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c index f9215643c71a..f3aff605554d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c @@ -146,7 +146,7 @@ int dpu_rm_init(struct dpu_rm *rm, struct dpu_hw_pingpong *hw; const struct dpu_pingpong_cfg *pp = &cat->pingpong[i]; - hw = dpu_hw_pingpong_init(pp, mmio); + hw = dpu_hw_pingpong_init(pp, mmio, cat->mdss_ver); if (IS_ERR(hw)) { rc = PTR_ERR(hw); DPU_ERROR("failed pingpong object creation: err %d\n", From patchwork Mon Sep 4 02:04:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 720198 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BAB53C71153 for ; Mon, 4 Sep 2023 02:05:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350537AbjIDCFD (ORCPT ); Sun, 3 Sep 2023 22:05:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35526 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350516AbjIDCFC (ORCPT ); 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Sun, 03 Sep 2023 19:04:56 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar , Marijn Suijten Cc: Stephen Boyd , David Airlie , Daniel Vetter , Bjorn Andersson , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH v3 3/8] drm/msm/dpu: drop the DPU_PINGPONG_TE flag Date: Mon, 4 Sep 2023 05:04:49 +0300 Message-Id: <20230904020454.2945667-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230904020454.2945667-1-dmitry.baryshkov@linaro.org> References: <20230904020454.2945667-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The DPU_PINGPONG_TE flag became unused, we can drop it now. Reviewed-by: Marijn Suijten Signed-off-by: Dmitry Baryshkov Reviewed-by: Stephen Boyd --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 4 +--- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index 713dfc079718..d89bdd0dd27a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -79,7 +79,7 @@ (BIT(DPU_DIM_LAYER) | BIT(DPU_MIXER_COMBINED_ALPHA)) #define PINGPONG_SDM845_MASK \ - (BIT(DPU_PINGPONG_DITHER) | BIT(DPU_PINGPONG_TE) | BIT(DPU_PINGPONG_DSC)) + (BIT(DPU_PINGPONG_DITHER) | BIT(DPU_PINGPONG_DSC)) #define PINGPONG_SDM845_TE2_MASK \ (PINGPONG_SDM845_MASK | BIT(DPU_PINGPONG_TE2)) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index 6c9634209e9f..9aac937285b1 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -119,7 +119,6 @@ enum { /** * PINGPONG sub-blocks - * @DPU_PINGPONG_TE Tear check block * @DPU_PINGPONG_TE2 Additional tear check block for split pipes * @DPU_PINGPONG_SPLIT PP block supports split fifo * @DPU_PINGPONG_SLAVE PP block is a suitable slave for split fifo @@ -128,8 +127,7 @@ enum { * @DPU_PINGPONG_MAX */ enum { - DPU_PINGPONG_TE = 0x1, - DPU_PINGPONG_TE2, + DPU_PINGPONG_TE2 = 0x1, DPU_PINGPONG_SPLIT, DPU_PINGPONG_SLAVE, DPU_PINGPONG_DITHER, From patchwork Mon Sep 4 02:04:50 2023 Content-Type: text/plain; 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Reviewed-by: Marijn Suijten Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 48 ++++++++++----------- 1 file changed, 22 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c index 8ec6505d9e78..dd67686f5403 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c @@ -524,31 +524,6 @@ static void dpu_hw_intf_program_intf_cmd_cfg(struct dpu_hw_intf *ctx, DPU_REG_WRITE(&ctx->hw, INTF_CONFIG2, intf_cfg2); } -static void _setup_intf_ops(struct dpu_hw_intf_ops *ops, - unsigned long cap, const struct dpu_mdss_version *mdss_rev) -{ - ops->setup_timing_gen = dpu_hw_intf_setup_timing_engine; - ops->setup_prg_fetch = dpu_hw_intf_setup_prg_fetch; - ops->get_status = dpu_hw_intf_get_status; - ops->enable_timing = dpu_hw_intf_enable_timing_engine; - ops->get_line_count = dpu_hw_intf_get_line_count; - if (cap & BIT(DPU_INTF_INPUT_CTRL)) - ops->bind_pingpong_blk = dpu_hw_intf_bind_pingpong_blk; - ops->setup_misr = dpu_hw_intf_setup_misr; - ops->collect_misr = dpu_hw_intf_collect_misr; - - if (cap & BIT(DPU_INTF_TE)) { - ops->enable_tearcheck = dpu_hw_intf_enable_te; - ops->disable_tearcheck = dpu_hw_intf_disable_te; - ops->connect_external_te = dpu_hw_intf_connect_external_te; - ops->vsync_sel = dpu_hw_intf_vsync_sel; - ops->disable_autorefresh = dpu_hw_intf_disable_autorefresh; - } - - if (mdss_rev->core_major_ver >= 7) - ops->program_intf_cmd_cfg = dpu_hw_intf_program_intf_cmd_cfg; -} - struct dpu_hw_intf *dpu_hw_intf_init(const struct dpu_intf_cfg *cfg, void __iomem *addr, const struct dpu_mdss_version *mdss_rev) { @@ -571,7 +546,28 @@ struct dpu_hw_intf *dpu_hw_intf_init(const struct dpu_intf_cfg *cfg, */ c->idx = cfg->id; c->cap = cfg; - _setup_intf_ops(&c->ops, c->cap->features, mdss_rev); + + c->ops.setup_timing_gen = dpu_hw_intf_setup_timing_engine; + c->ops.setup_prg_fetch = dpu_hw_intf_setup_prg_fetch; + c->ops.get_status = dpu_hw_intf_get_status; + c->ops.enable_timing = dpu_hw_intf_enable_timing_engine; + c->ops.get_line_count = dpu_hw_intf_get_line_count; + c->ops.setup_misr = dpu_hw_intf_setup_misr; + c->ops.collect_misr = dpu_hw_intf_collect_misr; + + if (cfg->features & BIT(DPU_INTF_INPUT_CTRL)) + c->ops.bind_pingpong_blk = dpu_hw_intf_bind_pingpong_blk; + + if (cfg->features & BIT(DPU_INTF_TE)) { + c->ops.enable_tearcheck = dpu_hw_intf_enable_te; + c->ops.disable_tearcheck = dpu_hw_intf_disable_te; + c->ops.connect_external_te = dpu_hw_intf_connect_external_te; + c->ops.vsync_sel = dpu_hw_intf_vsync_sel; + c->ops.disable_autorefresh = dpu_hw_intf_disable_autorefresh; + } + + if (mdss_rev->core_major_ver >= 7) + c->ops.program_intf_cmd_cfg = dpu_hw_intf_program_intf_cmd_cfg; return c; } From patchwork Mon Sep 4 02:04:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 720196 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3EEDC83F2D for ; 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Sun, 03 Sep 2023 19:04:58 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id t13-20020a2e9c4d000000b002bce0e9385asm1818237ljj.9.2023.09.03.19.04.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Sep 2023 19:04:58 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar , Marijn Suijten Cc: Stephen Boyd , David Airlie , Daniel Vetter , Bjorn Andersson , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH v3 5/8] drm/msm/dpu: enable INTF TE operations only when supported by HW Date: Mon, 4 Sep 2023 05:04:51 +0300 Message-Id: <20230904020454.2945667-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230904020454.2945667-1-dmitry.baryshkov@linaro.org> References: <20230904020454.2945667-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The DPU_INTF_TE bit is set for all INTF blocks on DPU >= 5.0, however only INTF_1 and INTF_2 actually support tearing control (both are INTF_DSI). Rather than trying to limit the DPU_INTF_TE feature bit to those two INTF instances, check for the major && INTF type. Reviewed-by: Marijn Suijten Signed-off-by: Dmitry Baryshkov Reviewed-by: Stephen Boyd --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c index dd67686f5403..95ff2f5ebbaa 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c @@ -558,7 +558,10 @@ struct dpu_hw_intf *dpu_hw_intf_init(const struct dpu_intf_cfg *cfg, if (cfg->features & BIT(DPU_INTF_INPUT_CTRL)) c->ops.bind_pingpong_blk = dpu_hw_intf_bind_pingpong_blk; - if (cfg->features & BIT(DPU_INTF_TE)) { + /* INTF TE is only for DSI interfaces */ + if (mdss_rev->core_major_ver >= 5 && cfg->type == INTF_DSI) { + WARN_ON(!cfg->intr_tear_rd_ptr); + c->ops.enable_tearcheck = dpu_hw_intf_enable_te; c->ops.disable_tearcheck = dpu_hw_intf_disable_te; c->ops.connect_external_te = dpu_hw_intf_connect_external_te; From patchwork Mon Sep 4 02:04:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 720026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ACB96CA0FE9 for ; Mon, 4 Sep 2023 02:05:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350357AbjIDCFL (ORCPT ); Sun, 3 Sep 2023 22:05:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35554 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350538AbjIDCFI (ORCPT ); Sun, 3 Sep 2023 22:05:08 -0400 Received: from mail-lj1-x229.google.com (mail-lj1-x229.google.com [IPv6:2a00:1450:4864:20::229]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3F488106 for ; Sun, 3 Sep 2023 19:05:01 -0700 (PDT) Received: by mail-lj1-x229.google.com with SMTP id 38308e7fff4ca-2bcc4347d2dso12734031fa.0 for ; Sun, 03 Sep 2023 19:05:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1693793099; x=1694397899; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=y/rDp6IsMw91trU1zOp/Hjm/TPrfSTJ5k8RTiYBXbIA=; b=sSyHaadGJHqZ0iUR/+hlpud/aJfdkf2Ar6SVnpmlDrK1EspuiFd5pf1OhfQt/7t/WO 3mx7uNd0udEhRHLe+9R5jllN6ORaXrJ4DvXK8eSiiO2w9LQyYIPfi9S3h6lLV0A6IC5L NPiChiYdZFLQlB1dwc9HV5JZgQBqAnzEFrRFTLRkmSShTEx0kzEPCgmGwNWJm4DzfCxo jmeVRe4GaFxeOoml36oqahsbqMa1PucSVfZIkURQs64xeHkLm5UwpsJ/xI1YBZGD5HWL RVTQeyCkuC94kyBZ496srFPdTQdJeU1kUeTVAUsA1fxXU615eBvHPrTp1NUrVqdh3lo6 hFnQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693793099; x=1694397899; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=y/rDp6IsMw91trU1zOp/Hjm/TPrfSTJ5k8RTiYBXbIA=; b=RnUEESKptZB0LkFq9LJeIHBshQ8MMHCKlyHmDs95bn2MvxN+oINh/nbWkgLkBEqtpJ tf5OR2PF6Szik0mpe215tqCOJZr3nSQE+Q55z0iLphKSSgb90Lu7shuA5YJRgKfb0Cfu nPsRlnU17vSs5xh/JRivBgAaYvQ5JryHFiqAPGJYNINFqT4mTsRIXv8rbL8K5DFjK5lS yNtfc0XrEBhQyTRnyhL+XW3xBKbqBUSboc5WxjDDkJBhkwuwX6QQ0OkUbMBe3r5rhYR+ c01k/+FC4OSM0WoOiK6xh46BQtcyELGjw0lTbhUxsTEovcEYrj26SN5hViaYWIWmo91E CGnw== X-Gm-Message-State: AOJu0YxL7StAfQYHju5eEql1Zvxq5GhNABNTU2CfSKiwHbj0OWwawWGb O+0Di7KS5ZqO1ATbuFLOzWLJig== X-Google-Smtp-Source: AGHT+IGc6DjrSpswdTIrEcQhdnq2iRRuzXUIadPblyBTMgGfolFtfbD0pPK6ytUe2ccHrV35qZiVIg== X-Received: by 2002:a2e:804e:0:b0:2bd:169e:3819 with SMTP id p14-20020a2e804e000000b002bd169e3819mr5684898ljg.17.1693793099632; Sun, 03 Sep 2023 19:04:59 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id t13-20020a2e9c4d000000b002bce0e9385asm1818237ljj.9.2023.09.03.19.04.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Sep 2023 19:04:59 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar , Marijn Suijten Cc: Stephen Boyd , David Airlie , Daniel Vetter , Bjorn Andersson , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH v3 6/8] drm/msm/dpu: drop DPU_INTF_TE feature flag Date: Mon, 4 Sep 2023 05:04:52 +0300 Message-Id: <20230904020454.2945667-7-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230904020454.2945667-1-dmitry.baryshkov@linaro.org> References: <20230904020454.2945667-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Replace the only user of the DPU_INTF_TE feature flag with the direct DPU version comparison. Reviewed-by: Marijn Suijten Signed-off-by: Dmitry Baryshkov Reviewed-by: Stephen Boyd --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 5 +++-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 -- 3 files changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c index df88358e7037..e03b2075639d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c @@ -776,8 +776,9 @@ struct dpu_encoder_phys *dpu_encoder_phys_cmd_init( phys_enc->intf_mode = INTF_MODE_CMD; cmd_enc->stream_sel = 0; - phys_enc->has_intf_te = test_bit(DPU_INTF_TE, - &phys_enc->hw_intf->cap->features); + /* DPU before 5.0 use PINGPONG for TE handling */ + if (phys_enc->dpu_kms->catalog->mdss_ver->core_major_ver >= 5) + phys_enc->has_intf_te = true; atomic_set(&cmd_enc->pending_vblank_cnt, 0); init_waitqueue_head(&cmd_enc->pending_vblank_wq); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index d89bdd0dd27a..a1aada630780 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -100,7 +100,6 @@ #define INTF_SC7180_MASK \ (BIT(DPU_INTF_INPUT_CTRL) | \ - BIT(DPU_INTF_TE) | \ BIT(DPU_INTF_STATUS_SUPPORTED) | \ BIT(DPU_DATA_HCTL_EN)) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index 9aac937285b1..e5add4384830 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -158,7 +158,6 @@ enum { * INTF sub-blocks * @DPU_INTF_INPUT_CTRL Supports the setting of pp block from which * pixel data arrives to this INTF - * @DPU_INTF_TE INTF block has TE configuration support * @DPU_DATA_HCTL_EN Allows data to be transferred at different rate * than video timing * @DPU_INTF_STATUS_SUPPORTED INTF block has INTF_STATUS register @@ -166,7 +165,6 @@ enum { */ enum { DPU_INTF_INPUT_CTRL = 0x1, - DPU_INTF_TE, DPU_DATA_HCTL_EN, DPU_INTF_STATUS_SUPPORTED, DPU_INTF_MAX From patchwork Mon Sep 4 02:04:53 2023 Content-Type: text/plain; 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Reviewed-by: Marijn Suijten Signed-off-by: Dmitry Baryshkov Reviewed-by: Stephen Boyd --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 8 -------- 1 file changed, 8 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c index e03b2075639d..d18236bd98e6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c @@ -108,14 +108,6 @@ static void dpu_encoder_phys_cmd_te_rd_ptr_irq(void *arg, int irq_idx) struct dpu_encoder_phys *phys_enc = arg; struct dpu_encoder_phys_cmd *cmd_enc; - if (phys_enc->has_intf_te) { - if (!phys_enc->hw_intf) - return; - } else { - if (!phys_enc->hw_pp) - return; - } - DPU_ATRACE_BEGIN("rd_ptr_irq"); cmd_enc = to_dpu_encoder_phys_cmd(phys_enc); From patchwork Mon Sep 4 02:04:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 720025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6225AC71153 for ; Mon, 4 Sep 2023 02:05:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350538AbjIDCFL (ORCPT ); Sun, 3 Sep 2023 22:05:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35576 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350541AbjIDCFJ (ORCPT ); Sun, 3 Sep 2023 22:05:09 -0400 Received: from mail-lj1-x22b.google.com (mail-lj1-x22b.google.com [IPv6:2a00:1450:4864:20::22b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C6196A9 for ; Sun, 3 Sep 2023 19:05:02 -0700 (PDT) Received: by mail-lj1-x22b.google.com with SMTP id 38308e7fff4ca-2bccda76fb1so14814441fa.2 for ; Sun, 03 Sep 2023 19:05:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1693793101; x=1694397901; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ND9TWls6WljGZ9WIziWPWxaNspuAqLv4XdjEfOK8lUI=; b=LbhPGXVjre00Z/HPi3uZa2zGwqeFY9CpP1FGxKu/DXxPpuQO2KIR2iqJxFpVpSGxTi I6LrbyXOK76pp78ZWzOPzJ9YElZqr8S5C4riJbtXkhHI7BfnrHTcyyaKd9XajkzjlTfW rvIgPQEbWBNZYzA7gmOsdHpe4x97Yjw0gIVWeistbU0p24wIvS9QuSi+drSEhytD1EgI EroLHWb4oPjkA9z4QPWsSRCLn7y6IB2vd2SiRDavjADeozuIj9vj/PjUuZof1HH+qNKF 89MQ8uII7/Ng8KZZJPSfMFIJ/qVWldeQmPM70NQg3ZPzzDt5zbj6+yk2201SFWtZm3cU iVTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693793101; x=1694397901; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ND9TWls6WljGZ9WIziWPWxaNspuAqLv4XdjEfOK8lUI=; b=UPWfLFiC69QJDIuAqhQ9DhMfJm92dWynVOxYR761nKElkvch8YXz+fUAQlZznYW6ta t3WuVdxwTw2nJvOu8asGrpqhfUx7fR+ER7jS6zuvCQFKeCb/C+pn72lpegB5w2Do/CnX a08Y3eVWbPTuHlSbvoeXwBrGVT+37tjMr/OI00IOj/gMKuBxGdTTlMnhtRlpKFg4f0e+ HbPbwGdhUC3UNNEoHxg3WEC02FYL1w1TnGUnwpcjGuDABzIShzHYyYHAcmnLnHT+HYht 9MbZtidYGnP6GRYkmXwqGwLZEeTnE40Tu7xxw6uUDZmrX2Kz6faLpqXBeph8s+SgNOaF UiHA== X-Gm-Message-State: AOJu0YyISlBoeAJvF5JuWRz1VFLnu4R1dDSs8vWrORBicDE8+bXJoqUg fnr16Tw93gw583bErAoVDefwFnxSKjKND9AdYKI= X-Google-Smtp-Source: AGHT+IFWbfGA5SPwQb9KAW491TGzx4BsLhxrFJCHwvDlY00nbTmmGEYFV+xN3Jn9gSryCqTk/mI8/A== X-Received: by 2002:a2e:8608:0:b0:2bc:dada:dbe0 with SMTP id a8-20020a2e8608000000b002bcdadadbe0mr6270880lji.10.1693793101188; Sun, 03 Sep 2023 19:05:01 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id t13-20020a2e9c4d000000b002bce0e9385asm1818237ljj.9.2023.09.03.19.05.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Sep 2023 19:05:00 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar , Marijn Suijten Cc: Stephen Boyd , David Airlie , Daniel Vetter , Bjorn Andersson , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH v3 8/8] drm/msm/dpu: move INTF tearing checks to dpu_encoder_phys_cmd_init Date: Mon, 4 Sep 2023 05:04:54 +0300 Message-Id: <20230904020454.2945667-9-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230904020454.2945667-1-dmitry.baryshkov@linaro.org> References: <20230904020454.2945667-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org As the INTF is fixed at the encoder creation time, we can move the check whether INTF supports tearchck to dpu_encoder_phys_cmd_init(). This function can return an error if INTF doesn't have required feature. Performing this check in dpu_encoder_phys_cmd_tearcheck_config() is less useful, as this function returns void. Signed-off-by: Dmitry Baryshkov Reviewed-by: Stephen Boyd --- .../drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 39 +++++++++++-------- 1 file changed, 23 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c index d18236bd98e6..ca1296379c4d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c @@ -325,24 +325,21 @@ static void dpu_encoder_phys_cmd_tearcheck_config( unsigned long vsync_hz; struct dpu_kms *dpu_kms; - if (phys_enc->has_intf_te) { - if (!phys_enc->hw_intf || - !phys_enc->hw_intf->ops.enable_tearcheck) { - DPU_DEBUG_CMDENC(cmd_enc, "tearcheck not supported\n"); - return; - } - - DPU_DEBUG_CMDENC(cmd_enc, ""); - } else { - if (!phys_enc->hw_pp || - !phys_enc->hw_pp->ops.enable_tearcheck) { - DPU_DEBUG_CMDENC(cmd_enc, "tearcheck not supported\n"); - return; - } - - DPU_DEBUG_CMDENC(cmd_enc, "pp %d\n", phys_enc->hw_pp->idx - PINGPONG_0); + /* + * TODO: if/when resource allocation is refactored, move this to a + * place where the driver can actually return an error. + */ + if (!phys_enc->has_intf_te && + (!phys_enc->hw_pp || + !phys_enc->hw_pp->ops.enable_tearcheck)) { + DPU_DEBUG_CMDENC(cmd_enc, "tearcheck not supported\n"); + return; } + DPU_DEBUG_CMDENC(cmd_enc, "intf %d pp %d\n", + phys_enc->hw_intf ? phys_enc->hw_intf->idx - INTF_0 : -1, + phys_enc->hw_pp ? phys_enc->hw_pp->idx - PINGPONG_0 : -1); + mode = &phys_enc->cached_mode; dpu_kms = phys_enc->dpu_kms; @@ -768,10 +765,20 @@ struct dpu_encoder_phys *dpu_encoder_phys_cmd_init( phys_enc->intf_mode = INTF_MODE_CMD; cmd_enc->stream_sel = 0; + if (!phys_enc->hw_intf) { + DPU_ERROR_CMDENC(cmd_enc, "no INTF provided\n"); + return ERR_PTR(-EINVAL); + } + /* DPU before 5.0 use PINGPONG for TE handling */ if (phys_enc->dpu_kms->catalog->mdss_ver->core_major_ver >= 5) phys_enc->has_intf_te = true; + if (phys_enc->has_intf_te && !phys_enc->hw_intf->ops.enable_tearcheck) { + DPU_ERROR_CMDENC(cmd_enc, "tearcheck not supported\n"); + return ERR_PTR(-EINVAL); + } + atomic_set(&cmd_enc->pending_vblank_cnt, 0); init_waitqueue_head(&cmd_enc->pending_vblank_wq);