From patchwork Mon Sep 4 15:57:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Botka X-Patchwork-Id: 720077 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 592DFCA0FF6 for ; Mon, 4 Sep 2023 15:57:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349806AbjIDP5Q (ORCPT ); Mon, 4 Sep 2023 11:57:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35156 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348444AbjIDP5O (ORCPT ); Mon, 4 Sep 2023 11:57:14 -0400 Received: from relay01.th.seeweb.it (relay01.th.seeweb.it [5.144.164.162]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8EB0BCFD; Mon, 4 Sep 2023 08:57:09 -0700 (PDT) Received: from v0.lan (bband-dyn191.178-41-225.t-com.sk [178.41.225.191]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by m-r1.th.seeweb.it (Postfix) with ESMTPSA id 7DE5B1F963; Mon, 4 Sep 2023 17:57:05 +0200 (CEST) From: Martin Botka Date: Mon, 04 Sep 2023 17:57:01 +0200 Subject: [PATCH 1/6] firmware: smccc: Export revision soc_id function MIME-Version: 1.0 Message-Id: <20230904-cpufreq-h616-v1-1-b8842e525c43@somainline.org> References: <20230904-cpufreq-h616-v1-0-b8842e525c43@somainline.org> In-Reply-To: <20230904-cpufreq-h616-v1-0-b8842e525c43@somainline.org> To: Mark Rutland , Lorenzo Pieralisi , Sudeep Holla , "Rafael J. Wysocki" , Viresh Kumar , Yangtao Li , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-sunxi@lists.linux.dev, devicetree@vger.kernel.org, Andre Przywara , Alan Ma , Luke Harrison , Marijn Suijten , AngeloGioacchino Del Regno , Konrad Dybcio , Rogerio Goncalves , Martin Botka , Martin Botka X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1693843024; l=650; i=martin.botka@somainline.org; s=20230811; h=from:subject:message-id; bh=kr+kQu42jftnzRysfuRliIXntokD55LnjWm0KkOrQRY=; b=pAzHKAaWc3uxAZHLFKPmIIe/nbRnKh/YE++nWe15qMHVrrI0vNt1Ph6hE+aFzN+4S1wpRixuy C3B8nQmhvtKBDaa/gTX1xPTp4ZewRLtv2es7NWSHg0vT3FkLoNVVVaQ X-Developer-Key: i=martin.botka@somainline.org; a=ed25519; pk=aTCd3jmwU8GrJidWg3DSKLpdVMcpFzXzCSLXLR6NtWU= Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org arm_smccc_get_soc_id_revision need to be exported so it can be used by sun50i cpufreq driver. Signed-off-by: Martin Botka --- drivers/firmware/smccc/smccc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/firmware/smccc/smccc.c b/drivers/firmware/smccc/smccc.c index db818f9dcb8e..d670635914ec 100644 --- a/drivers/firmware/smccc/smccc.c +++ b/drivers/firmware/smccc/smccc.c @@ -69,6 +69,7 @@ s32 arm_smccc_get_soc_id_revision(void) { return smccc_soc_id_revision; } +EXPORT_SYMBOL_GPL(arm_smccc_get_soc_id_revision); static int __init smccc_devices_init(void) { From patchwork Mon Sep 4 15:57:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Botka X-Patchwork-Id: 720320 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 779CFCA0FFA for ; Mon, 4 Sep 2023 15:57:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1353250AbjIDP5Q (ORCPT ); Mon, 4 Sep 2023 11:57:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35130 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345270AbjIDP5O (ORCPT ); Mon, 4 Sep 2023 11:57:14 -0400 Received: from relay02.th.seeweb.it (relay02.th.seeweb.it [5.144.164.163]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 83947CCC for ; Mon, 4 Sep 2023 08:57:09 -0700 (PDT) Received: from v0.lan (bband-dyn191.178-41-225.t-com.sk [178.41.225.191]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by m-r1.th.seeweb.it (Postfix) with ESMTPSA id 493011FAFE; Mon, 4 Sep 2023 17:57:06 +0200 (CEST) From: Martin Botka Date: Mon, 04 Sep 2023 17:57:02 +0200 Subject: [PATCH 2/6] cpufreq: dt-platdev: Blocklist allwinner,h616 SoC MIME-Version: 1.0 Message-Id: <20230904-cpufreq-h616-v1-2-b8842e525c43@somainline.org> References: <20230904-cpufreq-h616-v1-0-b8842e525c43@somainline.org> In-Reply-To: <20230904-cpufreq-h616-v1-0-b8842e525c43@somainline.org> To: Mark Rutland , Lorenzo Pieralisi , Sudeep Holla , "Rafael J. Wysocki" , Viresh Kumar , Yangtao Li , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-sunxi@lists.linux.dev, devicetree@vger.kernel.org, Andre Przywara , Alan Ma , Luke Harrison , Marijn Suijten , AngeloGioacchino Del Regno , Konrad Dybcio , Rogerio Goncalves , Martin Botka , Martin Botka X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1693843024; l=763; i=martin.botka@somainline.org; s=20230811; h=from:subject:message-id; bh=y6+Jp6XdKlMolFv5lUKbS3BMDgQUVTv9Ux9Y9Pn0TiI=; b=jYK1Ddg2mSPl2rn47FMupLfy4TQbq4y4Ff2LU45va19Z4Fmq+B+x7B57OviVOXwqZEwVGQpX+ L7sv0XXIIk8D2MXSGs4p4If3SIc5J6qsYkfdvrBDMpnb7vKRS9UECKB X-Developer-Key: i=martin.botka@somainline.org; a=ed25519; pk=aTCd3jmwU8GrJidWg3DSKLpdVMcpFzXzCSLXLR6NtWU= Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The AllWinner H616 uses H6 cpufreq driver. Add it to blocklist so its not created twice Signed-off-by: Martin Botka --- drivers/cpufreq/cpufreq-dt-platdev.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c index e2b20080de3a..51818cef8979 100644 --- a/drivers/cpufreq/cpufreq-dt-platdev.c +++ b/drivers/cpufreq/cpufreq-dt-platdev.c @@ -104,6 +104,7 @@ static const struct of_device_id allowlist[] __initconst = { */ static const struct of_device_id blocklist[] __initconst = { { .compatible = "allwinner,sun50i-h6", }, + { .compatible = "allwinner,sun50i-h616", }, { .compatible = "apple,arm-platform", }, From patchwork Mon Sep 4 15:57:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Botka X-Patchwork-Id: 720321 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 68FB0C83F2C for ; Mon, 4 Sep 2023 15:57:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348948AbjIDP5O (ORCPT ); Mon, 4 Sep 2023 11:57:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35080 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233243AbjIDP5O (ORCPT ); Mon, 4 Sep 2023 11:57:14 -0400 Received: from relay02.th.seeweb.it (relay02.th.seeweb.it [IPv6:2001:4b7a:2000:18::163]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 84DC2CD7; Mon, 4 Sep 2023 08:57:09 -0700 (PDT) Received: from v0.lan (bband-dyn191.178-41-225.t-com.sk [178.41.225.191]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by m-r1.th.seeweb.it (Postfix) with ESMTPSA id 0D0E21FBA5; Mon, 4 Sep 2023 17:57:07 +0200 (CEST) From: Martin Botka Date: Mon, 04 Sep 2023 17:57:03 +0200 Subject: [PATCH 3/6] dt-bindings: opp: Add compatible for H616 MIME-Version: 1.0 Message-Id: <20230904-cpufreq-h616-v1-3-b8842e525c43@somainline.org> References: <20230904-cpufreq-h616-v1-0-b8842e525c43@somainline.org> In-Reply-To: <20230904-cpufreq-h616-v1-0-b8842e525c43@somainline.org> To: Mark Rutland , Lorenzo Pieralisi , Sudeep Holla , "Rafael J. Wysocki" , Viresh Kumar , Yangtao Li , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-sunxi@lists.linux.dev, devicetree@vger.kernel.org, Andre Przywara , Alan Ma , Luke Harrison , Marijn Suijten , AngeloGioacchino Del Regno , Konrad Dybcio , Rogerio Goncalves , Martin Botka , Martin Botka X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1693843024; l=1233; i=martin.botka@somainline.org; s=20230811; h=from:subject:message-id; bh=vkpyJtpACo5loCh7uIWuezcAm00aYr/8qEBY1Y7a4p0=; b=LsSyA8ltGbBj/87WeIZvhIIr7CW27Ba6QPMzBx6lX+DRdiVacfciJrzaKnjSiasT24rMfXkvF kHkob6+ZQ/jBcRr0WKQr0aVbKXpqug9ql3yQNGreOaV45y6DciUQFZ/ X-Developer-Key: i=martin.botka@somainline.org; a=ed25519; pk=aTCd3jmwU8GrJidWg3DSKLpdVMcpFzXzCSLXLR6NtWU= Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org We need to add compatible for H616 to H6 cpufreq driver bindings. Also enable opp_supported_hw property that will be needed for H616. Signed-off-by: Martin Botka --- .../bindings/opp/allwinner,sun50i-h6-operating-points.yaml | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/opp/allwinner,sun50i-h6-operating-points.yaml b/Documentation/devicetree/bindings/opp/allwinner,sun50i-h6-operating-points.yaml index 51f62c3ae194..2fa1199f2d23 100644 --- a/Documentation/devicetree/bindings/opp/allwinner,sun50i-h6-operating-points.yaml +++ b/Documentation/devicetree/bindings/opp/allwinner,sun50i-h6-operating-points.yaml @@ -23,7 +23,10 @@ allOf: properties: compatible: - const: allwinner,sun50i-h6-operating-points + contains: + enum: + - allwinner,sun50i-h6-operating-points + - allwinner,sun50i-h616-operating-points nvmem-cells: description: | @@ -47,6 +50,7 @@ patternProperties: properties: opp-hz: true clock-latency-ns: true + opp-supported-hw: true patternProperties: "^opp-microvolt-speed[0-9]$": true From patchwork Mon Sep 4 15:57:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Botka X-Patchwork-Id: 720318 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7A5EBC83F2C for ; Mon, 4 Sep 2023 15:57:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1353253AbjIDP5R (ORCPT ); Mon, 4 Sep 2023 11:57:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35168 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1351275AbjIDP5P (ORCPT ); Mon, 4 Sep 2023 11:57:15 -0400 Received: from relay02.th.seeweb.it (relay02.th.seeweb.it [IPv6:2001:4b7a:2000:18::163]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E8531E42 for ; Mon, 4 Sep 2023 08:57:09 -0700 (PDT) Received: from v0.lan (bband-dyn191.178-41-225.t-com.sk [178.41.225.191]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by m-r1.th.seeweb.it (Postfix) with ESMTPSA id CC8541FBC6; Mon, 4 Sep 2023 17:57:07 +0200 (CEST) From: Martin Botka Date: Mon, 04 Sep 2023 17:57:04 +0200 Subject: [PATCH 4/6] cpufreq: sun50i: Add H616 support MIME-Version: 1.0 Message-Id: <20230904-cpufreq-h616-v1-4-b8842e525c43@somainline.org> References: <20230904-cpufreq-h616-v1-0-b8842e525c43@somainline.org> In-Reply-To: <20230904-cpufreq-h616-v1-0-b8842e525c43@somainline.org> To: Mark Rutland , Lorenzo Pieralisi , Sudeep Holla , "Rafael J. Wysocki" , Viresh Kumar , Yangtao Li , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-sunxi@lists.linux.dev, devicetree@vger.kernel.org, Andre Przywara , Alan Ma , Luke Harrison , Marijn Suijten , AngeloGioacchino Del Regno , Konrad Dybcio , Rogerio Goncalves , Martin Botka , Martin Botka X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1693843024; l=7580; i=martin.botka@somainline.org; s=20230811; h=from:subject:message-id; bh=uOkhsPX7y5/oVyy/A3DXMbJiwLZ7PuGRSeJiB4vSb0g=; b=nJ3k//b9hWLBAuPFPIZjbYazaVXZ0ahtMcLt3XRaJn0zpDjMrt9za9k7aGbFK7+zJRgshNEx8 jVATPvuWhAzAxMUTOhYg6qcR2XIbW5LDDHzs9Lzi5hm98w8ufV+FxjN X-Developer-Key: i=martin.botka@somainline.org; a=ed25519; pk=aTCd3jmwU8GrJidWg3DSKLpdVMcpFzXzCSLXLR6NtWU= Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org AllWinner H616 SoC has few revisions that support different list of uV and frequencies. Some revisions have the same NVMEM value and thus we have to check the SoC revision from SMCCC to differentiate between them. Signed-off-by: Martin Botka --- drivers/cpufreq/sun50i-cpufreq-nvmem.c | 149 ++++++++++++++++++++++++++++----- 1 file changed, 126 insertions(+), 23 deletions(-) diff --git a/drivers/cpufreq/sun50i-cpufreq-nvmem.c b/drivers/cpufreq/sun50i-cpufreq-nvmem.c index 4321d7bbe769..19c126fb081e 100644 --- a/drivers/cpufreq/sun50i-cpufreq-nvmem.c +++ b/drivers/cpufreq/sun50i-cpufreq-nvmem.c @@ -10,6 +10,7 @@ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt +#include #include #include #include @@ -23,20 +24,94 @@ #define NVMEM_MASK 0x7 #define NVMEM_SHIFT 5 +struct sunxi_cpufreq_soc_data { + int (*efuse_xlate)(u32 *versions, u32 *efuse, char *name, size_t len); + u8 ver_freq_limit; +}; + static struct platform_device *cpufreq_dt_pdev, *sun50i_cpufreq_pdev; +static int sun50i_h616_efuse_xlate(u32 *versions, u32 *efuse, char *name, size_t len) +{ + int value = 0; + u32 speedgrade = 0; + u32 i; + int ver_bits = arm_smccc_get_soc_id_revision(); + + if (len > 4) { + pr_err("Invalid nvmem cell length\n"); + return -EINVAL; + } + + for (i = 0; i < len; i++) + speedgrade |= (efuse[i] << (i * 8)); + + switch (speedgrade) { + case 0x2000: + value = 0; + break; + case 0x2400: + case 0x7400: + case 0x2c00: + case 0x7c00: + if (ver_bits <= 1) { + /* ic version A/B */ + value = 1; + } else { + /* ic version C and later version */ + value = 2; + } + break; + case 0x5000: + case 0x5400: + case 0x6000: + value = 3; + break; + case 0x5c00: + value = 4; + break; + case 0x5d00: + default: + value = 0; + } + *versions = (1 << value); + snprintf(name, MAX_NAME_LEN, "speed%d", value); + return 0; +} + +static int sun50i_h6_efuse_xlate(u32 *versions, u32 *efuse, char *name, size_t len) +{ + int efuse_value = (*efuse >> NVMEM_SHIFT) & NVMEM_MASK; + + /* + * We treat unexpected efuse values as if the SoC was from + * the slowest bin. Expected efuse values are 1-3, slowest + * to fastest. + */ + if (efuse_value >= 1 && efuse_value <= 3) + *versions = efuse_value - 1; + else + *versions = 0; + + snprintf(name, MAX_NAME_LEN, "speed%d", *versions); + return 0; +} + /** * sun50i_cpufreq_get_efuse() - Determine speed grade from efuse value + * @soc_data: Struct containing soc specific data & functions * @versions: Set to the value parsed from efuse + * @name: Set to the name of speed * * Returns 0 if success. */ -static int sun50i_cpufreq_get_efuse(u32 *versions) +static int sun50i_cpufreq_get_efuse(const struct sunxi_cpufreq_soc_data *soc_data, + u32 *versions, char *name) { struct nvmem_cell *speedbin_nvmem; struct device_node *np; struct device *cpu_dev; - u32 *speedbin, efuse_value; + u32 *speedbin; size_t len; int ret; @@ -48,9 +123,9 @@ static int sun50i_cpufreq_get_efuse(u32 *versions) if (!np) return -ENOENT; - ret = of_device_is_compatible(np, - "allwinner,sun50i-h6-operating-points"); - if (!ret) { + if (of_device_is_compatible(np, "allwinner,sun50i-h6-operating-points")) { + } else if (of_device_is_compatible(np, "allwinner,sun50i-h616-operating-points")) { + } else { of_node_put(np); return -ENOENT; } @@ -66,17 +141,9 @@ static int sun50i_cpufreq_get_efuse(u32 *versions) if (IS_ERR(speedbin)) return PTR_ERR(speedbin); - efuse_value = (*speedbin >> NVMEM_SHIFT) & NVMEM_MASK; - - /* - * We treat unexpected efuse values as if the SoC was from - * the slowest bin. Expected efuse values are 1-3, slowest - * to fastest. - */ - if (efuse_value >= 1 && efuse_value <= 3) - *versions = efuse_value - 1; - else - *versions = 0; + ret = soc_data->efuse_xlate(versions, speedbin, name, len); + if (ret) + return ret; kfree(speedbin); return 0; @@ -84,25 +151,30 @@ static int sun50i_cpufreq_get_efuse(u32 *versions) static int sun50i_cpufreq_nvmem_probe(struct platform_device *pdev) { + const struct of_device_id *match; + const struct sunxi_cpufreq_soc_data *soc_data; int *opp_tokens; char name[MAX_NAME_LEN]; unsigned int cpu; - u32 speed = 0; + u32 version = 0; int ret; + match = dev_get_platdata(&pdev->dev); + if (!match) + return -EINVAL; + soc_data = match->data; + opp_tokens = kcalloc(num_possible_cpus(), sizeof(*opp_tokens), GFP_KERNEL); if (!opp_tokens) return -ENOMEM; - ret = sun50i_cpufreq_get_efuse(&speed); + ret = sun50i_cpufreq_get_efuse(match->data, &version, name); if (ret) { kfree(opp_tokens); return ret; } - snprintf(name, MAX_NAME_LEN, "speed%d", speed); - for_each_possible_cpu(cpu) { struct device *cpu_dev = get_cpu_device(cpu); @@ -117,6 +189,16 @@ static int sun50i_cpufreq_nvmem_probe(struct platform_device *pdev) pr_err("Failed to set prop name\n"); goto free_opp; } + + if (soc_data->ver_freq_limit) { + opp_tokens[cpu] = dev_pm_opp_set_supported_hw(cpu_dev, + &version, 1); + if (opp_tokens[cpu] < 0) { + ret = opp_tokens[cpu]; + pr_err("Failed to set hw\n"); + goto free_opp; + } + } } cpufreq_dt_pdev = platform_device_register_simple("cpufreq-dt", -1, @@ -132,6 +214,8 @@ static int sun50i_cpufreq_nvmem_probe(struct platform_device *pdev) free_opp: for_each_possible_cpu(cpu) dev_pm_opp_put_prop_name(opp_tokens[cpu]); + if (soc_data->ver_freq_limit) + dev_pm_opp_put_supported_hw(opp_tokens[cpu]); kfree(opp_tokens); return ret; @@ -140,12 +224,21 @@ static int sun50i_cpufreq_nvmem_probe(struct platform_device *pdev) static int sun50i_cpufreq_nvmem_remove(struct platform_device *pdev) { int *opp_tokens = platform_get_drvdata(pdev); + const struct of_device_id *match; + const struct sunxi_cpufreq_soc_data *soc_data; unsigned int cpu; + match = dev_get_platdata(&pdev->dev); + if (!match) + return -EINVAL; + soc_data = match->data; + platform_device_unregister(cpufreq_dt_pdev); for_each_possible_cpu(cpu) dev_pm_opp_put_prop_name(opp_tokens[cpu]); + if (soc_data->ver_freq_limit) + dev_pm_opp_put_supported_hw(opp_tokens[cpu]); kfree(opp_tokens); @@ -160,8 +253,18 @@ static struct platform_driver sun50i_cpufreq_driver = { }, }; +static const struct sunxi_cpufreq_soc_data sun50i_h616_data = { + .efuse_xlate = sun50i_h616_efuse_xlate, + .ver_freq_limit = true, +}; + +static const struct sunxi_cpufreq_soc_data sun50i_h6_data = { + .efuse_xlate = sun50i_h6_efuse_xlate, +}; + static const struct of_device_id sun50i_cpufreq_match_list[] = { - { .compatible = "allwinner,sun50i-h6" }, + { .compatible = "allwinner,sun50i-h6", .data = &sun50i_h6_data }, + { .compatible = "allwinner,sun50i-h616", .data = &sun50i_h616_data }, {} }; MODULE_DEVICE_TABLE(of, sun50i_cpufreq_match_list); @@ -197,8 +300,8 @@ static int __init sun50i_cpufreq_init(void) return ret; sun50i_cpufreq_pdev = - platform_device_register_simple("sun50i-cpufreq-nvmem", - -1, NULL, 0); + platform_device_register_data(NULL, "sun50i-cpufreq-nvmem", + -1, match, sizeof(*match)); ret = PTR_ERR_OR_ZERO(sun50i_cpufreq_pdev); if (ret == 0) return 0; From patchwork Mon Sep 4 15:57:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Botka X-Patchwork-Id: 720076 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8C3ACCA0FFC for ; Mon, 4 Sep 2023 15:57:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239766AbjIDP5R (ORCPT ); Mon, 4 Sep 2023 11:57:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35190 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1353223AbjIDP5P (ORCPT ); Mon, 4 Sep 2023 11:57:15 -0400 Received: from relay02.th.seeweb.it (relay02.th.seeweb.it [5.144.164.163]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A8F4AE5D for ; Mon, 4 Sep 2023 08:57:10 -0700 (PDT) Received: from v0.lan (bband-dyn191.178-41-225.t-com.sk [178.41.225.191]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by m-r1.th.seeweb.it (Postfix) with ESMTPSA id 92F80200DC; Mon, 4 Sep 2023 17:57:08 +0200 (CEST) From: Martin Botka Date: Mon, 04 Sep 2023 17:57:05 +0200 Subject: [PATCH 5/6] arm64: dts: allwinner: h616: Add CPU Operating Performance Points table MIME-Version: 1.0 Message-Id: <20230904-cpufreq-h616-v1-5-b8842e525c43@somainline.org> References: <20230904-cpufreq-h616-v1-0-b8842e525c43@somainline.org> In-Reply-To: <20230904-cpufreq-h616-v1-0-b8842e525c43@somainline.org> To: Mark Rutland , Lorenzo Pieralisi , Sudeep Holla , "Rafael J. Wysocki" , Viresh Kumar , Yangtao Li , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-sunxi@lists.linux.dev, devicetree@vger.kernel.org, Andre Przywara , Alan Ma , Luke Harrison , Marijn Suijten , AngeloGioacchino Del Regno , Konrad Dybcio , Rogerio Goncalves , Martin Botka , Martin Botka X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1693843024; l=4851; i=martin.botka@somainline.org; s=20230811; h=from:subject:message-id; bh=ZyTs95wiIyvmN1gbK2qSdTK4VyZDXqdQv5Y0SxAq2Rk=; b=Pmytw8jIYJK6fsuUEfiSHlfEP7WedUyOYqucysSFK6q9uyb86M3hCB9byZG+4ySi6JIZ6Mv7Y 3mP/BIvEH4zCImrvZJin4j5kU9yhS/7gi8UWRE9b3aNJqYNGB1/QKb7 X-Developer-Key: i=martin.botka@somainline.org; a=ed25519; pk=aTCd3jmwU8GrJidWg3DSKLpdVMcpFzXzCSLXLR6NtWU= Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add an Operating Performance Points table for the CPU cores to enable Dynamic Voltage & Frequency Scaling on the H616. Also add the needed cpu_speed_grade nvmem cell. Signed-off-by: Martin Botka --- .../boot/dts/allwinner/sun50i-h616-cpu-opp.dtsi | 129 +++++++++++++++++++++ arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi | 4 + 2 files changed, 133 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-cpu-opp.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616-cpu-opp.dtsi new file mode 100644 index 000000000000..4c7eaba511a9 --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-cpu-opp.dtsi @@ -0,0 +1,129 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (C) 2023 Martin Botka + +/ { + cpu_opp_table: cpu-opp-table { + compatible = "allwinner,sun50i-h616-operating-points"; + nvmem-cells = <&cpu_speed_grade>; + opp-shared; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + opp-microvolt-speed0 = <900000>; + opp-microvolt-speed1 = <900000>; + opp-microvolt-speed2 = <900000>; + opp-microvolt-speed3 = <900000>; + opp-microvolt-speed4 = <900000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-supported-hw = <0x1f>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt-speed1 = <900000>; + opp-microvolt-speed4 = <900000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-supported-hw = <0x12>; + }; + + opp-720000000 { + opp-hz = /bits/ 64 <720000000>; + opp-microvolt-speed0 = <900000>; + opp-microvolt-speed2 = <900000>; + opp-microvolt-speed3 = <900000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-supported-hw = <0xd>; + }; + + opp-792000000 { + opp-hz = /bits/ 64 <792000000>; + opp-microvolt-speed1 = <900000>; + opp-microvolt-speed4 = <940000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-supported-hw = <0x12>; + }; + + opp-936000000 { + opp-hz = /bits/ 64 <936000000>; + opp-microvolt-speed0 = <900000>; + opp-microvolt-speed2 = <900000>; + opp-microvolt-speed3 = <900000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-supported-hw = <0xd>; + }; + + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt-speed0 = <950000>; + opp-microvolt-speed1 = <940000>; + opp-microvolt-speed2 = <950000>; + opp-microvolt-speed3 = <950000>; + opp-microvolt-speed4 = <1020000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-supported-hw = <0x1f>; + }; + + opp-1104000000 { + opp-hz = /bits/ 64 <1104000000>; + opp-microvolt-speed0 = <1000000>; + opp-microvolt-speed2 = <1000000>; + opp-microvolt-speed3 = <1000000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-supported-hw = <0xd>; + }; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt-speed0 = <1050000>; + opp-microvolt-speed1 = <1020000>; + opp-microvolt-speed2 = <1050000>; + opp-microvolt-speed3 = <1050000>; + opp-microvolt-speed4 = <1100000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-supported-hw = <0x1f>; + }; + + opp-1320000000 { + opp-hz = /bits/ 64 <1320000000>; + opp-microvolt-speed0 = <1100000>; + opp-microvolt-speed2 = <1100000>; + opp-microvolt-speed3 = <1100000>; + opp-microvolt-speed4 = <1100000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-supported-hw = <0x1d>; + }; + + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt-speed0 = <1100000>; + opp-microvolt-speed2 = <1100000>; + opp-microvolt-speed3 = <1100000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-supported-hw = <0xd>; + }; + + opp-1512000000 { + opp-hz = /bits/ 64 <1512000000>; + opp-microvolt-speed1 = <1100000>; + opp-microvolt-speed3 = <1100000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-supported-hw = <0xa>; + }; + }; +}; + +&cpu0 { + operating-points-v2 = <&cpu_opp_table>; +}; + +&cpu1 { + operating-points-v2 = <&cpu_opp_table>; +}; + +&cpu2 { + operating-points-v2 = <&cpu_opp_table>; +}; + +&cpu3 { + operating-points-v2 = <&cpu_opp_table>; +}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi index 063db9634e5f..78e79c591dba 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi @@ -143,6 +143,10 @@ sid: efuse@3006000 { ths_calibration: thermal-sensor-calibration@14 { reg = <0x14 0x8>; }; + + cpu_speed_grade: cpu_speed_grade@0 { + reg = <0x0 2>; + }; }; watchdog: watchdog@30090a0 { From patchwork Mon Sep 4 15:57:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Botka X-Patchwork-Id: 720319 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1E876C83F3F for ; Mon, 4 Sep 2023 15:57:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1353262AbjIDP5U (ORCPT ); Mon, 4 Sep 2023 11:57:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35290 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1351560AbjIDP5T (ORCPT ); Mon, 4 Sep 2023 11:57:19 -0400 Received: from relay01.th.seeweb.it (relay01.th.seeweb.it [5.144.164.162]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 52325CE0 for ; Mon, 4 Sep 2023 08:57:16 -0700 (PDT) Received: from v0.lan (bband-dyn191.178-41-225.t-com.sk [178.41.225.191]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by m-r1.th.seeweb.it (Postfix) with ESMTPSA id 5B3FE201B0; Mon, 4 Sep 2023 17:57:09 +0200 (CEST) From: Martin Botka Date: Mon, 04 Sep 2023 17:57:06 +0200 Subject: [PATCH 6/6] arm64: dts: allwinner: h616: Add cooling cells MIME-Version: 1.0 Message-Id: <20230904-cpufreq-h616-v1-6-b8842e525c43@somainline.org> References: <20230904-cpufreq-h616-v1-0-b8842e525c43@somainline.org> In-Reply-To: <20230904-cpufreq-h616-v1-0-b8842e525c43@somainline.org> To: Mark Rutland , Lorenzo Pieralisi , Sudeep Holla , "Rafael J. Wysocki" , Viresh Kumar , Yangtao Li , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-sunxi@lists.linux.dev, devicetree@vger.kernel.org, Andre Przywara , Alan Ma , Luke Harrison , Marijn Suijten , AngeloGioacchino Del Regno , Konrad Dybcio , Rogerio Goncalves , Martin Botka , Martin Botka X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1693843024; l=1174; i=martin.botka@somainline.org; s=20230811; h=from:subject:message-id; bh=qJv56yjDvCMxLlVKkO9qD49pos1hnuOnNYRbCB0UPg0=; b=zMLqucwWJskJLNOgqJTLSKacT6rQBC1cwrFNHN3F2BAMkUGpUNzTlKyvratAfDhTp2hqBTdRU xmbBKBWUWsrDX4Dj9koFphUDq/Thv1MDc4BtfGIm6hqMCQAin2R3D3B X-Developer-Key: i=martin.botka@somainline.org; a=ed25519; pk=aTCd3jmwU8GrJidWg3DSKLpdVMcpFzXzCSLXLR6NtWU= Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add cooling cells so we enable passive cooling on CPU by regulating CPU voltage and frequency Signed-off-by: Martin Botka --- arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi index 78e79c591dba..7dc4c95ea280 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi @@ -26,6 +26,7 @@ cpu0: cpu@0 { reg = <0>; enable-method = "psci"; clocks = <&ccu CLK_CPUX>; + #cooling-cells = <2>; }; cpu1: cpu@1 { @@ -34,6 +35,7 @@ cpu1: cpu@1 { reg = <1>; enable-method = "psci"; clocks = <&ccu CLK_CPUX>; + #cooling-cells = <2>; }; cpu2: cpu@2 { @@ -42,6 +44,7 @@ cpu2: cpu@2 { reg = <2>; enable-method = "psci"; clocks = <&ccu CLK_CPUX>; + #cooling-cells = <2>; }; cpu3: cpu@3 { @@ -50,6 +53,7 @@ cpu3: cpu@3 { reg = <3>; enable-method = "psci"; clocks = <&ccu CLK_CPUX>; + #cooling-cells = <2>; }; };