From patchwork Tue Jul 23 21:35:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 169565 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp9377102ilk; Tue, 23 Jul 2019 14:37:39 -0700 (PDT) X-Google-Smtp-Source: APXvYqwp7E7l/zlYJ6bmZ3TqJTuKQWKIUzNejGsBbInmC4gFwwPEYqwdKmOHn1YF4fJaP0yguHvP X-Received: by 2002:a02:c95a:: with SMTP id u26mr78414356jao.15.1563917859051; Tue, 23 Jul 2019 14:37:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1563917859; cv=none; d=google.com; s=arc-20160816; b=TMDuMg5elpR9ng7yg5AYPWl9x4cvUnP5euN7FGyxZtm+mTd9/kUIPEyPLvMwytgqio ldwBfPGff1uMpmT2j7Mm4c49wzsLWOBcdBv5uamcddvmkvHzBbLF+9QNOkBA1Lgns8ts fSVGWiCDjmzm0nfyV/Tz3avvOdavb/BwAjncQy5o24HAgA2+Z18p8qu8cB1y1IXDSdDp VmPcVOuemHF7tipU+Vz9Z5y1PAjquP71NlOnj/J9WWHHqMu0ggiLkxe6QYg1phuHzbUJ NSbuOVQKeHUtdJmya/wDdYwcKENBAM6tzJgx6gOKZakskvtmhSSs+d40TiB0J3E4wOW3 Lb3w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=SBM9rcL02njLtqZuF8aVErSQwDVj2oLJ7DeI6aSNZtU=; b=VJLrSEi3XO/Hd/2wCrWNsThhC7PnFU0iRY3P2soCqzLxY5KtxdBSpYDtvugX2V3uYs xTM4YW88eQ+gjQRaMOgOcTqhHt0ene4UaWUZFI1Or2ciiXa7199ShGfad4++bphn8NL2 gOewPgwx0gVt8Rib6WcEHNv2lgUg4pJbybqbBBln6h4TctzOLQjeEdYrzBi2rXip2jtX qMZQe1ncfthSdCOpfEpT2kkxgk7N9dv3rcGzbU+Bf7Q7S96d9KDpK0ZNa5Z1lSusFxEf T9ecETla3xZjuLHJCeADTRD7XKwP5z0QvG316sGdOFmCogM+sCmYuK5/SggVXdQFfntC zAZA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id w3si62405722jae.112.2019.07.23.14.37.38 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 23 Jul 2019 14:37:39 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hq2S6-0001vf-8b; Tue, 23 Jul 2019 21:36:06 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hq2S4-0001vL-Ly for xen-devel@lists.xenproject.org; Tue, 23 Jul 2019 21:36:04 +0000 X-Inumbo-ID: dd82f3b8-ad91-11e9-b2fc-8fe1da1518da Received: from foss.arm.com (unknown [217.140.110.172]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTP id dd82f3b8-ad91-11e9-b2fc-8fe1da1518da; Tue, 23 Jul 2019 21:36:01 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C8C821509; Tue, 23 Jul 2019 14:36:00 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 076A33F71F; Tue, 23 Jul 2019 14:35:59 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Tue, 23 Jul 2019 22:35:47 +0100 Message-Id: <20190723213553.22300-2-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190723213553.22300-1-julien.grall@arm.com> References: <20190723213553.22300-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH 1/7] xen/public: arch-arm: Restrict the visibility of struct vcpu_guest_core_regs X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Andrew Cooper , Julien Grall , Stefano Stabellini , Volodymyr Babchuk MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Currently, the structure vcpu_guest_core_regs is part of the public API. This implies that any change in the structure should be backward compatible. However, the structure is only needed by the tools and Xen. It is also not expected to be ever used outside of that context. So we could save us some headache by only declaring the structure for Xen and tools. Suggested-by: Andrew Cooper Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini --- This is a follow-up of the discussion [1]. [1] <3c245c5b-51c6-1d0e-ad6c-42414573166f@arm.com> Changes in v3: - Avoid introduce a new #ifdef in the header by moving the definitions later on. --- xen/include/public/arch-arm.h | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/xen/include/public/arch-arm.h b/xen/include/public/arch-arm.h index 3e8cdc151d..7ce139a0f5 100644 --- a/xen/include/public/arch-arm.h +++ b/xen/include/public/arch-arm.h @@ -197,6 +197,18 @@ } while ( 0 ) #define set_xen_guest_handle(hnd, val) set_xen_guest_handle_raw(hnd, val) +typedef uint64_t xen_pfn_t; +#define PRI_xen_pfn PRIx64 +#define PRIu_xen_pfn PRIu64 + +/* Maximum number of virtual CPUs in legacy multi-processor guests. */ +/* Only one. All other VCPUS must use VCPUOP_register_vcpu_info */ +#define XEN_LEGACY_MAX_VCPUS 1 + +typedef uint64_t xen_ulong_t; +#define PRI_xen_ulong PRIx64 + +#if defined(__XEN__) || defined(__XEN_TOOLS__) #if defined(__GNUC__) && !defined(__STRICT_ANSI__) /* Anonymous union includes both 32- and 64-bit names (e.g., r0/x0). */ # define __DECL_REG(n64, n32) union { \ @@ -272,18 +284,6 @@ DEFINE_XEN_GUEST_HANDLE(vcpu_guest_core_regs_t); #undef __DECL_REG -typedef uint64_t xen_pfn_t; -#define PRI_xen_pfn PRIx64 -#define PRIu_xen_pfn PRIu64 - -/* Maximum number of virtual CPUs in legacy multi-processor guests. */ -/* Only one. All other VCPUS must use VCPUOP_register_vcpu_info */ -#define XEN_LEGACY_MAX_VCPUS 1 - -typedef uint64_t xen_ulong_t; -#define PRI_xen_ulong PRIx64 - -#if defined(__XEN__) || defined(__XEN_TOOLS__) struct vcpu_guest_context { #define _VGCF_online 0 #define VGCF_online (1<<_VGCF_online) From patchwork Tue Jul 23 21:35:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 169568 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp9377150ilk; Tue, 23 Jul 2019 14:37:42 -0700 (PDT) X-Google-Smtp-Source: APXvYqwqYOtOSXVKd0x4V9dzJWbW5WKM9oqUojP1rF6XbZfCCKeFKWXlbFvSQ0g0L6A5c8M36rMT X-Received: by 2002:a05:6638:5:: with SMTP id z5mr9252773jao.58.1563917862454; Tue, 23 Jul 2019 14:37:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1563917862; cv=none; d=google.com; s=arc-20160816; b=Jes48W0W74w2B3YCqh3I+D6meLdw1+2U4yQiTM0p2dnBdCASEAdWgxb1jwXmf+bLwF SyxQAqGkLN7DdWL1HFNKNZ1+N9x/YpSvPuFCcDFFS/JOS1F1oLfeJRQiHaDnrY/12APQ g6FS+GGWIzcD2kNCfVtmW1E1b1OUgCwGCi1miHnQ5Xyki8f0EZhBlbp5cXAtdSQCLHSS WG9egw8QzKLFfwbMyF1OAfSorKirmJti2czB8fGm4nvnL2Sm2H2/fJIGMuqLjXR6yUWF TMkAdcumQ1yiZ3CNbyERieEMx33j9BFqzvjCWEWeiqUl+t+v/kn+nFZdNwfZZPc9uKEl RFxw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=tBCw0P7Z40dCQRtCjpGo/jIaWN3mMkjRgJtlRJJ1zvw=; b=rTBKux52QjfdWIbt/utQW6B8hmxVaqBCS4zidR/z8rgg+g6xrKaFNwsU8p1xFNXrZb /J3GSHK0bWG4kDbYd16zfy+IRkAy1r5CzMSO71o+ZDhndu02LLNt0w7vyIhdXcTQ7Wls sllc3yaKkSJmefhnCzqCyxVhgVd2CrRBOVzirFJnZGFkKPf7/MC1y/LfUZj5AvdJTGD+ oNl+HiJ7tMO99KWE68eKNqZxJBENGdUcA1Ufyl2VbJpjsY9u9kCY2vjXpSU1OfYLqTvP wIgVO2tdzU6cDKJoHqPYxbE0bcaEgqjwQnXmJcqBQ4/amLbeFZvJIM25+muRLAEwnLPW AEcA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id 187si4069992jaz.24.2019.07.23.14.37.42 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 23 Jul 2019 14:37:42 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hq2S7-0001wH-AI; Tue, 23 Jul 2019 21:36:07 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hq2S5-0001vW-69 for xen-devel@lists.xenproject.org; Tue, 23 Jul 2019 21:36:05 +0000 X-Inumbo-ID: de4fdb74-ad91-11e9-8980-bc764e045a96 Received: from foss.arm.com (unknown [217.140.110.172]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id de4fdb74-ad91-11e9-8980-bc764e045a96; Tue, 23 Jul 2019 21:36:02 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0D0341596; Tue, 23 Jul 2019 14:36:02 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 09A133F71F; Tue, 23 Jul 2019 14:36:00 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Tue, 23 Jul 2019 22:35:48 +0100 Message-Id: <20190723213553.22300-3-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190723213553.22300-1-julien.grall@arm.com> References: <20190723213553.22300-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH 2/7] xen/arm: SCTLR_EL1 is a 64-bit register on Arm64 X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Stefano Stabellini , Wei Liu , George Dunlap , Ian Jackson , Julien Grall , Volodymyr Babchuk MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" On Arm64, system registers are always 64-bit including SCTLR_EL1. However, Xen is assuming this is 32-bit because earlier revision of Armv8 had the top 32-bit RES0 (see ARM DDI0595.b). >From Armv8.5, some bits in [63:32] will be defined and allowed to be modified by the guest. So we would effectively reset those bits to 0 after each context switch. This means the guest may not function correctly afterwards. Rather than resetting to 0 the bits [63:32], preserve them acxcross context switch. Note that the corresponding register on Arm32 (i.e SCTLR) is always 32-bit. So we need to use register_t anywhere we deal the SCTLR{,_EL1}. Outside interface is switched to use 64-bit to allow ABI compatibility between 32-bit and 64-bit. Signed-off-by: Julien Grall Reviewed-by: Volodymyr Babchuk Reviewed-by: Stefano Stabellini --- All the other system registers should be switched to 64-bit. This is done separatly as this is the only system register that currently not save/restore correctly. I would consider to backport it as we would end up to disable features behind the back of the guest. --- tools/xentrace/xenctx.c | 4 +++- xen/arch/arm/guest_walk.c | 2 +- xen/arch/arm/traps.c | 10 +++++----- xen/include/asm-arm/domain.h | 3 ++- xen/include/asm-arm/p2m.h | 4 ++-- xen/include/public/arch-arm.h | 4 ++-- 6 files changed, 15 insertions(+), 12 deletions(-) diff --git a/tools/xentrace/xenctx.c b/tools/xentrace/xenctx.c index e647179e19..2fa864f867 100644 --- a/tools/xentrace/xenctx.c +++ b/tools/xentrace/xenctx.c @@ -598,6 +598,8 @@ static void print_ctx_32(vcpu_guest_context_t *ctx) printf("r12_fiq: %08"PRIx32"\n", regs->r12_fiq); printf("\n"); + /* SCTLR is always 32-bit */ + printf("SCTLR: %08"PRIx32"\n", (uint32_t)ctx->sctlr); } #ifdef __aarch64__ @@ -659,6 +661,7 @@ static void print_ctx_64(vcpu_guest_context_t *ctx) printf("x28: %016"PRIx64"\t", regs->x28); printf("x29: %016"PRIx64"\n", regs->x29); printf("\n"); + printf("SCTLR_EL1: %016"PRIx64"\n", ctx->sctlr); } #endif /* __aarch64__ */ @@ -675,7 +678,6 @@ static void print_ctx(vcpu_guest_context_any_t *ctx_any) print_ctx_32(ctx); #endif - printf("SCTLR: %08"PRIx32"\n", ctx->sctlr); printf("TTBCR: %016"PRIx64"\n", ctx->ttbcr); printf("TTBR0: %016"PRIx64"\n", ctx->ttbr0); printf("TTBR1: %016"PRIx64"\n", ctx->ttbr1); diff --git a/xen/arch/arm/guest_walk.c b/xen/arch/arm/guest_walk.c index c6d6e23bf5..a1cdd7f4af 100644 --- a/xen/arch/arm/guest_walk.c +++ b/xen/arch/arm/guest_walk.c @@ -589,7 +589,7 @@ static bool guest_walk_ld(const struct vcpu *v, bool guest_walk_tables(const struct vcpu *v, vaddr_t gva, paddr_t *ipa, unsigned int *perms) { - uint32_t sctlr = READ_SYSREG(SCTLR_EL1); + register_t sctlr = READ_SYSREG(SCTLR_EL1); register_t tcr = READ_SYSREG(TCR_EL1); unsigned int _perms; diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 3103620323..111a2029e6 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -384,7 +384,7 @@ void panic_PAR(uint64_t par) static void cpsr_switch_mode(struct cpu_user_regs *regs, int mode) { - uint32_t sctlr = READ_SYSREG32(SCTLR_EL1); + register_t sctlr = READ_SYSREG(SCTLR_EL1); regs->cpsr &= ~(PSR_MODE_MASK|PSR_IT_MASK|PSR_JAZELLE|PSR_BIG_ENDIAN|PSR_THUMB); @@ -400,7 +400,7 @@ static void cpsr_switch_mode(struct cpu_user_regs *regs, int mode) static vaddr_t exception_handler32(vaddr_t offset) { - uint32_t sctlr = READ_SYSREG32(SCTLR_EL1); + register_t sctlr = READ_SYSREG(SCTLR_EL1); if ( sctlr & SCTLR_A32_EL1_V ) return 0xffff0000 + offset; @@ -719,7 +719,7 @@ crash_system: struct reg_ctxt { /* Guest-side state */ - uint32_t sctlr_el1; + register_t sctlr_el1; register_t tcr_el1; uint64_t ttbr0_el1, ttbr1_el1; #ifdef CONFIG_ARM_32 @@ -822,7 +822,7 @@ static void show_registers_32(const struct cpu_user_regs *regs, if ( guest_mode ) { - printk(" SCTLR: %08"PRIx32"\n", ctxt->sctlr_el1); + printk(" SCTLR: %"PRIregister"\n", ctxt->sctlr_el1); printk(" TCR: %08"PRIregister"\n", ctxt->tcr_el1); printk(" TTBR0: %016"PRIx64"\n", ctxt->ttbr0_el1); printk(" TTBR1: %016"PRIx64"\n", ctxt->ttbr1_el1); @@ -894,7 +894,7 @@ static void show_registers_64(const struct cpu_user_regs *regs, printk(" ESR_EL1: %08"PRIx32"\n", ctxt->esr_el1); printk(" FAR_EL1: %016"PRIx64"\n", ctxt->far); printk("\n"); - printk(" SCTLR_EL1: %08"PRIx32"\n", ctxt->sctlr_el1); + printk(" SCTLR_EL1: %"PRIregister"\n", ctxt->sctlr_el1); printk(" TCR_EL1: %08"PRIregister"\n", ctxt->tcr_el1); printk(" TTBR0_EL1: %016"PRIx64"\n", ctxt->ttbr0_el1); printk(" TTBR1_EL1: %016"PRIx64"\n", ctxt->ttbr1_el1); diff --git a/xen/include/asm-arm/domain.h b/xen/include/asm-arm/domain.h index 2960a53e69..86ebdd2bcf 100644 --- a/xen/include/asm-arm/domain.h +++ b/xen/include/asm-arm/domain.h @@ -167,7 +167,8 @@ struct arch_vcpu #endif /* Control Registers */ - uint32_t actlr, sctlr; + register_t sctlr; + uint32_t actlr; uint32_t cpacr; uint32_t contextidr; diff --git a/xen/include/asm-arm/p2m.h b/xen/include/asm-arm/p2m.h index 2f89bb00c3..03f2ee75c1 100644 --- a/xen/include/asm-arm/p2m.h +++ b/xen/include/asm-arm/p2m.h @@ -391,12 +391,12 @@ static inline int set_foreign_p2m_entry(struct domain *d, unsigned long gfn, */ static inline bool vcpu_has_cache_enabled(struct vcpu *v) { - const uint32_t mask = SCTLR_Axx_ELx_C | SCTLR_Axx_ELx_M; + const register_t mask = SCTLR_Axx_ELx_C | SCTLR_Axx_ELx_M; /* Only works with the current vCPU */ ASSERT(current == v); - return (READ_SYSREG32(SCTLR_EL1) & mask) == mask; + return (READ_SYSREG(SCTLR_EL1) & mask) == mask; } #endif /* _XEN_P2M_H */ diff --git a/xen/include/public/arch-arm.h b/xen/include/public/arch-arm.h index 7ce139a0f5..d9a06efbd8 100644 --- a/xen/include/public/arch-arm.h +++ b/xen/include/public/arch-arm.h @@ -291,7 +291,7 @@ struct vcpu_guest_context { struct vcpu_guest_core_regs user_regs; /* Core CPU registers */ - uint32_t sctlr; + uint64_t sctlr; uint64_t ttbcr, ttbr0, ttbr1; }; typedef struct vcpu_guest_context vcpu_guest_context_t; @@ -380,7 +380,7 @@ typedef uint64_t xen_callback_t; #define PSR_GUEST32_INIT (PSR_ABT_MASK|PSR_FIQ_MASK|PSR_IRQ_MASK|PSR_MODE_SVC) #define PSR_GUEST64_INIT (PSR_ABT_MASK|PSR_FIQ_MASK|PSR_IRQ_MASK|PSR_MODE_EL1h) -#define SCTLR_GUEST_INIT 0x00c50078 +#define SCTLR_GUEST_INIT xen_mk_ullong(0x00c50078) /* * Virtual machine platform (memory layout, interrupts) From patchwork Tue Jul 23 21:35:49 2019 Content-Type: text/plain; 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[192.237.175.120]) by mx.google.com with ESMTPS id h22si57564285ior.159.2019.07.23.14.37.40 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 23 Jul 2019 14:37:40 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hq2S6-0001vs-I9; Tue, 23 Jul 2019 21:36:06 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hq2S4-0001vM-M8 for xen-devel@lists.xenproject.org; Tue, 23 Jul 2019 21:36:04 +0000 X-Inumbo-ID: decb42d4-ad91-11e9-a732-23c2ab580807 Received: from foss.arm.com (unknown [217.140.110.172]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTP id decb42d4-ad91-11e9-a732-23c2ab580807; Tue, 23 Jul 2019 21:36:03 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E76A515A1; Tue, 23 Jul 2019 14:36:02 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 411EB3F71F; Tue, 23 Jul 2019 14:36:02 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Tue, 23 Jul 2019 22:35:49 +0100 Message-Id: <20190723213553.22300-4-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190723213553.22300-1-julien.grall@arm.com> References: <20190723213553.22300-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH 3/7] xen/arm: Rework psr_mode_is_32bit() X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , Stefano Stabellini , Volodymyr Babchuk MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" psr_mode_is_32bit() prototype does not match the rest of the helpers for the process state. Looking at the callers, most of them will access struct cpu_user_regs just for calling psr_mode_is_32bit(). The macro is now reworked to take a struct cpu_user_regs in parameter. At the same time take the opportunity to switch to a static inline helper. Lastly, when compiled for 32-bit, Xen will only support 32-bit guest. So it is pointless to check whether the register state correspond to 64-bit or not. Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini --- xen/arch/arm/traps.c | 28 ++++++++++++++-------------- xen/include/asm-arm/regs.h | 9 ++++++++- 2 files changed, 22 insertions(+), 15 deletions(-) diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 111a2029e6..54e66a86d0 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -919,7 +919,7 @@ static void _show_registers(const struct cpu_user_regs *regs, #ifdef CONFIG_ARM_64 else if ( is_64bit_domain(v->domain) ) { - if ( psr_mode_is_32bit(regs->cpsr) ) + if ( psr_mode_is_32bit(regs) ) { BUG_ON(!usr_mode(regs)); show_registers_32(regs, ctxt, guest_mode, v); @@ -1625,7 +1625,7 @@ int check_conditional_instr(struct cpu_user_regs *regs, const union hsr hsr) { unsigned long it; - BUG_ON( !psr_mode_is_32bit(regs->cpsr) || !(cpsr&PSR_THUMB) ); + BUG_ON( !psr_mode_is_32bit(regs) || !(cpsr & PSR_THUMB) ); it = ( (cpsr >> (10-2)) & 0xfc) | ((cpsr >> 25) & 0x3 ); @@ -1650,7 +1650,7 @@ int check_conditional_instr(struct cpu_user_regs *regs, const union hsr hsr) void advance_pc(struct cpu_user_regs *regs, const union hsr hsr) { unsigned long itbits, cond, cpsr = regs->cpsr; - bool is_thumb = psr_mode_is_32bit(cpsr) && (cpsr & PSR_THUMB); + bool is_thumb = psr_mode_is_32bit(regs) && (cpsr & PSR_THUMB); if ( is_thumb && (cpsr & PSR_IT_MASK) ) { @@ -2078,32 +2078,32 @@ void do_trap_guest_sync(struct cpu_user_regs *regs) advance_pc(regs, hsr); break; case HSR_EC_CP15_32: - GUEST_BUG_ON(!psr_mode_is_32bit(regs->cpsr)); + GUEST_BUG_ON(!psr_mode_is_32bit(regs)); perfc_incr(trap_cp15_32); do_cp15_32(regs, hsr); break; case HSR_EC_CP15_64: - GUEST_BUG_ON(!psr_mode_is_32bit(regs->cpsr)); + GUEST_BUG_ON(!psr_mode_is_32bit(regs)); perfc_incr(trap_cp15_64); do_cp15_64(regs, hsr); break; case HSR_EC_CP14_32: - GUEST_BUG_ON(!psr_mode_is_32bit(regs->cpsr)); + GUEST_BUG_ON(!psr_mode_is_32bit(regs)); perfc_incr(trap_cp14_32); do_cp14_32(regs, hsr); break; case HSR_EC_CP14_64: - GUEST_BUG_ON(!psr_mode_is_32bit(regs->cpsr)); + GUEST_BUG_ON(!psr_mode_is_32bit(regs)); perfc_incr(trap_cp14_64); do_cp14_64(regs, hsr); break; case HSR_EC_CP14_DBG: - GUEST_BUG_ON(!psr_mode_is_32bit(regs->cpsr)); + GUEST_BUG_ON(!psr_mode_is_32bit(regs)); perfc_incr(trap_cp14_dbg); do_cp14_dbg(regs, hsr); break; case HSR_EC_CP: - GUEST_BUG_ON(!psr_mode_is_32bit(regs->cpsr)); + GUEST_BUG_ON(!psr_mode_is_32bit(regs)); perfc_incr(trap_cp); do_cp(regs, hsr); break; @@ -2114,7 +2114,7 @@ void do_trap_guest_sync(struct cpu_user_regs *regs) * ARMv7 (DDI 0406C.b): B1.14.8 * ARMv8 (DDI 0487A.d): D1-1501 Table D1-44 */ - GUEST_BUG_ON(!psr_mode_is_32bit(regs->cpsr)); + GUEST_BUG_ON(!psr_mode_is_32bit(regs)); perfc_incr(trap_smc32); do_trap_smc(regs, hsr); break; @@ -2122,7 +2122,7 @@ void do_trap_guest_sync(struct cpu_user_regs *regs) { register_t nr; - GUEST_BUG_ON(!psr_mode_is_32bit(regs->cpsr)); + GUEST_BUG_ON(!psr_mode_is_32bit(regs)); perfc_incr(trap_hvc32); #ifndef NDEBUG if ( (hsr.iss & 0xff00) == 0xff00 ) @@ -2137,7 +2137,7 @@ void do_trap_guest_sync(struct cpu_user_regs *regs) } #ifdef CONFIG_ARM_64 case HSR_EC_HVC64: - GUEST_BUG_ON(psr_mode_is_32bit(regs->cpsr)); + GUEST_BUG_ON(psr_mode_is_32bit(regs)); perfc_incr(trap_hvc64); #ifndef NDEBUG if ( (hsr.iss & 0xff00) == 0xff00 ) @@ -2153,12 +2153,12 @@ void do_trap_guest_sync(struct cpu_user_regs *regs) * * ARMv8 (DDI 0487A.d): D1-1501 Table D1-44 */ - GUEST_BUG_ON(psr_mode_is_32bit(regs->cpsr)); + GUEST_BUG_ON(psr_mode_is_32bit(regs)); perfc_incr(trap_smc64); do_trap_smc(regs, hsr); break; case HSR_EC_SYSREG: - GUEST_BUG_ON(psr_mode_is_32bit(regs->cpsr)); + GUEST_BUG_ON(psr_mode_is_32bit(regs)); perfc_incr(trap_sysreg); do_sysreg(regs, hsr); break; diff --git a/xen/include/asm-arm/regs.h b/xen/include/asm-arm/regs.h index ddc6eba9ce..0e3e56b452 100644 --- a/xen/include/asm-arm/regs.h +++ b/xen/include/asm-arm/regs.h @@ -13,7 +13,14 @@ #define psr_mode(psr,m) (((psr) & PSR_MODE_MASK) == m) -#define psr_mode_is_32bit(psr) !!((psr) & PSR_MODE_BIT) +static inline bool psr_mode_is_32bit(const struct cpu_user_regs *regs) +{ +#ifdef CONFIG_ARM_32 + return true; +#else + return !!(regs->cpsr & PSR_MODE_BIT); +#endif +} #define usr_mode(r) psr_mode((r)->cpsr,PSR_MODE_USR) #define fiq_mode(r) psr_mode((r)->cpsr,PSR_MODE_FIQ) From patchwork Tue Jul 23 21:35:50 2019 Content-Type: text/plain; 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[192.237.175.120]) by mx.google.com with ESMTPS id b10si55696455ioq.76.2019.07.23.14.37.36 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 23 Jul 2019 14:37:36 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hq2S6-0001w1-Rh; Tue, 23 Jul 2019 21:36:06 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hq2S5-0001vV-3J for xen-devel@lists.xenproject.org; Tue, 23 Jul 2019 21:36:05 +0000 X-Inumbo-ID: df4cb4aa-ad91-11e9-8980-bc764e045a96 Received: from foss.arm.com (unknown [217.140.110.172]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id df4cb4aa-ad91-11e9-8980-bc764e045a96; Tue, 23 Jul 2019 21:36:03 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CDA5F15A2; Tue, 23 Jul 2019 14:36:03 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 275DA3F71F; Tue, 23 Jul 2019 14:36:03 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Tue, 23 Jul 2019 22:35:50 +0100 Message-Id: <20190723213553.22300-5-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190723213553.22300-1-julien.grall@arm.com> References: <20190723213553.22300-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH 4/7] xen/arm: traps: Avoid using BUG_ON() in _show_registers() X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , Stefano Stabellini , Volodymyr Babchuk MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" At the moment, _show_registers() is using a BUG_ON() to assert only userspace will run 32-bit code in a 64-bit domain. Such extra precaution is not necessary and could be avoided by only checking the CPU mode to decide whether show_registers_64() or show_reigsters_32() should be called. This has also the nice advantage to avoid nested if in the code. Signed-off-by: Julien Grall Reviewed-by: Volodymyr Babchuk Acked-by: Stefano Stabellini --- xen/arch/arm/traps.c | 16 +++------------- 1 file changed, 3 insertions(+), 13 deletions(-) diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 54e66a86d0..132686ee0f 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -914,21 +914,11 @@ static void _show_registers(const struct cpu_user_regs *regs, if ( guest_mode ) { - if ( is_32bit_domain(v->domain) ) + if ( psr_mode_is_32bit(regs) ) show_registers_32(regs, ctxt, guest_mode, v); #ifdef CONFIG_ARM_64 - else if ( is_64bit_domain(v->domain) ) - { - if ( psr_mode_is_32bit(regs) ) - { - BUG_ON(!usr_mode(regs)); - show_registers_32(regs, ctxt, guest_mode, v); - } - else - { - show_registers_64(regs, ctxt, guest_mode, v); - } - } + else + show_registers_64(regs, ctxt, guest_mode, v); #endif } else From patchwork Tue Jul 23 21:35:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 169566 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp9377103ilk; Tue, 23 Jul 2019 14:37:39 -0700 (PDT) X-Google-Smtp-Source: APXvYqzPGMg8aC8NB73gN8oMi2fx56iAenqCY89h5/Ig6wl+NplnCgum89X8iG1Vd0NxCjZwFxLg X-Received: by 2002:a02:b016:: with SMTP id p22mr35749418jah.121.1563917859102; Tue, 23 Jul 2019 14:37:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1563917859; cv=none; d=google.com; s=arc-20160816; b=kTh3tpNYqJ+F2vauvWh/H10OJ6LwVEb+5vaswnhSl1VWoLDcX+dKeaY45+TFPP5G8e cO5AwGdD4YeARprIQjUEMCyDemtHu93TirWucOODuafQbS+JJpHI6fWnwnfodWmR2lUX /XrT3+ciDpxSXMYvcSNOoz0JIxKhXNfAbWCiuP7P7T1hYV08/1UgLIwuW7xGr0DlzzeS Z2VrjjnBbzgcmN9cFllPNaSusP4za61qx55riBR/IjH2+So6zvkvrmZMPxiAWlBe77RO 0AGLdcrfXJFLZ4CruvHmFSzQDPGFJ1ERnWjM5V0QWTznakGQFYUI6VLNF94Fbb9oZRR+ Hpfw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=LF4hW/6/Zxe5Hv3wfgcnaBbCFNL8gJuXb+VF1+Fk9Wg=; b=sw7NGsVfG8lmiFMC0N/AvKBmtGtCSmQyoPGxjxUuIgAe4ooy/W/7vWHOes48fUbfiD FJF1yPJ2fpsjRll0q8ro2HFWq2Ik08KEOIWkYb/cOYAM2rRpqjvzt4n7NwaP+M2rmqMz L7BnefzbZA70fsLQiuDjMi+nU7DLviSrAc8jZK6TJ8z5ix5B9BhPlyxYy122UQ4hTZWk PMExNp6Vthl2GIErMQlMp+MeFWwDJSRMunySv6bkO1r//3yZJThejHFEZJSyIrsjX5no X+GJmusOX08W8HGENP1iOL1/h1JD3g+epjU8uofSSqtYAvVkzH066GANtNJSfDERfSHf Co7g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id r1si72554080jac.1.2019.07.23.14.37.39 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 23 Jul 2019 14:37:39 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hq2S8-0001wp-J0; Tue, 23 Jul 2019 21:36:08 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hq2S6-0001vh-BJ for xen-devel@lists.xenproject.org; Tue, 23 Jul 2019 21:36:06 +0000 X-Inumbo-ID: dfec0d65-ad91-11e9-8980-bc764e045a96 Received: from foss.arm.com (unknown [217.140.110.172]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id dfec0d65-ad91-11e9-8980-bc764e045a96; Tue, 23 Jul 2019 21:36:05 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B43DE1509; Tue, 23 Jul 2019 14:36:04 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 0DAAD3F71F; Tue, 23 Jul 2019 14:36:03 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Tue, 23 Jul 2019 22:35:51 +0100 Message-Id: <20190723213553.22300-6-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190723213553.22300-1-julien.grall@arm.com> References: <20190723213553.22300-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH 5/7] xen/arm: traps: Avoid BUG_ON() in do_trap_brk() X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , Stefano Stabellini , Volodymyr Babchuk MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" At the moment, do_trap_brk() is using a BUG_ON() to check the hardware has been correctly configured during boot. Any error when configuring the hardware could result to a guest 'brk' trapping in the hypervisor and crash it. This is pretty harsh to kill Xen when actually killing the guest would be enough as misconfiguring this trap would not lead to exposing sensitive data. Replace the BUG_ON() with crashing the guest. Signed-off-by: Julien Grall Reviewed-by: Volodymyr Babchuk Reviewed-by: Stefano Stabellini --- xen/arch/arm/traps.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 132686ee0f..ef37ca6bde 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -1304,10 +1304,15 @@ int do_bug_frame(const struct cpu_user_regs *regs, vaddr_t pc) #ifdef CONFIG_ARM_64 static void do_trap_brk(struct cpu_user_regs *regs, const union hsr hsr) { - /* HCR_EL2.TGE and MDCR_EL2.TDE are not set so we never receive - * software breakpoint exception for EL1 and EL0 here. + /* + * HCR_EL2.TGE and MDCR_EL2.TDR are currently not set. So we should + * never receive software breakpoing exception for EL1 and EL0 here. */ - BUG_ON(!hyp_mode(regs)); + if ( !hyp_mode(regs) ) + { + domain_crash(current->domain); + return; + } switch ( hsr.brk.comment ) { From patchwork Tue Jul 23 21:35:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 169563 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp9377078ilk; Tue, 23 Jul 2019 14:37:37 -0700 (PDT) X-Google-Smtp-Source: APXvYqzVvZRdac4l08+/DweClOaGG3qMGee1XyLK/2cDvHX3sS23ppUPue/kXkWejGSAZweUG10y X-Received: by 2002:a6b:cd86:: with SMTP id d128mr72564664iog.234.1563917857569; Tue, 23 Jul 2019 14:37:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1563917857; cv=none; d=google.com; s=arc-20160816; b=fK6mx2RZZcnzSsj21W3EsS5tS3iCzIroFVefs4gmjyQfY09zmbiaDx181H8tZ1YIMk mn+T/Hom0aUxmigkArIUAuIZC1nDKakHVXBpX0xmjeN+FyjD31Xy4nFmpTT4DIoxUF5z Jr2eVNOU07DmdRR0AZMDoWOpKNx3lPget7/+K9Crkt51tL62Bd0Onvbqf4Q3UKlxLucX Tg7AJ6E+3avkaiXtjrO+OyWfJBTmqZqKY/fYNeTjQMA4ryYJ+EEEkGuRfeNke22Uk+sw FVkzplufxm10kx+C+0uVcERIUvKqZrDJl2RxjPypqQozXccqMXJ/MW12JdBGmTOX58nf go+A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=NUwQ4vdhc9XdyDsiKnbldzs/HJfPaeNVYo17KgVW3X4=; b=ClrL3VPNrWUeRaTZXwYONLpb8uk2r5Ls80aHoUlZ+7cy/3xM0hdTXN7KRJ1z5b5gt2 nFQb9loqPXjqrZiyD+pAcuWy88lhjG1GqwcV13xN03PGnnU1A0Xro+2Fxk+uPFHv5B08 tMdBv8APj5hR4HEFnei/7ovLsyQ+OeuxzElVuCfTKKGgiiq2dccGljWR9a/tzmIUbdm5 LRypWJ505MXum9GJ+fCRUztCkf7dqIs6NtLY0l3RGvNB2FwvtbplFyHY9tSe2G1o9CbV M7D9f9I5tXqYYfWBuwBBH7uMAyaxcsossKhOSGhi663e9//7x8Fz3OHag/nGHWIqifeo 9GaA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id m18si64002229jaa.95.2019.07.23.14.37.37 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 23 Jul 2019 14:37:37 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hq2S8-0001x2-Tw; Tue, 23 Jul 2019 21:36:08 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hq2S6-0001vj-DQ for xen-devel@lists.xenproject.org; Tue, 23 Jul 2019 21:36:06 +0000 X-Inumbo-ID: e0536cd1-ad91-11e9-8980-bc764e045a96 Received: from foss.arm.com (unknown [217.140.110.172]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id e0536cd1-ad91-11e9-8980-bc764e045a96; Tue, 23 Jul 2019 21:36:05 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9A9DB1596; Tue, 23 Jul 2019 14:36:05 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E84FA3F71F; Tue, 23 Jul 2019 14:36:04 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Tue, 23 Jul 2019 22:35:52 +0100 Message-Id: <20190723213553.22300-7-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190723213553.22300-1-julien.grall@arm.com> References: <20190723213553.22300-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH 6/7] xen/arm: vsmc: The function identifier is always 32-bit X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , Stefano Stabellini , Volodymyr Babchuk MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" On Arm64, the SMCCC function identifier is always stored in the first 32-bit of x0 register. The rest of the bits are not defined and should be ignored. This means the variable funcid should be an uint32_t rather than register_t. Signed-off-by: Julien Grall Reviewed-by: Volodymyr Babchuk Reviewed-by: Stefano Stabellini --- xen/arch/arm/vsmc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/vsmc.c b/xen/arch/arm/vsmc.c index f8e350311d..a36db15fff 100644 --- a/xen/arch/arm/vsmc.c +++ b/xen/arch/arm/vsmc.c @@ -220,7 +220,7 @@ static bool vsmccc_handle_call(struct cpu_user_regs *regs) { bool handled = false; const union hsr hsr = { .bits = regs->hsr }; - register_t funcid = get_user_reg(regs, 0); + uint32_t funcid = get_user_reg(regs, 0); /* * Check immediate value for HVC32, HVC64 and SMC64. @@ -286,7 +286,7 @@ static bool vsmccc_handle_call(struct cpu_user_regs *regs) if ( !handled ) { - gprintk(XENLOG_INFO, "Unhandled SMC/HVC: %08"PRIregister"\n", funcid); + gprintk(XENLOG_INFO, "Unhandled SMC/HVC: %#x\n", funcid); /* Inform caller that function is not supported. */ set_user_reg(regs, 0, ARM_SMCCC_ERR_UNKNOWN_FUNCTION); From patchwork Tue Jul 23 21:35:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 169569 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp9377132ilk; Tue, 23 Jul 2019 14:37:41 -0700 (PDT) X-Google-Smtp-Source: APXvYqyV3MQsykMGcSVOv8SvOFrdoGN5JMqiimMEU5V8PapoSCJUy11Z9BZ5sCy9maHlQ3IKdsYS X-Received: by 2002:a6b:7602:: with SMTP id g2mr62519628iom.82.1563917861212; Tue, 23 Jul 2019 14:37:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1563917861; cv=none; d=google.com; s=arc-20160816; b=dAu1ZG9u4ilWSvSshhSAbUDI47edfRSWroGNyDNPmmmwglgJEqFab4wUo0TnZzknEo EknZnhEdVywIo39U98v1x9CEnYVoND6ozF+irTL9TShHGdbpvl2VJzntXp46DozgVV4y dn6xX2gJhYlYaHZXo1a8SYTQAuwf6ctplGDzJPf993UjtQgTX2Ds73EpFgV5GDrWNhmO rbuh8iwnk3ly01D25gebVaJIYjwvfzfWrUh//LcgIz8qfrGpEm+Yaxrn3KIgSI8ojYVK VpVwfJ6fO4iE38+zycK0IrIA0gjveUB3cJiYOTuuAC/QUdqMnFAwCjWIWCfQ/6xbYFIB ze5Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=dRBsfodqMkRZkUfU9SO6opvdgRGLKQSD7zzyzw8WCCI=; b=Z2RUA20LF08cRCPOechDr+sqXINoQgqhAl8zycF3WVtzBIGXlZp47hoGdzt1/YQnZC 0ARwHHFvPWWErQbQJQhdtx+tfa9PqzeihnKjhAKAdk8LvcQ1DATzcNSZGjCDbu0rG5fX Pfb8S2v2JdGZIck0ml6M3CbRJkLn1zl5mRx8wxL8DMSoL7oundtY/L0fg4OuJ+m9cKC+ yGXGl+n2mNWhDw9mJE8flcj1FOSUHmDfAhzCvGsQylca94TIjqJ9ZDxSZRfNnSbB8iNj p2c5uSk6a/jGr5Wl0ue/fiIsZnmzGRBsmDLWodePdYBwCZrwMdqDYvqAFawCXFXhEtXO aRrQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id e12si66012180jap.92.2019.07.23.14.37.41 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 23 Jul 2019 14:37:41 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hq2S9-0001xB-8M; Tue, 23 Jul 2019 21:36:09 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hq2S7-0001wZ-ME for xen-devel@lists.xenproject.org; Tue, 23 Jul 2019 21:36:07 +0000 X-Inumbo-ID: e0e21da4-ad91-11e9-8980-bc764e045a96 Received: from foss.arm.com (unknown [217.140.110.172]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id e0e21da4-ad91-11e9-8980-bc764e045a96; Tue, 23 Jul 2019 21:36:06 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8112A28; Tue, 23 Jul 2019 14:36:06 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id CEE933F71F; Tue, 23 Jul 2019 14:36:05 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Tue, 23 Jul 2019 22:35:53 +0100 Message-Id: <20190723213553.22300-8-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190723213553.22300-1-julien.grall@arm.com> References: <20190723213553.22300-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH 7/7] xen/arm: types: Specify the zero padding in the definition of PRIregister X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , Stefano Stabellini , Volodymyr Babchuk MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The definition of PRIregister varies between Arm32 and Arm64 (32-bit vs 64-bit). However, some of the users uses the wrong padding. For more consistency, the padding is now moved into the PRIregister and varies depending on the architecture. Signed-off-by: Julien Grall Reviewed-by: Volodymyr Babchuk Acked-by: Stefano Stabellini --- xen/arch/arm/traps.c | 10 +++++----- xen/include/asm-arm/types.h | 4 ++-- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index ef37ca6bde..f062ae6f6a 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -797,7 +797,7 @@ static void show_registers_32(const struct cpu_user_regs *regs, if ( guest_mode ) { - printk("USR: SP: %08"PRIx32" LR: %08"PRIregister"\n", + printk("USR: SP: %08"PRIx32" LR: %"PRIregister"\n", regs->sp_usr, regs->lr); printk("SVC: SP: %08"PRIx32" LR: %08"PRIx32" SPSR:%08"PRIx32"\n", regs->sp_svc, regs->lr_svc, regs->spsr_svc); @@ -815,7 +815,7 @@ static void show_registers_32(const struct cpu_user_regs *regs, #ifndef CONFIG_ARM_64 else { - printk("HYP: SP: %08"PRIx32" LR: %08"PRIregister"\n", regs->sp, regs->lr); + printk("HYP: SP: %08"PRIx32" LR: %"PRIregister"\n", regs->sp, regs->lr); } #endif printk("\n"); @@ -823,7 +823,7 @@ static void show_registers_32(const struct cpu_user_regs *regs, if ( guest_mode ) { printk(" SCTLR: %"PRIregister"\n", ctxt->sctlr_el1); - printk(" TCR: %08"PRIregister"\n", ctxt->tcr_el1); + printk(" TCR: %"PRIregister"\n", ctxt->tcr_el1); printk(" TTBR0: %016"PRIx64"\n", ctxt->ttbr0_el1); printk(" TTBR1: %016"PRIx64"\n", ctxt->ttbr1_el1); printk(" IFAR: %08"PRIx32", IFSR: %08"PRIx32"\n" @@ -895,7 +895,7 @@ static void show_registers_64(const struct cpu_user_regs *regs, printk(" FAR_EL1: %016"PRIx64"\n", ctxt->far); printk("\n"); printk(" SCTLR_EL1: %"PRIregister"\n", ctxt->sctlr_el1); - printk(" TCR_EL1: %08"PRIregister"\n", ctxt->tcr_el1); + printk(" TCR_EL1: %"PRIregister"\n", ctxt->tcr_el1); printk(" TTBR0_EL1: %016"PRIx64"\n", ctxt->ttbr0_el1); printk(" TTBR1_EL1: %016"PRIx64"\n", ctxt->ttbr1_el1); printk("\n"); @@ -934,7 +934,7 @@ static void _show_registers(const struct cpu_user_regs *regs, printk("\n"); printk(" SCTLR_EL2: %08"PRIx32"\n", READ_SYSREG32(SCTLR_EL2)); - printk(" HCR_EL2: %016"PRIregister"\n", READ_SYSREG(HCR_EL2)); + printk(" HCR_EL2: %"PRIregister"\n", READ_SYSREG(HCR_EL2)); printk(" TTBR0_EL2: %016"PRIx64"\n", READ_SYSREG64(TTBR0_EL2)); printk("\n"); printk(" ESR_EL2: %08"PRIx32"\n", regs->hsr); diff --git a/xen/include/asm-arm/types.h b/xen/include/asm-arm/types.h index 30f95078cb..89aae25ffe 100644 --- a/xen/include/asm-arm/types.h +++ b/xen/include/asm-arm/types.h @@ -41,7 +41,7 @@ typedef u64 paddr_t; #define INVALID_PADDR (~0ULL) #define PRIpaddr "016llx" typedef u32 register_t; -#define PRIregister "x" +#define PRIregister "08x" #elif defined (CONFIG_ARM_64) typedef signed long s64; typedef unsigned long u64; @@ -51,7 +51,7 @@ typedef u64 paddr_t; #define INVALID_PADDR (~0UL) #define PRIpaddr "016lx" typedef u64 register_t; -#define PRIregister "lx" +#define PRIregister "016lx" #endif #if defined(__SIZE_TYPE__)