From patchwork Tue Sep 19 11:59:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephan Gerhold X-Patchwork-Id: 725174 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0F190CD54B9 for ; Tue, 19 Sep 2023 12:00:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229772AbjISMAF (ORCPT ); Tue, 19 Sep 2023 08:00:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60226 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229552AbjISMAF (ORCPT ); Tue, 19 Sep 2023 08:00:05 -0400 Received: from mx.kernkonzept.com (serv1.kernkonzept.com [IPv6:2a01:4f8:1c1c:b490::2]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9BEC6F3; Tue, 19 Sep 2023 04:59:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=kernkonzept.com; s=mx1; h=Cc:To:In-Reply-To:References:Message-Id: Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date:From: Reply-To:Content-ID:Content-Description; bh=ffq0+SGQ8MUyYv3w6IpPZxS0q3DMyt6jN+7SxiKE6GE=; b=h4XzlwIRhiYBdzseaguyIujdfD W0inlorb+nsWhFe+7Cg7EYSihkirHCVsbkhk9/uVrYbABXUupX2AensJOgWtSTHSdLu0etROnDxwv QeVnIrdamJNS1SlXLtdZ5ALZAviHRCN9S045FUopzdbQeH3e/6zAfneYMVvWoNu5SrOI8XQD7SS4l MzOZXjjv3Xqod5dA7iDD9sTPvpWn3Qwk4GI7NLHtCQaXXUevsMEgN8C3Ki4CT8R5LardtukmKaHOj Apyc+zh3St92vYI1AIomGYUDFk596doTu0GeE9iK3ZVXXTwArwLdvLuZSJokMTwGmGSefG5fp9BF9 V6VMLpcg==; Received: from [10.22.3.24] (helo=serv1.dd1.int.kernkonzept.com) by mx.kernkonzept.com with esmtpsa (TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim 4.96) id 1qiZOV-004b4T-1G; Tue, 19 Sep 2023 13:59:55 +0200 From: Stephan Gerhold Date: Tue, 19 Sep 2023 13:59:48 +0200 Subject: [PATCH v2 1/4] spi: dt-bindings: qup: Document power-domains and OPP MIME-Version: 1.0 Message-Id: <20230919-spi-qup-dvfs-v2-1-1bac2e9ab8db@kernkonzept.com> References: <20230919-spi-qup-dvfs-v2-0-1bac2e9ab8db@kernkonzept.com> In-Reply-To: <20230919-spi-qup-dvfs-v2-0-1bac2e9ab8db@kernkonzept.com> To: Mark Brown Cc: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Stephan Gerhold , Krzysztof Kozlowski X-Mailer: b4 0.12.3 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Document power-domains and operating-points-v2 to allow making performance state votes for certain clock frequencies of the SPI QUP controller. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Stephan Gerhold --- Documentation/devicetree/bindings/spi/qcom,spi-qup.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-qup.yaml b/Documentation/devicetree/bindings/spi/qcom,spi-qup.yaml index 93f14dd01afc..1e498a791406 100644 --- a/Documentation/devicetree/bindings/spi/qcom,spi-qup.yaml +++ b/Documentation/devicetree/bindings/spi/qcom,spi-qup.yaml @@ -47,6 +47,11 @@ properties: interrupts: maxItems: 1 + operating-points-v2: true + + power-domains: + maxItems: 1 + reg: maxItems: 1 @@ -63,6 +68,7 @@ examples: - | #include #include + #include spi@7575000 { compatible = "qcom,spi-qup-v2.2.1"; @@ -76,6 +82,8 @@ examples: pinctrl-1 = <&blsp1_spi1_sleep>; dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; dma-names = "tx", "rx"; + power-domains = <&rpmpd MSM8996_VDDCX>; + operating-points-v2 = <&spi_opp_table>; #address-cells = <1>; #size-cells = <0>; }; From patchwork Tue Sep 19 11:59:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephan Gerhold X-Patchwork-Id: 725173 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1B7B5EED612 for ; Tue, 19 Sep 2023 12:00:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230331AbjISMAG (ORCPT ); Tue, 19 Sep 2023 08:00:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60242 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229853AbjISMAF (ORCPT ); Tue, 19 Sep 2023 08:00:05 -0400 Received: from mx.kernkonzept.com (serv1.kernkonzept.com [IPv6:2a01:4f8:1c1c:b490::2]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 972F1E3; Tue, 19 Sep 2023 04:59:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=kernkonzept.com; s=mx1; h=Cc:To:In-Reply-To:References:Message-Id: Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date:From: Reply-To:Content-ID:Content-Description; bh=7Gt4TKjLSJcXOSLnXDaTB2+6o7ALKK+hltx0sbV1x1k=; b=pMDkiW9exbVAQG4r2+8jAeOpkh d20oAnv9G45lYOiYcJHFKl3l1Fs1RKNNNZ+5/iBHEnRWxhJtHEe7+uyx1sB6p4DldiJ2n8XAxXzg6 37kVueDxjq/Wm8IsJxz5j36P8GM7E3vy7dIdMPIxNynUqi+YD8eLR8Ew3fiubq847I/2w7QlF9iqF KfluCoEnHsYdEpwNCHb1Im8+jEjodiSGnWy9yWBFLNIbh/HspBCqx/rAns+e3stYK1RySc2E9yXDb Rz1bNzn7d1hLHBZIjo9+zzfq8PQ+y8wqi9INOUY+fwd+ioKT7sww9r+driM5UN3MajdA3+3kXEcXx BsVbYx2w==; Received: from [10.22.3.24] (helo=serv1.dd1.int.kernkonzept.com) by mx.kernkonzept.com with esmtpsa (TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim 4.96) id 1qiZOW-004b4T-28; Tue, 19 Sep 2023 13:59:56 +0200 From: Stephan Gerhold Date: Tue, 19 Sep 2023 13:59:49 +0200 Subject: [PATCH v2 2/4] spi: qup: Parse OPP table for DVFS support MIME-Version: 1.0 Message-Id: <20230919-spi-qup-dvfs-v2-2-1bac2e9ab8db@kernkonzept.com> References: <20230919-spi-qup-dvfs-v2-0-1bac2e9ab8db@kernkonzept.com> In-Reply-To: <20230919-spi-qup-dvfs-v2-0-1bac2e9ab8db@kernkonzept.com> To: Mark Brown Cc: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Stephan Gerhold X-Mailer: b4 0.12.3 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Parse the OPP table from the device tree and use dev_pm_opp_set_rate() instead of clk_set_rate() to allow making performance state for power domains specified in the OPP table. This is needed to guarantee correct behavior of the clock, especially with the higher clock/SPI bus frequencies. Acked-by: Konrad Dybcio Signed-off-by: Stephan Gerhold --- drivers/spi/spi-qup.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c index 4b6f6b25219b..bf043be3a2a9 100644 --- a/drivers/spi/spi-qup.c +++ b/drivers/spi/spi-qup.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -667,7 +668,7 @@ static int spi_qup_io_prep(struct spi_device *spi, struct spi_transfer *xfer) return -EIO; } - ret = clk_set_rate(controller->cclk, xfer->speed_hz); + ret = dev_pm_opp_set_rate(controller->dev, xfer->speed_hz); if (ret) { dev_err(controller->dev, "fail to set frequency %d", xfer->speed_hz); @@ -1027,6 +1028,15 @@ static int spi_qup_probe(struct platform_device *pdev) return -ENXIO; } + ret = devm_pm_opp_set_clkname(dev, "core"); + if (ret) + return ret; + + /* OPP table is optional */ + ret = devm_pm_opp_of_add_table(dev); + if (ret && ret != -ENODEV) + return dev_err_probe(dev, ret, "invalid OPP table\n"); + host = spi_alloc_host(dev, sizeof(struct spi_qup)); if (!host) { dev_err(dev, "cannot allocate host\n"); From patchwork Tue Sep 19 11:59:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephan Gerhold X-Patchwork-Id: 724634 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3136CD5BA0 for ; Tue, 19 Sep 2023 12:00:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230428AbjISMAI (ORCPT ); Tue, 19 Sep 2023 08:00:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60244 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230385AbjISMAH (ORCPT ); Tue, 19 Sep 2023 08:00:07 -0400 Received: from mx.kernkonzept.com (serv1.kernkonzept.com [IPv6:2a01:4f8:1c1c:b490::2]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 82A23F4; Tue, 19 Sep 2023 05:00:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=kernkonzept.com; s=mx1; h=Cc:To:In-Reply-To:References:Message-Id: Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date:From: Reply-To:Content-ID:Content-Description; bh=UFT/kNZvjITibF9Ff1wzT/ZwHXknsQ9chPcc6jD+0QE=; b=G+bxTuqmExwrQpdM49OLK/Ndyz TuRMp1GDp4s7+GmK/4tta+YNWsJn/ttbIoouCGf5KPpNeZxAYBzzebBAhIvPe1wTtZHiVOC9Z0CnT NByoiuEpEOG388I1ZUW/QINNh6No9njhSH9uHtYRORenz7fmKoIR9qNHGSEJ0nP/0SEejSpi5dfUZ ztbCGiWrN5KMyL3/3SGMGrBd3jfpESCkRhH1AaG3PJw9QLuSfG+mB4Y54LqdDnSoki/KDn0iAzke+ pFGHQw1fl/jBef+cNbMg0YSV9jxeR6Yk0XvbqujvNqdCzEEclKLen3IEbwqqUTmA5txG/jqGKPQqs r1LaEQrA==; Received: from [10.22.3.24] (helo=serv1.dd1.int.kernkonzept.com) by mx.kernkonzept.com with esmtpsa (TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim 4.96) id 1qiZOY-004b4T-11; Tue, 19 Sep 2023 13:59:58 +0200 From: Stephan Gerhold Date: Tue, 19 Sep 2023 13:59:50 +0200 Subject: [PATCH v2 3/4] spi: dt-bindings: qup: Document interconnects MIME-Version: 1.0 Message-Id: <20230919-spi-qup-dvfs-v2-3-1bac2e9ab8db@kernkonzept.com> References: <20230919-spi-qup-dvfs-v2-0-1bac2e9ab8db@kernkonzept.com> In-Reply-To: <20230919-spi-qup-dvfs-v2-0-1bac2e9ab8db@kernkonzept.com> To: Mark Brown Cc: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Stephan Gerhold , Krzysztof Kozlowski X-Mailer: b4 0.12.3 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org When the SPI QUP controller is used together with a DMA engine it needs to vote for the interconnect path to the DRAM. Otherwise it may be unable to access the memory quickly enough. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Stephan Gerhold --- Documentation/devicetree/bindings/spi/qcom,spi-qup.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-qup.yaml b/Documentation/devicetree/bindings/spi/qcom,spi-qup.yaml index 1e498a791406..88be13268962 100644 --- a/Documentation/devicetree/bindings/spi/qcom,spi-qup.yaml +++ b/Documentation/devicetree/bindings/spi/qcom,spi-qup.yaml @@ -44,6 +44,9 @@ properties: - const: tx - const: rx + interconnects: + maxItems: 1 + interrupts: maxItems: 1 @@ -67,6 +70,7 @@ unevaluatedProperties: false examples: - | #include + #include #include #include @@ -84,6 +88,7 @@ examples: dma-names = "tx", "rx"; power-domains = <&rpmpd MSM8996_VDDCX>; operating-points-v2 = <&spi_opp_table>; + interconnects = <&pnoc MASTER_BLSP_1 &bimc SLAVE_EBI_CH0>; #address-cells = <1>; #size-cells = <0>; }; From patchwork Tue Sep 19 11:59:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephan Gerhold X-Patchwork-Id: 725172 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 414EACD5BA1 for ; Tue, 19 Sep 2023 12:00:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231317AbjISMAN (ORCPT ); Tue, 19 Sep 2023 08:00:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60254 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230469AbjISMAJ (ORCPT ); Tue, 19 Sep 2023 08:00:09 -0400 Received: from mx.kernkonzept.com (serv1.kernkonzept.com [IPv6:2a01:4f8:1c1c:b490::2]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 89987F7; Tue, 19 Sep 2023 05:00:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=kernkonzept.com; s=mx1; h=Cc:To:In-Reply-To:References:Message-Id: Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date:From: Reply-To:Content-ID:Content-Description; bh=UyKwlUDaiF86KyNIUUsDgQd4DUj+MPMX/4UCY0BXI9Y=; b=REBqlop70cSboq5iJNGVHKCeGW 6XxFjt4uD+NCxBn3zPI5ruKbModWdn68BfW3J2lF77MW5o/Wcv6iXtU36fYuBIv57Z1A+M0XAooSU ADY5wDJw875gcegSY3FTuZXPPXOn4wYEbcsA8/StbpPXdPh+Gsu0JC/IDHWeXjnHW1zu/cbtWkijw Drq9SSlN4YQLGCbHS0zlYjcDj/X5+gKcHjGGmxDCuG7wSGJLtRdFs9+Aea5dP8Jz5oL+PAr8OYJjT S+rowje+lrrFPAVJyWs00XtHryNeg+ydBxpxrHctOL8NWqvzspH1GYvmqy/cth6YXpYqro4p/fAud 4lZX4IdQ==; Received: from [10.22.3.24] (helo=serv1.dd1.int.kernkonzept.com) by mx.kernkonzept.com with esmtpsa (TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim 4.96) id 1qiZOZ-004b4T-1o; Tue, 19 Sep 2023 13:59:59 +0200 From: Stephan Gerhold Date: Tue, 19 Sep 2023 13:59:51 +0200 Subject: [PATCH v2 4/4] spi: qup: Vote for interconnect bandwidth to DRAM MIME-Version: 1.0 Message-Id: <20230919-spi-qup-dvfs-v2-4-1bac2e9ab8db@kernkonzept.com> References: <20230919-spi-qup-dvfs-v2-0-1bac2e9ab8db@kernkonzept.com> In-Reply-To: <20230919-spi-qup-dvfs-v2-0-1bac2e9ab8db@kernkonzept.com> To: Mark Brown Cc: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Stephan Gerhold X-Mailer: b4 0.12.3 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org When the SPI QUP controller is used together with a DMA engine it needs to vote for the interconnect path to the DRAM. Otherwise it may be unable to access the memory quickly enough. The requested peak bandwidth is dependent on the SPI core/bus clock so that the bandwidth scales together with the selected SPI speed. To avoid sending votes too often the bandwidth is always requested when a DMA transfer starts, but dropped only on runtime suspend. Runtime suspend should only happen if no transfer is active. After resumption we can defer the next vote until the first DMA transfer actually happens. Signed-off-by: Stephan Gerhold --- The bandwidth calculation is taken over from Qualcomm's downstream/vendor driver [1]. Due to lack of documentation about the interconnect setup/behavior I cannot say exactly if this is right. Unfortunately, this is not implemented very consistently downstream... [1]: https://git.codelinaro.org/clo/la/kernel/msm-3.18/-/commit/deca0f346089d32941d6d8194ae9605554486413 --- drivers/spi/spi-qup.c | 38 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c index bf043be3a2a9..2af63040ac6e 100644 --- a/drivers/spi/spi-qup.c +++ b/drivers/spi/spi-qup.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -122,11 +123,14 @@ #define SPI_DELAY_THRESHOLD 1 #define SPI_DELAY_RETRY 10 +#define SPI_BUS_WIDTH 8 + struct spi_qup { void __iomem *base; struct device *dev; struct clk *cclk; /* core clock */ struct clk *iclk; /* interface clock */ + struct icc_path *icc_path; /* interconnect to RAM */ int irq; spinlock_t lock; @@ -149,6 +153,8 @@ struct spi_qup { int mode; struct dma_slave_config rx_conf; struct dma_slave_config tx_conf; + + u32 bw_speed_hz; }; static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer); @@ -181,6 +187,23 @@ static inline bool spi_qup_is_valid_state(struct spi_qup *controller) return opstate & QUP_STATE_VALID; } +static int spi_qup_vote_bw(struct spi_qup *controller, u32 speed_hz) +{ + u32 needed_peak_bw; + int ret; + + if (controller->bw_speed_hz == speed_hz) + return 0; + + needed_peak_bw = Bps_to_icc(speed_hz * SPI_BUS_WIDTH); + ret = icc_set_bw(controller->icc_path, 0, needed_peak_bw); + if (ret) + return ret; + + controller->bw_speed_hz = speed_hz; + return 0; +} + static int spi_qup_set_state(struct spi_qup *controller, u32 state) { unsigned long loop; @@ -451,6 +474,12 @@ static int spi_qup_do_dma(struct spi_device *spi, struct spi_transfer *xfer, struct scatterlist *tx_sgl, *rx_sgl; int ret; + ret = spi_qup_vote_bw(qup, xfer->speed_hz); + if (ret) { + dev_err(qup->dev, "fail to vote for ICC bandwidth: %d\n", ret); + return -EIO; + } + if (xfer->rx_buf) rx_done = spi_qup_dma_done; else if (xfer->tx_buf) @@ -994,6 +1023,7 @@ static void spi_qup_set_cs(struct spi_device *spi, bool val) static int spi_qup_probe(struct platform_device *pdev) { struct spi_controller *host; + struct icc_path *icc_path; struct clk *iclk, *cclk; struct spi_qup *controller; struct resource *res; @@ -1019,6 +1049,11 @@ static int spi_qup_probe(struct platform_device *pdev) if (IS_ERR(iclk)) return PTR_ERR(iclk); + icc_path = devm_of_icc_get(dev, NULL); + if (IS_ERR(icc_path)) + return dev_err_probe(dev, PTR_ERR(icc_path), + "failed to get interconnect path\n"); + /* This is optional parameter */ if (of_property_read_u32(dev->of_node, "spi-max-frequency", &max_freq)) max_freq = SPI_MAX_RATE; @@ -1070,6 +1105,7 @@ static int spi_qup_probe(struct platform_device *pdev) controller->base = base; controller->iclk = iclk; controller->cclk = cclk; + controller->icc_path = icc_path; controller->irq = irq; ret = spi_qup_init_dma(host, res->start); @@ -1190,6 +1226,7 @@ static int spi_qup_pm_suspend_runtime(struct device *device) writel_relaxed(config, controller->base + QUP_CONFIG); clk_disable_unprepare(controller->cclk); + spi_qup_vote_bw(controller, 0); clk_disable_unprepare(controller->iclk); return 0; @@ -1241,6 +1278,7 @@ static int spi_qup_suspend(struct device *device) return ret; clk_disable_unprepare(controller->cclk); + spi_qup_vote_bw(controller, 0); clk_disable_unprepare(controller->iclk); return 0; }