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[178.235.177.23]) by smtp.gmail.com with ESMTPSA id f19-20020a056402151300b0053090e2afafsm7020643edw.22.2023.09.26.11.24.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Sep 2023 11:24:42 -0700 (PDT) From: Konrad Dybcio Date: Tue, 26 Sep 2023 20:24:36 +0200 Subject: [PATCH 1/7] drm/msm/a6xx: Fix unknown speedbin case Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20230926-topic-a643-v1-1-7af6937ac0a3@linaro.org> References: <20230926-topic-a643-v1-0-7af6937ac0a3@linaro.org> In-Reply-To: <20230926-topic-a643-v1-0-7af6937ac0a3@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , cros-qcom-dts-watchers@chromium.org, Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Stephen Boyd , Akhil P Oommen Cc: Marijn Suijten , Luca Weiss , Rob Clark , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1695752677; l=1465; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=3B0yIPSygi0wMpl7xpS+ZhhsZWi7J9UA34HRlycQuyk=; b=Iu9f1ructFVGASge8ugqNeXgxQC0RA2BFUwle16+fVrgAArXS0bQ1QC4HXS8kP4G+m1Yn6duX ykCLE1FvC4ZB+qXAkv5ObgAqFPAY+KWSMuSl/qkqVw74fcluxKFF3Oe X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net When opp-supported-hw is present under an OPP node, but no form of opp_set_supported_hw() has been called, that OPP is ignored by the API and marked as unsupported. Before Commit c928a05e4415 ("drm/msm/adreno: Move speedbin mapping to device table"), an unknown speedbin would result in marking all OPPs as available, but it's better to avoid potentially overclocking the silicon - the GMU will simply refuse to power up the chip. Currently, the Adreno speedbin code does just that (AND returns an invalid error, (int)UINT_MAX). Fix that by defaulting to speedbin 0 (which is conveniently always bound to fuseval == 0). Fixes: c928a05e4415 ("drm/msm/adreno: Move speedbin mapping to device table") Signed-off-by: Konrad Dybcio Reviewed-by: Akhil P Oommen --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index d4e85e24002f..522ca7fe6762 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2237,7 +2237,7 @@ static int a6xx_set_supported_hw(struct device *dev, const struct adreno_info *i DRM_DEV_ERROR(dev, "missing support for speed-bin: %u. Some OPPs may not be supported by hardware\n", speedbin); - return UINT_MAX; + supp_hw = BIT(0); /* Default */ } ret = devm_pm_opp_set_supported_hw(dev, &supp_hw, 1); From patchwork Tue Sep 26 18:24:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 726496 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 55D3E42BFA for ; Tue, 26 Sep 2023 18:24:49 +0000 (UTC) Received: from mail-ed1-x52c.google.com (mail-ed1-x52c.google.com [IPv6:2a00:1450:4864:20::52c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D5CF3126 for ; Tue, 26 Sep 2023 11:24:47 -0700 (PDT) Received: by mail-ed1-x52c.google.com with SMTP id 4fb4d7f45d1cf-53447d0241eso4042875a12.3 for ; Tue, 26 Sep 2023 11:24:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1695752686; x=1696357486; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=1mXLi+0rIXccn25x+LJrv2RkBxKqdDr4aU+Gv5GVsoM=; b=qvdlTL4BzurGFCOGcZshuDnvSoaEC9Mq/N+iKHOo4GKJkciE5GyDteT1HiOH6cnNdS nU2G4VfEPPWJcotzqBtm52lE+xkBacPjXscnEZ/jfgXIMMeSQJeTpxmNV4jQ5FM/oQLe RAht6h1kgw0wDtNosz2Epv7oLPmzdngwgIhJwMv6bnkEY561e2Tgl2e1Y5SE9+HE8bT6 Arbep1HaJaAU5vBy6WXgUjPQDEXZFtUEP2t2uqXrB7Mqbmh2uBPLXGV6wGIEYhq8uIlT yFsgqVm2+9ZZy3mCZIAvShjXXA/CeG1P/gElwVML657qUEMXj0zX3p1rubG8ii76HR8h Tj6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695752686; x=1696357486; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1mXLi+0rIXccn25x+LJrv2RkBxKqdDr4aU+Gv5GVsoM=; b=luJkFlSoNv1vnxarjifSP6xe0yU+1jP/pjRPk4LH3A1hGfpCfBJaRrfsHpjBcarVFb r92u/O2JyLUXNB1C6kiIz9DbS2J2gzrRmq3ftzyVP7/4bgaK25CZ3CvYdsVN/9x5+96m NkIUL76xyvTGSij+HGtiA9XdF5GqbIPEhkipw3ddPghsM4NhGwS00TAG3rJZmGBfmD68 jhKWwBVbJik3H6ZQOzCTDLWJjMTzTSCTOsC8L7lO7BaxLfeWaT/+Np2kRFRznnVUTkDi eR9LJ23+EbZgesV/I0V5JSxsR66hj3MubO1i3woFe62Oy3xGdhIbZVVMg8mXkA5lID/L 65Dw== X-Gm-Message-State: AOJu0YyBIPqXiwbM03kvph1q+FJGCBR4WDynC4QwtzXYGKrNeffVqTNc Kdeydc94qDU4XW/xOls/Nn94ZA== X-Google-Smtp-Source: AGHT+IGh0ktD94Pk4wwsYiXRvrPoEyd0YO/XrDphwvk3G5mbEos4//shaUTYKbj122Zo01fAUAE68Q== X-Received: by 2002:aa7:d7c7:0:b0:51e:53eb:88a3 with SMTP id e7-20020aa7d7c7000000b0051e53eb88a3mr8851616eds.25.1695752686393; Tue, 26 Sep 2023 11:24:46 -0700 (PDT) Received: from [10.167.154.1] (178235177023.dynamic-4-waw-k-1-1-0.vectranet.pl. [178.235.177.23]) by smtp.gmail.com with ESMTPSA id f19-20020a056402151300b0053090e2afafsm7020643edw.22.2023.09.26.11.24.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Sep 2023 11:24:46 -0700 (PDT) From: Konrad Dybcio Date: Tue, 26 Sep 2023 20:24:38 +0200 Subject: [PATCH 3/7] drm/msm/adreno: Add A635 speedbin 0xac (A643) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20230926-topic-a643-v1-3-7af6937ac0a3@linaro.org> References: <20230926-topic-a643-v1-0-7af6937ac0a3@linaro.org> In-Reply-To: <20230926-topic-a643-v1-0-7af6937ac0a3@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , cros-qcom-dts-watchers@chromium.org, Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Stephen Boyd , Akhil P Oommen Cc: Marijn Suijten , Luca Weiss , Rob Clark , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1695752677; l=751; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=4Rw51EV+m1pbTmR00ftxlMR26PkphHnsyFSR2kZ1LeI=; b=SXUVrGfcSRMs/58bky5kYAUilsScEIoXeRRt6NDpibqMT9twn8G3KlhPx8o0SOlAHp7e6EZAZ ljAxQUAiqQsAsx7kSjWbCIUQoLnRFJOt84DDBQzWxWuw9V//8Y+N+Ur X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Downstream calls this the "speedbin 1", but that number is already occupied. Use index two. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/adreno_device.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index 16527fe8584d..4977fd759b5b 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -460,6 +460,7 @@ static const struct adreno_info gpulist[] = { .speedbins = ADRENO_SPEEDBINS( { 0, 0 }, { 117, 0 }, + { 172, 2 }, /* Called speedbin 1 downstream, but let's not break things! */ { 190, 1 }, ), }, { From patchwork Tue Sep 26 18:24:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 726495 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1AF5642BFA for ; Tue, 26 Sep 2023 18:24:54 +0000 (UTC) Received: from mail-lf1-x129.google.com (mail-lf1-x129.google.com [IPv6:2a00:1450:4864:20::129]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 92724120 for ; Tue, 26 Sep 2023 11:24:52 -0700 (PDT) Received: by mail-lf1-x129.google.com with SMTP id 2adb3069b0e04-50437c618b4so12900492e87.2 for ; Tue, 26 Sep 2023 11:24:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1695752691; x=1696357491; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=JSsmJJyHe36J6r6QQN8EBPervMH/lsHyGZmLHEQGT3w=; b=qRef7QQ4Y0aE/PfLnNoJhKKwy3B2TYzDdfrvuoUXh3IbUnkdzfkGyGIcQKjQqGeQ3Q wu4SEEUCpIhGJEttpiLU9ngucPS+xS0ifvAo4uVZGeJ6Kc7XruNokiJkEWrn1sLU2bUb 0XPPMvT5S0m8nmY1dBRMq09Qss89sJ9Qv7MKrx4DpMIUq62Ov4yuftKLV/IPgFwlY6VC D8ZJH/VTqJVKA9Lqa9wMm/5Kdm9otCjxo/hJe9g+NptWcRe1nGV2ULiqy6DOWFLV1dqx /bLLJHYQn6OYWoEz4fHcwmF3x/erOoW0GEQdF1dWmbnfOrpwvzGy10dDqzys5cukkwUR zKDA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695752691; x=1696357491; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JSsmJJyHe36J6r6QQN8EBPervMH/lsHyGZmLHEQGT3w=; b=DZ4FlHsoFQm0FbOX37I4TrXFKzjss5ZVWf7Tqh68po+kfclGFItADYniYztteLHAaK 76CuxrLH5i503VGZ/jzvLXzjJ3DA1KCCE9LxE9yBwtgcApR2C3buV/KFC+YKCKtPAM+P Jxj4myOwAYFdNrn8NEuro/v2yQvMxfGryaFyt7x5kZeBGyvEzxcOyEmq94eDrDi+e8PX v9Uxd6IW0xTKgiYV5vZ9Kke4sWct5MHZsXQ6BFSOUDKq6e55u1XFLAiPEhHOepPN8HpV G09s7r6soUTXdn80dhY28U6AvzvAsc9eONFpnIFeFB15IjFYFa2rg3aP22mYeV75KTyE WIJg== X-Gm-Message-State: AOJu0YwM1AWGgWqzbOfgYFGXJhlnDCD9/1VK7bzbBa51bfg/2ey8aT95 unHmRHw4gB4CEQgphNMyFjdycg== X-Google-Smtp-Source: AGHT+IFxdFFgpcBTFxSLcZfqdtgfPTF/TNGZldeq7ysgqWnx8RGOLQ5gHMDX+UzFDSjdg3j002TJ9A== X-Received: by 2002:ac2:53ac:0:b0:503:2877:67e3 with SMTP id j12-20020ac253ac000000b00503287767e3mr8396426lfh.6.1695752690659; Tue, 26 Sep 2023 11:24:50 -0700 (PDT) Received: from [10.167.154.1] (178235177023.dynamic-4-waw-k-1-1-0.vectranet.pl. [178.235.177.23]) by smtp.gmail.com with ESMTPSA id f19-20020a056402151300b0053090e2afafsm7020643edw.22.2023.09.26.11.24.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Sep 2023 11:24:50 -0700 (PDT) From: Konrad Dybcio Date: Tue, 26 Sep 2023 20:24:40 +0200 Subject: [PATCH 5/7] arm64: dts: qcom: sc7280: Fix up GPU SIDs Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20230926-topic-a643-v1-5-7af6937ac0a3@linaro.org> References: <20230926-topic-a643-v1-0-7af6937ac0a3@linaro.org> In-Reply-To: <20230926-topic-a643-v1-0-7af6937ac0a3@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , cros-qcom-dts-watchers@chromium.org, Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Stephen Boyd , Akhil P Oommen Cc: Marijn Suijten , Luca Weiss , Rob Clark , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1695752677; l=1149; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=OKCYVjhQ/19k9GeBxxh+l0sjJaWU5GkjdhxKB9u2/vs=; b=9SVEap5bj9/9iIFUrp99rqRpCkF1yJSJnavWYyJzILyjurm26Pij46Bw+/KnOwd6frqVCvagj hxwquK7i3gkByj7w1dl5dnEr24gj8ym5NJr5mweF32LNem2LLWjiRad X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net GPU_SMMU SID 1 is meant for Adreno LPAC (Low Priority Async Compute). On platforms that support it (in firmware), it is necessary to describe that link, or Adreno register access will hang the board. Add that and fix up the SMR mask of SID 0, which seems to have been copypasted from another SoC. Fixes: 96c471970b7b ("arm64: dts: qcom: sc7280: Add gpu support") Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index c38ddf267ef5..0d96d1454c49 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2603,7 +2603,8 @@ gpu: gpu@3d00000 { "cx_mem", "cx_dbgc"; interrupts = ; - iommus = <&adreno_smmu 0 0x401>; + iommus = <&adreno_smmu 0 0x400>, + <&adreno_smmu 1 0x400>; operating-points-v2 = <&gpu_opp_table>; qcom,gmu = <&gmu>; interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; From patchwork Tue Sep 26 18:24:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 726494 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 14C0D42BFA for ; Tue, 26 Sep 2023 18:24:58 +0000 (UTC) Received: from mail-ed1-x530.google.com (mail-ed1-x530.google.com [IPv6:2a00:1450:4864:20::530]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0A0501A5 for ; Tue, 26 Sep 2023 11:24:55 -0700 (PDT) Received: by mail-ed1-x530.google.com with SMTP id 4fb4d7f45d1cf-533d6a8d6b6so7580352a12.2 for ; Tue, 26 Sep 2023 11:24:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1695752694; x=1696357494; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=gcsTNpsjbN2SKqWT86OIi6rzpyQaQonBZGDEar8VbjY=; b=fzK/WDQr6gSfQrXmNn3vKUxX4OGgnfQ5Aac74bu5IC/6y29W15b6wJP85Qk+PCHB1i GwyuUItnpZFdqB30SGAr114DJPvr9SAOhyU1cuh1YLsD6kWshR4JYW7DC+0rz0fT/KxH 3zC2S3Ul5sekWqQsdoynbnzBjMVJy/CZ0yxzJod9iJXEDSZV1qcUe5jRj6UzHe21PDhO dDKiMNLweduxjk/PxsSoWH386R0OJ+Nb2O/p9HeJOQc1aIBNGGrYk0eqZ8cmcKcCN0Ep tEjnP4CSf9riQjfu9/2i7Sc2d4CQgVLzuU0xRoAVTQhEE6/QHhC1mCeKpJT6PMd+zBUG 3JLQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695752694; x=1696357494; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gcsTNpsjbN2SKqWT86OIi6rzpyQaQonBZGDEar8VbjY=; b=I4UoBSFws46cLtYnF0e6QoV4jxTpqRl9L5wRr/JEN8iTb5ix4yan5kMytcsyf39Q1C RWobx0tHxJAKeXlvZStUenfoIqOLJe1CHES3IqHl1BLDCJDHSKgQ8o8WHHpAtnK5F2ic 4rvgvNC/g+9Nu9LKL9A1X77WxjIiz2yA5nxct/l28oXaZZX6zgxHwvz/dtlBr9PxHhZ7 nays+2lWRHZzysdAT5inHMJdLysPcL4TbIbxEXOQwJK6x5vX8AULjxa+3KZ0k0q8QOZt RHyoyAPhiNf/ISCsIPqNe+rPdWZt97DxTymPJ7Yr+s1/pTOveHO+C39eVs50pLlKD+ma oeVw== X-Gm-Message-State: AOJu0YznsDjLz5FbLxAXToiA8feGlG+ZYoA802bn/4GWaKdx0MdED55r wth8WarSgJinG2rsNwqYPEpjug== X-Google-Smtp-Source: AGHT+IHSDS5XqFLTJ3Fj4mnDdxfJXQcOrG9mYsIt1RG52uxZWsc1JdF5u15aBVAjCYJy3NW7NDbP+g== X-Received: by 2002:aa7:da8b:0:b0:52a:66c0:1e9b with SMTP id q11-20020aa7da8b000000b0052a66c01e9bmr8454988eds.30.1695752694412; Tue, 26 Sep 2023 11:24:54 -0700 (PDT) Received: from [10.167.154.1] (178235177023.dynamic-4-waw-k-1-1-0.vectranet.pl. [178.235.177.23]) by smtp.gmail.com with ESMTPSA id f19-20020a056402151300b0053090e2afafsm7020643edw.22.2023.09.26.11.24.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Sep 2023 11:24:54 -0700 (PDT) From: Konrad Dybcio Date: Tue, 26 Sep 2023 20:24:42 +0200 Subject: [PATCH 7/7] arm64: dts: qcom: sc7280: Add 0xac Adreno speed bin Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20230926-topic-a643-v1-7-7af6937ac0a3@linaro.org> References: <20230926-topic-a643-v1-0-7af6937ac0a3@linaro.org> In-Reply-To: <20230926-topic-a643-v1-0-7af6937ac0a3@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , cros-qcom-dts-watchers@chromium.org, Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Stephen Boyd , Akhil P Oommen Cc: Marijn Suijten , Luca Weiss , Rob Clark , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1695752677; l=2100; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=9BePAqziunVu9kZivYgvv/caBkDoTl2qS9g1hj02Wgg=; b=DftHVsKPD4gXQnOXwv6J08JDe4kPe9q61Uq+Yk6OGVwbAalLbxGFp7JSs/NLklUN8hzuG4ORl P20Q6ZH69KsAaETW8eBjDpCidhznk2dyYWm7+g8ddSZevjirhjhF8yS X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net A643 (A635 speedbin 0xac) tops out at 812 MHz. Fill in the opp-supported-hw appropriately. Note that fuseval 0xac is referred to as speedbin 1 downstream, but that was already in use upstream, so 2 was chosen instead. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index edaca6c2cf8c..ccc2dd6c45de 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2626,14 +2626,14 @@ opp-315000000 { opp-hz = /bits/ 64 <315000000>; opp-level = ; opp-peak-kBps = <1804000>; - opp-supported-hw = <0x03>; + opp-supported-hw = <0x07>; }; opp-450000000 { opp-hz = /bits/ 64 <450000000>; opp-level = ; opp-peak-kBps = <4068000>; - opp-supported-hw = <0x03>; + opp-supported-hw = <0x07>; }; /* Only applicable for SKUs which has 550Mhz as Fmax */ @@ -2648,28 +2648,28 @@ opp-550000000-1 { opp-hz = /bits/ 64 <550000000>; opp-level = ; opp-peak-kBps = <6832000>; - opp-supported-hw = <0x02>; + opp-supported-hw = <0x06>; }; opp-608000000 { opp-hz = /bits/ 64 <608000000>; opp-level = ; opp-peak-kBps = <8368000>; - opp-supported-hw = <0x02>; + opp-supported-hw = <0x06>; }; opp-700000000 { opp-hz = /bits/ 64 <700000000>; opp-level = ; opp-peak-kBps = <8532000>; - opp-supported-hw = <0x02>; + opp-supported-hw = <0x06>; }; opp-812000000 { opp-hz = /bits/ 64 <812000000>; opp-level = ; opp-peak-kBps = <8532000>; - opp-supported-hw = <0x02>; + opp-supported-hw = <0x06>; }; opp-840000000 {