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[176.131.222.246]) by smtp.gmail.com with ESMTPSA id j16-20020a056000125000b00326f5d0ce0asm997037wrx.21.2023.10.03.01.27.37 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 03 Oct 2023 01:27:38 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Bernhard Beschow , Marcel Apfelbaum , Markus Armbruster , Richard Henderson , Peter Xu , Jason Wang , "Michael S. Tsirkin" , Eduardo Habkost , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 1/5] hw/intc/apic: Use ERRP_GUARD() in apic_common_realize() Date: Tue, 3 Oct 2023 10:27:24 +0200 Message-ID: <20231003082728.83496-2-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231003082728.83496-1-philmd@linaro.org> References: <20231003082728.83496-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=philmd@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org APICCommonClass::realize() is a DeviceRealize() handler which take an Error** parameter and can fail. Do not proceed further on failure. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Xu --- hw/intc/apic_common.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/hw/intc/apic_common.c b/hw/intc/apic_common.c index 68ad30e2f5..bccb4241c2 100644 --- a/hw/intc/apic_common.c +++ b/hw/intc/apic_common.c @@ -257,6 +257,7 @@ static const VMStateDescription vmstate_apic_common; static void apic_common_realize(DeviceState *dev, Error **errp) { + ERRP_GUARD(); APICCommonState *s = APIC_COMMON(dev); APICCommonClass *info; static DeviceState *vapic; @@ -267,6 +268,9 @@ static void apic_common_realize(DeviceState *dev, Error **errp) info = APIC_COMMON_GET_CLASS(s); info->realize(dev, errp); + if (*errp) { + return; + } /* Note: We need at least 1M to map the VAPIC option ROM */ if (!vapic && s->vapic_control & VAPIC_ENABLE_MASK && From patchwork Tue Oct 3 08:27:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 728719 Delivered-To: patch@linaro.org Received: by 2002:a5d:60c8:0:b0:31d:da82:a3b4 with SMTP id x8csp2032589wrt; Tue, 3 Oct 2023 01:28:38 -0700 (PDT) X-Google-Smtp-Source: AGHT+IG52nk/FH8yEkICXiq9Y8oVp3RQ+OCpqwPZaRBZWDQU3O8N33+jkFDDo1eag1rHfa86y8VJ X-Received: by 2002:a0c:e30e:0:b0:655:da42:b92a with SMTP id s14-20020a0ce30e000000b00655da42b92amr13836813qvl.13.1696321718049; Tue, 03 Oct 2023 01:28:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696321718; cv=none; d=google.com; s=arc-20160816; b=h00LE2EO0urPg9/FnBx8iO+FpK8lAbP/zGT+Spyvk410kEE1Z/p9RoxfuFmUL8br72 2VGDckmEaFDJ0iD3RbN2TBhWW1tUotTBPeGYCd12AXnUQ7ojFsq66rFcC0PPFCEuMtty bs8XEfzYjcQF/+ddv5v6wf4XkhM9uKu67XWc5AvTxyqZ3f5XDmONNBR9LMcB3XvuDxKu 6mp7DFZrx6TD7wZZOHjo9dGmq2A+Y/99hSAAy4G1y3LKlauKm2I/s1Z4qY4BhPZeUdrb vfPydP23lfJ8IGscm3k+2cDLgXmbFpqAtmNzJRekGJlQZIFZK/I60lubIribW8PiDyHD StQA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=+NncaZm4Rq7ypawzJ8HayEn0g0SZFapHip8wBEcGgdE=; fh=biB0OdKYuvljSiUGLVdYZIMuRed58bIG1HesIB1fX9c=; b=RZLx0ekfqEQs7F+vGRBFt6nkTzyUB4qiFpwC4QUdDeP3zt0KIF6KeZ/sMXJ8MbPAIx kVomzTO4f+HKW/JhOeUbV8Bs09ph+AGeExhgUK4NoYCPKhdYa7nF1e9OIv79Mb4ZYipP UWi2PCQILF9DEKzz4Lzr4GC3rc67XBUKfNhMr3aTcy1PrWMUymJSq3H/OXpqSJ8YzKy2 ryQudhu8+0uxU4oyLw22Eb1tGY1vGrapKWYgeLny5Gt5nsimGgY31N0+LwgkAS6Db7cz zTBnGZWq8WH4ay6r3Y9NUO629nzl3H+xGEIG9X2kXtr9CGOdlyxVSvBRXmRb3WaPQZ5a YkVA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="t82/BKoJ"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.131.222.246]) by smtp.gmail.com with ESMTPSA id p8-20020a1c7408000000b003fefcbe7fa8sm707360wmc.28.2023.10.03.01.27.44 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 03 Oct 2023 01:27:45 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Bernhard Beschow , Marcel Apfelbaum , Markus Armbruster , Richard Henderson , Peter Xu , Jason Wang , "Michael S. Tsirkin" , Eduardo Habkost , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 2/5] hw/i386/apic: Defer error check from apic_get_class to kvm_apic_realize Date: Tue, 3 Oct 2023 10:27:25 +0200 Message-ID: <20231003082728.83496-3-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231003082728.83496-1-philmd@linaro.org> References: <20231003082728.83496-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philmd@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org apic_get_class() isn't supposed to fail. kvm_apic_realize() is DeviceRealize() handler, which can fail. Defer the error check to the latter. Signed-off-by: Philippe Mathieu-Daudé --- hw/i386/kvm/apic.c | 5 +++++ target/i386/cpu-sysemu.c | 8 -------- 2 files changed, 5 insertions(+), 8 deletions(-) diff --git a/hw/i386/kvm/apic.c b/hw/i386/kvm/apic.c index 1e89ca0899..4883308247 100644 --- a/hw/i386/kvm/apic.c +++ b/hw/i386/kvm/apic.c @@ -228,6 +228,11 @@ static void kvm_apic_realize(DeviceState *dev, Error **errp) { APICCommonState *s = APIC_COMMON(dev); + if (!kvm_irqchip_in_kernel()) { + error_setg(errp, "KVM does not support userspace APIC"); + return; + } + memory_region_init_io(&s->io_memory, OBJECT(s), &kvm_apic_io_ops, s, "kvm-apic-msi", APIC_SPACE_SIZE); diff --git a/target/i386/cpu-sysemu.c b/target/i386/cpu-sysemu.c index 2375e48178..6a228c9178 100644 --- a/target/i386/cpu-sysemu.c +++ b/target/i386/cpu-sysemu.c @@ -253,10 +253,6 @@ APICCommonClass *apic_get_class(Error **errp) /* TODO: in-kernel irqchip for hvf */ if (kvm_enabled()) { - if (!kvm_irqchip_in_kernel()) { - error_setg(errp, "KVM does not support userspace APIC"); - return NULL; - } apic_type = "kvm-apic"; } else if (xen_enabled()) { apic_type = "xen-apic"; @@ -272,10 +268,6 @@ void x86_cpu_apic_create(X86CPU *cpu, Error **errp) APICCommonState *apic; APICCommonClass *apic_class = apic_get_class(errp); - if (!apic_class) { - return; - } - cpu->apic_state = DEVICE(object_new_with_class(OBJECT_CLASS(apic_class))); object_property_add_child(OBJECT(cpu), "lapic", OBJECT(cpu->apic_state)); From patchwork Tue Oct 3 08:27:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 728721 Delivered-To: patch@linaro.org Received: by 2002:a5d:60c8:0:b0:31d:da82:a3b4 with SMTP id x8csp2032683wrt; Tue, 3 Oct 2023 01:28:54 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGoSdPbwvSTbNUI/REmtgrdTqMWAVw+wYsezmTBEvFCXTg4/+U+WIvrLga3x9jd9vP9lukL X-Received: by 2002:a05:622a:453:b0:410:a2c4:d696 with SMTP id o19-20020a05622a045300b00410a2c4d696mr17579751qtx.35.1696321734467; Tue, 03 Oct 2023 01:28:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696321734; cv=none; d=google.com; s=arc-20160816; b=svyUnkXWsxl7vyXsFt5UUpyFhht35H+5h4Yyt8KDkltKGkV4LQxOs9++hR7PknzgAw eoyb4GfTuJUofO2mquGsqpVg9QdjfZhcdxoUlAEO+748sAA+cEpvQFq474mRSYQtjaK2 US2K1HyGZSkkQHsK+DlsBul9MPQmsO+AOjK4u/eT1i/vqI4E+qRjI8O/U1drRNAxjtJE W/AjH47ltqOT2j7yj/hoX/zwSkakKs/mbq64xfCZAuF4Rub/Nq6w09rdKoIfK9CjcS5o B7iV3ZwShuuwgDg3GDOE28DjP1gFe7dzdOJip7qAqY8KAe537K+E0S96LHC/05yTvBVm UxdA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=FLDFiGj6aFnMNrOsUcD90TH387DbLMzLOhHMLFfm8as=; fh=biB0OdKYuvljSiUGLVdYZIMuRed58bIG1HesIB1fX9c=; b=gfh1pxiqq+GJMBBj3mbhDYyCEAHqCOb/uo0B7ZnPkC4fDrdpgsgUtfeFby/efhlr1Q WHDPy8Rl24eitOd/g1PJnyTq7sP6f0O9F8qCiZdUogfJxp+WuxEZwa1OIqPmojsyNpJZ la45iibvezEJv4AdxeRWP9iWiGJFFCmkM8DbjYx9kEQ6Qn0+KVNqhMOg9DmEKyPOEm62 Bv1I4GvaMvOhyIYGDg3LBJjzvJxSABAQ0PSyx6HHZBNKxwmMBuwD4mJ4MTZH5pHawJCd VmQ/bvfybxX0xtpoWQ0lMm0oz6TkWXNWVpZakJVMS1a+5uDf1Nexa03NGravxselaL/4 McOA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CDs2ZZkw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.131.222.246]) by smtp.gmail.com with ESMTPSA id u19-20020a7bc053000000b003fefaf299b6sm698061wmc.38.2023.10.03.01.27.51 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 03 Oct 2023 01:27:52 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Bernhard Beschow , Marcel Apfelbaum , Markus Armbruster , Richard Henderson , Peter Xu , Jason Wang , "Michael S. Tsirkin" , Eduardo Habkost , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 3/5] hw/i386/apic: Simplify apic_get_class() Date: Tue, 3 Oct 2023 10:27:26 +0200 Message-ID: <20231003082728.83496-4-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231003082728.83496-1-philmd@linaro.org> References: <20231003082728.83496-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::12d; envelope-from=philmd@linaro.org; helo=mail-lf1-x12d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Now than apic_get_class() can not fail, remove its Error** parameter. It can't return NULL neither, so simplify x86_cpu_apic_create(). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Xu --- include/hw/i386/apic_internal.h | 2 +- hw/i386/amd_iommu.c | 2 +- hw/i386/intel_iommu.c | 4 ++-- target/i386/cpu-sysemu.c | 4 ++-- 4 files changed, 6 insertions(+), 6 deletions(-) diff --git a/include/hw/i386/apic_internal.h b/include/hw/i386/apic_internal.h index 5f2ba24bfc..e61ad04769 100644 --- a/include/hw/i386/apic_internal.h +++ b/include/hw/i386/apic_internal.h @@ -225,6 +225,6 @@ static inline int apic_get_bit(uint32_t *tab, int index) return !!(tab[i] & mask); } -APICCommonClass *apic_get_class(Error **errp); +APICCommonClass *apic_get_class(void); #endif /* QEMU_APIC_INTERNAL_H */ diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index c98a3c6e11..0a95025ab7 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -1368,7 +1368,7 @@ static MemTxResult amdvi_mem_ir_write(void *opaque, hwaddr addr, return MEMTX_ERROR; } - apic_get_class(NULL)->send_msi(&to); + apic_get_class()->send_msi(&to); trace_amdvi_mem_ir_write(to.address, to.data); return MEMTX_OK; diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 2c832ab68b..dffe3583bd 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -397,7 +397,7 @@ static void vtd_generate_interrupt(IntelIOMMUState *s, hwaddr mesg_addr_reg, trace_vtd_irq_generate(msi.address, msi.data); - apic_get_class(NULL)->send_msi(&msi); + apic_get_class()->send_msi(&msi); } /* Generate a fault event to software via MSI if conditions are met. @@ -3554,7 +3554,7 @@ static MemTxResult vtd_mem_ir_write(void *opaque, hwaddr addr, return MEMTX_ERROR; } - apic_get_class(NULL)->send_msi(&to); + apic_get_class()->send_msi(&to); return MEMTX_OK; } diff --git a/target/i386/cpu-sysemu.c b/target/i386/cpu-sysemu.c index 6a228c9178..9038c65267 100644 --- a/target/i386/cpu-sysemu.c +++ b/target/i386/cpu-sysemu.c @@ -247,7 +247,7 @@ void x86_cpu_machine_reset_cb(void *opaque) cpu_reset(CPU(cpu)); } -APICCommonClass *apic_get_class(Error **errp) +APICCommonClass *apic_get_class(void) { const char *apic_type = "apic"; @@ -266,7 +266,7 @@ APICCommonClass *apic_get_class(Error **errp) void x86_cpu_apic_create(X86CPU *cpu, Error **errp) { APICCommonState *apic; - APICCommonClass *apic_class = apic_get_class(errp); + APICCommonClass *apic_class = apic_get_class(); cpu->apic_state = DEVICE(object_new_with_class(OBJECT_CLASS(apic_class))); object_property_add_child(OBJECT(cpu), "lapic", From patchwork Tue Oct 3 08:27:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 728723 Delivered-To: patch@linaro.org Received: by 2002:a5d:60c8:0:b0:31d:da82:a3b4 with SMTP id x8csp2032754wrt; Tue, 3 Oct 2023 01:29:10 -0700 (PDT) X-Google-Smtp-Source: AGHT+IE3BigvnHij6189Q3y45whtZVPpiM86JySEV0LCrU6hmSKkkmCWU7Y+5gp4/AMIWJ8tmKL1 X-Received: by 2002:a0c:dd86:0:b0:64b:997f:5a73 with SMTP id v6-20020a0cdd86000000b0064b997f5a73mr13321642qvk.0.1696321750593; Tue, 03 Oct 2023 01:29:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696321750; cv=none; d=google.com; s=arc-20160816; b=F7Qp6WKtX51LwWT+NHW9ob5yUbD9WbSy7YlBXK5tC3mfUIEu7k0lb73bvw6hs/3VZf 5lGfBY4CVdjVnPvMiVT9EoorzUTVtt4j+kLbplkedflvdSsTH5wdkB5NKzafq4K29H80 5cA4OJPlxNWk3g8NV45BZtJ3V3dFpEt8A2OsAgmsTM/VmYr2eGMRfXKYLonKiGh3rM6o UDkN8e91wktB5O7QZMes9R2AjeRSYe5elvC93Dcto4Lqw0deJQbgYe2TkP9z7GJqwa6e KGvPmCph0Ssj3xWVf9rzdrUxv2RnoN/glfHEE13kzgM7VMPM0c/N0GanIf+Hpo7w73EM rCWA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=6tbksfbbfGHxqsqPubKWDwtMEoe2M3iP09KnCYcyqbI=; fh=biB0OdKYuvljSiUGLVdYZIMuRed58bIG1HesIB1fX9c=; b=ds41TNpdmMK9SXJPWIzQ2+xFqBPKOQUGxxnhLzxnODZj8b+DOMoQw/EL5KtnwOewh7 hMrJGxHSAkR3+Jo3OfDXU3E+Dwa8pA8veMmvpvuDiySoS9T41GOkNZpdVEF0+V5eiYR5 BWsfgV9MJlxImKPVNC3i/mpfH/6gScGxbPPC08/SSNTMujc5qMcBzvqaV1zDTk12w5Ke Tn6CHmxjrKKjmI4EAIQmZjCxuU/0RSOKuRLi8HaEhvNLBsLkvIzvld3W/TmLR9tQuTlY YbGb+SRtlUYu6CietKAgu81/0oDh7+R0Lxl3eSvsT9d+ryEZ4ctKPj4OPTJzX7Jh5FsW yULQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="QlI/w7/9"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.131.222.246]) by smtp.gmail.com with ESMTPSA id o3-20020a5d6843000000b003143867d2ebsm989890wrw.63.2023.10.03.01.27.58 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 03 Oct 2023 01:27:59 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Bernhard Beschow , Marcel Apfelbaum , Markus Armbruster , Richard Henderson , Peter Xu , Jason Wang , "Michael S. Tsirkin" , Eduardo Habkost , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 4/5] hw/intc/apic: Rename x86_cpu_apic_create() -> x86_cpu_apic_new() Date: Tue, 3 Oct 2023 10:27:27 +0200 Message-ID: <20231003082728.83496-5-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231003082728.83496-1-philmd@linaro.org> References: <20231003082728.83496-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=philmd@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org x86_cpu_apic_create()'s Error** parameter is unused, drop it. While there is no convention, QDev methods are usually named with _new() / _realize() suffixes. Rename as appropriate. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Xu --- target/i386/cpu-internal.h | 2 +- hw/intc/apic_common.c | 2 +- target/i386/cpu-sysemu.c | 2 +- target/i386/cpu.c | 5 +---- 4 files changed, 4 insertions(+), 7 deletions(-) diff --git a/target/i386/cpu-internal.h b/target/i386/cpu-internal.h index 9baac5c0b4..8299b347f7 100644 --- a/target/i386/cpu-internal.h +++ b/target/i386/cpu-internal.h @@ -62,7 +62,7 @@ GuestPanicInformation *x86_cpu_get_crash_info(CPUState *cs); void x86_cpu_get_crash_info_qom(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp); -void x86_cpu_apic_create(X86CPU *cpu, Error **errp); +void x86_cpu_apic_new(X86CPU *cpu); void x86_cpu_apic_realize(X86CPU *cpu, Error **errp); void x86_cpu_machine_reset_cb(void *opaque); #endif /* !CONFIG_USER_ONLY */ diff --git a/hw/intc/apic_common.c b/hw/intc/apic_common.c index bccb4241c2..8a79eacdb0 100644 --- a/hw/intc/apic_common.c +++ b/hw/intc/apic_common.c @@ -451,7 +451,7 @@ static void apic_common_class_init(ObjectClass *klass, void *data) dc->unrealize = apic_common_unrealize; /* * Reason: APIC and CPU need to be wired up by - * x86_cpu_apic_create() + * x86_cpu_apic_new() */ dc->user_creatable = false; } diff --git a/target/i386/cpu-sysemu.c b/target/i386/cpu-sysemu.c index 9038c65267..373dc6b1c7 100644 --- a/target/i386/cpu-sysemu.c +++ b/target/i386/cpu-sysemu.c @@ -263,7 +263,7 @@ APICCommonClass *apic_get_class(void) return APIC_COMMON_CLASS(object_class_by_name(apic_type)); } -void x86_cpu_apic_create(X86CPU *cpu, Error **errp) +void x86_cpu_apic_new(X86CPU *cpu) { APICCommonState *apic; APICCommonClass *apic_class = apic_get_class(); diff --git a/target/i386/cpu.c b/target/i386/cpu.c index ed72883bf3..69d56bae91 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7418,10 +7418,7 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp) qemu_register_reset(x86_cpu_machine_reset_cb, cpu); if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > 1) { - x86_cpu_apic_create(cpu, &local_err); - if (local_err != NULL) { - goto out; - } + x86_cpu_apic_new(cpu); } #endif From patchwork Tue Oct 3 08:27:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 728724 Delivered-To: patch@linaro.org Received: by 2002:a5d:60c8:0:b0:31d:da82:a3b4 with SMTP id x8csp2032881wrt; Tue, 3 Oct 2023 01:29:37 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHe9aA7RWVA4+Ex24QpJ7Qa8znYp/XACDcz1mEGzPpFhB2ILqc2oDycYd/RQ/bpVZ/fA1eZ X-Received: by 2002:a0c:b346:0:b0:65a:f5e3:5ac0 with SMTP id a6-20020a0cb346000000b0065af5e35ac0mr13957996qvf.51.1696321776880; Tue, 03 Oct 2023 01:29:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696321776; cv=none; d=google.com; s=arc-20160816; b=tdfOMGrWTab5lPZj3/bAn/ne8KpeGlsiuvlVrLCHQBlrNiYt/ercxUAqI7opjK2vVa rOXLwyRi8s9Sx6TENxTWYaLnPDkh5Y/kxQwih9joRptGAvzi9bPqGSz4hPdKDqflIpOe t6B9N/V2T3y9KdDx+KcnA+KjZiI/pr6sd9ejovE+sN3B6hzXAZV8PTL53r8rsPp3Btg5 WwOK88AuCyCgWRyXo4N8UzipwKFbrh1s3JFBeBgQDDt2+JyrGHkVN01lgtMwQ48slCVH 00BYWvbTGN7z6OLapuDd1mxwBtHFWvk5Gbl9wFNz8IaZHPO/dtGL0c8S8pqubHdXRZmp cH2Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=SqRKfDmguxU9p8cA86t//6SsyEhs/b5kalnp32Nd8Eo=; fh=biB0OdKYuvljSiUGLVdYZIMuRed58bIG1HesIB1fX9c=; b=P1A7IW1PmdOWMQrZ+K2/jw5spJnzksIDU8oZfQw01FZzgX42QlndRnWukqf4U3gEem HoNUef4yJGt47VnIfMAVO7JxO1nAyb5yPJfuc2blCyPwDS2yz5UCWfjhYY8aFXR75nVU kqA64mL0JEcUmMYlb+PV1yKHdcGEDCZth94vs/I5LO5zPyYwZgz/LMBBer6wQJk6BVAw czGiuUtpCvv07vVWnFhNWu9/LlSLfI+IgXMb9K78CMQOQBEpIhUt1KTas4MdiYNBYTIU l6cc4b536fzTXQYGaJawFeWmI/ss8LDFsiptca+xWg5nru7YsX0gPQ7QxzpkVGblkLoa nfNg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=uty5On1B; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.131.222.246]) by smtp.gmail.com with ESMTPSA id 9-20020a05600c234900b00405c7591b09sm701014wmq.35.2023.10.03.01.28.04 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 03 Oct 2023 01:28:05 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Bernhard Beschow , Marcel Apfelbaum , Markus Armbruster , Richard Henderson , Peter Xu , Jason Wang , "Michael S. Tsirkin" , Eduardo Habkost , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 5/5] hw/intc/apic: Pass CPU using QOM link property Date: Tue, 3 Oct 2023 10:27:28 +0200 Message-ID: <20231003082728.83496-6-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231003082728.83496-1-philmd@linaro.org> References: <20231003082728.83496-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::132; envelope-from=philmd@linaro.org; helo=mail-lf1-x132.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org QOM objects shouldn't access each other internals fields except using the QOM API. Declare the 'cpu' and 'base-addr' properties, set them using object_property_set_link() and qdev_prop_set_uint32() respectively. Since the _set_link() call can't fail, use &error_abort in case there is a programming error. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- hw/intc/apic_common.c | 2 ++ target/i386/cpu-sysemu.c | 9 ++++----- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/hw/intc/apic_common.c b/hw/intc/apic_common.c index 8a79eacdb0..be7cf3b332 100644 --- a/hw/intc/apic_common.c +++ b/hw/intc/apic_common.c @@ -398,6 +398,8 @@ static Property apic_properties_common[] = { true), DEFINE_PROP_BOOL("legacy-instance-id", APICCommonState, legacy_instance_id, false), + DEFINE_PROP_LINK("cpu", APICCommonState, cpu, TYPE_X86_CPU, X86CPU *), + DEFINE_PROP_UINT32("base-addr", APICCommonState, apicbase, 0), DEFINE_PROP_END_OF_LIST(), }; diff --git a/target/i386/cpu-sysemu.c b/target/i386/cpu-sysemu.c index 373dc6b1c7..b084706531 100644 --- a/target/i386/cpu-sysemu.c +++ b/target/i386/cpu-sysemu.c @@ -265,7 +265,6 @@ APICCommonClass *apic_get_class(void) void x86_cpu_apic_new(X86CPU *cpu) { - APICCommonState *apic; APICCommonClass *apic_class = apic_get_class(); cpu->apic_state = DEVICE(object_new_with_class(OBJECT_CLASS(apic_class))); @@ -273,11 +272,11 @@ void x86_cpu_apic_new(X86CPU *cpu) OBJECT(cpu->apic_state)); object_unref(OBJECT(cpu->apic_state)); + object_property_set_link(OBJECT(cpu->apic_state), "cpu", + OBJECT(cpu), &error_abort); qdev_prop_set_uint32(cpu->apic_state, "id", cpu->apic_id); - /* TODO: convert to link<> */ - apic = APIC_COMMON(cpu->apic_state); - apic->cpu = cpu; - apic->apicbase = APIC_DEFAULT_ADDRESS | MSR_IA32_APICBASE_ENABLE; + qdev_prop_set_uint32(cpu->apic_state, "base-addr", + APIC_DEFAULT_ADDRESS | MSR_IA32_APICBASE_ENABLE); } void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)