From patchwork Mon Oct 2 18:59:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 729052 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4174E1A719 for ; Mon, 2 Oct 2023 18:59:46 +0000 (UTC) Received: from mail-lf1-x12d.google.com (mail-lf1-x12d.google.com [IPv6:2a00:1450:4864:20::12d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2362ECE for ; Mon, 2 Oct 2023 11:59:44 -0700 (PDT) Received: by mail-lf1-x12d.google.com with SMTP id 2adb3069b0e04-50567477b29so30651e87.3 for ; Mon, 02 Oct 2023 11:59:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1696273182; x=1696877982; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=zXetwuwd7eyQ9A3g1yCGm8/1oY3jPgf1yMAkZGiV+mc=; b=SPkqjC6IJnIPlumbAYm4nu9q2TgH4/KlMAFeFaXF3nXK/lO1Cb7ObacoaNmJ0fYkID +2CWF7W4kWERi3dke9Bc7ga4bE7GvH/vr974woxskuqdw79/lIBvsj9tOfnvnzrl3S/F 7izcsyX8wIFk69U5Tto1Me4+R7FHUJLwhMJo+SloVLOSZgAVTYTjYRjxpBNA+/VYbTOV cNROSXJiDHK7nV7pC0CS9uMSLsDDI2MGbCGWRAQQ5JdEmqz53qMhvgjKOcZ9a0NFKBK6 t7aNoYTRVSeYGbUwaTERS5DLgxqxsc4NSmufJoVGN7yhPkozAp2xgERbSU8It1H+S5rv LUfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696273182; x=1696877982; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zXetwuwd7eyQ9A3g1yCGm8/1oY3jPgf1yMAkZGiV+mc=; b=q7L+m+sImUM7SDs97CX8iQBuCllQgJ9bQr8AF16x0TpcOFSJUF9jVBhDsej++wDAIv 3cYa8ST9ATkcCCiJG9ZRpJd3EgEIqh/WfkOrhG/bhs7czdvEyKy8EKZFJPKH0AthIxit jLTcQwJFZwdoXpn9Qdh2RGC7yEjq3WRQpnF+yfKeHO1CufG5UD6DmOT/u3w/KPQ3KYRT Ff8mcCGDbQB+5zd3tz2e6q4y/GaDSnMkTV3bf/sfFfpvqrUDmOpyjMgv6LAxekNBDFWU Z42fBIXpnE2qCr+m+vCMWJKIz10xxuSi2XDNhBz6aW9s+EOrc8QdU/JHSz7yqbGNCTfC YykQ== X-Gm-Message-State: AOJu0YxLqgqou2QdSgGQUc3+SOrw/JwrdMZbP8B2YrIfCAnE5hIT6oiy Hzd5svFqBejQagMgk91db9AkAQ== X-Google-Smtp-Source: AGHT+IHw0bsKYu/a7Q4FTDbZaZhUadyxYML+nweVMGrn9ermZvYwwiCn7W5vccf+ApXG4a+qB5yerw== X-Received: by 2002:a05:6512:ea1:b0:503:2642:435e with SMTP id bi33-20020a0565120ea100b005032642435emr11407227lfb.66.1696273181901; Mon, 02 Oct 2023 11:59:41 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id t6-20020a19ad06000000b00502d7365e8fsm2443981lfc.137.2023.10.02.11.59.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Oct 2023 11:59:41 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold , Rob Herring Subject: [PATCH v5 1/6] dt-bindings: opp: opp-v2-kryo-cpu: support Qualcomm Krait SoCs Date: Mon, 2 Oct 2023 21:59:35 +0300 Message-Id: <20231002185940.1271800-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231002185940.1271800-1-dmitry.baryshkov@linaro.org> References: <20231002185940.1271800-1-dmitry.baryshkov@linaro.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Exted the opp-v2-kryo-cpu.yaml to support defining OPP tables for the previous generation of Qualcomm CPUs, 32-bit Krait-based platforms. It makes no sense to use 'operating-points-v2-kryo-cpu' compatibility node for the Krait cores. Add support for the Krait-specific 'operating-points-v2-krait-cpu' compatibility string and the relevant opp-microvolt subclasses properties. The listed opp-supported-hw values are applicable only to msm8996 / msm8996pro platforms. Remove the enum as other platforms will use other bit values. It makes little sense to list all possible values for all the platforms here. Acked-by: Rob Herring Signed-off-by: Dmitry Baryshkov --- .../devicetree/bindings/opp/opp-v2-kryo-cpu.yaml | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml b/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml index 27ea7eca73e5..316f9c7804e4 100644 --- a/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml +++ b/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml @@ -26,7 +26,9 @@ description: | properties: compatible: - const: operating-points-v2-kryo-cpu + enum: + - operating-points-v2-krait-cpu + - operating-points-v2-kryo-cpu nvmem-cells: description: | @@ -65,14 +67,16 @@ patternProperties: 5: MSM8996SG, speedbin 1 6: MSM8996SG, speedbin 2 7-31: unused - enum: [0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, - 0x9, 0xd, 0xe, 0xf, - 0x10, 0x20, 0x30, 0x70] + + Other platforms use bits directly corresponding to speedbin index. clock-latency-ns: true required-opps: true + patternProperties: + '^opp-microvolt-speed[0-9]+-pvs[0-9]+$': true + required: - opp-hz From patchwork Mon Oct 2 18:59:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 729051 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B1AF61F18C for ; Mon, 2 Oct 2023 18:59:47 +0000 (UTC) Received: from mail-lf1-x136.google.com (mail-lf1-x136.google.com [IPv6:2a00:1450:4864:20::136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 92240C9 for ; Mon, 2 Oct 2023 11:59:44 -0700 (PDT) Received: by mail-lf1-x136.google.com with SMTP id 2adb3069b0e04-502e7d66c1eso38689e87.1 for ; Mon, 02 Oct 2023 11:59:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1696273182; x=1696877982; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=uUMMYHvgPHC3FfvjsnckoOJeoQiZG6ia/eSTyXFZQWY=; b=ZhI8t8stGzgFJbpADZZ5VJoJGDvPoaxXXcKMlhIUM22511S9yUN2bRwROclKU+ugfw kwZAureA2ymlIctRf/9KGeuNXRON1zE4KVClgIZbR1s2LidbVuiR5kC2j2TDsTmvOHFY 3S4dclPNG7O1MYZnDC5V5NQC/ntpU6VrVY6V2urEmpewgCSLl7xYcppIC6XPYIkjCj6e JCwcfVSBAXG3jWlG3FzxScwSgR13gzQXP66dD05sausEjOfXblPwQOGgfHZzyamrt2py WNL9j1kIComsU2cLllR+ZVHn30UYb1ytCmXiwIISHEjoZc79WFPRXdQa5Eg/x9fdioZQ W+nw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696273183; x=1696877983; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uUMMYHvgPHC3FfvjsnckoOJeoQiZG6ia/eSTyXFZQWY=; b=omTRCRQ1OXBpkSj498lmEu6bFgjslOcNb9gdwdM65N+OnNBlLBLfQqeLEQpKnOnweP +BxzwrR5u4cv9duG5xSnUDwGm26oHXZj/0Hd610SbbGd2Zt/cBQclm+aBmrQ/9HhD7tH No4BFIZLKi9wKIeds/yNR+WBJ3ruETzbYGpvs3p5Xz5mqIauxxMW7KXAu1ErRnLh3x/i MZDaRR+fNI0t53nhBMlkMKATgPNwF5SxrUn4j/8ZZH6uRElq2Y5K3hnWIwbyTi9cN/KH J/tA1XJjSRxM8vzMs1voTWVj7B0QIG9BT7q4KvaywLU49xEeza2+rsMj79Vi0rTpCV6m yNDQ== X-Gm-Message-State: AOJu0YyivzND63krL5LiyM29JXDBNQN8BmkVD/6GrCtLd+BOcE9eDXUV cOGYl0jLLkLsNYup6iWORjm5kw== X-Google-Smtp-Source: AGHT+IEgxFY+35KvD5H3tSxWVYVRmZNUF09HNGbEzDO2oFLSFdd5IOhZLmpK+kmZLitoT04UbgVrRg== X-Received: by 2002:a19:f814:0:b0:503:343a:829f with SMTP id a20-20020a19f814000000b00503343a829fmr9526676lff.23.1696273182683; Mon, 02 Oct 2023 11:59:42 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id t6-20020a19ad06000000b00502d7365e8fsm2443981lfc.137.2023.10.02.11.59.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Oct 2023 11:59:42 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold Subject: [PATCH v5 2/6] cpufreq: qcom-nvmem: create L2 cache device Date: Mon, 2 Oct 2023 21:59:36 +0300 Message-Id: <20231002185940.1271800-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231002185940.1271800-1-dmitry.baryshkov@linaro.org> References: <20231002185940.1271800-1-dmitry.baryshkov@linaro.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Scaling the frequencies on some of Qualcomm Krait platforms (e.g. APQ8064) also requires scaling of the L2 cache frequency. As the l2-cache device node is places under /cpus/ path, it is not created by default by the OF code. Create corresponding device here. Signed-off-by: Dmitry Baryshkov --- drivers/cpufreq/qcom-cpufreq-nvmem.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c index 84d7033e5efe..919f2ee9cafe 100644 --- a/drivers/cpufreq/qcom-cpufreq-nvmem.c +++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -377,6 +378,7 @@ static int __init qcom_cpufreq_init(void) { struct device_node *np = of_find_node_by_path("/"); const struct of_device_id *match; + unsigned int cpu; int ret; if (!np) @@ -387,6 +389,25 @@ static int __init qcom_cpufreq_init(void) if (!match) return -ENODEV; + for_each_possible_cpu(cpu) { + struct device *dev = get_cpu_device(cpu); + struct platform_device *pdev; + struct device_node *cache; + + cache = of_find_next_cache_node(dev->of_node); + if (!cache) + continue; + + if (of_device_is_compatible(cache, "qcom,krait-l2-cache")) { + pdev = of_platform_device_create(cache, NULL, NULL); + /* ignore, this error is not fatal */ + if (!pdev) + pr_err("%s: %pe, failed to create L2 cache node\n", __func__, pdev); + } + + of_node_put(cache); + } + ret = platform_driver_register(&qcom_cpufreq_driver); if (unlikely(ret < 0)) return ret; From patchwork Mon Oct 2 18:59:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 729050 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9DD8D1F18C for ; Mon, 2 Oct 2023 18:59:49 +0000 (UTC) Received: from mail-lf1-x133.google.com (mail-lf1-x133.google.com [IPv6:2a00:1450:4864:20::133]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CF608DC for ; Mon, 2 Oct 2023 11:59:46 -0700 (PDT) Received: by mail-lf1-x133.google.com with SMTP id 2adb3069b0e04-50567477b29so30701e87.3 for ; Mon, 02 Oct 2023 11:59:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1696273185; x=1696877985; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2jjTNnguvLOGzQRpp4J4p+5ap6mcEJVkzoAyjCrZDG0=; b=NQ2jQ/OFw/PTK1BnEpgfXw0gQY1B6T6VWOtV2+gPJ9XYDEOfgrnJc2S3dOoh9aT6E7 DjoEhl+0un/5nhJOnP06zXn1KhPMoc0svDl29u3mpI3yhlQ43fhWHUvLf8GLUwejL1El mP3fA2cFAHogS3aD6me1+vlvr0ybcz/UJ77KJTM1gxMN8+IMvwfySyEq+2QOUu8WAsin n1vFIFiu4QAq8H+k1QS/OZxZuWRxT62NU9DeattywJHR4oBm92ua0M4mzQ0RB3aSEbfV nJa4byizxuaL9ORc7Q9BkJkLakdu5bvOW1sqC6LTmT5ZDXxYlGmXlg6We+bIcv7MFKL3 WtuA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696273185; x=1696877985; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2jjTNnguvLOGzQRpp4J4p+5ap6mcEJVkzoAyjCrZDG0=; b=Tix7XPFQkqdPJM5dXg5/8Sj7SrP45NDn8u0n0R2BBTxBEHqtd9DSi0mj9t9cEfM0ub 0f+Mwazi5Ep2DRIdOgjMKiXaOQrOQ3vxe3FLFCHoJoBTbTnrg5TKDrIqRW3koWwoZbn3 ddwPwRKEp0AmxUPmcCo91wSUJeyEUpJHxV/OSSHPrG0i95ONCBMdBrnzxujc+HZBBBR/ WKgYpKJNj99F67q1nxlhR0F+nJLc1lz7llcAQAWC9dBEXEh6Y6M2bZawulDjE+KeS31k tfycZvoqcIlJ8vT4gHx0NHzBdXjjYjV8+AGzy3O/fe6kyiXk6ThtSp0/LB1jEpdNvtHH srzA== X-Gm-Message-State: AOJu0YxbhiI3VW8J77EfuZ9FiJO5wBEG+rP3K/s0d1fzGB1SFMqCVKcM PLOuPhLfpY80gH/hktelQ41c6Q== X-Google-Smtp-Source: AGHT+IF9di7HXMGcz4wrofKDMcmvUiyBh0pXCdwNqtXi9q6sEWgaWOUBvf+9O6tKdebgvtPgvS3+NQ== X-Received: by 2002:a05:6512:acb:b0:502:d743:9fc4 with SMTP id n11-20020a0565120acb00b00502d7439fc4mr14105432lfu.37.1696273185145; Mon, 02 Oct 2023 11:59:45 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id t6-20020a19ad06000000b00502d7365e8fsm2443981lfc.137.2023.10.02.11.59.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Oct 2023 11:59:44 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold Subject: [PATCH v5 5/6] cpufreq: qcom-nvmem: provide separate configuration data for apq8064 Date: Mon, 2 Oct 2023 21:59:39 +0300 Message-Id: <20231002185940.1271800-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231002185940.1271800-1-dmitry.baryshkov@linaro.org> References: <20231002185940.1271800-1-dmitry.baryshkov@linaro.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net APQ8064 can scale core voltage according to the frequency needs. Rather than reusing the A/B format multiplexer, use a simple fuse parsing function and configure required regulator. Signed-off-by: Dmitry Baryshkov --- drivers/cpufreq/qcom-cpufreq-nvmem.c | 49 ++++++++++++++++++++++++++-- 1 file changed, 47 insertions(+), 2 deletions(-) diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c index e5c17d9f5a24..e1cf677b0c6f 100644 --- a/drivers/cpufreq/qcom-cpufreq-nvmem.c +++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include @@ -39,6 +40,7 @@ struct qcom_cpufreq_match_data { char **pvs_name, struct qcom_cpufreq_drv *drv); const char **genpd_names; + const char * const *regulator_names; }; struct qcom_cpufreq_drv { @@ -203,6 +205,34 @@ static int qcom_cpufreq_krait_name_version(struct device *cpu_dev, return ret; } +static int qcom_cpufreq_apq8064_name_version(struct device *cpu_dev, + struct nvmem_cell *speedbin_nvmem, + char **pvs_name, + struct qcom_cpufreq_drv *drv) +{ + int speed = 0, pvs = 0; + u8 *speedbin; + size_t len; + + speedbin = nvmem_cell_read(speedbin_nvmem, &len); + if (IS_ERR(speedbin)) + return PTR_ERR(speedbin); + + if (len != 4) + return -EINVAL; + + get_krait_bin_format_a(cpu_dev, &speed, &pvs, speedbin); + + snprintf(*pvs_name, sizeof("speedXX-pvsXX"), "speed%d-pvs%d", + speed, pvs); + + drv->versions = (1 << speed); + + kfree(speedbin); + + return 0; +} + static const struct qcom_cpufreq_match_data match_data_kryo = { .get_version = qcom_cpufreq_kryo_name_version, }; @@ -217,6 +247,16 @@ static const struct qcom_cpufreq_match_data match_data_qcs404 = { .genpd_names = qcs404_genpd_names, }; +static const char * apq8064_regulator_names[] = { + "vdd-core", + NULL +}; + +static const struct qcom_cpufreq_match_data match_data_apq8064 = { + .get_version = qcom_cpufreq_apq8064_name_version, + .regulator_names = apq8064_regulator_names, +}; + static int qcom_cpufreq_probe(struct platform_device *pdev) { struct qcom_cpufreq_drv *drv; @@ -304,7 +344,12 @@ static int qcom_cpufreq_probe(struct platform_device *pdev) config.virt_devs = NULL; } - if (config.supported_hw || config.genpd_names) { + if (drv->data->regulator_names) + config.regulator_names = drv->data->regulator_names; + + if (config.supported_hw || + config.genpd_names || + config.regulator_names) { drv->opp_tokens[cpu] = dev_pm_opp_set_config(cpu_dev, &config); if (drv->opp_tokens[cpu] < 0) { ret = drv->opp_tokens[cpu]; @@ -361,7 +406,7 @@ static const struct of_device_id qcom_cpufreq_match_list[] __initconst = { { .compatible = "qcom,msm8996", .data = &match_data_kryo }, { .compatible = "qcom,qcs404", .data = &match_data_qcs404 }, { .compatible = "qcom,ipq8064", .data = &match_data_krait }, - { .compatible = "qcom,apq8064", .data = &match_data_krait }, + { .compatible = "qcom,apq8064", .data = &match_data_apq8064 }, { .compatible = "qcom,msm8974", .data = &match_data_krait }, { .compatible = "qcom,msm8960", .data = &match_data_krait }, {},