From patchwork Thu Aug 1 08:15:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 170315 Delivered-To: patch@linaro.org Received: by 2002:a92:512:0:0:0:0:0 with SMTP id q18csp5085104ile; Thu, 1 Aug 2019 01:19:40 -0700 (PDT) X-Google-Smtp-Source: APXvYqzin5302EZRaIN65chA/m8RWRUsszOJ8mw/4b+GPNbU+NujS/7E97r2qVfUsdf5JIP4AiiK X-Received: by 2002:a63:5a4d:: with SMTP id k13mr114389111pgm.174.1564647580353; Thu, 01 Aug 2019 01:19:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564647580; cv=none; d=google.com; s=arc-20160816; b=DPd4bZFExk24RElPExbN5w3bjDGfjoGa/e2xEWcno6QNo4t2VaTbx/TfKEkklUvMjV C+8j66dI7iq7AKmPj5qSugfLNLOkGoMRui8SZFOf5TMB2xj3lawefzHOE0tWbD+EL56w /eA4MsEbIVyvwaqLhqeRTxZ5MceV7fok50OFHo+gJotVuZsPLyjwFszfzj/dpeSpfSiX /FWU1UBPbD6bzPNuOQPpZf4bILECUzgcEvT9/RofZrTsxJLx1wUTUB686EnJkGU15Z5s PIWZPn6UOGTAPcTIFOiCfi7rpRlezmNK0PO2aWKm3s4+KB1SxhepzehKcsvOtxFdB1M/ Hllw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=yC2M+WqtpDn8WEqkn0+0Dw3Z53HTrfg3c6ZZe0WXdnU=; b=t+huzIXHPLbcvYF0eXEFrn3hbvbPQy7gPf35H3gFhYo0356B8wT5sPfdUDIVwkmkmG zF/fl5jyYMPy5TAKhLReuYor1fECLroenREThfKU/mV5krH2YLZcM1BoBqNDwZmvgcPM KiYZKUVxN3/cvFuWKgQSGJXOJ87bWimt7zYs4W0RBD2iq/V0LO8Cwe8I/9YzL6zCAENP c5ztSEzh6hIVwxL2E6nhMdZlmCThfexITjMtutung/5LI8HjA7ovMxR5j/zCoRsxG8PH EL8EyQ5rFHe6lJdhQr2EOgZ1l2LkDKdKtLY/OgMelIcoJFliObaSTpFol9vn6PVRroAd AcCw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=d3x4fDlK; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id ch18si32232418plb.76.2019.08.01.01.19.40; Thu, 01 Aug 2019 01:19:40 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=d3x4fDlK; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730402AbfHAITj (ORCPT + 14 others); Thu, 1 Aug 2019 04:19:39 -0400 Received: from mail-pl1-f196.google.com ([209.85.214.196]:42819 "EHLO mail-pl1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730392AbfHAITj (ORCPT ); Thu, 1 Aug 2019 04:19:39 -0400 Received: by mail-pl1-f196.google.com with SMTP id ay6so31901724plb.9 for ; Thu, 01 Aug 2019 01:19:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yC2M+WqtpDn8WEqkn0+0Dw3Z53HTrfg3c6ZZe0WXdnU=; b=d3x4fDlKvawzWe9SM/hXbJjH0xa2FdWDAb+Q1xG4XXXFjcwqAj01I6oNP+ixKaTvOG r1uM2XDjSkYI4uxtL0fgwqHxF8KjG25ICOelKht4h1FTz60e3olLaOgI1yWgKCKu4gfJ +l5ujKt2riwQxCc/TLA92//Na186jC3Klft3HOTziXCeDW/FOFRGrmv6ua9qRYdfhu+X Fa8AAaeHBKkLKZID6jDTGHEOBAerlARYuCXkbCVbgeRQ9KBtTkhr2YXOqBD7PusHXUo0 ZLXtFbYqRUUHdlbdujXYPHJx0wuICOydTANirYlhyo8Odonfpf9VDUtO5jWGurCAYFnq JZ9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yC2M+WqtpDn8WEqkn0+0Dw3Z53HTrfg3c6ZZe0WXdnU=; b=kv0EDPj0Jpm99xNJ+kg9HpBHqtzSHqQJQyo+208jj44N6/xQ7h97MrDMAGSedg3Lzo Nbt5slAvd8C7aLgLSKjzzw3CF7RzK0mZY8Gk3QFGBW9ZpcbU9KAx3lWsE+HtSNhWWbWU F3MS9ffZHo0UNC4udnxRYWs1WEgqOAkLUKwg8xMSz5kSJVg7qvr90xug+zJdMn/nch6J zzeD7808VNuntXDRUCLp4Gk0dNVAc9j0AQEozBCzodqOj5hHCCOPWZTZMlcabmpF0Za0 xptY+/65J8pBSUilIyasKqniq2F4oc/4tKd4GAG1WCQEFjHbxVJbi+P4y4JL1U88VPX+ UM3w== X-Gm-Message-State: APjAAAXHFmuU+T/VnOb68HQ14F/RKYx0fXtsah8qGG8cF7RzIz+SiI7x 6Ev18pE8S8se5VQsqUgJFgUNXwEFOeg= X-Received: by 2002:a17:902:1e2:: with SMTP id b89mr17081410plb.7.1564647578418; Thu, 01 Aug 2019 01:19:38 -0700 (PDT) Received: from localhost ([122.172.28.117]) by smtp.gmail.com with ESMTPSA id n185sm53001398pga.16.2019.08.01.01.19.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 01 Aug 2019 01:19:37 -0700 (PDT) From: Viresh Kumar To: stable@vger.kernel.org Cc: Viresh Kumar , Julien Thierry , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Marc Zyngier , Mark Rutland , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com, guohanjun@huawei.com Subject: [PATCH ARM32 v4.4 V2 01/47] ARM: 8478/2: arm/arm64: add arm-smccc Date: Thu, 1 Aug 2019 13:45:45 +0530 Message-Id: <5159d5da6d24267d412df97131045996b5e06b45.1564646727.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Jens Wiklander commit 98dd64f34f47ce19b388d9015f767f48393a81eb upstream. Adds helpers to do SMC and HVC based on ARM SMC Calling Convention. CONFIG_HAVE_ARM_SMCCC is enabled for architectures that may support the SMC or HVC instruction. It's the responsibility of the caller to know if the SMC instruction is supported by the platform. This patch doesn't provide an implementation of the declared functions. Later patches will bring in implementations and set CONFIG_HAVE_ARM_SMCCC for ARM and ARM64 respectively. Reviewed-by: Lorenzo Pieralisi Signed-off-by: Jens Wiklander Signed-off-by: Russell King [ v4.4: Added #ifndef __ASSEMBLY__ section to fix compilation issues ] Signed-off-by: Viresh Kumar --- drivers/firmware/Kconfig | 3 ++ include/linux/arm-smccc.h | 107 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 110 insertions(+) create mode 100644 include/linux/arm-smccc.h -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/drivers/firmware/Kconfig b/drivers/firmware/Kconfig index cf478fe6b335..49a3a1185bb6 100644 --- a/drivers/firmware/Kconfig +++ b/drivers/firmware/Kconfig @@ -173,6 +173,9 @@ config QCOM_SCM_64 def_bool y depends on QCOM_SCM && ARM64 +config HAVE_ARM_SMCCC + bool + source "drivers/firmware/broadcom/Kconfig" source "drivers/firmware/google/Kconfig" source "drivers/firmware/efi/Kconfig" diff --git a/include/linux/arm-smccc.h b/include/linux/arm-smccc.h new file mode 100644 index 000000000000..611d10580340 --- /dev/null +++ b/include/linux/arm-smccc.h @@ -0,0 +1,107 @@ +/* + * Copyright (c) 2015, Linaro Limited + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#ifndef __LINUX_ARM_SMCCC_H +#define __LINUX_ARM_SMCCC_H + +#include +#include + +/* + * This file provides common defines for ARM SMC Calling Convention as + * specified in + * http://infocenter.arm.com/help/topic/com.arm.doc.den0028a/index.html + */ + +#define ARM_SMCCC_STD_CALL 0 +#define ARM_SMCCC_FAST_CALL 1 +#define ARM_SMCCC_TYPE_SHIFT 31 + +#define ARM_SMCCC_SMC_32 0 +#define ARM_SMCCC_SMC_64 1 +#define ARM_SMCCC_CALL_CONV_SHIFT 30 + +#define ARM_SMCCC_OWNER_MASK 0x3F +#define ARM_SMCCC_OWNER_SHIFT 24 + +#define ARM_SMCCC_FUNC_MASK 0xFFFF + +#define ARM_SMCCC_IS_FAST_CALL(smc_val) \ + ((smc_val) & (ARM_SMCCC_FAST_CALL << ARM_SMCCC_TYPE_SHIFT)) +#define ARM_SMCCC_IS_64(smc_val) \ + ((smc_val) & (ARM_SMCCC_SMC_64 << ARM_SMCCC_CALL_CONV_SHIFT)) +#define ARM_SMCCC_FUNC_NUM(smc_val) ((smc_val) & ARM_SMCCC_FUNC_MASK) +#define ARM_SMCCC_OWNER_NUM(smc_val) \ + (((smc_val) >> ARM_SMCCC_OWNER_SHIFT) & ARM_SMCCC_OWNER_MASK) + +#define ARM_SMCCC_CALL_VAL(type, calling_convention, owner, func_num) \ + (((type) << ARM_SMCCC_TYPE_SHIFT) | \ + ((calling_convention) << ARM_SMCCC_CALL_CONV_SHIFT) | \ + (((owner) & ARM_SMCCC_OWNER_MASK) << ARM_SMCCC_OWNER_SHIFT) | \ + ((func_num) & ARM_SMCCC_FUNC_MASK)) + +#define ARM_SMCCC_OWNER_ARCH 0 +#define ARM_SMCCC_OWNER_CPU 1 +#define ARM_SMCCC_OWNER_SIP 2 +#define ARM_SMCCC_OWNER_OEM 3 +#define ARM_SMCCC_OWNER_STANDARD 4 +#define ARM_SMCCC_OWNER_TRUSTED_APP 48 +#define ARM_SMCCC_OWNER_TRUSTED_APP_END 49 +#define ARM_SMCCC_OWNER_TRUSTED_OS 50 +#define ARM_SMCCC_OWNER_TRUSTED_OS_END 63 + +#ifndef __ASSEMBLY__ + +/** + * struct arm_smccc_res - Result from SMC/HVC call + * @a0-a3 result values from registers 0 to 3 + */ +struct arm_smccc_res { + unsigned long a0; + unsigned long a1; + unsigned long a2; + unsigned long a3; +}; + +/** + * arm_smccc_smc() - make SMC calls + * @a0-a7: arguments passed in registers 0 to 7 + * @res: result values from registers 0 to 3 + * + * This function is used to make SMC calls following SMC Calling Convention. + * The content of the supplied param are copied to registers 0 to 7 prior + * to the SMC instruction. The return values are updated with the content + * from register 0 to 3 on return from the SMC instruction. + */ +asmlinkage void arm_smccc_smc(unsigned long a0, unsigned long a1, + unsigned long a2, unsigned long a3, unsigned long a4, + unsigned long a5, unsigned long a6, unsigned long a7, + struct arm_smccc_res *res); + +/** + * arm_smccc_hvc() - make HVC calls + * @a0-a7: arguments passed in registers 0 to 7 + * @res: result values from registers 0 to 3 + * + * This function is used to make HVC calls following SMC Calling + * Convention. The content of the supplied param are copied to registers 0 + * to 7 prior to the HVC instruction. The return values are updated with + * the content from register 0 to 3 on return from the HVC instruction. + */ +asmlinkage void arm_smccc_hvc(unsigned long a0, unsigned long a1, + unsigned long a2, unsigned long a3, unsigned long a4, + unsigned long a5, unsigned long a6, unsigned long a7, + struct arm_smccc_res *res); + +#endif /*__ASSEMBLY__*/ +#endif /*__LINUX_ARM_SMCCC_H*/ From patchwork Thu Aug 1 08:15:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 170316 Delivered-To: patch@linaro.org Received: by 2002:a92:512:0:0:0:0:0 with SMTP id q18csp5085144ile; Thu, 1 Aug 2019 01:19:42 -0700 (PDT) X-Google-Smtp-Source: APXvYqzW6Fx/cTZJleaVA11PiSQHR67onR8ZOb3lRhhttTouMQy0dCVsS7gA5bVNRnBh2pZR7gJw X-Received: by 2002:aa7:9513:: with SMTP id b19mr52079250pfp.30.1564647582684; Thu, 01 Aug 2019 01:19:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564647582; cv=none; d=google.com; s=arc-20160816; b=VAnPHTYLZGlDqp4qLJCXIpnAiWDTFTe3AQeMTxruyhv6UKdxuZ4MhPiolyaIhyG6lw CsX7bFr6Vs48sqszNxwiAqJoDYS7FtmlLqsz35dzsunIb0NbR2mofa7g/PgdO49quNmc XPJqoFKuL7x9ZPT5kTErSSxdo5Yn5v6qHu6tndBshPhrJj8rFwdL9XPVn1IWSUtHrxN/ uCacXQHXieXqfCdDHAgfmhlvphjFa91OcBaLGfjegi4j3+ivhM8qxXyGFYyZAknMxLAx W5BACWk32zecfOZVK2DF3N6chd3iPUZ7WhYFzqBtL6PZ1lnqITqvHCX9Ojd+Sk/oPRiG 4i7w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=FDb8snX7fHtHRXPBtLwcic7/q7BlhqslXapsBvvT9m4=; b=eHRbUZaCKXlh6P0di9jXD9uUk2t63OB8tuj/DUVnziaMDBB3ZD6fMqXyAL4BIqi79R 49f737xOudORV9hvyqoVQdWkIH6GGNu5vKpg3qlC+JhvNXCSYnNGQVELei0g+HVHBOjW WGPgLjntTChDq5ra5iuQzsfh6WaBfa0mgYu/44ie1EkskuJz8gV2NVdMUqOa+rqQ0X3j DkEXGXpX97nn/dhX/5FoL/m/DiUqSbs2iHlq8sQnk6nEpotrbu7HdOi7UBJB2fnna8l9 wyBzZZ79duNIdJtaRl9UJBan2DAi3+SbGt+8/y9ToA/U//OONU2P+s+1/OjIsSIDyygN pq3A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=lj9Gf1gl; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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The new SMC Calling Convention (v1.1) allows for a reduced overhead when calling into the firmware, and provides a new feature discovery mechanism. Make it visible to KVM guests. Tested-by: Ard Biesheuvel Reviewed-by: Christoffer Dall Signed-off-by: Marc Zyngier Signed-off-by: Catalin Marinas [ Viresh: Picked only arm-smccc.h changes ] Signed-off-by: Viresh Kumar --- include/linux/arm-smccc.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/include/linux/arm-smccc.h b/include/linux/arm-smccc.h index 611d10580340..da9f3916f9a9 100644 --- a/include/linux/arm-smccc.h +++ b/include/linux/arm-smccc.h @@ -60,6 +60,19 @@ #define ARM_SMCCC_OWNER_TRUSTED_OS 50 #define ARM_SMCCC_OWNER_TRUSTED_OS_END 63 +#define ARM_SMCCC_VERSION_1_0 0x10000 +#define ARM_SMCCC_VERSION_1_1 0x10001 + +#define ARM_SMCCC_VERSION_FUNC_ID \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_32, \ + 0, 0) + +#define ARM_SMCCC_ARCH_FEATURES_FUNC_ID \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_32, \ + 0, 1) + #ifndef __ASSEMBLY__ /** From patchwork Thu Aug 1 08:15:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 170317 Delivered-To: patch@linaro.org Received: by 2002:a92:512:0:0:0:0:0 with SMTP id q18csp5085174ile; Thu, 1 Aug 2019 01:19:45 -0700 (PDT) X-Google-Smtp-Source: APXvYqwtIAFxGX6gED/fIIvwU5O9nyzYNoYJXB0TpJFCjJYD2p6afpE8PDPxbdNizPBfT/0I8LES X-Received: by 2002:a63:6106:: with SMTP id v6mr1682257pgb.36.1564647585116; Thu, 01 Aug 2019 01:19:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564647585; cv=none; d=google.com; s=arc-20160816; b=G/E8SpiA07JOFojpkQQlcH64RC21BpQTvTQkUnTSCdE4e2q+9DCcHeg8UGgYEd9G36 88ebTM7wcNUuup6X3YF86hhU/mHL1rrrGnWJVfs1O5NDfck+QDP68EfsyXAOQy1syuuz ZdwznMuCISxI68woWhE7MWRMFluQHjvCYopvMJYxZ0uuDIkiD0ularq1nRWhFE2rOagl sHV3ZdK+hIr0u1eolYIntQzfXHTA9BQTZah7spho1qx+tys/x609lU0Wyx1jw1WZQu6W PmilrpwJ9oa7V29R5jlTvPF2ANGEC57iaKv0ZUeqNoe4nDX7Yvwts3I8IDt8+V3mzUGz TJqQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=z7GSqiJ6aBNFVvBBcZiH2v3S1Pbs9vo106t8SFNGIe4=; b=jyGTPwwgLTQnD+/foWc0QBt/5iMkROvAcIMqI4fsgq8YcFG00KIprcazLTiWxPpwbb 8zWzgQlsuXchOc1HwJYSyxEzvxYKaBi58fUtDzqltTeyi2Pq4eW4q28NJ0E8sWyrNCJr mPa5lbNbpBYIaDVaIz06iinG52GZrzwGbzutuiGunJcYD4CYQhvYPnnRhTCHroQE7Ivp 537FVXDPPfOdJhuMaaIox1+nb9IflmTz8UF0H28VscyWfapV6CMk29BnCijgyNZWz1Bp UnjTfvFoROZSsFwzI7u/LCWev8iklg5kHKz9vNwhZREE8h3t5yIuJYJj/LlEnyp5m25p Frjg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cYaRmjxp; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id ch18si32232418plb.76.2019.08.01.01.19.44; Thu, 01 Aug 2019 01:19:45 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cYaRmjxp; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730458AbfHAITo (ORCPT + 14 others); Thu, 1 Aug 2019 04:19:44 -0400 Received: from mail-pg1-f193.google.com ([209.85.215.193]:46979 "EHLO mail-pg1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730392AbfHAITo (ORCPT ); Thu, 1 Aug 2019 04:19:44 -0400 Received: by mail-pg1-f193.google.com with SMTP id k189so14684731pgk.13 for ; Thu, 01 Aug 2019 01:19:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=z7GSqiJ6aBNFVvBBcZiH2v3S1Pbs9vo106t8SFNGIe4=; b=cYaRmjxpRpihR3ST0Z43FI6gGebPhfoWhCbpU+IMiA14zAmRrIrwHkLNPGxQbO3dwQ GKIF1ls+9uq+hNUdROGeAa0AknTV9vYQ5TFKVHdwI/2EmvyukmhMRTDGiva55cX2FenL aGDOJ5qzMHxinEWIcGbZyYj1dw2pxHV/LjncanSzzQL3S6e2pW5AVum+1MNUj63YHMgI N3LCp/eNbnqtm6aGhrAr6JZ+sPtBGtd3EyRopNtHb2rYD6dzl/Nm03uWLQROVJdNpWp7 tXl7No6eYiHWr+8KJFDPN8JbC84yPGs9/3Latvd+MfH6CI93+nX4fYz1N+Wls25RH5UP oHBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=z7GSqiJ6aBNFVvBBcZiH2v3S1Pbs9vo106t8SFNGIe4=; b=fK00QAWMZ6PSf0dsc4WzvhjN5W+f7+F0VJV/vpZYKlLUFnpBaswMj77PPEfK5EiFYp ApubR6xHxVIlVj54ueielf/ChmulZe+P65T2SRsPv6hc5rPy3/MINr2h1GFTqTVu1cAd rln3CHG1qZToR0DdiXX5K7Pl1i8dmWHwAjK6xbG4tkqQLYEs3opL9qjyZm71QJ/SRsoe m2+VLCJO3Am4pM9y302jNQXEzqZZMwqRDYHwwJj3wOE6JbK9H64Q5uSQh3IBRkdJmkaz FCMHj4QbHyir7bnwObJ5FHcmQKXTpHfEq1cR6Ggbof2eZv4aXebcRdELKH5TjSA+35y6 Qpdg== X-Gm-Message-State: APjAAAVyEpNJhJFd9yAGOecj4dpYAXW71KQlG2pajwD+312DlIbxdmzS KW7iwmkKoe/oqhAxAkp/IYYvN52Hajo= X-Received: by 2002:a62:3c3:: with SMTP id 186mr51852915pfd.21.1564647583498; Thu, 01 Aug 2019 01:19:43 -0700 (PDT) Received: from localhost ([122.172.28.117]) by smtp.gmail.com with ESMTPSA id l1sm91579706pfl.9.2019.08.01.01.19.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 01 Aug 2019 01:19:43 -0700 (PDT) From: Viresh Kumar To: stable@vger.kernel.org Cc: Viresh Kumar , Julien Thierry , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Marc Zyngier , Mark Rutland , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com, guohanjun@huawei.com Subject: [PATCH ARM32 v4.4 V2 03/47] arm64: KVM: Report SMCCC_ARCH_WORKAROUND_1 BP hardening support Date: Thu, 1 Aug 2019 13:45:47 +0530 Message-Id: <62376918dc348842e21f6eb62235220f53d35cdb.1564646727.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Marc Zyngier commit 6167ec5c9145cdf493722dfd80a5d48bafc4a18a upstream. A new feature of SMCCC 1.1 is that it offers firmware-based CPU workarounds. In particular, SMCCC_ARCH_WORKAROUND_1 provides BP hardening for CVE-2017-5715. If the host has some mitigation for this issue, report that we deal with it using SMCCC_ARCH_WORKAROUND_1, as we apply the host workaround on every guest exit. Tested-by: Ard Biesheuvel Reviewed-by: Christoffer Dall Signed-off-by: Marc Zyngier Signed-off-by: Catalin Marinas [ Viresh: Picked on only arm-smccc.h changes ] Signed-off-by: Viresh Kumar --- include/linux/arm-smccc.h | 5 +++++ 1 file changed, 5 insertions(+) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/include/linux/arm-smccc.h b/include/linux/arm-smccc.h index da9f3916f9a9..1f02e4045a9e 100644 --- a/include/linux/arm-smccc.h +++ b/include/linux/arm-smccc.h @@ -73,6 +73,11 @@ ARM_SMCCC_SMC_32, \ 0, 1) +#define ARM_SMCCC_ARCH_WORKAROUND_1 \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_32, \ + 0, 0x8000) + #ifndef __ASSEMBLY__ /** From patchwork Thu Aug 1 08:15:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 170318 Delivered-To: patch@linaro.org Received: by 2002:a92:512:0:0:0:0:0 with SMTP id q18csp5085226ile; Thu, 1 Aug 2019 01:19:47 -0700 (PDT) X-Google-Smtp-Source: APXvYqyIIgGiqa33XuubupsBlmVJiiOV/hTt3M/KsrJJfbSVUUAUYW3mJnGAiwZZQt9h4dNXLNNu X-Received: by 2002:a17:902:a409:: with SMTP id p9mr125844072plq.218.1564647587783; Thu, 01 Aug 2019 01:19:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564647587; cv=none; d=google.com; s=arc-20160816; b=i5DqbbR92x5vcASRi7chCUwVnP4z2TcZytmkvsIFjC/e7/KLI06yQUO2Cw9BBLU4A6 cESxvIePLVYLu8X6ZGvhMdHPQbp0Ciu2D6za3ze3PGAmMKxiZy2kv6iqiF6oMaI0GP8n y09z7fZ1NN4548ZIZGr2Tk9KsFkCnZUzxUTs35BviVLkIB7q7DEMhx4juMar8sDfS3qF NYzWXV0M9TNxqPw+4FpqCeVicfjat4DWZaWSSeqrcXNSZXjAAtTTwO0snmRVGa5FflZS tWu2MuZ8gn2uM9+QxKwz1h5e6JHuVJgmaLpuYGoCFr2vPR5laQGCRyKFhV4nnQmwKH6C 7CxQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=tUK8ETga6k61l9Q+/z8rY6SIV6XG+DcjRuCd/1NWAIQ=; b=wFjQzkgMt6yo07qEk8hhN30qwUW8vKZQyHotIR4c1TuN0zW/MTvbSz7LLRhqYGPMNc nJ0YKDjmpkwLF9Us3zdZ2g9Af9BQPp/ZqvSLffWgpqLq5eyMEPT9XqtJ3kvMzwRYJsFF yoSuj9KxaMiuiZ/SdEvWUqGltYc4WnQWQh1ILM6Khe0pi0OHR9vxqpKcblK8Uh5QJLaO O02AHs4mLwtSNgJf4MfGsa4cgq8DWoED9Xydin2DsTo3V/kiRTanXlRo/duE1kXbydH9 JfhV9cjN8XftHcYu7sa314INjp8XonBTYALd2+MGmSkXpMuw5S3AAssl6VurFevCGyBM XObw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Y4Z6CBEl; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id ch18si32232418plb.76.2019.08.01.01.19.47; Thu, 01 Aug 2019 01:19:47 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Y4Z6CBEl; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730478AbfHAITr (ORCPT + 14 others); Thu, 1 Aug 2019 04:19:47 -0400 Received: from mail-pf1-f194.google.com ([209.85.210.194]:34840 "EHLO mail-pf1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730392AbfHAITq (ORCPT ); Thu, 1 Aug 2019 04:19:46 -0400 Received: by mail-pf1-f194.google.com with SMTP id u14so33622544pfn.2 for ; Thu, 01 Aug 2019 01:19:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tUK8ETga6k61l9Q+/z8rY6SIV6XG+DcjRuCd/1NWAIQ=; b=Y4Z6CBElGedbCLchp/1U5zm7RwIzsZW7sSPLelgGoB0UAR3fmAUIaWPRqbBzItY+SU dFonmxxfBMwagZLJREXeHezpHMh1Y3Qa90lYmEqpzmwy29/QR4lMPJUVtQqcTlzsoblx YvUQeTrTR+Rrgn6wBdIS/56xvJGBvX6qMt3nWeY6Yf+7kSNhghxr4XIm9GLXOVwOTBSx bMwSdkvjuTyiv2KCbxqdBmearRidRn1z3nSssV2qaK3kQU+stZQ6DIV2/gHkdIaGZ1iJ d0MueB6aYPyB3wiVuCenso27YAaY7cBchl80Fj6Qc729nXHTSmJRi2P+ieiXaWhAkbNl +6jQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tUK8ETga6k61l9Q+/z8rY6SIV6XG+DcjRuCd/1NWAIQ=; b=ivYpt2KSJt+PFy7V+UySdUHssiqT6tTwi+Ur3mKAwml+fKCKLECj0tX4kle7xeUMN8 LIlNJjJLpKxvMGKFiVP0RncApXx8wnqwlh+XBiKqtuPwGRKKP9hcRzFHSBT2upxC5jKU Ym7VZaeOlHN2F07wfWl9r64yvX6SKnfp/bszikfeK5gzGzAFyiIPKZXW/+GUUOrK11Lo 6siMPdHFyHKe6dBlEtTGr9g6Z2EDCLVNJutCWcQPvpelNZ4k1KN0MwF0o7OwRkqX2eyb 6Lmvdtl3La/TzdjdULpp/h97soYKKCNRP2JlIK6HhHTw39OGALiDUJot0Z2R6CUUYIyT 6FDg== X-Gm-Message-State: APjAAAWtaTWMNLFi911j7zg6PxS2gr91yr99ygPIGr8un9AF0qIbvbvt nJi6qTCXxU1VhV50oPNgzOOuq39D1wY= X-Received: by 2002:a63:d34c:: with SMTP id u12mr103456545pgi.114.1564647585962; Thu, 01 Aug 2019 01:19:45 -0700 (PDT) Received: from localhost ([122.172.28.117]) by smtp.gmail.com with ESMTPSA id y23sm72885680pfo.106.2019.08.01.01.19.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 01 Aug 2019 01:19:45 -0700 (PDT) From: Viresh Kumar To: stable@vger.kernel.org Cc: Viresh Kumar , Julien Thierry , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Marc Zyngier , Mark Rutland , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com, guohanjun@huawei.com Subject: [PATCH ARM32 v4.4 V2 04/47] drivers/firmware: Expose psci_get_version through psci_ops structure Date: Thu, 1 Aug 2019 13:45:48 +0530 Message-Id: <64c1d3d45f10e811674aad1f583b346fcf3a8707.1564646727.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Will Deacon commit d68e3ba5303f7e1099f51fdcd155f5263da8569b upstream. Entry into recent versions of ARM Trusted Firmware will invalidate the CPU branch predictor state in order to protect against aliasing attacks. This patch exposes the PSCI "VERSION" function via psci_ops, so that it can be invoked outside of the PSCI driver where necessary. Acked-by: Lorenzo Pieralisi Signed-off-by: Will Deacon Signed-off-by: Catalin Marinas Signed-off-by: Viresh Kumar --- drivers/firmware/psci.c | 2 ++ include/linux/psci.h | 1 + 2 files changed, 3 insertions(+) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/drivers/firmware/psci.c b/drivers/firmware/psci.c index ae70d2485ca1..290f8982e7b3 100644 --- a/drivers/firmware/psci.c +++ b/drivers/firmware/psci.c @@ -305,6 +305,8 @@ static void __init psci_init_migrate(void) static void __init psci_0_2_set_functions(void) { pr_info("Using standard PSCI v0.2 function IDs\n"); + psci_ops.get_version = psci_get_version; + psci_function_id[PSCI_FN_CPU_SUSPEND] = PSCI_FN_NATIVE(0_2, CPU_SUSPEND); psci_ops.cpu_suspend = psci_cpu_suspend; diff --git a/include/linux/psci.h b/include/linux/psci.h index 12c4865457ad..04b4d92c7791 100644 --- a/include/linux/psci.h +++ b/include/linux/psci.h @@ -25,6 +25,7 @@ bool psci_power_state_loses_context(u32 state); bool psci_power_state_is_valid(u32 state); struct psci_operations { + u32 (*get_version)(void); int (*cpu_suspend)(u32 state, unsigned long entry_point); int (*cpu_off)(u32 state); int (*cpu_on)(unsigned long cpuid, unsigned long entry_point); From patchwork Thu Aug 1 08:15:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 170319 Delivered-To: patch@linaro.org Received: by 2002:a92:512:0:0:0:0:0 with SMTP id q18csp5085274ile; Thu, 1 Aug 2019 01:19:50 -0700 (PDT) X-Google-Smtp-Source: APXvYqw4qmXjjZ9RANcPaMlB3e6zAljRjQgSMyXfOTuYTFox1hoGGG9bqLp/N44ExgNQDTzQ+Pcp X-Received: by 2002:a17:90a:cb01:: with SMTP id z1mr7125380pjt.93.1564647590267; Thu, 01 Aug 2019 01:19:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564647590; cv=none; d=google.com; s=arc-20160816; b=dyS/0SB4XuydtreBHkcR6eQu+FOmE8/4UQeKRp8UQNH5gX23LFdUZbuEomq3cP5yUw JSOo2E91CssHBvj8HW2LAf1g0IVZKhcT30oI4pNBrDSCTMQHQ7HZ7upL8sSnH5ucG7kG qBeN8zESz0897g2Q2Ex9leM0xDK/qEno/Rr10MicBBgmDLKKsz6kyGLJMQTmMKifk/Td 6pi1sy4W9glmxmNvHEWRx+HMsJscryMZfiZW3ZG4k+zqHNdLPcMV7VecPf87t7zuqIrW XZz4PauAQeOYZIoykX5NADyeerOes05i8Hf8Cl0TbUfhY8AwsBWGCWQS3oM6qzjzaAoe ofEg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=lhetsf/v1WHqsODDPiuS8lCaAlBwJqZTnWnIuf4OhuE=; b=yP20piNFLr9nNMDvOJdiZZaGIBv6hwLQnuTF83mJgpQbT7F9Xdp2MUQweiMVYALN+w 2oHlbNQabryFHind3k8M4LgKp3PB4uJTrUNmVPLDrR+HtelEpvkDrioU4b97g5pXO1pl RD3uexmviNWnh2NVOdF6dJE7lyPo8x0wOXE8mNBGhd9OKW0TnqbxyVrT+arXGn2qoHBJ 9Q5jj1cJLiz2dkrc/RC2MCq0dohXTu1HYJrCOirJYAlPFHVwS8eSgu7qljrLW+RR5b7o mawNXuwOzv2+9EaWvqrsPstGV8ISxx4R/VlkxeFLxgRFLvl8WSCMirEbMbi6nGU48oBF xwKQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IeSrybNX; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id ch18si32232418plb.76.2019.08.01.01.19.50; Thu, 01 Aug 2019 01:19:50 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IeSrybNX; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730392AbfHAITt (ORCPT + 14 others); Thu, 1 Aug 2019 04:19:49 -0400 Received: from mail-pf1-f194.google.com ([209.85.210.194]:46677 "EHLO mail-pf1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730381AbfHAITt (ORCPT ); Thu, 1 Aug 2019 04:19:49 -0400 Received: by mail-pf1-f194.google.com with SMTP id c3so10466826pfa.13 for ; Thu, 01 Aug 2019 01:19:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lhetsf/v1WHqsODDPiuS8lCaAlBwJqZTnWnIuf4OhuE=; b=IeSrybNXM1FIuaHjdY8UGbg00YzSWruFMn1J7qNAW3drOxKc0UR8dxZDM5PD/UwY9x crfCdf8Q/xTPuaVROFU/r8eIsG9JXSdJGbjUk2DQH+rIPUUK8C3VNg2wcYriMmtqGNJT 7j4NI63W+dSuf3NJWh0T7mG2Cw8wSakGtzWws8D97SnvRP6mpWDaG62Q8ukYZh3xNWAS bHT+s5u0WQ5XjcbNpFziJfAkntmqjT2wtaDVQ0RzER6/blMnFCrZhvS1x/2b6IzqPe2o t8qPEVYRxsRguSB7/QUcvmTdeatQF8Of3ll29ZRRZ4t3FmlNSiDoNElGjxoS23J1Irhp k1wQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lhetsf/v1WHqsODDPiuS8lCaAlBwJqZTnWnIuf4OhuE=; b=nIcZqAAPlyPDPnAQrrtIEvtwXwaahJwdvohC56k2o1hW5qg1xCIVX6mONruT5HBFqj cZlExZWZc1IaOy68Eg/gRV7BciB5gnwwSTXp4oiF00z9NPCBSZ0/jRQaEoLNXYOcitsF 6+LvKktu30HbO+2jRJ34v5g5r6ZrPjfg2bfBCoD7Lnl31oMASmO9HPs4Q9v4NnSitGv9 MaufcW+jV+envvPWZG/kHh606tHjDwpoIUwrxxJIslj2+PaVYgsRAglLpFtbEP7DOMQU UBlNi8IxD4TfRxlOa4EFxiun5jT/Kbk9IZXKzd3EH0tcITjfSOAECXrw5VBK8kOcP1ha fCvw== X-Gm-Message-State: APjAAAVg+1lEXbk6qwJU8nxDPoWV9agKOJBTwcxdqA8Zbt/11Cm/gsu9 yyW78vQm34tZTioWHFLRwzR1X/hRxeA= X-Received: by 2002:a17:90a:1ac5:: with SMTP id p63mr7090797pjp.25.1564647588607; Thu, 01 Aug 2019 01:19:48 -0700 (PDT) Received: from localhost ([122.172.28.117]) by smtp.gmail.com with ESMTPSA id f64sm74385803pfa.115.2019.08.01.01.19.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 01 Aug 2019 01:19:48 -0700 (PDT) From: Viresh Kumar To: stable@vger.kernel.org Cc: Viresh Kumar , Julien Thierry , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Marc Zyngier , Mark Rutland , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com, guohanjun@huawei.com Subject: [PATCH ARM32 v4.4 V2 05/47] firmware/psci: Expose PSCI conduit Date: Thu, 1 Aug 2019 13:45:49 +0530 Message-Id: <9af0ed2a4a54549532931e98643daa5ed274ac8f.1564646727.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Marc Zyngier commit 09a8d6d48499f93e2abde691f5800081cd858726 upstream. In order to call into the firmware to apply workarounds, it is useful to find out whether we're using HVC or SMC. Let's expose this through the psci_ops. Acked-by: Lorenzo Pieralisi Reviewed-by: Robin Murphy Tested-by: Ard Biesheuvel Signed-off-by: Marc Zyngier Signed-off-by: Catalin Marinas Signed-off-by: Viresh Kumar --- drivers/firmware/psci.c | 28 +++++++++++++++++++++++----- include/linux/psci.h | 7 +++++++ 2 files changed, 30 insertions(+), 5 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/drivers/firmware/psci.c b/drivers/firmware/psci.c index 290f8982e7b3..7b2665f6b38d 100644 --- a/drivers/firmware/psci.c +++ b/drivers/firmware/psci.c @@ -54,7 +54,9 @@ bool psci_tos_resident_on(int cpu) return cpu == resident_cpu; } -struct psci_operations psci_ops; +struct psci_operations psci_ops = { + .conduit = PSCI_CONDUIT_NONE, +}; typedef unsigned long (psci_fn)(unsigned long, unsigned long, unsigned long, unsigned long); @@ -187,6 +189,22 @@ static unsigned long psci_migrate_info_up_cpu(void) 0, 0, 0); } +static void set_conduit(enum psci_conduit conduit) +{ + switch (conduit) { + case PSCI_CONDUIT_HVC: + invoke_psci_fn = __invoke_psci_fn_hvc; + break; + case PSCI_CONDUIT_SMC: + invoke_psci_fn = __invoke_psci_fn_smc; + break; + default: + WARN(1, "Unexpected PSCI conduit %d\n", conduit); + } + + psci_ops.conduit = conduit; +} + static int get_set_conduit_method(struct device_node *np) { const char *method; @@ -199,9 +217,9 @@ static int get_set_conduit_method(struct device_node *np) } if (!strcmp("hvc", method)) { - invoke_psci_fn = __invoke_psci_fn_hvc; + set_conduit(PSCI_CONDUIT_HVC); } else if (!strcmp("smc", method)) { - invoke_psci_fn = __invoke_psci_fn_smc; + set_conduit(PSCI_CONDUIT_SMC); } else { pr_warn("invalid \"method\" property: %s\n", method); return -EINVAL; @@ -463,9 +481,9 @@ int __init psci_acpi_init(void) pr_info("probing for conduit method from ACPI.\n"); if (acpi_psci_use_hvc()) - invoke_psci_fn = __invoke_psci_fn_hvc; + set_conduit(PSCI_CONDUIT_HVC); else - invoke_psci_fn = __invoke_psci_fn_smc; + set_conduit(PSCI_CONDUIT_SMC); return psci_probe(); } diff --git a/include/linux/psci.h b/include/linux/psci.h index 04b4d92c7791..e071a1b8ddb5 100644 --- a/include/linux/psci.h +++ b/include/linux/psci.h @@ -24,6 +24,12 @@ bool psci_tos_resident_on(int cpu); bool psci_power_state_loses_context(u32 state); bool psci_power_state_is_valid(u32 state); +enum psci_conduit { + PSCI_CONDUIT_NONE, + PSCI_CONDUIT_SMC, + PSCI_CONDUIT_HVC, +}; + struct psci_operations { u32 (*get_version)(void); int (*cpu_suspend)(u32 state, unsigned long entry_point); @@ -33,6 +39,7 @@ struct psci_operations { int (*affinity_info)(unsigned long target_affinity, unsigned long lowest_affinity_level); int (*migrate_info_type)(void); + enum psci_conduit conduit; }; extern struct psci_operations psci_ops; From patchwork Thu Aug 1 08:15:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 170320 Delivered-To: patch@linaro.org Received: by 2002:a92:512:0:0:0:0:0 with SMTP id q18csp5085326ile; Thu, 1 Aug 2019 01:19:52 -0700 (PDT) X-Google-Smtp-Source: APXvYqzY07qJ+6LNLHhnwh4DLQhlcNGAbDbQ+LBLgDR+SWQNgdJIdX0Ee8OgD+lWWVFxxTumoBuH X-Received: by 2002:a17:902:848b:: with SMTP id c11mr123987030plo.217.1564647592741; Thu, 01 Aug 2019 01:19:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564647592; cv=none; d=google.com; s=arc-20160816; b=U3IaO6pGEjAfi1YstG7t27zodYYp/5BcYM00U1GD7KmmpwJAsow0T1hG7QUjRvLD+c oN9F/tlWFZ0AXTRkHhNk4gvI3xxxXCyLfWjP6JlAMXdd0Z3k6aVnL7KBItAXMzGavJCp lhp033HjU/HqkDr3wNngR71UUz3Z6O0VMGZgHP/qtF7bdrZrlocIswr25yJF4i5Qdejg 8ig5Ioe1+E96Ss6YetS/EO+fnWiQawNVKcZijs2bhXCpSoR9V9PVoctRwLI/BsbZdgu0 K/9o39T4VDgmpHrpRSz55Vb+RIloAb3Fwr1VMr7DgHcd8ALl/7lmoYmnDTZENPNCJBEq f4pg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=8FgYZ0lVoh76yEFRGdkiTuXxRHgDjc15a9Db0UAG0RM=; b=jSsjy3z6erX2bvuMBccVxIRM28Hrrs4euzu3ibO4z7nEs1ehKD30gtqn6MupGDP+1J kVoEYLGzo/07ptfvcSLNhqRnGIlRiNxIHYaSyvIbc2BSw29omYzQzzM04yJYoMp/uuaf bPs7CS37AqQRCG/yFJQt0iig6XqkZc0uap+9+9L7DzaNjip4tX+smpF47XDfqOZg9gQN 63YeiI97T8bJfSGb0wxJSB9gaIZyccEzRamnRW/OqBSGvfKtmb52hcNPmib5Vl50Qsmt pHaxpXr/Qtzd57WWFvwiSzgE5L+vMf2KgRvYMNC6LxiAdFMmg2hmKrUxebGfCem8YsXs 6WKg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=U2pFy8zp; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id ch18si32232418plb.76.2019.08.01.01.19.52; Thu, 01 Aug 2019 01:19:52 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=U2pFy8zp; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730399AbfHAITw (ORCPT + 14 others); Thu, 1 Aug 2019 04:19:52 -0400 Received: from mail-pl1-f196.google.com ([209.85.214.196]:43593 "EHLO mail-pl1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730381AbfHAITw (ORCPT ); Thu, 1 Aug 2019 04:19:52 -0400 Received: by mail-pl1-f196.google.com with SMTP id 4so24862373pld.10 for ; Thu, 01 Aug 2019 01:19:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8FgYZ0lVoh76yEFRGdkiTuXxRHgDjc15a9Db0UAG0RM=; b=U2pFy8zplP29YpsCH8W5CImqW9kDRTXequpz5TZjdTd/cKjWqInrw3Uwd1AL2uD6lU qbZ/TwswNmotIc7tfzAT06bNLn3+R8t/4ayZ3lv6smnADiIqJ77U8FH5+ntKrSwXrMCf XkgfLzlAC8TJa9x6Elq24iJrBFMA2SC0pp/liR93dQ4TUU8E2GuBBHp6WlVS6LSJhNao ImLUvMYM8Id3R/lKhgjC7TaPnfvasBP4OyyrDRFHP8oH957QYy7TLvliiwmwD+dQAitC aEVWiulUEAtHO7t4spHHwYrNSMz+RgEFMpvh3JV3t4gQZMGjxPO20KwIbAnbo9bsihGo c+7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8FgYZ0lVoh76yEFRGdkiTuXxRHgDjc15a9Db0UAG0RM=; b=ls+cNyXc5mZ1F/jaf/rljfwENA0487i1p2lc7Uy4YtuROp2YzZ0YczVSHS88Orp9DO XOYRYzVQ9i8pg976xIDg7aE1q7WgMDXsHz/J9kHrk6J1YjNqR91mCJ9M260N9buh0awG Ct2qDBr5JOWcVMhCGm7rzQscoFaz6/f1pI6RolRT3Tf3vxbnQO6MSi7zRQFxZUzcObni pB7DmOWIezTp4zrLLR0Ch8HWNHUjJsKiCr3esNF21WasuibnKBSb166SpQgP+vO2+GYd QMgfyFDYtlwA3boy9HxjP9C2HfHObcZzL+Fsqt8QiUnEyop1W4gXMUVvVQ86WMghuIxQ GdZg== X-Gm-Message-State: APjAAAWY4YM/ti67oJqsHTGe91n+Bv+jQFg8Fz/H3AWe0n6cPgeEnlaU MvdEBXdOf1OQWuBxKP/k5uIC1haFbFo= X-Received: by 2002:a17:902:ff05:: with SMTP id f5mr120452352plj.116.1564647591056; Thu, 01 Aug 2019 01:19:51 -0700 (PDT) Received: from localhost ([122.172.28.117]) by smtp.gmail.com with ESMTPSA id l6sm71842795pga.72.2019.08.01.01.19.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 01 Aug 2019 01:19:50 -0700 (PDT) From: Viresh Kumar To: stable@vger.kernel.org Cc: Viresh Kumar , Julien Thierry , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Marc Zyngier , Mark Rutland , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com, guohanjun@huawei.com Subject: [PATCH ARM32 v4.4 V2 06/47] firmware/psci: Expose SMCCC version through psci_ops Date: Thu, 1 Aug 2019 13:45:50 +0530 Message-Id: X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Marc Zyngier commit e78eef554a912ef6c1e0bbf97619dafbeae3339f upstream. Since PSCI 1.0 allows the SMCCC version to be (indirectly) probed, let's do that at boot time, and expose the version of the calling convention as part of the psci_ops structure. Acked-by: Lorenzo Pieralisi Reviewed-by: Robin Murphy Tested-by: Ard Biesheuvel Signed-off-by: Marc Zyngier Signed-off-by: Catalin Marinas [ v4.4: Included arm-smccc.h ] Signed-off-by: Viresh Kumar --- drivers/firmware/psci.c | 28 ++++++++++++++++++++++++++++ include/linux/psci.h | 6 ++++++ 2 files changed, 34 insertions(+) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/drivers/firmware/psci.c b/drivers/firmware/psci.c index 7b2665f6b38d..0809a48e8089 100644 --- a/drivers/firmware/psci.c +++ b/drivers/firmware/psci.c @@ -13,6 +13,7 @@ #define pr_fmt(fmt) "psci: " fmt +#include #include #include #include @@ -56,6 +57,7 @@ bool psci_tos_resident_on(int cpu) struct psci_operations psci_ops = { .conduit = PSCI_CONDUIT_NONE, + .smccc_version = SMCCC_VERSION_1_0, }; typedef unsigned long (psci_fn)(unsigned long, unsigned long, @@ -320,6 +322,31 @@ static void __init psci_init_migrate(void) pr_info("Trusted OS resident on physical CPU 0x%lx\n", cpuid); } +static void __init psci_init_smccc(void) +{ + u32 ver = ARM_SMCCC_VERSION_1_0; + int feature; + + feature = psci_features(ARM_SMCCC_VERSION_FUNC_ID); + + if (feature != PSCI_RET_NOT_SUPPORTED) { + u32 ret; + ret = invoke_psci_fn(ARM_SMCCC_VERSION_FUNC_ID, 0, 0, 0); + if (ret == ARM_SMCCC_VERSION_1_1) { + psci_ops.smccc_version = SMCCC_VERSION_1_1; + ver = ret; + } + } + + /* + * Conveniently, the SMCCC and PSCI versions are encoded the + * same way. No, this isn't accidental. + */ + pr_info("SMC Calling Convention v%d.%d\n", + PSCI_VERSION_MAJOR(ver), PSCI_VERSION_MINOR(ver)); + +} + static void __init psci_0_2_set_functions(void) { pr_info("Using standard PSCI v0.2 function IDs\n"); @@ -368,6 +395,7 @@ static int __init psci_probe(void) psci_init_migrate(); if (PSCI_VERSION_MAJOR(ver) >= 1) { + psci_init_smccc(); psci_init_cpu_suspend(); psci_init_system_suspend(); } diff --git a/include/linux/psci.h b/include/linux/psci.h index e071a1b8ddb5..e5c3277bfd78 100644 --- a/include/linux/psci.h +++ b/include/linux/psci.h @@ -30,6 +30,11 @@ enum psci_conduit { PSCI_CONDUIT_HVC, }; +enum smccc_version { + SMCCC_VERSION_1_0, + SMCCC_VERSION_1_1, +}; + struct psci_operations { u32 (*get_version)(void); int (*cpu_suspend)(u32 state, unsigned long entry_point); @@ -40,6 +45,7 @@ struct psci_operations { unsigned long lowest_affinity_level); int (*migrate_info_type)(void); enum psci_conduit conduit; + enum smccc_version smccc_version; }; extern struct psci_operations psci_ops; From patchwork Thu Aug 1 08:15:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 170321 Delivered-To: patch@linaro.org Received: by 2002:a92:512:0:0:0:0:0 with SMTP id q18csp5085394ile; Thu, 1 Aug 2019 01:19:55 -0700 (PDT) X-Google-Smtp-Source: APXvYqwot+gcJ2kcNokAOiSb9OIMUP7Z3lErV/42Nqp7h0HxDKzffzzLn1CmkWnyRcHC5NS0R2d0 X-Received: by 2002:a17:902:4683:: with SMTP id p3mr114989028pld.31.1564647595704; Thu, 01 Aug 2019 01:19:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564647595; cv=none; d=google.com; s=arc-20160816; b=wSnwgldiEj0dIrNe9k4Lbp0pIQLcDVt909BHw4UqNTm191bSejt4z3qWpAk7Pwjm2M 4Oy+BP3MV4UcvtYVqcHfAt/87W1j9yUQMsLCsVVEqsksXpaFU539yY8yp+HsdkRPNHOE IDSMyUzpoYFkZ437bdhvzFfmTPyt4ijiKbC2EJtRHPCz+rIFfYr9RQUGlchdtJh684sd XSDt25BNWQSRqPC7qTR7c8mCaaFlYaxxRHiqpDIdZwRN/U1G2YA43ytkQ+llkKaEV+if 1+Z3R5B/P74qenAHtHXpjHBf7dPG5xroa1gjnNwB3yNJrO4MsvLcHv0Nlui45Orf6TrO 6ukQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=QAkAWOSid7lK0+CYFipQ6VxUVVXehQyD0WFI7UyGT+o=; b=ghCtiYyiWodshuX+OHD7ryl0p1GqrS4nD8xJSPA4CNFBDPRwYvSMicmd1Hcr4SWjV2 U4RZaxARkWYf1Whn++Q4sQdSOglxcIUmPq8BO0feVizy4EMm/aXhB49aIL85/Jds56Gc jBAKHeAcnLd5OCjoE6+kh1HbQyPqavbPuMo77dleplpzjPpO5p+jWN2SyIziP8iA7/dU A7itVMhvkc2NLy9WYkzTN6HUosiT/WWMJ8wDXeLTcpFJRc1bNvofgZIGjNBz/ZVNEPfz Myui05b47gD+ks9mhNic20ajNtA4WB4b3OYGbZW/3VAblCklp9SBZTw0ulx9TNnh7+im zw4g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VbI6KvBY; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id ch18si32232418plb.76.2019.08.01.01.19.55; Thu, 01 Aug 2019 01:19:55 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VbI6KvBY; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731025AbfHAITz (ORCPT + 14 others); Thu, 1 Aug 2019 04:19:55 -0400 Received: from mail-pg1-f194.google.com ([209.85.215.194]:44250 "EHLO mail-pg1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730381AbfHAITy (ORCPT ); Thu, 1 Aug 2019 04:19:54 -0400 Received: by mail-pg1-f194.google.com with SMTP id i18so33733652pgl.11 for ; Thu, 01 Aug 2019 01:19:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QAkAWOSid7lK0+CYFipQ6VxUVVXehQyD0WFI7UyGT+o=; b=VbI6KvBYoAleWdpoNuid44aSrwYNmD6XVjYIU7cCDTWY4VDquc62cFzYoqAjoNU4c6 nZdCxO4QKpSqcfDfWapRYMgqaUzdTVFD6QEiTM4dIJb0ZM1ABvlyVKKWWtNPpds1G3lU 4p92/NPa79XeTp/RqJA3evytYoQgQIeWoUDGGWbUFJL5yJfeteKwslbEPL6XJ81zlmu4 mqBei4tEDuRtTA5ILbqgU4DBk8LIhWRf6SJUr11/UyQJ9nEkk3ZEB73W/A5g/oRFW5pC orshzn6ourcm7mrF/MHU430GQUWbheLftyEwlurTTVsAnK2IQGUQJyEuSSSvo2QsVTeB QOfw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QAkAWOSid7lK0+CYFipQ6VxUVVXehQyD0WFI7UyGT+o=; b=nRKlgGq4L31I9rhd/vrkT2LlzTw2kXxGFbVvj8XzqhJegVLZhhyapkJQLeAiyEfIlh nfqeIsphRrwq3ms8F6ScTaKAVKi4kdo+ZYvvVAQ2E4pzpFX+xxA1Plvv4ZLpd2Fu8ZKB smX9onBd6CZuDrqGS9fDTm3o1/Bym/xGzwoIXT4QlEu8Ttid7KJLxrNjBsLTTAtkJprd FLXnsaOlsn6duQYxsbM58SluvIHX71+Bfsh7S7Y4MsGs05awqnkiDTUnl/OWzts39Cre lpFWRjfTqcigzdXKTNc5I1nBJe06FYPbz9z8KlAZTl5OduWgDyhlI+4hfHlc+nd9Glr4 Rnqw== X-Gm-Message-State: APjAAAXwX+uCEvpmCATqkqH0USyX9ZHzO2GKqSLqQ4SPwBbuKhMgjHQJ pDRqAMu6SprkFd6crg/3x7OWyujiPt0= X-Received: by 2002:a63:5162:: with SMTP id r34mr686278pgl.229.1564647593609; Thu, 01 Aug 2019 01:19:53 -0700 (PDT) Received: from localhost ([122.172.28.117]) by smtp.gmail.com with ESMTPSA id u24sm10002220pgk.31.2019.08.01.01.19.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 01 Aug 2019 01:19:53 -0700 (PDT) From: Viresh Kumar To: stable@vger.kernel.org Cc: Viresh Kumar , Julien Thierry , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Marc Zyngier , Mark Rutland , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com, guohanjun@huawei.com Subject: [PATCH ARM32 v4.4 V2 07/47] arm/arm64: smccc: Make function identifiers an unsigned quantity Date: Thu, 1 Aug 2019 13:45:51 +0530 Message-Id: X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Marc Zyngier commit ded4c39e93f3b72968fdb79baba27f3b83dad34c upstream. Function identifiers are a 32bit, unsigned quantity. But we never tell so to the compiler, resulting in the following: 4ac: b26187e0 mov x0, #0xffffffff80000001 We thus rely on the firmware narrowing it for us, which is not always a reasonable expectation. Cc: stable@vger.kernel.org Reported-by: Ard Biesheuvel Acked-by: Ard Biesheuvel Reviewed-by: Robin Murphy Tested-by: Ard Biesheuvel Signed-off-by: Marc Zyngier Signed-off-by: Catalin Marinas Signed-off-by: Viresh Kumar --- include/linux/arm-smccc.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/include/linux/arm-smccc.h b/include/linux/arm-smccc.h index 1f02e4045a9e..4c45fd75db5d 100644 --- a/include/linux/arm-smccc.h +++ b/include/linux/arm-smccc.h @@ -16,6 +16,7 @@ #include #include +#include /* * This file provides common defines for ARM SMC Calling Convention as @@ -23,8 +24,8 @@ * http://infocenter.arm.com/help/topic/com.arm.doc.den0028a/index.html */ -#define ARM_SMCCC_STD_CALL 0 -#define ARM_SMCCC_FAST_CALL 1 +#define ARM_SMCCC_STD_CALL _AC(0,U) +#define ARM_SMCCC_FAST_CALL _AC(1,U) #define ARM_SMCCC_TYPE_SHIFT 31 #define ARM_SMCCC_SMC_32 0 From patchwork Thu Aug 1 08:15:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 170322 Delivered-To: patch@linaro.org Received: by 2002:a92:512:0:0:0:0:0 with SMTP id q18csp5085450ile; Thu, 1 Aug 2019 01:19:58 -0700 (PDT) X-Google-Smtp-Source: APXvYqxQ41QgfrsFLwZ5Ur8+8MbxywiigilRg8TNZaWpOwWgdv7JvCJkbmMykWHpeGdbWBpUsPVr X-Received: by 2002:a17:902:846:: with SMTP id 64mr124709348plk.265.1564647598139; Thu, 01 Aug 2019 01:19:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564647598; cv=none; d=google.com; s=arc-20160816; b=p+rI56kqFNomPw1i20vcnTyx83nogWb9dfbdp+R2NIDT4wo+lecjWi95DdwPJt5sj6 Lt03aN4oGGc2jMXd9L83p4+1PNRVtJGDiEfgiWeW8Kqyg+nab0Dnsm/vjsFqSHa8UTfA ApM68D7rObm/HvRJcd0x4yevNemqkru3zbxEqgRIsq1h9Jf7zRbNiuqEOxA0nHAJtS+7 03EZsm2NNj1sLP7SkHQ+iWn+xa3HCwGbWUJbio/aiWoWVwX66HIetLQrB4wZZh0140ej 6cPs3ynZ4g/BJRrZSMer8LXO7CATCDGsaWN6ScNiohLhxGVMf/EsmMsZHc2McruZibGU TOzQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=kulBovnYLz4YjgSJ0sOniJhX8Qcc8ljUXoag6+mJQMI=; b=OFtSj/XwR1B831uc/o5+t/FLY63Dk+7J0ke4IpVYw7rzFxa+mXvL2zi9rFbC8H4hEz p6Csb36rfhJn467MZqa81rGSv93NlYqYsTzhHTuTNVlbtTRhD8v7xuy2cWIoHGcbnT9w Q8bN2AKpy0fjIGKb8Ohs/ChKHCGCX00qDQl6ATexPHPePh/zGM1kVZxeq/xEkcQNhZsI mpR39pyAqBtgXm7womU7jyTxvS2pKPHMWMhO8h9ntm0crgTi0OQ1jXiykNIocUk65uZ1 MIir4bi1kASr0EPaWs+aIZK3BiCOPio0J1xdlcvWN8yHErufzFg5ksL5OpAuvcVkZx4x bUXQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=neGmzSpV; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id ch18si32232418plb.76.2019.08.01.01.19.57; Thu, 01 Aug 2019 01:19:58 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=neGmzSpV; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731030AbfHAIT5 (ORCPT + 14 others); Thu, 1 Aug 2019 04:19:57 -0400 Received: from mail-pf1-f194.google.com ([209.85.210.194]:40179 "EHLO mail-pf1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730381AbfHAIT5 (ORCPT ); Thu, 1 Aug 2019 04:19:57 -0400 Received: by mail-pf1-f194.google.com with SMTP id p184so33598520pfp.7 for ; Thu, 01 Aug 2019 01:19:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kulBovnYLz4YjgSJ0sOniJhX8Qcc8ljUXoag6+mJQMI=; b=neGmzSpV9c10RXeRmHvS3wtU+YOChR6vVVa7bFABnNxRBXpWpg59bG6VB4CB5sMp9u FhfBeZ5ASzEClrF62JZxBQBWIRuetSSbJtsT8SvGAkcgb8Ingpygb97sGCHM7A8gIObj 7vl8EJSxYKKYi8dUiQtPeKFeJP9Zuf+GQ3Kf8GRGlTcmSn8D/Jx1NKLDlGnoOoRp5N35 4DGMTXyfBuGk0OnMk9O9B2r7V6L3FE4PN247GpREoXR1sw1WrcTV9uYWW/yD+iCtm/8s VNLM7FAWakHBNBZwUvhs2JBWRPLJ2OkcA2ZZjEc7DrUPAZipe68TZd9XqMbZ5SGaK27y UrWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kulBovnYLz4YjgSJ0sOniJhX8Qcc8ljUXoag6+mJQMI=; b=iH0GZGcil1zslxwRxCPrk1CT6wwUJ7lVgMBc4MT3zUMWXFtua18TQTSMPJVW85ZEGW z7E0tLwDeY3ebWGEASVofEavQhz/ZLMBWwgODpmwBkBAOgZk781jIrglUesKpVY0T2ke ggndxBFgyAs+SZ5FXchF8iMcv/IlkmBX3aucRHFfbRzXQb5u+l32T8ooYetZ6KL44UNE tHT7i2UonGtfBPY2jbsrnSdZuFWWWzf6gY3ARQUtpmIc7jRtsCPMyyK/X0D+ESY03iPD wbiE5Xt+k/YMnQOBkQDYGdjzK28KPatq8n6ASC740Vm80OyTxI7aBHOQb1QU5Ak5Pqb3 m3BA== X-Gm-Message-State: APjAAAU9R0PLjledo9pAvDUOeDp+HvxPIgJTeqNr399c1N55uISA7QUO fZEdnbTjtJAUn523UdlpK7giQoSyDeU= X-Received: by 2002:aa7:9254:: with SMTP id 20mr53661464pfp.212.1564647596176; Thu, 01 Aug 2019 01:19:56 -0700 (PDT) Received: from localhost ([122.172.28.117]) by smtp.gmail.com with ESMTPSA id g2sm83127276pfi.26.2019.08.01.01.19.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 01 Aug 2019 01:19:55 -0700 (PDT) From: Viresh Kumar To: stable@vger.kernel.org Cc: Viresh Kumar , Julien Thierry , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Marc Zyngier , Mark Rutland , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com, guohanjun@huawei.com Subject: [PATCH ARM32 v4.4 V2 08/47] arm/arm64: smccc: Implement SMCCC v1.1 inline primitive Date: Thu, 1 Aug 2019 13:45:52 +0530 Message-Id: X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Marc Zyngier commit f2d3b2e8759a5833df6f022e42df2d581e6d843c upstream. One of the major improvement of SMCCC v1.1 is that it only clobbers the first 4 registers, both on 32 and 64bit. This means that it becomes very easy to provide an inline version of the SMC call primitive, and avoid performing a function call to stash the registers that would otherwise be clobbered by SMCCC v1.0. Reviewed-by: Robin Murphy Tested-by: Ard Biesheuvel Signed-off-by: Marc Zyngier Signed-off-by: Catalin Marinas Signed-off-by: Viresh Kumar --- include/linux/arm-smccc.h | 141 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 141 insertions(+) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/include/linux/arm-smccc.h b/include/linux/arm-smccc.h index 4c45fd75db5d..60c2ad6316d8 100644 --- a/include/linux/arm-smccc.h +++ b/include/linux/arm-smccc.h @@ -122,5 +122,146 @@ asmlinkage void arm_smccc_hvc(unsigned long a0, unsigned long a1, unsigned long a5, unsigned long a6, unsigned long a7, struct arm_smccc_res *res); +/* SMCCC v1.1 implementation madness follows */ +#ifdef CONFIG_ARM64 + +#define SMCCC_SMC_INST "smc #0" +#define SMCCC_HVC_INST "hvc #0" + +#elif defined(CONFIG_ARM) +#include +#include + +#define SMCCC_SMC_INST __SMC(0) +#define SMCCC_HVC_INST __HVC(0) + +#endif + +#define ___count_args(_0, _1, _2, _3, _4, _5, _6, _7, _8, x, ...) x + +#define __count_args(...) \ + ___count_args(__VA_ARGS__, 7, 6, 5, 4, 3, 2, 1, 0) + +#define __constraint_write_0 \ + "+r" (r0), "=&r" (r1), "=&r" (r2), "=&r" (r3) +#define __constraint_write_1 \ + "+r" (r0), "+r" (r1), "=&r" (r2), "=&r" (r3) +#define __constraint_write_2 \ + "+r" (r0), "+r" (r1), "+r" (r2), "=&r" (r3) +#define __constraint_write_3 \ + "+r" (r0), "+r" (r1), "+r" (r2), "+r" (r3) +#define __constraint_write_4 __constraint_write_3 +#define __constraint_write_5 __constraint_write_4 +#define __constraint_write_6 __constraint_write_5 +#define __constraint_write_7 __constraint_write_6 + +#define __constraint_read_0 +#define __constraint_read_1 +#define __constraint_read_2 +#define __constraint_read_3 +#define __constraint_read_4 "r" (r4) +#define __constraint_read_5 __constraint_read_4, "r" (r5) +#define __constraint_read_6 __constraint_read_5, "r" (r6) +#define __constraint_read_7 __constraint_read_6, "r" (r7) + +#define __declare_arg_0(a0, res) \ + struct arm_smccc_res *___res = res; \ + register u32 r0 asm("r0") = a0; \ + register unsigned long r1 asm("r1"); \ + register unsigned long r2 asm("r2"); \ + register unsigned long r3 asm("r3") + +#define __declare_arg_1(a0, a1, res) \ + struct arm_smccc_res *___res = res; \ + register u32 r0 asm("r0") = a0; \ + register typeof(a1) r1 asm("r1") = a1; \ + register unsigned long r2 asm("r2"); \ + register unsigned long r3 asm("r3") + +#define __declare_arg_2(a0, a1, a2, res) \ + struct arm_smccc_res *___res = res; \ + register u32 r0 asm("r0") = a0; \ + register typeof(a1) r1 asm("r1") = a1; \ + register typeof(a2) r2 asm("r2") = a2; \ + register unsigned long r3 asm("r3") + +#define __declare_arg_3(a0, a1, a2, a3, res) \ + struct arm_smccc_res *___res = res; \ + register u32 r0 asm("r0") = a0; \ + register typeof(a1) r1 asm("r1") = a1; \ + register typeof(a2) r2 asm("r2") = a2; \ + register typeof(a3) r3 asm("r3") = a3 + +#define __declare_arg_4(a0, a1, a2, a3, a4, res) \ + __declare_arg_3(a0, a1, a2, a3, res); \ + register typeof(a4) r4 asm("r4") = a4 + +#define __declare_arg_5(a0, a1, a2, a3, a4, a5, res) \ + __declare_arg_4(a0, a1, a2, a3, a4, res); \ + register typeof(a5) r5 asm("r5") = a5 + +#define __declare_arg_6(a0, a1, a2, a3, a4, a5, a6, res) \ + __declare_arg_5(a0, a1, a2, a3, a4, a5, res); \ + register typeof(a6) r6 asm("r6") = a6 + +#define __declare_arg_7(a0, a1, a2, a3, a4, a5, a6, a7, res) \ + __declare_arg_6(a0, a1, a2, a3, a4, a5, a6, res); \ + register typeof(a7) r7 asm("r7") = a7 + +#define ___declare_args(count, ...) __declare_arg_ ## count(__VA_ARGS__) +#define __declare_args(count, ...) ___declare_args(count, __VA_ARGS__) + +#define ___constraints(count) \ + : __constraint_write_ ## count \ + : __constraint_read_ ## count \ + : "memory" +#define __constraints(count) ___constraints(count) + +/* + * We have an output list that is not necessarily used, and GCC feels + * entitled to optimise the whole sequence away. "volatile" is what + * makes it stick. + */ +#define __arm_smccc_1_1(inst, ...) \ + do { \ + __declare_args(__count_args(__VA_ARGS__), __VA_ARGS__); \ + asm volatile(inst "\n" \ + __constraints(__count_args(__VA_ARGS__))); \ + if (___res) \ + *___res = (typeof(*___res)){r0, r1, r2, r3}; \ + } while (0) + +/* + * arm_smccc_1_1_smc() - make an SMCCC v1.1 compliant SMC call + * + * This is a variadic macro taking one to eight source arguments, and + * an optional return structure. + * + * @a0-a7: arguments passed in registers 0 to 7 + * @res: result values from registers 0 to 3 + * + * This macro is used to make SMC calls following SMC Calling Convention v1.1. + * The content of the supplied param are copied to registers 0 to 7 prior + * to the SMC instruction. The return values are updated with the content + * from register 0 to 3 on return from the SMC instruction if not NULL. + */ +#define arm_smccc_1_1_smc(...) __arm_smccc_1_1(SMCCC_SMC_INST, __VA_ARGS__) + +/* + * arm_smccc_1_1_hvc() - make an SMCCC v1.1 compliant HVC call + * + * This is a variadic macro taking one to eight source arguments, and + * an optional return structure. + * + * @a0-a7: arguments passed in registers 0 to 7 + * @res: result values from registers 0 to 3 + * + * This macro is used to make HVC calls following SMC Calling Convention v1.1. + * The content of the supplied param are copied to registers 0 to 7 prior + * to the HVC instruction. The return values are updated with the content + * from register 0 to 3 on return from the HVC instruction if not NULL. + */ +#define arm_smccc_1_1_hvc(...) __arm_smccc_1_1(SMCCC_HVC_INST, __VA_ARGS__) + #endif /*__ASSEMBLY__*/ #endif /*__LINUX_ARM_SMCCC_H*/ From patchwork Thu Aug 1 08:15:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 170323 Delivered-To: patch@linaro.org Received: by 2002:a92:512:0:0:0:0:0 with SMTP id q18csp5085496ile; Thu, 1 Aug 2019 01:20:00 -0700 (PDT) X-Google-Smtp-Source: APXvYqwT2rSsCLGHNL31cb6J/k5wX4+K7+fT3gWJN/4CrPqku0BHFvBzksGJgKONPIUN0GkJTW6j X-Received: by 2002:a17:902:9b94:: with SMTP id y20mr124311378plp.260.1564647600389; Thu, 01 Aug 2019 01:20:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564647600; cv=none; d=google.com; s=arc-20160816; b=mdFV4BhCN+88kpgcXfSuHKqTgxpRYbrLhKMsrh9eePgVIp46iTUF8U1OFWkmyvlwl5 jPA+03AoWR40ez4yJpA3ixFSsUk3XjldL/jIDnWDeSEPq1SuISed8Jsddnr6lWNkzz1H LWhV3HN2giYNCi8CK5J2LpQd9Wic1j0Wg0qILcgxuOB+xsl1F1iYMYJolD1x/E4DqMTU phq42cFxnD00PDLvo1s/Lf03eBwrRvPe6LxFeTUZ0owe9CwSQGhxnLQ9aBycBZqOd3Ig 0VdrAo1AvH3ZwaB+L+ZjaY6ryNO3AoGgjgTchqdRnQKPZTUiErLrl1C0joi0ToDRDFBo ywaA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=2QHSmiN7bxUJS4+X9m2RMygxyxd4x6cpBibWrQPbZA4=; b=tCZw3jw2FPcWv5+N+F3z61IcdGWQ1+1OHQbj+hVAhrF4F7cbEA9msPsM2dYtgh+RjW irJXaCnUG9KBPP3q3EWAXLY4CJ0TIeBIo2nLGibjjaBVCADN3lDv7aH60c/jgf1YTdNj Yu5slfXs1glH7JEIHC4XnHYtDGL1kWcvRy8b15PARJZ/xx6PcncaC8nH7mMVKbgam+gf J0KckEnQs/+r8IVvbnjtfBYhbWJc8F/B2fnaXfCSrLEKEAPkfg5PI9S9QrO3Me0RAmQ3 zguCp8FemTAUMD8qoSHRWDX1N+GEl617UobQSZPAyihikWhsTern2s5MYdM+eww8xwMO AYDw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gyCpFTJu; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Add CPU part numbers for Cortex A53, A57, A72, A73, A75 and the Broadcom Brahma B15 CPU. Signed-off-by: Russell King Acked-by: Florian Fainelli Boot-tested-by: Tony Lindgren Reviewed-by: Tony Lindgren Acked-by: Marc Zyngier Signed-off-by: David A. Long Signed-off-by: Viresh Kumar --- arch/arm/include/asm/cputype.h | 8 ++++++++ 1 file changed, 8 insertions(+) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h index e9d04f475929..76bb3bd060d1 100644 --- a/arch/arm/include/asm/cputype.h +++ b/arch/arm/include/asm/cputype.h @@ -74,8 +74,16 @@ #define ARM_CPU_PART_CORTEX_A12 0x4100c0d0 #define ARM_CPU_PART_CORTEX_A17 0x4100c0e0 #define ARM_CPU_PART_CORTEX_A15 0x4100c0f0 +#define ARM_CPU_PART_CORTEX_A53 0x4100d030 +#define ARM_CPU_PART_CORTEX_A57 0x4100d070 +#define ARM_CPU_PART_CORTEX_A72 0x4100d080 +#define ARM_CPU_PART_CORTEX_A73 0x4100d090 +#define ARM_CPU_PART_CORTEX_A75 0x4100d0a0 #define ARM_CPU_PART_MASK 0xff00fff0 +/* Broadcom cores */ +#define ARM_CPU_PART_BRAHMA_B15 0x420000f0 + #define ARM_CPU_XSCALE_ARCH_MASK 0xe000 #define ARM_CPU_XSCALE_ARCH_V1 0x2000 #define ARM_CPU_XSCALE_ARCH_V2 0x4000 From patchwork Thu Aug 1 08:15:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 170324 Delivered-To: patch@linaro.org Received: by 2002:a92:512:0:0:0:0:0 with SMTP id q18csp5085542ile; Thu, 1 Aug 2019 01:20:03 -0700 (PDT) X-Google-Smtp-Source: APXvYqxrx6amD26Rc82oVBnZY6XYrsBdse785kiVtO3BWM8gU7pR7WtaH/HfQLHxrdDuqr+JUZCA X-Received: by 2002:a17:90a:5207:: with SMTP id v7mr6924302pjh.127.1564647603024; Thu, 01 Aug 2019 01:20:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564647603; cv=none; d=google.com; s=arc-20160816; b=VZpqMT6hsaioVl0nzSInRshpmiMUhcB4TvgTOR1nCCzZYqcM+4bjD1d8Ljk/JzpqBR 3/S/RSkwefdCSNcX+1G7nXGSyfoHg5m0Uh86v0OTWpk1EK1bWHFOliahf0WgoB4cqJgj zoEe+x2sUNMpQwK7zI3yfjccGnb+3Y9LF3Sytg/Xe3AIGwq4oaCwz3Ssn7qWl9s34v9h nmzKExtxbyGmHsYEEQUNSI+Tb45Z8tGI6CSyjdwseU5Jz9hye/8b3pCBleiqXDu8mvtV cWQKqFUFM7v7+G3jPtaspuaguCrFOBYIcAOeWyAijqD1eXD9LBIK1c/gGYNpgaQ+vGZu YJ+w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=2ThYg/2PcaE2XPc0i5Ecb1/dXdxeDGNU8nmJ2xJHUWI=; b=qBNdNin6G6IV9xYvJgPJc4HwuKBvnAFA+1AtTn/NDwzRQ75vl8fUGxtlurGfz9/sg1 X7bCl0rWPC9D3dag0entKHfl6jYDXxsH6WB/AeGB4Vnb9gwUTRkbsmB+pUjogPHmxAuL ojwhfplJo8CqEXJApzqzfxa1tie/szzMdz+2By2h1fQhDtJdUX7kgXWgmx55Xk1KHLww qAG2sOS7bG62Zw7+dd7v1e+N1lBXl+9SSMxYL6GSN0iRkWzhvFzVA9hr/xq8sKEnXKCe CgIfQAYzWOvFpoJ2C1O/Q/HYLSbO0qoDI52Ujuaeat3HTSEnCHuKdWMUf+sAcjNh8Zx9 d6Uw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=qgyOciaZ; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Prepare the processor bug infrastructure so that it can be expanded to check for per-processor bugs. Signed-off-by: Russell King Reviewed-by: Florian Fainelli Boot-tested-by: Tony Lindgren Reviewed-by: Tony Lindgren Acked-by: Marc Zyngier Signed-off-by: David A. Long Signed-off-by: Viresh Kumar --- arch/arm/include/asm/bugs.h | 4 ++-- arch/arm/kernel/Makefile | 1 + arch/arm/kernel/bugs.c | 9 +++++++++ 3 files changed, 12 insertions(+), 2 deletions(-) create mode 100644 arch/arm/kernel/bugs.c -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm/include/asm/bugs.h b/arch/arm/include/asm/bugs.h index a97f1ea708d1..ed122d294f3f 100644 --- a/arch/arm/include/asm/bugs.h +++ b/arch/arm/include/asm/bugs.h @@ -10,10 +10,10 @@ #ifndef __ASM_BUGS_H #define __ASM_BUGS_H -#ifdef CONFIG_MMU extern void check_writebuffer_bugs(void); -#define check_bugs() check_writebuffer_bugs() +#ifdef CONFIG_MMU +extern void check_bugs(void); #else #define check_bugs() do { } while (0) #endif diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile index 3c789496297f..f936cec24f72 100644 --- a/arch/arm/kernel/Makefile +++ b/arch/arm/kernel/Makefile @@ -30,6 +30,7 @@ else obj-y += entry-armv.o endif +obj-$(CONFIG_MMU) += bugs.o obj-$(CONFIG_CPU_IDLE) += cpuidle.o obj-$(CONFIG_ISA_DMA_API) += dma.o obj-$(CONFIG_FIQ) += fiq.o fiqasm.o diff --git a/arch/arm/kernel/bugs.c b/arch/arm/kernel/bugs.c new file mode 100644 index 000000000000..88024028bb70 --- /dev/null +++ b/arch/arm/kernel/bugs.c @@ -0,0 +1,9 @@ +// SPDX-Identifier: GPL-2.0 +#include +#include +#include + +void __init check_bugs(void) +{ + check_writebuffer_bugs(); +} From patchwork Thu Aug 1 08:15:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 170325 Delivered-To: patch@linaro.org Received: by 2002:a92:512:0:0:0:0:0 with SMTP id q18csp5085581ile; Thu, 1 Aug 2019 01:20:05 -0700 (PDT) X-Google-Smtp-Source: APXvYqwfOZp4KNVqCRi2X/GK3Xl+LxyDouzmH+11NLIBYoZNRXW/E1ZNMjkZb4OS2Ej6T11zDimQ X-Received: by 2002:a17:902:b285:: with SMTP id u5mr35762398plr.329.1564647605479; Thu, 01 Aug 2019 01:20:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564647605; cv=none; d=google.com; s=arc-20160816; b=p0vO4X6o9TshQnWD6nKqiAkdJ1m8rMXkUKPYnMBUCPzglEz5v8sXa6veYwYWKVzTsG n3WkEISS81RgpgbkZOi5QejqSO0HHcVTR7hT7RYVDyy5Xiphcyw3cYzYh5K8krrB8gXX FOstMB55ydTJxm1q+aQkQAsS3FJfajyBEKZZg28XkvUAHEPzFORuYKqlZrM9ArBtwOAS cwDNvyeD7K5uLeDMs8jxbESz0FmKVdRYsGgWGO4fnc8hJLhBUWXGIGU5cKe14XABtws3 dXMNMIwnaMXqNjNuMl+yzUajrYKmJROOZYHg0O3KTjgw2hQET6WtwXD2cMNw1MkdLujm 3rZw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=X5q/embD7eXIzs5RT/nIptjidKOY81lXVOsi7bVlsas=; b=rZI90/PbTTqq4hYAZdoz4zxkSav7LIOowZ8FUsD7IKEQAHvWVE4k92IhG2pXPdmkFY w5weKjjs2PAjhP8NvFMYSZ1Qrq8avamJjSU0wuGerVdNxomm/E97qTrlEhQUqWJCHZ+q sxKt3Um3/pRTvKP/+ahNdOHwblQjGXtIpT/BmQKEpasKk5LUJewhPLhod0BaIyqHLDgl YgqV6VXAi29CaPLfEgJ4WX14SSTan/dLvR101m58wst8XsNgLFubtgcZyydBA4iv8vHC mEmpL0h+p1mqK8SiA0YUFSviKlxcaA+g1tDw1rOv7oT2q1gFRh4pDhUtcIOBEaJkhbph R5fw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=h+PuW0lE; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Check for CPU bugs when secondary processors are being brought online, and also when CPUs are resuming from a low power mode. This gives an opportunity to check that processor specific bug workarounds are correctly enabled for all paths that a CPU re-enters the kernel. Signed-off-by: Russell King Reviewed-by: Florian Fainelli Boot-tested-by: Tony Lindgren Reviewed-by: Tony Lindgren Acked-by: Marc Zyngier Signed-off-by: David A. Long Signed-off-by: Viresh Kumar --- arch/arm/include/asm/bugs.h | 2 ++ arch/arm/kernel/bugs.c | 5 +++++ arch/arm/kernel/smp.c | 4 ++++ arch/arm/kernel/suspend.c | 2 ++ 4 files changed, 13 insertions(+) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm/include/asm/bugs.h b/arch/arm/include/asm/bugs.h index ed122d294f3f..73a99c72a930 100644 --- a/arch/arm/include/asm/bugs.h +++ b/arch/arm/include/asm/bugs.h @@ -14,8 +14,10 @@ extern void check_writebuffer_bugs(void); #ifdef CONFIG_MMU extern void check_bugs(void); +extern void check_other_bugs(void); #else #define check_bugs() do { } while (0) +#define check_other_bugs() do { } while (0) #endif #endif diff --git a/arch/arm/kernel/bugs.c b/arch/arm/kernel/bugs.c index 88024028bb70..16e7ba2a9cc4 100644 --- a/arch/arm/kernel/bugs.c +++ b/arch/arm/kernel/bugs.c @@ -3,7 +3,12 @@ #include #include +void check_other_bugs(void) +{ +} + void __init check_bugs(void) { check_writebuffer_bugs(); + check_other_bugs(); } diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c index 0f1c11861147..bafbd29c6e64 100644 --- a/arch/arm/kernel/smp.c +++ b/arch/arm/kernel/smp.c @@ -29,6 +29,7 @@ #include #include +#include #include #include #include @@ -396,6 +397,9 @@ asmlinkage void secondary_start_kernel(void) * before we continue - which happens after __cpu_up returns. */ set_cpu_online(cpu, true); + + check_other_bugs(); + complete(&cpu_running); local_irq_enable(); diff --git a/arch/arm/kernel/suspend.c b/arch/arm/kernel/suspend.c index 9a2f882a0a2d..134f0d432610 100644 --- a/arch/arm/kernel/suspend.c +++ b/arch/arm/kernel/suspend.c @@ -1,6 +1,7 @@ #include #include +#include #include #include #include @@ -34,6 +35,7 @@ int cpu_suspend(unsigned long arg, int (*fn)(unsigned long)) cpu_switch_mm(mm->pgd, mm); local_flush_bp_all(); local_flush_tlb_all(); + check_other_bugs(); } return ret; From patchwork Thu Aug 1 08:15:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 170326 Delivered-To: patch@linaro.org Received: by 2002:a92:512:0:0:0:0:0 with SMTP id q18csp5085648ile; Thu, 1 Aug 2019 01:20:09 -0700 (PDT) X-Google-Smtp-Source: APXvYqzjroGFMlhx3WZrj7sYlato8naDRAAqiOKAZZio0XarnnJKZPirFT1Fn5JeCGNIy4FJvUZK X-Received: by 2002:a17:902:381:: with SMTP id d1mr121796594pld.331.1564647608798; Thu, 01 Aug 2019 01:20:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564647608; cv=none; d=google.com; s=arc-20160816; b=szaNvGoBeOR6uePyxrkl2qRg0+4aPDzXidNzrYX+gukhZqXlX1P7lOttCUwjA/QIwR OJBgVv2iLyJtGM8ttVXQ5VmXKagB8FR6jI5QRhA0chcHT2/w6LIyZQnDDRwlMbdOeqGD UnBjOPzhrq77HEUzDjaxvwTN/BFDDo3uEoP8M1uQEb7O9CGaZkasnC4Au/XILLbB28IB cBwvXQkuKU6y+QgIdWv/jGAidv3PFci4cvZ/y/moo19DrGgQzoRCqX5UBXyFAR1KrDGU UdfLbKqcWSVQCdRVp35r7WYNDDy+vKuNNt8AaxtHIMWq40syktLYJzr/BR72rPOlF24u CtEw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=TdEXa/ACn7xvRmbVhm+K3Nf7xZB7iBxOAU/Z5YPY+9w=; b=PLTT1Y4RdhvW/rwpoOW2l6eD301OKBGapawmPCW7UbGEk+AoaQ/i9ec5sAyLzauiA1 nFWzeWXLGogWo+y3/ki8/yY2F78Ys6VDw5vKVlIyvuJdJ2jargmjkkcEwHFyx6E3sSZD Tai6V+RF+KzbTLp9haxDGwoQSE+0TnwskZoODnhRVMPt61RcZE37E6vO086+PM765AYh aCgdlc8JdlRP30rgzh/RClVpcs82Lem/4rtpZy0YJd1b/kV3zAysQ9L7ZWZ1ffTLs7HZ TqYAoiRs2Fr+15+xZK4QoC59y8EV2ot33uQn7Q8tR2+5HOHgJHmNlXV7ajTJGUTwXR3A NbBg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Yc1AA1CJ; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Add support for per-processor bug checking - each processor function descriptor gains a function pointer for this check, which must not be an __init function. If non-NULL, this will be called whenever a CPU enters the kernel via which ever path (boot CPU, secondary CPU startup, CPU resuming, etc.) This allows processor specific bug checks to validate that workaround bits are properly enabled by firmware via all entry paths to the kernel. Signed-off-by: Russell King Reviewed-by: Florian Fainelli Boot-tested-by: Tony Lindgren Reviewed-by: Tony Lindgren Acked-by: Marc Zyngier Signed-off-by: David A. Long Signed-off-by: Viresh Kumar --- arch/arm/include/asm/proc-fns.h | 4 ++++ arch/arm/kernel/bugs.c | 4 ++++ arch/arm/mm/proc-macros.S | 3 ++- 3 files changed, 10 insertions(+), 1 deletion(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm/include/asm/proc-fns.h b/arch/arm/include/asm/proc-fns.h index 8877ad5ffe10..f379f5f849a9 100644 --- a/arch/arm/include/asm/proc-fns.h +++ b/arch/arm/include/asm/proc-fns.h @@ -36,6 +36,10 @@ extern struct processor { * Set up any processor specifics */ void (*_proc_init)(void); + /* + * Check for processor bugs + */ + void (*check_bugs)(void); /* * Disable any processor specifics */ diff --git a/arch/arm/kernel/bugs.c b/arch/arm/kernel/bugs.c index 16e7ba2a9cc4..7be511310191 100644 --- a/arch/arm/kernel/bugs.c +++ b/arch/arm/kernel/bugs.c @@ -5,6 +5,10 @@ void check_other_bugs(void) { +#ifdef MULTI_CPU + if (processor.check_bugs) + processor.check_bugs(); +#endif } void __init check_bugs(void) diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S index c671f345266a..212147c78f4b 100644 --- a/arch/arm/mm/proc-macros.S +++ b/arch/arm/mm/proc-macros.S @@ -258,13 +258,14 @@ mcr p15, 0, ip, c7, c10, 4 @ data write barrier .endm -.macro define_processor_functions name:req, dabort:req, pabort:req, nommu=0, suspend=0 +.macro define_processor_functions name:req, dabort:req, pabort:req, nommu=0, suspend=0, bugs=0 .type \name\()_processor_functions, #object .align 2 ENTRY(\name\()_processor_functions) .word \dabort .word \pabort .word cpu_\name\()_proc_init + .word \bugs .word cpu_\name\()_proc_fin .word cpu_\name\()_reset .word cpu_\name\()_do_idle From patchwork Thu Aug 1 08:15:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 170327 Delivered-To: patch@linaro.org Received: by 2002:a92:512:0:0:0:0:0 with SMTP id q18csp5085665ile; Thu, 1 Aug 2019 01:20:11 -0700 (PDT) X-Google-Smtp-Source: APXvYqwjTbpzL3ddUg8xiDGAPTWHIuqehDbO5CrZBVWz/sq9PUYB6hwLErLTydwm25WLa7Xq1dNx X-Received: by 2002:a17:902:8696:: with SMTP id g22mr121333631plo.249.1564647611429; Thu, 01 Aug 2019 01:20:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564647611; cv=none; d=google.com; s=arc-20160816; b=VMyo9eBRIwzyx+foqZvEwAE6Vkrgt/QVsghmAEAXafgBf2T06guWUjSGEnaHeMCTiQ anR6OX7EiqTMP9WsrF345snfMZoMIM5sfud65d5sLwGIoUoZYPXyHqfTCzE3w5wgEX/7 7zFVCgYyXrsrJPChsJBQmFLH6ofeLVh4s13ccUjEfzKB+9xLgbhuGWBVsIilsa5SN2Xm g2jVA+tblfhrWjAKiiYDEmUdF5ahoPd58xBDVrpiQN8i6RHyLcEU/PpVdpg9pzdfmT7/ 4K7cy/Xt8D9FArEEZRLceuBdiBavU3olj55bjmC8k+6ZYFyoJ7+eSCiJ74zA5Hw3vmT3 xnsA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=QZrcuQ9yf2dvoM/LK+86CRpxpDI5KmyMnFr+EN3SZok=; b=OQnXVJCscIQssEn8zwgAPqcgZ5uDFIHTvB5kAS3PKmiLJEfxmcrxEtJIZfRYi7LApI hG/DBo007z0KUXoPnK7Qk2feRzSIELKq138PV4CeSpm0wc0k9Opwz9yKvY8WIdX7vuES e/N1JK6yPz3E14yGkIhGCgTnTEDRc3Wo7S+tEGiBy4rQdjOXgVpPEqfJFCXRfrbGk5Vp AJC8KisXr17gr98qFMjvkqeUEubZU9+isrZwkoVkzTNh3PX3Ne17FA/R3yrHJmUqncRz qqHwd7zudSdL3oVZ+GF62vselBPx5VOMy1u0/F0gdfllRTskMX5lJE3TMTe3zytauBOx ijEQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JQrn7jF9; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Add a Kconfig symbol for CPUs which are vulnerable to the Spectre attacks. Signed-off-by: Russell King Reviewed-by: Florian Fainelli Boot-tested-by: Tony Lindgren Reviewed-by: Tony Lindgren Acked-by: Marc Zyngier Signed-off-by: David A. Long Signed-off-by: Viresh Kumar --- arch/arm/mm/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 41218867a9a6..7ef92e6692ab 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -396,6 +396,7 @@ config CPU_V7 select CPU_CP15_MPU if !MMU select CPU_HAS_ASID if MMU select CPU_PABRT_V7 + select CPU_SPECTRE if MMU select CPU_TLB_V7 if MMU # ARMv7M @@ -793,6 +794,9 @@ config CPU_BPREDICT_DISABLE help Say Y here to disable branch prediction. If unsure, say N. +config CPU_SPECTRE + bool + config TLS_REG_EMUL bool select NEED_KUSER_HELPERS From patchwork Thu Aug 1 08:15:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 170328 Delivered-To: patch@linaro.org Received: by 2002:a92:512:0:0:0:0:0 with SMTP id q18csp5085749ile; Thu, 1 Aug 2019 01:20:16 -0700 (PDT) X-Google-Smtp-Source: APXvYqz4lO8WWrWGeV7W2+056Zd9IBabO+AOodJ8ihdXo+e0/4fU3ufUIwxWHB/vEvvZWXwfGKGs X-Received: by 2002:a65:44cb:: with SMTP id g11mr71645055pgs.288.1564647616350; Thu, 01 Aug 2019 01:20:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564647616; cv=none; d=google.com; s=arc-20160816; b=bh/WuC6yzoLlrMnlStLPc+0L5O8EORT0OFzxvzh8WsU42mBXGrOvVarKcJT4mksETj qjHByevXMvWyx5D+5ffJ0iS85RKFm5D/JQqTZDv8tVwE12gYw+/QqXAa+IPpXjI5WNcT tRbBhILwCbaJymRJZMp5wozhX5Vnbtd6ZYya+0ySv1IPB4+45nvM5PQDrh0pftihXUDt 7vODEk96VXNimRz/Jr31kSBf5w+5macfaC7ySCHLOnGxWjda3ffk8rcIoI3CEOmxcWAI rnWhxgNbsNyZxp9ioqZUwHSEnOoJmpoNYUt1GxNwRz9ePX6DWWf0MYn7L4MgpColQwSC 1uMQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=CrIyupKIrKrrK5tgrFteGLmJmhdaioApkHetxHZMz8k=; b=tAZHu1QjMX2E/5jo6DDLvcvtN9Ox91dO0BtVMHxRG1aKkWyt+Dm/nAou887FAWeZXM k5EoiJoxrWfxlZYZHa66SNGsZSzOrSiU1PG3JtPDDOfTNzH8JlXwyYzHZbx4hCLNu72j dIbEB7NzD4AUKCjAUEJ+IbLgRDh/Nu345A1kOTcHBZTG7qIKkPB4e1FfwOK+JkbyTZ9f UMMVWmndGktMi2WgkYsBc+QbdLZSkxXIYd+tghq0OWQPZWVMoO5a+/4pLlVBYwaIilDC 9/ZhiORjLdEIp+3MGYQDHq2NRiURDE/QtVyacX7xJaZFu4Rn/Eo3XGB1d/10lWG5eqsJ uhEg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=K2QIFbnp; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Required manual merge of arch/arm/mm/proc-v7.S. Harden the branch predictor against Spectre v2 attacks on context switches for ARMv7 and later CPUs. We do this by: Cortex A9, A12, A17, A73, A75: invalidating the BTB. Cortex A15, Brahma B15: invalidating the instruction cache. Cortex A57 and Cortex A72 are not addressed in this patch. Cortex R7 and Cortex R8 are also not addressed as we do not enforce memory protection on these cores. Signed-off-by: Russell King Boot-tested-by: Tony Lindgren Reviewed-by: Tony Lindgren Acked-by: Marc Zyngier Signed-off-by: David A. Long Signed-off-by: Viresh Kumar --- arch/arm/mm/Kconfig | 19 ++++++ arch/arm/mm/proc-v7-2level.S | 6 -- arch/arm/mm/proc-v7.S | 125 +++++++++++++++++++++++++++-------- 3 files changed, 115 insertions(+), 35 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 7ef92e6692ab..71115afb71a0 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -797,6 +797,25 @@ config CPU_BPREDICT_DISABLE config CPU_SPECTRE bool +config HARDEN_BRANCH_PREDICTOR + bool "Harden the branch predictor against aliasing attacks" if EXPERT + depends on CPU_SPECTRE + default y + help + Speculation attacks against some high-performance processors rely + on being able to manipulate the branch predictor for a victim + context by executing aliasing branches in the attacker context. + Such attacks can be partially mitigated against by clearing + internal branch predictor state and limiting the prediction + logic in some situations. + + This config option will take CPU-specific actions to harden + the branch predictor against aliasing attacks and may rely on + specific instruction sequences or control bits being set by + the system firmware. + + If unsure, say Y. + config TLS_REG_EMUL bool select NEED_KUSER_HELPERS diff --git a/arch/arm/mm/proc-v7-2level.S b/arch/arm/mm/proc-v7-2level.S index c6141a5435c3..f8d45ad2a515 100644 --- a/arch/arm/mm/proc-v7-2level.S +++ b/arch/arm/mm/proc-v7-2level.S @@ -41,11 +41,6 @@ * even on Cortex-A8 revisions not affected by 430973. * If IBE is not set, the flush BTAC/BTB won't do anything. */ -ENTRY(cpu_ca8_switch_mm) -#ifdef CONFIG_MMU - mov r2, #0 - mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB -#endif ENTRY(cpu_v7_switch_mm) #ifdef CONFIG_MMU mmid r1, r1 @ get mm->context.id @@ -66,7 +61,6 @@ ENTRY(cpu_v7_switch_mm) #endif bx lr ENDPROC(cpu_v7_switch_mm) -ENDPROC(cpu_ca8_switch_mm) /* * cpu_v7_set_pte_ext(ptep, pte) diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 8e1ea433c3f1..c2950317c7c2 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -87,6 +87,17 @@ ENTRY(cpu_v7_dcache_clean_area) ret lr ENDPROC(cpu_v7_dcache_clean_area) +ENTRY(cpu_v7_iciallu_switch_mm) + mov r3, #0 + mcr p15, 0, r3, c7, c5, 0 @ ICIALLU + b cpu_v7_switch_mm +ENDPROC(cpu_v7_iciallu_switch_mm) +ENTRY(cpu_v7_bpiall_switch_mm) + mov r3, #0 + mcr p15, 0, r3, c7, c5, 6 @ flush BTAC/BTB + b cpu_v7_switch_mm +ENDPROC(cpu_v7_bpiall_switch_mm) + string cpu_v7_name, "ARMv7 Processor" .align @@ -152,31 +163,6 @@ ENTRY(cpu_v7_do_resume) ENDPROC(cpu_v7_do_resume) #endif -/* - * Cortex-A8 - */ - globl_equ cpu_ca8_proc_init, cpu_v7_proc_init - globl_equ cpu_ca8_proc_fin, cpu_v7_proc_fin - globl_equ cpu_ca8_reset, cpu_v7_reset - globl_equ cpu_ca8_do_idle, cpu_v7_do_idle - globl_equ cpu_ca8_dcache_clean_area, cpu_v7_dcache_clean_area - globl_equ cpu_ca8_set_pte_ext, cpu_v7_set_pte_ext - globl_equ cpu_ca8_suspend_size, cpu_v7_suspend_size -#ifdef CONFIG_ARM_CPU_SUSPEND - globl_equ cpu_ca8_do_suspend, cpu_v7_do_suspend - globl_equ cpu_ca8_do_resume, cpu_v7_do_resume -#endif - -/* - * Cortex-A9 processor functions - */ - globl_equ cpu_ca9mp_proc_init, cpu_v7_proc_init - globl_equ cpu_ca9mp_proc_fin, cpu_v7_proc_fin - globl_equ cpu_ca9mp_reset, cpu_v7_reset - globl_equ cpu_ca9mp_do_idle, cpu_v7_do_idle - globl_equ cpu_ca9mp_dcache_clean_area, cpu_v7_dcache_clean_area - globl_equ cpu_ca9mp_switch_mm, cpu_v7_switch_mm - globl_equ cpu_ca9mp_set_pte_ext, cpu_v7_set_pte_ext .globl cpu_ca9mp_suspend_size .equ cpu_ca9mp_suspend_size, cpu_v7_suspend_size + 4 * 2 #ifdef CONFIG_ARM_CPU_SUSPEND @@ -490,10 +476,75 @@ ENDPROC(__v7_setup) @ define struct processor (see and proc-macros.S) define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1 + +#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR + @ generic v7 bpiall on context switch + globl_equ cpu_v7_bpiall_proc_init, cpu_v7_proc_init + globl_equ cpu_v7_bpiall_proc_fin, cpu_v7_proc_fin + globl_equ cpu_v7_bpiall_reset, cpu_v7_reset + globl_equ cpu_v7_bpiall_do_idle, cpu_v7_do_idle + globl_equ cpu_v7_bpiall_dcache_clean_area, cpu_v7_dcache_clean_area + globl_equ cpu_v7_bpiall_set_pte_ext, cpu_v7_set_pte_ext + globl_equ cpu_v7_bpiall_suspend_size, cpu_v7_suspend_size +#ifdef CONFIG_ARM_CPU_SUSPEND + globl_equ cpu_v7_bpiall_do_suspend, cpu_v7_do_suspend + globl_equ cpu_v7_bpiall_do_resume, cpu_v7_do_resume +#endif + define_processor_functions v7_bpiall, dabort=v7_early_abort, pabort=v7_pabort, suspend=1 + +#define HARDENED_BPIALL_PROCESSOR_FUNCTIONS v7_bpiall_processor_functions +#else +#define HARDENED_BPIALL_PROCESSOR_FUNCTIONS v7_processor_functions +#endif + #ifndef CONFIG_ARM_LPAE + @ Cortex-A8 - always needs bpiall switch_mm implementation + globl_equ cpu_ca8_proc_init, cpu_v7_proc_init + globl_equ cpu_ca8_proc_fin, cpu_v7_proc_fin + globl_equ cpu_ca8_reset, cpu_v7_reset + globl_equ cpu_ca8_do_idle, cpu_v7_do_idle + globl_equ cpu_ca8_dcache_clean_area, cpu_v7_dcache_clean_area + globl_equ cpu_ca8_set_pte_ext, cpu_v7_set_pte_ext + globl_equ cpu_ca8_switch_mm, cpu_v7_bpiall_switch_mm + globl_equ cpu_ca8_suspend_size, cpu_v7_suspend_size +#ifdef CONFIG_ARM_CPU_SUSPEND + globl_equ cpu_ca8_do_suspend, cpu_v7_do_suspend + globl_equ cpu_ca8_do_resume, cpu_v7_do_resume +#endif define_processor_functions ca8, dabort=v7_early_abort, pabort=v7_pabort, suspend=1 + + @ Cortex-A9 - needs more registers preserved across suspend/resume + @ and bpiall switch_mm for hardening + globl_equ cpu_ca9mp_proc_init, cpu_v7_proc_init + globl_equ cpu_ca9mp_proc_fin, cpu_v7_proc_fin + globl_equ cpu_ca9mp_reset, cpu_v7_reset + globl_equ cpu_ca9mp_do_idle, cpu_v7_do_idle + globl_equ cpu_ca9mp_dcache_clean_area, cpu_v7_dcache_clean_area +#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR + globl_equ cpu_ca9mp_switch_mm, cpu_v7_bpiall_switch_mm +#else + globl_equ cpu_ca9mp_switch_mm, cpu_v7_switch_mm +#endif + globl_equ cpu_ca9mp_set_pte_ext, cpu_v7_set_pte_ext define_processor_functions ca9mp, dabort=v7_early_abort, pabort=v7_pabort, suspend=1 #endif + + @ Cortex-A15 - needs iciallu switch_mm for hardening + globl_equ cpu_ca15_proc_init, cpu_v7_proc_init + globl_equ cpu_ca15_proc_fin, cpu_v7_proc_fin + globl_equ cpu_ca15_reset, cpu_v7_reset + globl_equ cpu_ca15_do_idle, cpu_v7_do_idle + globl_equ cpu_ca15_dcache_clean_area, cpu_v7_dcache_clean_area +#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR + globl_equ cpu_ca15_switch_mm, cpu_v7_iciallu_switch_mm +#else + globl_equ cpu_ca15_switch_mm, cpu_v7_switch_mm +#endif + globl_equ cpu_ca15_set_pte_ext, cpu_v7_set_pte_ext + globl_equ cpu_ca15_suspend_size, cpu_v7_suspend_size + globl_equ cpu_ca15_do_suspend, cpu_v7_do_suspend + globl_equ cpu_ca15_do_resume, cpu_v7_do_resume + define_processor_functions ca15, dabort=v7_early_abort, pabort=v7_pabort, suspend=1 #ifdef CONFIG_CPU_PJ4B define_processor_functions pj4b, dabort=v7_early_abort, pabort=v7_pabort, suspend=1 #endif @@ -600,7 +651,7 @@ ENDPROC(__v7_setup) __v7_ca12mp_proc_info: .long 0x410fc0d0 .long 0xff0ffff0 - __v7_proc __v7_ca12mp_proc_info, __v7_ca12mp_setup + __v7_proc __v7_ca12mp_proc_info, __v7_ca12mp_setup, proc_fns = HARDENED_BPIALL_PROCESSOR_FUNCTIONS .size __v7_ca12mp_proc_info, . - __v7_ca12mp_proc_info /* @@ -610,7 +661,7 @@ ENDPROC(__v7_setup) __v7_ca15mp_proc_info: .long 0x410fc0f0 .long 0xff0ffff0 - __v7_proc __v7_ca15mp_proc_info, __v7_ca15mp_setup + __v7_proc __v7_ca15mp_proc_info, __v7_ca15mp_setup, proc_fns = ca15_processor_functions .size __v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info /* @@ -620,7 +671,7 @@ ENDPROC(__v7_setup) __v7_b15mp_proc_info: .long 0x420f00f0 .long 0xff0ffff0 - __v7_proc __v7_b15mp_proc_info, __v7_b15mp_setup + __v7_proc __v7_b15mp_proc_info, __v7_b15mp_setup, proc_fns = ca15_processor_functions .size __v7_b15mp_proc_info, . - __v7_b15mp_proc_info /* @@ -630,9 +681,25 @@ ENDPROC(__v7_setup) __v7_ca17mp_proc_info: .long 0x410fc0e0 .long 0xff0ffff0 - __v7_proc __v7_ca17mp_proc_info, __v7_ca17mp_setup + __v7_proc __v7_ca17mp_proc_info, __v7_ca17mp_setup, proc_fns = HARDENED_BPIALL_PROCESSOR_FUNCTIONS .size __v7_ca17mp_proc_info, . - __v7_ca17mp_proc_info + /* ARM Ltd. Cortex A73 processor */ + .type __v7_ca73_proc_info, #object +__v7_ca73_proc_info: + .long 0x410fd090 + .long 0xff0ffff0 + __v7_proc __v7_ca73_proc_info, __v7_setup, proc_fns = HARDENED_BPIALL_PROCESSOR_FUNCTIONS + .size __v7_ca73_proc_info, . - __v7_ca73_proc_info + + /* ARM Ltd. Cortex A75 processor */ + .type __v7_ca75_proc_info, #object +__v7_ca75_proc_info: + .long 0x410fd0a0 + .long 0xff0ffff0 + __v7_proc __v7_ca75_proc_info, __v7_setup, proc_fns = HARDENED_BPIALL_PROCESSOR_FUNCTIONS + .size __v7_ca75_proc_info, . - __v7_ca75_proc_info + /* * Qualcomm Inc. Krait processors. */ From patchwork Thu Aug 1 08:15:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 170356 Delivered-To: patch@linaro.org Received: by 2002:a92:512:0:0:0:0:0 with SMTP id q18csp5088456ile; Thu, 1 Aug 2019 01:22:47 -0700 (PDT) X-Google-Smtp-Source: APXvYqxVUAlLsiY9JekPuxZGEZN3oeV3dZBExULEroxhhkZFBOo79ixPpTh4On9lPTcNpxwi/qay X-Received: by 2002:a65:6458:: with SMTP id s24mr6656838pgv.158.1564647619015; Thu, 01 Aug 2019 01:20:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564647619; cv=none; d=google.com; s=arc-20160816; b=iCm9Liu3iE06OdnghcNnhWa+yw4a7E+mi5iaBVLr9mp86hHdOt59gCbPKCRrsQWYL+ 0LmigSRnGlS6xx7aL9k3aC3RrdRJ8RX3gQVwaKCxtCCtuHuGQJYLnHKAnQ3feTcafbpi XwYuC0y7PvBP6dn8BEpcVHTyEijdj7UL9u68I8zTfOdkZZVzE8xUCLqXh17oXR6Yx99N X2CSzzjOJKlda67l1mv/T0yeYicyJh+0DDIopDr1g/eM1JH1HWKciHEckAvvATqo1uIA hnh60AOPeWP0xSLYSyi8GEv7beUrqu7OC2yCRrJ8l4b0bhYMkabepO/dcOtynWUE420x 5CuQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Arpm02aGI6YJCtpiPBRj6TsiybDi8jaAFcwPdh06aYE=; b=tKMV8D5FD9Vd2ebyYBvBGHJwtMr7Fpt7EJilHyf5khecE4RirpBSoJoEDD5hgpswdd bOIcB7eeNUl8iMWMC95JgNAWxMwx1mOpiqMOGtFqEL+3j6rW6DvuhI5tQd2JwAkYyD5G KPOOyi+mKeSGwi+dDPPURk2BTigIMmB8SlgeN+oOqNQXjw30z89eJP475dUbxwZMgznT LDY3X3JX1e2K0dNd25oxaO5++L/DCNwOHekgvtQYG9Vma3dgx6DqQmy7/UlWbi7U00A/ FNrdfLw17NS0AdUez8kxLBI4sqbZ9v3GVcyvYAeiET8j97C7qijSTKdshHWabn7g+n9L JmPg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=KFNcIvSP; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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When the branch predictor hardening is enabled, firmware must have set the IBE bit in the auxiliary control register. If this bit has not been set, the Spectre workarounds will not be functional. Add validation that this bit is set, and print a warning at alert level if this is not the case. Signed-off-by: Russell King Reviewed-by: Florian Fainelli Boot-tested-by: Tony Lindgren Reviewed-by: Tony Lindgren Signed-off-by: David A. Long Signed-off-by: Viresh Kumar --- arch/arm/mm/Makefile | 2 +- arch/arm/mm/proc-v7-bugs.c | 36 ++++++++++++++++++++++++++++++++++++ arch/arm/mm/proc-v7.S | 4 ++-- 3 files changed, 39 insertions(+), 3 deletions(-) create mode 100644 arch/arm/mm/proc-v7-bugs.c -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile index 7f76d96ce546..35307176e46c 100644 --- a/arch/arm/mm/Makefile +++ b/arch/arm/mm/Makefile @@ -92,7 +92,7 @@ obj-$(CONFIG_CPU_MOHAWK) += proc-mohawk.o obj-$(CONFIG_CPU_FEROCEON) += proc-feroceon.o obj-$(CONFIG_CPU_V6) += proc-v6.o obj-$(CONFIG_CPU_V6K) += proc-v6.o -obj-$(CONFIG_CPU_V7) += proc-v7.o +obj-$(CONFIG_CPU_V7) += proc-v7.o proc-v7-bugs.o obj-$(CONFIG_CPU_V7M) += proc-v7m.o AFLAGS_proc-v6.o :=-Wa,-march=armv6 diff --git a/arch/arm/mm/proc-v7-bugs.c b/arch/arm/mm/proc-v7-bugs.c new file mode 100644 index 000000000000..e46557db6446 --- /dev/null +++ b/arch/arm/mm/proc-v7-bugs.c @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0 +#include +#include + +static __maybe_unused void cpu_v7_check_auxcr_set(bool *warned, + u32 mask, const char *msg) +{ + u32 aux_cr; + + asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (aux_cr)); + + if ((aux_cr & mask) != mask) { + if (!*warned) + pr_err("CPU%u: %s", smp_processor_id(), msg); + *warned = true; + } +} + +static DEFINE_PER_CPU(bool, spectre_warned); + +static void check_spectre_auxcr(bool *warned, u32 bit) +{ + if (IS_ENABLED(CONFIG_HARDEN_BRANCH_PREDICTOR) && + cpu_v7_check_auxcr_set(warned, bit, + "Spectre v2: firmware did not set auxiliary control register IBE bit, system vulnerable\n"); +} + +void cpu_v7_ca8_ibe(void) +{ + check_spectre_auxcr(this_cpu_ptr(&spectre_warned), BIT(6)); +} + +void cpu_v7_ca15_ibe(void) +{ + check_spectre_auxcr(this_cpu_ptr(&spectre_warned), BIT(0)); +} diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index c2950317c7c2..1436ad424f2a 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -511,7 +511,7 @@ ENDPROC(__v7_setup) globl_equ cpu_ca8_do_suspend, cpu_v7_do_suspend globl_equ cpu_ca8_do_resume, cpu_v7_do_resume #endif - define_processor_functions ca8, dabort=v7_early_abort, pabort=v7_pabort, suspend=1 + define_processor_functions ca8, dabort=v7_early_abort, pabort=v7_pabort, suspend=1, bugs=cpu_v7_ca8_ibe @ Cortex-A9 - needs more registers preserved across suspend/resume @ and bpiall switch_mm for hardening @@ -544,7 +544,7 @@ ENDPROC(__v7_setup) globl_equ cpu_ca15_suspend_size, cpu_v7_suspend_size globl_equ cpu_ca15_do_suspend, cpu_v7_do_suspend globl_equ cpu_ca15_do_resume, cpu_v7_do_resume - define_processor_functions ca15, dabort=v7_early_abort, pabort=v7_pabort, suspend=1 + define_processor_functions ca15, dabort=v7_early_abort, pabort=v7_pabort, suspend=1, bugs=cpu_v7_ca15_ibe #ifdef CONFIG_CPU_PJ4B define_processor_functions pj4b, dabort=v7_early_abort, pabort=v7_pabort, suspend=1 #endif From patchwork Thu Aug 1 08:16:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 170355 Delivered-To: patch@linaro.org Received: by 2002:a92:512:0:0:0:0:0 with SMTP id q18csp5088292ile; Thu, 1 Aug 2019 01:22:36 -0700 (PDT) X-Google-Smtp-Source: APXvYqxoyz88p3jpJghETJukrzobqjnEUYXpm4+gtqe33dscaPpZiV6oh0EOlMOsYi4ZSxjqas1c X-Received: by 2002:a63:4846:: with SMTP id x6mr82001503pgk.332.1564647620689; Thu, 01 Aug 2019 01:20:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564647620; cv=none; d=google.com; s=arc-20160816; b=egAP7r2uI5JJMawLdOOTElVByw1+8xArN2x9IkeGX9Mu6YFAduLy/3kve9SUTYtmFG X9zXvsUx5CTctUf9bESUP+qPP9D3lAYLgfZOxePSHuEw1DA/Iw8BxRyeZQnhtWVRozRE GtvvAjAwG51+EpXjEJXAD05z6QuAOro4IxOOIqK2q8s160diaqA/YCBCflQo+YKSAzGN EaGnSK1VqeyDgFqE1EYgjLcL73Uu8hjJXLq/0Lhs2AjooOleI7BxRoPwtXNcZHpQEdtJ HuLJ4fb9rU1p5Ye+5vG+WaHKAGMWXT44hGsx6RvNpDzn6lcNmI4innjwlTXfQpEid9U/ RMZA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=GWBuoPEcurWKDak0e2m8FiUiWeWYmr8zikb3n4XMh3U=; b=ofhK/8wc+ppMjl41dGSkV6YdnNT4IEhfDFaXDhjTWi2w+38iAMWRcd2V6X8IoPZz7O 3Z3FjpUUbN9WRsLfZGujH9/6h1slLSnDvEvjiPgRZ6WBQRPaLiZqHnZFBCRjBB7VubMP X6dGTfJXXEc9xt7ZtdjVIiSgmL0jq2NRszpwqUrY5rcaJmqGRXl6z03NRcZlvW/DhwrW iPd8pJ88TczcyjQZ55GJQihF/makaEBt0UcxXrvf1bKLQfUjDyIFHy6aW6GNMm3/hnT+ QiwoP7ilnLDr7zPtO2c1YIPVE/lpBApd7AVt3jBHKuJ9IOUeO5w2/79WaIgw7KKr1r8K pCtA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=q7HiAZVZ; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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This required some additional defines be brought back. In order to prevent aliasing attacks on the branch predictor, invalidate the BTB or instruction cache on CPUs that are known to be affected when taking an abort on a address that is outside of a user task limit: Cortex A8, A9, A12, A17, A73, A75: flush BTB. Cortex A15, Brahma B15: invalidate icache. If the IBE bit is not set, then there is little point to enabling the workaround. Signed-off-by: Russell King Boot-tested-by: Tony Lindgren Reviewed-by: Tony Lindgren Signed-off-by: Florian Fainelli Signed-off-by: David A. Long Signed-off-by: Viresh Kumar --- arch/arm/include/asm/cp15.h | 18 ++++++++ arch/arm/include/asm/system_misc.h | 15 ++++++ arch/arm/mm/fault.c | 3 ++ arch/arm/mm/proc-v7-bugs.c | 73 ++++++++++++++++++++++++++++-- arch/arm/mm/proc-v7.S | 8 ++-- 5 files changed, 109 insertions(+), 8 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm/include/asm/cp15.h b/arch/arm/include/asm/cp15.h index c3f11524f10c..b74b174ac9fc 100644 --- a/arch/arm/include/asm/cp15.h +++ b/arch/arm/include/asm/cp15.h @@ -49,6 +49,24 @@ #ifdef CONFIG_CPU_CP15 +#define __ACCESS_CP15(CRn, Op1, CRm, Op2) \ + "mrc", "mcr", __stringify(p15, Op1, %0, CRn, CRm, Op2), u32 +#define __ACCESS_CP15_64(Op1, CRm) \ + "mrrc", "mcrr", __stringify(p15, Op1, %Q0, %R0, CRm), u64 + +#define __read_sysreg(r, w, c, t) ({ \ + t __val; \ + asm volatile(r " " c : "=r" (__val)); \ + __val; \ +}) +#define read_sysreg(...) __read_sysreg(__VA_ARGS__) + +#define __write_sysreg(v, r, w, c, t) asm volatile(w " " c : : "r" ((t)(v))) +#define write_sysreg(v, ...) __write_sysreg(v, __VA_ARGS__) + +#define BPIALL __ACCESS_CP15(c7, 0, c5, 6) +#define ICIALLU __ACCESS_CP15(c7, 0, c5, 0) + extern unsigned long cr_alignment; /* defined in entry-armv.S */ static inline unsigned long get_cr(void) diff --git a/arch/arm/include/asm/system_misc.h b/arch/arm/include/asm/system_misc.h index a3d61ad984af..1fed41440af9 100644 --- a/arch/arm/include/asm/system_misc.h +++ b/arch/arm/include/asm/system_misc.h @@ -7,6 +7,7 @@ #include #include #include +#include extern void cpu_init(void); @@ -14,6 +15,20 @@ void soft_restart(unsigned long); extern void (*arm_pm_restart)(enum reboot_mode reboot_mode, const char *cmd); extern void (*arm_pm_idle)(void); +#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR +typedef void (*harden_branch_predictor_fn_t)(void); +DECLARE_PER_CPU(harden_branch_predictor_fn_t, harden_branch_predictor_fn); +static inline void harden_branch_predictor(void) +{ + harden_branch_predictor_fn_t fn = per_cpu(harden_branch_predictor_fn, + smp_processor_id()); + if (fn) + fn(); +} +#else +#define harden_branch_predictor() do { } while (0) +#endif + #define UDBG_UNDEFINED (1 << 0) #define UDBG_SYSCALL (1 << 1) #define UDBG_BADABORT (1 << 2) diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c index 0d20cd594017..afc8d7cf7625 100644 --- a/arch/arm/mm/fault.c +++ b/arch/arm/mm/fault.c @@ -163,6 +163,9 @@ __do_user_fault(struct task_struct *tsk, unsigned long addr, { struct siginfo si; + if (addr > TASK_SIZE) + harden_branch_predictor(); + #ifdef CONFIG_DEBUG_USER if (((user_debug & UDBG_SEGV) && (sig == SIGSEGV)) || ((user_debug & UDBG_BUS) && (sig == SIGBUS))) { diff --git a/arch/arm/mm/proc-v7-bugs.c b/arch/arm/mm/proc-v7-bugs.c index e46557db6446..85a2e3d6263c 100644 --- a/arch/arm/mm/proc-v7-bugs.c +++ b/arch/arm/mm/proc-v7-bugs.c @@ -2,7 +2,61 @@ #include #include -static __maybe_unused void cpu_v7_check_auxcr_set(bool *warned, +#include +#include +#include + +#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR +DEFINE_PER_CPU(harden_branch_predictor_fn_t, harden_branch_predictor_fn); + +static void harden_branch_predictor_bpiall(void) +{ + write_sysreg(0, BPIALL); +} + +static void harden_branch_predictor_iciallu(void) +{ + write_sysreg(0, ICIALLU); +} + +static void cpu_v7_spectre_init(void) +{ + const char *spectre_v2_method = NULL; + int cpu = smp_processor_id(); + + if (per_cpu(harden_branch_predictor_fn, cpu)) + return; + + switch (read_cpuid_part()) { + case ARM_CPU_PART_CORTEX_A8: + case ARM_CPU_PART_CORTEX_A9: + case ARM_CPU_PART_CORTEX_A12: + case ARM_CPU_PART_CORTEX_A17: + case ARM_CPU_PART_CORTEX_A73: + case ARM_CPU_PART_CORTEX_A75: + per_cpu(harden_branch_predictor_fn, cpu) = + harden_branch_predictor_bpiall; + spectre_v2_method = "BPIALL"; + break; + + case ARM_CPU_PART_CORTEX_A15: + case ARM_CPU_PART_BRAHMA_B15: + per_cpu(harden_branch_predictor_fn, cpu) = + harden_branch_predictor_iciallu; + spectre_v2_method = "ICIALLU"; + break; + } + if (spectre_v2_method) + pr_info("CPU%u: Spectre v2: using %s workaround\n", + smp_processor_id(), spectre_v2_method); +} +#else +static void cpu_v7_spectre_init(void) +{ +} +#endif + +static __maybe_unused bool cpu_v7_check_auxcr_set(bool *warned, u32 mask, const char *msg) { u32 aux_cr; @@ -13,24 +67,33 @@ static __maybe_unused void cpu_v7_check_auxcr_set(bool *warned, if (!*warned) pr_err("CPU%u: %s", smp_processor_id(), msg); *warned = true; + return false; } + return true; } static DEFINE_PER_CPU(bool, spectre_warned); -static void check_spectre_auxcr(bool *warned, u32 bit) +static bool check_spectre_auxcr(bool *warned, u32 bit) { - if (IS_ENABLED(CONFIG_HARDEN_BRANCH_PREDICTOR) && + return IS_ENABLED(CONFIG_HARDEN_BRANCH_PREDICTOR) && cpu_v7_check_auxcr_set(warned, bit, "Spectre v2: firmware did not set auxiliary control register IBE bit, system vulnerable\n"); } void cpu_v7_ca8_ibe(void) { - check_spectre_auxcr(this_cpu_ptr(&spectre_warned), BIT(6)); + if (check_spectre_auxcr(this_cpu_ptr(&spectre_warned), BIT(6))) + cpu_v7_spectre_init(); } void cpu_v7_ca15_ibe(void) { - check_spectre_auxcr(this_cpu_ptr(&spectre_warned), BIT(0)); + if (check_spectre_auxcr(this_cpu_ptr(&spectre_warned), BIT(0))) + cpu_v7_spectre_init(); +} + +void cpu_v7_bugs_init(void) +{ + cpu_v7_spectre_init(); } diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 1436ad424f2a..f6a4589b4fd2 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -474,8 +474,10 @@ ENDPROC(__v7_setup) __INITDATA + .weak cpu_v7_bugs_init + @ define struct processor (see and proc-macros.S) - define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1 + define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1, bugs=cpu_v7_bugs_init #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR @ generic v7 bpiall on context switch @@ -490,7 +492,7 @@ ENDPROC(__v7_setup) globl_equ cpu_v7_bpiall_do_suspend, cpu_v7_do_suspend globl_equ cpu_v7_bpiall_do_resume, cpu_v7_do_resume #endif - define_processor_functions v7_bpiall, dabort=v7_early_abort, pabort=v7_pabort, suspend=1 + define_processor_functions v7_bpiall, dabort=v7_early_abort, pabort=v7_pabort, suspend=1, bugs=cpu_v7_bugs_init #define HARDENED_BPIALL_PROCESSOR_FUNCTIONS v7_bpiall_processor_functions #else @@ -526,7 +528,7 @@ ENDPROC(__v7_setup) globl_equ cpu_ca9mp_switch_mm, cpu_v7_switch_mm #endif globl_equ cpu_ca9mp_set_pte_ext, cpu_v7_set_pte_ext - define_processor_functions ca9mp, dabort=v7_early_abort, pabort=v7_pabort, suspend=1 + define_processor_functions ca9mp, dabort=v7_early_abort, pabort=v7_pabort, suspend=1, bugs=cpu_v7_bugs_init #endif @ Cortex-A15 - needs iciallu switch_mm for hardening From patchwork Thu Aug 1 08:16:01 2019 Content-Type: text/plain; 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Add firmware based hardening for cores that require more complex handling in firmware. Signed-off-by: Russell King Boot-tested-by: Tony Lindgren Reviewed-by: Tony Lindgren Reviewed-by: Marc Zyngier Signed-off-by: David A. Long Signed-off-by: Viresh Kumar --- arch/arm/mm/proc-v7-bugs.c | 60 ++++++++++++++++++++++++++++++++++++++ arch/arm/mm/proc-v7.S | 21 +++++++++++++ 2 files changed, 81 insertions(+) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm/mm/proc-v7-bugs.c b/arch/arm/mm/proc-v7-bugs.c index 85a2e3d6263c..da25a38e1897 100644 --- a/arch/arm/mm/proc-v7-bugs.c +++ b/arch/arm/mm/proc-v7-bugs.c @@ -1,14 +1,20 @@ // SPDX-License-Identifier: GPL-2.0 +#include #include +#include #include #include #include +#include #include #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR DEFINE_PER_CPU(harden_branch_predictor_fn_t, harden_branch_predictor_fn); +extern void cpu_v7_smc_switch_mm(phys_addr_t pgd_phys, struct mm_struct *mm); +extern void cpu_v7_hvc_switch_mm(phys_addr_t pgd_phys, struct mm_struct *mm); + static void harden_branch_predictor_bpiall(void) { write_sysreg(0, BPIALL); @@ -19,6 +25,16 @@ static void harden_branch_predictor_iciallu(void) write_sysreg(0, ICIALLU); } +static void __maybe_unused call_smc_arch_workaround_1(void) +{ + arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_1, NULL); +} + +static void __maybe_unused call_hvc_arch_workaround_1(void) +{ + arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_WORKAROUND_1, NULL); +} + static void cpu_v7_spectre_init(void) { const char *spectre_v2_method = NULL; @@ -45,7 +61,51 @@ static void cpu_v7_spectre_init(void) harden_branch_predictor_iciallu; spectre_v2_method = "ICIALLU"; break; + +#ifdef CONFIG_ARM_PSCI + default: + /* Other ARM CPUs require no workaround */ + if (read_cpuid_implementor() == ARM_CPU_IMP_ARM) + break; + /* fallthrough */ + /* Cortex A57/A72 require firmware workaround */ + case ARM_CPU_PART_CORTEX_A57: + case ARM_CPU_PART_CORTEX_A72: { + struct arm_smccc_res res; + + if (psci_ops.smccc_version == SMCCC_VERSION_1_0) + break; + + switch (psci_ops.conduit) { + case PSCI_CONDUIT_HVC: + arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID, + ARM_SMCCC_ARCH_WORKAROUND_1, &res); + if ((int)res.a0 != 0) + break; + per_cpu(harden_branch_predictor_fn, cpu) = + call_hvc_arch_workaround_1; + processor.switch_mm = cpu_v7_hvc_switch_mm; + spectre_v2_method = "hypervisor"; + break; + + case PSCI_CONDUIT_SMC: + arm_smccc_1_1_smc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID, + ARM_SMCCC_ARCH_WORKAROUND_1, &res); + if ((int)res.a0 != 0) + break; + per_cpu(harden_branch_predictor_fn, cpu) = + call_smc_arch_workaround_1; + processor.switch_mm = cpu_v7_smc_switch_mm; + spectre_v2_method = "firmware"; + break; + + default: + break; + } } +#endif + } + if (spectre_v2_method) pr_info("CPU%u: Spectre v2: using %s workaround\n", smp_processor_id(), spectre_v2_method); diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index f6a4589b4fd2..b6359ce39fa7 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -9,6 +9,7 @@ * * This is the "shell" of the ARMv7 processor support. */ +#include #include #include #include @@ -87,6 +88,26 @@ ENTRY(cpu_v7_dcache_clean_area) ret lr ENDPROC(cpu_v7_dcache_clean_area) +#ifdef CONFIG_ARM_PSCI + .arch_extension sec +ENTRY(cpu_v7_smc_switch_mm) + stmfd sp!, {r0 - r3} + movw r0, #:lower16:ARM_SMCCC_ARCH_WORKAROUND_1 + movt r0, #:upper16:ARM_SMCCC_ARCH_WORKAROUND_1 + smc #0 + ldmfd sp!, {r0 - r3} + b cpu_v7_switch_mm +ENDPROC(cpu_v7_smc_switch_mm) + .arch_extension virt +ENTRY(cpu_v7_hvc_switch_mm) + stmfd sp!, {r0 - r3} + movw r0, #:lower16:ARM_SMCCC_ARCH_WORKAROUND_1 + movt r0, #:upper16:ARM_SMCCC_ARCH_WORKAROUND_1 + hvc #0 + ldmfd sp!, {r0 - r3} + b cpu_v7_switch_mm +ENDPROC(cpu_v7_smc_switch_mm) +#endif ENTRY(cpu_v7_iciallu_switch_mm) mov r3, #0 mcr p15, 0, r3, c7, c5, 0 @ ICIALLU From patchwork Thu Aug 1 08:16:02 2019 Content-Type: text/plain; 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Warn at error level if the context switching function is not what we are expecting. This can happen with big.Little systems, which we currently do not support. Signed-off-by: Russell King Boot-tested-by: Tony Lindgren Reviewed-by: Tony Lindgren Acked-by: Marc Zyngier Signed-off-by: David A. Long Signed-off-by: Viresh Kumar --- arch/arm/mm/proc-v7-bugs.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm/mm/proc-v7-bugs.c b/arch/arm/mm/proc-v7-bugs.c index da25a38e1897..5544b82a2e7a 100644 --- a/arch/arm/mm/proc-v7-bugs.c +++ b/arch/arm/mm/proc-v7-bugs.c @@ -12,6 +12,8 @@ #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR DEFINE_PER_CPU(harden_branch_predictor_fn_t, harden_branch_predictor_fn); +extern void cpu_v7_iciallu_switch_mm(phys_addr_t pgd_phys, struct mm_struct *mm); +extern void cpu_v7_bpiall_switch_mm(phys_addr_t pgd_phys, struct mm_struct *mm); extern void cpu_v7_smc_switch_mm(phys_addr_t pgd_phys, struct mm_struct *mm); extern void cpu_v7_hvc_switch_mm(phys_addr_t pgd_phys, struct mm_struct *mm); @@ -50,6 +52,8 @@ static void cpu_v7_spectre_init(void) case ARM_CPU_PART_CORTEX_A17: case ARM_CPU_PART_CORTEX_A73: case ARM_CPU_PART_CORTEX_A75: + if (processor.switch_mm != cpu_v7_bpiall_switch_mm) + goto bl_error; per_cpu(harden_branch_predictor_fn, cpu) = harden_branch_predictor_bpiall; spectre_v2_method = "BPIALL"; @@ -57,6 +61,8 @@ static void cpu_v7_spectre_init(void) case ARM_CPU_PART_CORTEX_A15: case ARM_CPU_PART_BRAHMA_B15: + if (processor.switch_mm != cpu_v7_iciallu_switch_mm) + goto bl_error; per_cpu(harden_branch_predictor_fn, cpu) = harden_branch_predictor_iciallu; spectre_v2_method = "ICIALLU"; @@ -82,6 +88,8 @@ static void cpu_v7_spectre_init(void) ARM_SMCCC_ARCH_WORKAROUND_1, &res); if ((int)res.a0 != 0) break; + if (processor.switch_mm != cpu_v7_hvc_switch_mm && cpu) + goto bl_error; per_cpu(harden_branch_predictor_fn, cpu) = call_hvc_arch_workaround_1; processor.switch_mm = cpu_v7_hvc_switch_mm; @@ -93,6 +101,8 @@ static void cpu_v7_spectre_init(void) ARM_SMCCC_ARCH_WORKAROUND_1, &res); if ((int)res.a0 != 0) break; + if (processor.switch_mm != cpu_v7_smc_switch_mm && cpu) + goto bl_error; per_cpu(harden_branch_predictor_fn, cpu) = call_smc_arch_workaround_1; processor.switch_mm = cpu_v7_smc_switch_mm; @@ -109,6 +119,11 @@ static void cpu_v7_spectre_init(void) if (spectre_v2_method) pr_info("CPU%u: Spectre v2: using %s workaround\n", smp_processor_id(), spectre_v2_method); + return; + +bl_error: + pr_err("CPU%u: Spectre v2: incorrect context switching function, system vulnerable\n", + cpu); } #else static void cpu_v7_spectre_init(void) From patchwork Thu Aug 1 08:16:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 170360 Delivered-To: patch@linaro.org Received: by 2002:a92:512:0:0:0:0:0 with SMTP id q18csp5088742ile; Thu, 1 Aug 2019 01:23:04 -0700 (PDT) X-Google-Smtp-Source: APXvYqyVOpfa7jWs25yIkHPEwEXXsKGdm7lu8trsuAzCXhZThHt/pJGjLr2mbNxY+Kfo3sv8IAOM X-Received: by 2002:a65:528d:: with SMTP id y13mr29454806pgp.120.1564647627712; Thu, 01 Aug 2019 01:20:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564647627; cv=none; d=google.com; s=arc-20160816; b=RgNkqGviNVfg16K6QDkz1d4tjpiBw0YkVLq7XteQAg3QjxzmbCvHiKcYmx8BKpnzGv lt99PAQljdMm+YFUfI18q9HZyqQw+H24W/2mXZ+9q/ctMnmHvDFxcoORgHlJS423FgzT KTfAagGhDHFW/9ViMfwCmDG4pLUMK80WRn4M7h9DVBlan7zU4oHY+BOZfyM6vgPvinCM oEMIHORv4TbBsVDZH5qrKKMRxYKYlbxJbiWI9r318cW/v7PQ8o2aqdf+SFij7ID6ZOHV olwPWz79idGx1+lM3XK4QLemgGsV45G4VhYj0G/+BgN5/1x3wgiu1zORhW8flotO2vZ6 jThA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=prTlbc1VpFmNDiAv6vpTx2HEDdjE/0SlqakQ6arRd2E=; b=rVzYRwVQp4qpJ29RFMFJJWRkxGJpqcOh76rmLc15XMTB9pc3OWDwakFhZG52xlpKOk XXolo+xKK1Silcr2z7iZLQwNjYXO+FW20qLuxa2cWbgekVJM0O0/vX4NpnexTV9MC8pH FmqYmiqKHNkUDrbEoaRakfAhayYKWrGsSJHSo/uhAghO/2PHdehtZVW2tUZTEAJu7INI cI5Vfg6RX8n8BeUASfg03FXxj15g9zGSNOuPNMD8bZqrnxeijrk4JroVpT1ez3ChrPJY PmYOF/kNt5LL7+XtbQ1lSvJ1ti9ILNn46bc52yHYlkFxYqIrRY3A8x5hKsDOCWnKiNU5 AlOg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pbXyYpmT; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Add assembly and C macros for the new CSDB instruction. Signed-off-by: Russell King Acked-by: Mark Rutland Boot-tested-by: Tony Lindgren Reviewed-by: Tony Lindgren Signed-off-by: David A. Long Signed-off-by: Viresh Kumar --- arch/arm/include/asm/assembler.h | 8 ++++++++ arch/arm/include/asm/barrier.h | 13 +++++++++++++ 2 files changed, 21 insertions(+) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h index 4a275fba6059..307901f88a1e 100644 --- a/arch/arm/include/asm/assembler.h +++ b/arch/arm/include/asm/assembler.h @@ -441,6 +441,14 @@ THUMB( orr \reg , \reg , #PSR_T_BIT ) .size \name , . - \name .endm + .macro csdb +#ifdef CONFIG_THUMB2_KERNEL + .inst.w 0xf3af8014 +#else + .inst 0xe320f014 +#endif + .endm + .macro check_uaccess, addr:req, size:req, limit:req, tmp:req, bad:req #ifndef CONFIG_CPU_USE_DOMAINS adds \tmp, \addr, #\size - 1 diff --git a/arch/arm/include/asm/barrier.h b/arch/arm/include/asm/barrier.h index 27c1d26b05b5..edd9e633a84b 100644 --- a/arch/arm/include/asm/barrier.h +++ b/arch/arm/include/asm/barrier.h @@ -18,6 +18,12 @@ #define isb(option) __asm__ __volatile__ ("isb " #option : : : "memory") #define dsb(option) __asm__ __volatile__ ("dsb " #option : : : "memory") #define dmb(option) __asm__ __volatile__ ("dmb " #option : : : "memory") +#ifdef CONFIG_THUMB2_KERNEL +#define CSDB ".inst.w 0xf3af8014" +#else +#define CSDB ".inst 0xe320f014" +#endif +#define csdb() __asm__ __volatile__(CSDB : : : "memory") #elif defined(CONFIG_CPU_XSC3) || __LINUX_ARM_ARCH__ == 6 #define isb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \ : : "r" (0) : "memory") @@ -38,6 +44,13 @@ #define dmb(x) __asm__ __volatile__ ("" : : : "memory") #endif +#ifndef CSDB +#define CSDB +#endif +#ifndef csdb +#define csdb() +#endif + #ifdef CONFIG_ARM_HEAVY_MB extern void (*soc_mb)(void); extern void arm_heavy_mb(void); From patchwork Thu Aug 1 08:16:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 170361 Delivered-To: patch@linaro.org Received: by 2002:a92:512:0:0:0:0:0 with SMTP id q18csp5088762ile; Thu, 1 Aug 2019 01:23:06 -0700 (PDT) X-Google-Smtp-Source: APXvYqyiAAor7ObrnKc01GBNaXY2ZbjSmI5UMpajGecgZ9DkO20fTEsK7A5qxgn3e+wEc6Y0jud9 X-Received: by 2002:a65:610a:: with SMTP id z10mr118182284pgu.178.1564647629663; Thu, 01 Aug 2019 01:20:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564647629; cv=none; d=google.com; s=arc-20160816; b=boCpYJn0pDtomX5L70WGnGU5Hm97HijVBPpNwJVYnpFqw3lM6ButQVhbWXZieyHOdJ K114exKSsUDBCB8vYmxARlhWwRfy02GV4lNTryY64TmKFEjtE4WdriN8cALH1wj1se/M V8gX/kd6hl6s168KEtzvOfOyaexUw1ymtIj/gQZdQ3W7KqEAtdG/d0eZYVyBstZQwJEA lWCV5Ndn1bHpUx4cQEhxXk6ow4X5XDAPGn8fIvdaiLiUdQb7XxEsT24AV19YjEPolOUe w8jlt6o/Co5AbeapCA/lnZ4VX7Lb5BP+sytJit9dA7/zmkV8O1aOjLC0yHlzYznLa3n6 +RHg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Ws1lkPqBsn87EY7GxNn+AzRrtY/P0vuzwO4T5yjsQK0=; b=cH2VUHJXwCTRh4TpTaAvcotDzziXpy0s7wqMQWiL81QPsNXThvZB7r0pz/3MaJeZO2 35kNqvpd2mR3r3QUk07iKz3FidxJgTjk5k7Qg2HFUkwOJ7EXK7pP1ryyPNCqbvMEZY5i NmBzRhcKdv+aHoohfbgE3I1NyqU/RvB1KSRBz6e9ERWYpZNdMA7El2t/oOGJklnCSFHI xioiNWA/PYH6osTAltSTNtlcElXBuEgdIi37wG3YDAB9YlGAIml2nZPSHaWzaCpqVzAD 0KKCIWEXtsWJOyfIs4L7iNH2f96wFqdD/qtDDgNBsxq1ml5t92DkIpwUmhlIeydR1H4K GNig== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vibnYP12; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f10si37407577pfq.194.2019.08.01.01.20.29; Thu, 01 Aug 2019 01:20:29 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vibnYP12; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729712AbfHAIU3 (ORCPT + 14 others); Thu, 1 Aug 2019 04:20:29 -0400 Received: from mail-pl1-f196.google.com ([209.85.214.196]:42881 "EHLO mail-pl1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731084AbfHAIU2 (ORCPT ); Thu, 1 Aug 2019 04:20:28 -0400 Received: by mail-pl1-f196.google.com with SMTP id ay6so31902582plb.9 for ; Thu, 01 Aug 2019 01:20:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Ws1lkPqBsn87EY7GxNn+AzRrtY/P0vuzwO4T5yjsQK0=; b=vibnYP12Yj8WtQhINzxmLEByeOMlswC0F2GsMI8dE21QSoRhhqbMo+P7AxcGVojRUA /hT+AkEZH0AS115dCqaaXUuSv0k+4joEOreBP/68Gjb0QidyVKyPg0W89H6SlBkzcfcp +cgas23ax3Ib54qSLu3Dip6Am24mT5q2SQImorxH2sBLXwAJweYLO4iBosEvBRd4DZrN efKdS/jHbZT1/UT+qeOxf/oohBhdIpK1I7/N7ZoMU/QH/q6/zPpQlJjvHkjPsQK66OCr FiBeYSXRrQraypOAvPkKR35SP+Z/gRLeDjKA3IcMFJn1qq0vSD4pyg4aIYuWEK11NbbJ rqEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Ws1lkPqBsn87EY7GxNn+AzRrtY/P0vuzwO4T5yjsQK0=; b=Cx4aSfdShRcwo/zTFj0J41yeeP+9IedHu6DHT1dyCEpWfNxiXFgbQUOSpcOI80hcgR aQeTpb9VYtoKp6647qX9NAl/4ubCKZcv1+8r2pUi/K+wav0totV94bf9upbcscbNK4pe 69ZwVuf4Czhh+bljHFnLo7mNKAwef/7KEYurKkvyh45/ShEC3QImkgxRfaSztogsB0X0 yUwpo9bKz8OlX/pWYL/+CNtUA1qIG9AP4WohbEKNCEfNfcct0QKF/ReSswJye/zrqXkV mFxXHNTF8oiMgbp4WDA9Dzif5XqhD0rOgaoNadfoDtrYHLcU3vlSBzgwOgjIzD0FpM6X ol2Q== X-Gm-Message-State: APjAAAXC0JeVmHSjU0bDvAQL3p26y5xULN7p7MEt5120VN5RcmLe5Qrm NRAJj3a41CC/b1+9iTDeY6817CRK2ko= X-Received: by 2002:a17:902:7043:: with SMTP id h3mr97891950plt.10.1564647627732; Thu, 01 Aug 2019 01:20:27 -0700 (PDT) Received: from localhost ([122.172.28.117]) by smtp.gmail.com with ESMTPSA id y194sm47237763pfg.116.2019.08.01.01.20.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 01 Aug 2019 01:20:27 -0700 (PDT) From: Viresh Kumar To: stable@vger.kernel.org Cc: Viresh Kumar , Julien Thierry , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Marc Zyngier , Mark Rutland , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com, guohanjun@huawei.com Subject: [PATCH ARM32 v4.4 V2 20/47] ARM: spectre-v1: add array_index_mask_nospec() implementation Date: Thu, 1 Aug 2019 13:46:04 +0530 Message-Id: <68b8f200fef6b51b5a140ef541fd4455ef704294.1564646727.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Russell King Commit 1d4238c56f9816ce0f9c8dbe42d7f2ad81cb6613 upstream. Add an implementation of the array_index_mask_nospec() function for mitigating Spectre variant 1 throughout the kernel. Signed-off-by: Russell King Acked-by: Mark Rutland Boot-tested-by: Tony Lindgren Reviewed-by: Tony Lindgren Signed-off-by: David A. Long Signed-off-by: Viresh Kumar --- arch/arm/include/asm/barrier.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm/include/asm/barrier.h b/arch/arm/include/asm/barrier.h index edd9e633a84b..744d70e1d202 100644 --- a/arch/arm/include/asm/barrier.h +++ b/arch/arm/include/asm/barrier.h @@ -108,5 +108,24 @@ do { \ #define smp_mb__before_atomic() smp_mb() #define smp_mb__after_atomic() smp_mb() +#ifdef CONFIG_CPU_SPECTRE +static inline unsigned long array_index_mask_nospec(unsigned long idx, + unsigned long sz) +{ + unsigned long mask; + + asm volatile( + "cmp %1, %2\n" + " sbc %0, %1, %1\n" + CSDB + : "=r" (mask) + : "r" (idx), "Ir" (sz) + : "cc"); + + return mask; +} +#define array_index_mask_nospec array_index_mask_nospec +#endif + #endif /* !__ASSEMBLY__ */ #endif /* __ASM_BARRIER_H */ From patchwork Thu Aug 1 08:16:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 170330 Delivered-To: patch@linaro.org Received: by 2002:a92:512:0:0:0:0:0 with SMTP id q18csp5086046ile; Thu, 1 Aug 2019 01:20:32 -0700 (PDT) X-Google-Smtp-Source: APXvYqxz01ELiO8vcTsBpUzhhF7FWd4ja/Fo9owL4sp18QnKscILtZjNhdLpuO1OY/T4qbLxrZj1 X-Received: by 2002:a63:c44c:: with SMTP id m12mr78608615pgg.396.1564647632372; Thu, 01 Aug 2019 01:20:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564647632; cv=none; d=google.com; s=arc-20160816; b=Ea77n77tDkEp4XlFaV4VBBcVV8td+4wAdIku1bf4Z8KvVXZpMTW12dIGvi4IRhWyfH Wx+FicMbu+kr27FV1Dyr97P2pl4k+0Uu4vnzvEuuY8Aezck9qftVqPTFTYniDxs71y0Y T6tSWQlgL7BzvtV1mgOiuT3k69Sf04ZnVPpbc0XSB4A29CBnvGlOHwjI/f9gb5p8Vfr/ FYwCRWIHylUHBDC5zZHVBawNijPqYyOI6xG+fAW1s1gHh3Xb/qn6LP7gecjEAG9i4r+l CCIYblQI8FoCktXxkiYPUb0vwbMI1LF3gvzj9+JtZMY+69fOGqajmxqz1KDx1NGxaDBB HEDw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=kLSGaDTr3EMSfGVKyIoCGH7cLmpO8I4it2r2qsg5/0U=; b=gyfYp6gMxXD0JNCWQbuNcpL7SLgA5W8+qp6E/SDcGbHRmYsAapA9HWu9WW+0WcXBWO az5CJnEVtROgpMgvzNKX0x5Yf1JU9xLI+eYFl0ysfXEfEbapDLeatPvOPWrZgb3ipyUQ WMLGB0Ub9xmy0GT0rgR3cIVMNRAeP3BxSpGEwTdE1p24Zum6FCd+LLWNX04150aZxJuI 3BqgCReuBypR/1cm247cUBTF3/xSnUmxgSkCJzF3f7X8gUwKXkEYk9eUqkck/P0pEAIa j4N0qyKaeyLgbAAd5sgyQL6NVvTA6MHW+7KW3XpxH8o+FZ0WoNlu52bAYY5cqheFS8sG O+BQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=S4Wz6Hsr; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Prevent speculation at the syscall table decoding by clamping the index used to zero on invalid system call numbers, and using the csdb speculative barrier. Signed-off-by: Russell King Acked-by: Mark Rutland Boot-tested-by: Tony Lindgren Reviewed-by: Tony Lindgren Signed-off-by: David A. Long Signed-off-by: Viresh Kumar --- arch/arm/kernel/entry-common.S | 18 +++++++----------- arch/arm/kernel/entry-header.S | 25 +++++++++++++++++++++++++ 2 files changed, 32 insertions(+), 11 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S index 30a7228eaceb..e969b18d9ff9 100644 --- a/arch/arm/kernel/entry-common.S +++ b/arch/arm/kernel/entry-common.S @@ -223,9 +223,7 @@ ENTRY(vector_swi) tst r10, #_TIF_SYSCALL_WORK @ are we tracing syscalls? bne __sys_trace - cmp scno, #NR_syscalls @ check upper syscall limit - badr lr, ret_fast_syscall @ return address - ldrcc pc, [tbl, scno, lsl #2] @ call sys_* routine + invoke_syscall tbl, scno, r10, ret_fast_syscall add r1, sp, #S_OFF 2: cmp scno, #(__ARM_NR_BASE - __NR_SYSCALL_BASE) @@ -258,14 +256,8 @@ ENDPROC(vector_swi) mov r1, scno add r0, sp, #S_OFF bl syscall_trace_enter - - badr lr, __sys_trace_return @ return address - mov scno, r0 @ syscall number (possibly new) - add r1, sp, #S_R0 + S_OFF @ pointer to regs - cmp scno, #NR_syscalls @ check upper syscall limit - ldmccia r1, {r0 - r6} @ have to reload r0 - r6 - stmccia sp, {r4, r5} @ and update the stack args - ldrcc pc, [tbl, scno, lsl #2] @ call sys_* routine + mov scno, r0 + invoke_syscall tbl, scno, r10, __sys_trace_return, reload=1 cmp scno, #-1 @ skip the syscall? bne 2b add sp, sp, #S_OFF @ restore stack @@ -317,6 +309,10 @@ ENTRY(sys_call_table) bic scno, r0, #__NR_OABI_SYSCALL_BASE cmp scno, #__NR_syscall - __NR_SYSCALL_BASE cmpne scno, #NR_syscalls @ check range +#ifdef CONFIG_CPU_SPECTRE + movhs scno, #0 + csdb +#endif stmloia sp, {r5, r6} @ shuffle args movlo r0, r1 movlo r1, r2 diff --git a/arch/arm/kernel/entry-header.S b/arch/arm/kernel/entry-header.S index 6d243e830516..86dfee487e24 100644 --- a/arch/arm/kernel/entry-header.S +++ b/arch/arm/kernel/entry-header.S @@ -373,6 +373,31 @@ #endif .endm + .macro invoke_syscall, table, nr, tmp, ret, reload=0 +#ifdef CONFIG_CPU_SPECTRE + mov \tmp, \nr + cmp \tmp, #NR_syscalls @ check upper syscall limit + movcs \tmp, #0 + csdb + badr lr, \ret @ return address + .if \reload + add r1, sp, #S_R0 + S_OFF @ pointer to regs + ldmccia r1, {r0 - r6} @ reload r0-r6 + stmccia sp, {r4, r5} @ update stack arguments + .endif + ldrcc pc, [\table, \tmp, lsl #2] @ call sys_* routine +#else + cmp \nr, #NR_syscalls @ check upper syscall limit + badr lr, \ret @ return address + .if \reload + add r1, sp, #S_R0 + S_OFF @ pointer to regs + ldmccia r1, {r0 - r6} @ reload r0-r6 + stmccia sp, {r4, r5} @ update stack arguments + .endif + ldrcc pc, [\table, \nr, lsl #2] @ call sys_* routine +#endif + .endm + /* * These are the registers used in the syscall handler, and allow us to * have in theory up to 7 arguments to a function - r0 to r6. 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However, with software PAN and the recent Spectre variant 1, the efficiency is reduced as these are no longer fast accessors. In the case of software PAN, it has to switch the domain register around each access, and with Spectre variant 1, it would have to repeat the access_ok() check for each access. It becomes much more efficient to use __copy_from_user() instead, so let's use this for the ARM integer registers. Acked-by: Mark Rutland Signed-off-by: Russell King Signed-off-by: David A. Long Signed-off-by: Viresh Kumar --- arch/arm/kernel/signal.c | 38 +++++++++++++++++++++----------------- 1 file changed, 21 insertions(+), 17 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c index 7b8f2141427b..a592bc0287f8 100644 --- a/arch/arm/kernel/signal.c +++ b/arch/arm/kernel/signal.c @@ -141,6 +141,7 @@ struct rt_sigframe { static int restore_sigframe(struct pt_regs *regs, struct sigframe __user *sf) { + struct sigcontext context; struct aux_sigframe __user *aux; sigset_t set; int err; @@ -149,23 +150,26 @@ static int restore_sigframe(struct pt_regs *regs, struct sigframe __user *sf) if (err == 0) set_current_blocked(&set); - __get_user_error(regs->ARM_r0, &sf->uc.uc_mcontext.arm_r0, err); - __get_user_error(regs->ARM_r1, &sf->uc.uc_mcontext.arm_r1, err); - __get_user_error(regs->ARM_r2, &sf->uc.uc_mcontext.arm_r2, err); - __get_user_error(regs->ARM_r3, &sf->uc.uc_mcontext.arm_r3, err); - __get_user_error(regs->ARM_r4, &sf->uc.uc_mcontext.arm_r4, err); - __get_user_error(regs->ARM_r5, &sf->uc.uc_mcontext.arm_r5, err); - __get_user_error(regs->ARM_r6, &sf->uc.uc_mcontext.arm_r6, err); - __get_user_error(regs->ARM_r7, &sf->uc.uc_mcontext.arm_r7, err); - __get_user_error(regs->ARM_r8, &sf->uc.uc_mcontext.arm_r8, err); - __get_user_error(regs->ARM_r9, &sf->uc.uc_mcontext.arm_r9, err); - __get_user_error(regs->ARM_r10, &sf->uc.uc_mcontext.arm_r10, err); - __get_user_error(regs->ARM_fp, &sf->uc.uc_mcontext.arm_fp, err); - __get_user_error(regs->ARM_ip, &sf->uc.uc_mcontext.arm_ip, err); - __get_user_error(regs->ARM_sp, &sf->uc.uc_mcontext.arm_sp, err); - __get_user_error(regs->ARM_lr, &sf->uc.uc_mcontext.arm_lr, err); - __get_user_error(regs->ARM_pc, &sf->uc.uc_mcontext.arm_pc, err); - __get_user_error(regs->ARM_cpsr, &sf->uc.uc_mcontext.arm_cpsr, err); + err |= __copy_from_user(&context, &sf->uc.uc_mcontext, sizeof(context)); + if (err == 0) { + regs->ARM_r0 = context.arm_r0; + regs->ARM_r1 = context.arm_r1; + regs->ARM_r2 = context.arm_r2; + regs->ARM_r3 = context.arm_r3; + regs->ARM_r4 = context.arm_r4; + regs->ARM_r5 = context.arm_r5; + regs->ARM_r6 = context.arm_r6; + regs->ARM_r7 = context.arm_r7; + regs->ARM_r8 = context.arm_r8; + regs->ARM_r9 = context.arm_r9; + regs->ARM_r10 = context.arm_r10; + regs->ARM_fp = context.arm_fp; + regs->ARM_ip = context.arm_ip; + regs->ARM_sp = context.arm_sp; + regs->ARM_lr = context.arm_lr; + regs->ARM_pc = context.arm_pc; + regs->ARM_cpsr = context.arm_cpsr; + } err |= !valid_user_regs(regs); From patchwork Thu Aug 1 08:16:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 170357 Delivered-To: patch@linaro.org Received: by 2002:a92:512:0:0:0:0:0 with SMTP id q18csp5088473ile; Thu, 1 Aug 2019 01:22:48 -0700 (PDT) X-Google-Smtp-Source: APXvYqyIKi5T3P7NYfOIiF6vssxCn/q73KadiWLdM5DPKxymQWdIoHFyNX5tT9hjey5QjT2sHrCa X-Received: by 2002:a62:7a8a:: with SMTP id v132mr51781463pfc.103.1564647637721; Thu, 01 Aug 2019 01:20:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564647637; cv=none; d=google.com; s=arc-20160816; b=XKuAWXDeYwBFwgxemK+lyJZNLqbYGG6EpgbgGDVgp9pZ5gyJB7fgR2tVoHTzLFbH+M OR4+biwqg7CoJfK6IXGrHxoavO3GBqVktgEwhPmVatiJbpkfc5pyUPa/wxM8Nn+1SZ9T HCd3d5ElQklogKWvKGxNnFxqM6MJHmnfm/LCodKSsuH1HscL4+ot+thr/0CLb6PFzibj r+2G5Jx5zFOzXFobUcfVynaGmoYHd09DGKoy45Kx73292uGawUN8yVfbmNusx5hNbxqJ 1c3hhrY6xdhLm6Q4Hh8bnnLVHO7z90nxMZYJfvj0TAezJ+FpaRyRIqT4P1FWBlNPPIZl ooJA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=uRyk3zcBxn+kArv7clzkKBJGfRbp0pIX9juxiKGvE2U=; b=lcn3UVQLujbtC1Memf9eiSlIfHwMbRmBLge2oAp43xrHi2B0rLpXw3V3LObRSTaNaq 4KgE2zb6kf0hc2a+gRM6T9LuTOQed7Zf4DFGhSPG355hKNr5Kz4KrCnoH0vLi4bzmFS2 QA74IvgGiPokPOq28/wQHYnr5WnNsbpdP1hWrAwIN0Nw+o1pEIDT+FDbk2S0Xv7Phabd 4QzA7gnr5IyVzHZQC1jY1xA5M2u8aOvBufyNbM0FNVLnruRovGyHHGW2IM6Sf/AP7wdJ nJEc0XuEiKxcFCXcz8VvqPUPD+4W6jofiz8bzJtySLq25fOZf1W+34hreNKl3aIqGSit iylg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="b2McCC/W"; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f10si37407577pfq.194.2019.08.01.01.20.37; Thu, 01 Aug 2019 01:20:37 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="b2McCC/W"; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730473AbfHAIUh (ORCPT + 14 others); Thu, 1 Aug 2019 04:20:37 -0400 Received: from mail-pg1-f193.google.com ([209.85.215.193]:44304 "EHLO mail-pg1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731089AbfHAIUg (ORCPT ); Thu, 1 Aug 2019 04:20:36 -0400 Received: by mail-pg1-f193.google.com with SMTP id i18so33734644pgl.11 for ; Thu, 01 Aug 2019 01:20:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=uRyk3zcBxn+kArv7clzkKBJGfRbp0pIX9juxiKGvE2U=; b=b2McCC/WCcGBPzkhtxUUkoJMeMcdJguyRODCBJ0WTu/VoS9DEEque4sOadkrF9Nbft lPCrVhWn8e8vlLv2WWnVQZJRuv3ttph1yCzYhXrPNBvES/oMHX2J1WpCdT1oG9MQMP+D Jt/0F9x460JOvtbf5koGqj6pES0Ec3SdobEldPLHFvYJvGZET5aHonfh2gMfP5ZT/VLg EJFEuXzxVGFfmlErLRbS0l/WPAPQuTGoCIH/i0Z5vanbDpw4ZjXJQREgsoYvtVVpVzbM eVc3rMqWzX0hfKrrk3QsXMlXzD6NdG5EZbR19l0oj43J9RBgyjDLk2+iB6/q7m5FMEvc 9xtA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uRyk3zcBxn+kArv7clzkKBJGfRbp0pIX9juxiKGvE2U=; b=kLqfenlKphL3DUeNjCNhHJpGoIWUWeHu7Y9AP55oX9DtMlBlu7o8APazRjQTUFnhqT M3mVA9w57Lz+ATvSnna+YvInIdB26/5V6pHjqr/6LHxjVUI1qL5vGTymh0qsve5wJlYC vDPUcgZGPj07Q3FFRdY4yuwA+71QDJe2vokhSBHq5zwYGnHE/eoI9MGk6fx1PW7MKfWX NHbbjk98MyQLcEVhjSd/QWtc3me2j2Ofy5VmkQnztAibwlM0nT96SQVJ9cxuiDr0ZUFi sCM8/AD1C2x5ONqNnxB88+R47eUOzKX15cNTWtTPRGLY9IBuff8Vti2VCSUOfdD8zwqL 6O4g== X-Gm-Message-State: APjAAAXLQE0BSYlAebtzTn0FmV66OLAehKGXuww5XdXw/fy3vmynXzNx ZTWg0C6Zb3Q5q7rgV2JDqoR7uFL9Y+8= X-Received: by 2002:aa7:9dcd:: with SMTP id g13mr53047380pfq.204.1564647635649; Thu, 01 Aug 2019 01:20:35 -0700 (PDT) Received: from localhost ([122.172.28.117]) by smtp.gmail.com with ESMTPSA id n17sm74761757pfq.182.2019.08.01.01.20.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 01 Aug 2019 01:20:35 -0700 (PDT) From: Viresh Kumar To: stable@vger.kernel.org Cc: Viresh Kumar , Julien Thierry , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Marc Zyngier , Mark Rutland , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com, guohanjun@huawei.com Subject: [PATCH ARM32 v4.4 V2 23/47] ARM: vfp: use __copy_from_user() when restoring VFP state Date: Thu, 1 Aug 2019 13:46:07 +0530 Message-Id: <8476fc23988444fda761ae9d99563cea0b21c191.1564646727.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Russell King Commit 42019fc50dfadb219f9e6ddf4c354f3837057d80 upstream. __get_user_error() is used as a fast accessor to make copying structure members in the signal handling path as efficient as possible. However, with software PAN and the recent Spectre variant 1, the efficiency is reduced as these are no longer fast accessors. In the case of software PAN, it has to switch the domain register around each access, and with Spectre variant 1, it would have to repeat the access_ok() check for each access. Use __copy_from_user() rather than __get_user_err() for individual members when restoring VFP state. Acked-by: Mark Rutland Signed-off-by: Russell King Signed-off-by: David A. Long Signed-off-by: Viresh Kumar --- arch/arm/include/asm/thread_info.h | 4 ++-- arch/arm/kernel/signal.c | 18 ++++++++---------- arch/arm/vfp/vfpmodule.c | 17 +++++++---------- 3 files changed, 17 insertions(+), 22 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h index 776757d1604a..57d2ad9c75ca 100644 --- a/arch/arm/include/asm/thread_info.h +++ b/arch/arm/include/asm/thread_info.h @@ -126,8 +126,8 @@ struct user_vfp_exc; extern int vfp_preserve_user_clear_hwstate(struct user_vfp __user *, struct user_vfp_exc __user *); -extern int vfp_restore_user_hwstate(struct user_vfp __user *, - struct user_vfp_exc __user *); +extern int vfp_restore_user_hwstate(struct user_vfp *, + struct user_vfp_exc *); #endif /* diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c index a592bc0287f8..76f85c38f2b8 100644 --- a/arch/arm/kernel/signal.c +++ b/arch/arm/kernel/signal.c @@ -107,21 +107,19 @@ static int preserve_vfp_context(struct vfp_sigframe __user *frame) return vfp_preserve_user_clear_hwstate(&frame->ufp, &frame->ufp_exc); } -static int restore_vfp_context(struct vfp_sigframe __user *frame) +static int restore_vfp_context(struct vfp_sigframe __user *auxp) { - unsigned long magic; - unsigned long size; - int err = 0; - - __get_user_error(magic, &frame->magic, err); - __get_user_error(size, &frame->size, err); + struct vfp_sigframe frame; + int err; + err = __copy_from_user(&frame, (char __user *) auxp, sizeof(frame)); if (err) - return -EFAULT; - if (magic != VFP_MAGIC || size != VFP_STORAGE_SIZE) + return err; + + if (frame.magic != VFP_MAGIC || frame.size != VFP_STORAGE_SIZE) return -EINVAL; - return vfp_restore_user_hwstate(&frame->ufp, &frame->ufp_exc); + return vfp_restore_user_hwstate(&frame.ufp, &frame.ufp_exc); } #endif diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c index 2a61e4b04600..7aa6366b2a8d 100644 --- a/arch/arm/vfp/vfpmodule.c +++ b/arch/arm/vfp/vfpmodule.c @@ -601,13 +601,11 @@ int vfp_preserve_user_clear_hwstate(struct user_vfp __user *ufp, } /* Sanitise and restore the current VFP state from the provided structures. */ -int vfp_restore_user_hwstate(struct user_vfp __user *ufp, - struct user_vfp_exc __user *ufp_exc) +int vfp_restore_user_hwstate(struct user_vfp *ufp, struct user_vfp_exc *ufp_exc) { struct thread_info *thread = current_thread_info(); struct vfp_hard_struct *hwstate = &thread->vfpstate.hard; unsigned long fpexc; - int err = 0; /* Disable VFP to avoid corrupting the new thread state. */ vfp_flush_hwstate(thread); @@ -616,17 +614,16 @@ int vfp_restore_user_hwstate(struct user_vfp __user *ufp, * Copy the floating point registers. There can be unused * registers see asm/hwcap.h for details. */ - err |= __copy_from_user(&hwstate->fpregs, &ufp->fpregs, - sizeof(hwstate->fpregs)); + memcpy(&hwstate->fpregs, &ufp->fpregs, sizeof(hwstate->fpregs)); /* * Copy the status and control register. */ - __get_user_error(hwstate->fpscr, &ufp->fpscr, err); + hwstate->fpscr = ufp->fpscr; /* * Sanitise and restore the exception registers. */ - __get_user_error(fpexc, &ufp_exc->fpexc, err); + fpexc = ufp_exc->fpexc; /* Ensure the VFP is enabled. */ fpexc |= FPEXC_EN; @@ -635,10 +632,10 @@ int vfp_restore_user_hwstate(struct user_vfp __user *ufp, fpexc &= ~(FPEXC_EX | FPEXC_FP2V); hwstate->fpexc = fpexc; - __get_user_error(hwstate->fpinst, &ufp_exc->fpinst, err); - __get_user_error(hwstate->fpinst2, &ufp_exc->fpinst2, err); + hwstate->fpinst = ufp_exc->fpinst; + hwstate->fpinst2 = ufp_exc->fpinst2; - return err ? -EFAULT : 0; + return 0; } /* From patchwork Thu Aug 1 08:16:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 170332 Delivered-To: patch@linaro.org Received: by 2002:a92:512:0:0:0:0:0 with SMTP id q18csp5086198ile; Thu, 1 Aug 2019 01:20:40 -0700 (PDT) X-Google-Smtp-Source: APXvYqxxDHGfyYFu23a9XF+tWAN72Jj7l2itgEAzsmdIp6FwaZSLNIjrEfDxmBWT4GabZ/R8LbvJ X-Received: by 2002:a65:518a:: with SMTP id h10mr116070225pgq.117.1564647640254; Thu, 01 Aug 2019 01:20:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564647640; cv=none; d=google.com; s=arc-20160816; b=FOr1zHKQqLcOzTgQagr5ozXNMti2YqtwHBso+pp0Cg4PkR8teWTXrrmjwrqp9XiyQA bTXCAReM75RrWm8IGMyW5RDYmUDSnNmD3Uq/7oLHTFRg1mbZt6Uwj8MwNVqibzGvuWHQ mdMeZlV/zaEOk8b+LHoBHRtknW3HdohCXKixx38tjBoJZevD7qGJZp7ycvbgDo8U5NpM +pqedH6k0NwFV+IyEhG9gOATG8UDHJ4JtcNDjbhlG8Y1qEEEIl+xf9xh7tPR+JBPfbzU Jy4OPBX+UuIOkPYKWTxkJWCUEf6BKAvBHek5vpBh3qWgorddKaakOmBmS+6A2UmD4LQ5 s03w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=cd+CJgxpyw48wYexEQLN0Ryuy346dGX9j+MO3rZWGCA=; b=EO3aTz7x+VB66U/B+b9v9Wu7wdB3y5bq4iXdiNG1vT+BOmkY8nbVNC93yxJa93F0fx N97IlBsFJJ+Y8+PIA7oSBOC1B8DQoUIF4JF3QQ2/IaCiyhRoxrJgCxcZtpkFuC46grBY UVUp4tfwFoSl5qse+i5E34lrdUzvFPOv59nJNOvDgrMMe9UFS3Yb3iE1Ljt7LwcAH2PS jNwdp+qXCdip4oopadQCOYtKLD4K9WaMqCUTiwsrLAJcAyqwNyEk25r1MfWbBMufKZ5k sRPFVe1lnRbi9QbgTfhA+GS2OKFM78ze9HGEaupGKmlfE7Gb0xkZRM3/NGEvedKBeBqr Ri6A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Z2hoeeYK; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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However, with software PAN and the recent Spectre variant 1, the efficiency is reduced as these are no longer fast accessors. In the case of software PAN, it has to switch the domain register around each access, and with Spectre variant 1, it would have to repeat the access_ok() check for each access. Rather than using __get_user_error() to copy each semops element member, copy each semops element in full using __copy_from_user(). Acked-by: Mark Rutland Signed-off-by: Russell King Signed-off-by: David A. Long Signed-off-by: Viresh Kumar --- arch/arm/kernel/sys_oabi-compat.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm/kernel/sys_oabi-compat.c b/arch/arm/kernel/sys_oabi-compat.c index 5f221acd21ae..640748e27035 100644 --- a/arch/arm/kernel/sys_oabi-compat.c +++ b/arch/arm/kernel/sys_oabi-compat.c @@ -328,9 +328,11 @@ asmlinkage long sys_oabi_semtimedop(int semid, return -ENOMEM; err = 0; for (i = 0; i < nsops; i++) { - __get_user_error(sops[i].sem_num, &tsops->sem_num, err); - __get_user_error(sops[i].sem_op, &tsops->sem_op, err); - __get_user_error(sops[i].sem_flg, &tsops->sem_flg, err); + struct oabi_sembuf osb; + err |= __copy_from_user(&osb, tsops, sizeof(osb)); + sops[i].sem_num = osb.sem_num; + sops[i].sem_op = osb.sem_op; + sops[i].sem_flg = osb.sem_flg; tsops++; } if (timeout) { From patchwork Thu Aug 1 08:16:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 170354 Delivered-To: patch@linaro.org Received: by 2002:a92:512:0:0:0:0:0 with SMTP id q18csp5088008ile; Thu, 1 Aug 2019 01:22:21 -0700 (PDT) X-Google-Smtp-Source: APXvYqxcEkUXLdtGh1pgx2uFCZNeviEkUTvYPZSnmMPftZrrAZBbL0NKl6a2DiJ33w9jh87Q6kOM X-Received: by 2002:a17:902:2808:: with SMTP id e8mr119724061plb.317.1564647644063; Thu, 01 Aug 2019 01:20:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564647644; cv=none; d=google.com; s=arc-20160816; b=x4jgzngBO4vfnSw/BkS5mRcBHCup41d3LzYxwFctfDoHiESQDJ8TLPGtFy/l458MDU WFZTlHax+ujPJyC6fmPpjhSGqJ4K9Ms5dipOwThE+dBVxlp/gf2JnsBi2p5fwuX/0oLL izug2Hkee5vWmzSB+q4pgmHh+9xJEThuKiAD23qt/ZWzgOwMX+3akzIAO6q+D3GGhpaY 3v65O+LRpHXTu/xfp7W3cXqgTowAN3rGp7HhRAkiinL55siQaKfq3azRTyBBQESZO5Pk fpCNkStbuJsDFY9gLiijoDSiA+6seS5JqiCvvoACW4TQWEAJL9+IOKa1CXsVRaq2qn8D ugMw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=fgFpO2t01PxhbBlSjah6QrAfkGefLJP0TJCP7weC9qM=; b=mX7qeQ+bghF11+CQanh8O+0gLR9k7jpAkjGRp6jN647+LIkeAJdpuPtOYI3P9JskPM Q5CCr2tGKTBh1XD/YQ4cUTdUQfN5GB7sqz+g5wJaP2/S+aWUVaSIgbdMezBgDrtrhdus zIdM8VgXGXSKAdiRy4TQvrRawlawqyXxIbrihoSYiKi3LfdHZn1wnG8bv8Rf20U5mBIm LyNjEam90I0eVePgDbaiDkDwIRq7vCyhDdMMXYfBv0nCT3tPRxA+CQVS0zr3/qrhvhvr fXq31XuLFjIBSJsX7zqam+fAsY0VwhIp/9wd/9tdwlgMYEfDEc3njV8ggeYAJNsI3ex3 4bWw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=byvD1gfB; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Borrow the x86 implementation of __inttype() to use in get_user() to select an integer type suitable to temporarily hold the result value. This is necessary to avoid propagating the volatile nature of the result argument, which can cause the following warning: lib/iov_iter.c:413:5: warning: optimization may eliminate reads and/or writes to register variables [-Wvolatile-register-var] Acked-by: Mark Rutland Signed-off-by: Russell King Signed-off-by: David A. Long Signed-off-by: Viresh Kumar --- arch/arm/include/asm/uaccess.h | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm/include/asm/uaccess.h b/arch/arm/include/asm/uaccess.h index cd8b589111ba..968b50063431 100644 --- a/arch/arm/include/asm/uaccess.h +++ b/arch/arm/include/asm/uaccess.h @@ -122,6 +122,13 @@ static inline void set_fs(mm_segment_t fs) : "cc"); \ flag; }) +/* + * This is a type: either unsigned long, if the argument fits into + * that type, or otherwise unsigned long long. + */ +#define __inttype(x) \ + __typeof__(__builtin_choose_expr(sizeof(x) > sizeof(0UL), 0ULL, 0UL)) + /* * Single-value transfer routines. They automatically use the right * size if we just have the right pointer type. Note that the functions @@ -191,7 +198,7 @@ extern int __get_user_64t_4(void *); ({ \ unsigned long __limit = current_thread_info()->addr_limit - 1; \ register const typeof(*(p)) __user *__p asm("r0") = (p);\ - register typeof(x) __r2 asm("r2"); \ + register __inttype(x) __r2 asm("r2"); \ register unsigned long __l asm("r1") = __limit; \ register int __e asm("r0"); \ unsigned int __ua_flags = uaccess_save_and_enable(); \ From patchwork Thu Aug 1 08:16:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 170333 Delivered-To: patch@linaro.org Received: by 2002:a92:512:0:0:0:0:0 with SMTP id q18csp5086282ile; Thu, 1 Aug 2019 01:20:46 -0700 (PDT) X-Google-Smtp-Source: APXvYqz8Boi/cW6oaP+10P11ULrdOukc26l0Z2jqqyZbKsBOCPm0pyLKiU9itsy2cPlmZDzTb8/t X-Received: by 2002:a63:381d:: with SMTP id f29mr120513935pga.101.1564647645590; Thu, 01 Aug 2019 01:20:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564647645; cv=none; d=google.com; s=arc-20160816; b=EODS98OCnS9d8y4aIoB88K25zC8+VSj86PKuMY3MZ2PMrlyDHcj3s1x08zCk/B0R5d 0FHSdgbhLJ3OUJrAxr8Rntt0aHqKZ+XR+UJMuNVdoTb7w1FjMnWpeoP8DdVQw4UO75IV ERM38W+1KoNztd10ZXh/zHaIhdPlO0u7Kb4gHxJnlwI1j+ygyOjd8PoymIco6jq9CkLV p8aV7+iwJa/RLMYgyhKUvXoNDbxnfxkqCVqoTY8uZ5fE0cuEREV2kzOwMxCD5WbX/tIF YPRo3JbsVgnO6DIAcsO6S5n4fesNtaOsko6NT9kkirKqaij1c8ZJmxgZ1DeTXY0y0eau oaDw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=38pdn6yMPIMVV02QHWSD6x84Nqpn4d6LkQlpQyJb38o=; b=pPu2sMDekswnhIJj6ziD84u6jGW5VPIauAzt1yG9l0K1K41tVaZdQBqHCu0mXVxs4F f8EPJ4vc7Q5iPd7eMf6mTPl6j/xVq4rgQG82YMRZVT4pZYpjRU3+Bv1MIjGdWEHNRYBu VfPd6rt5ITPuqy5DoWeymVoLxap9ZJLjdBbfURcbJZCZaK9ESN0DZhHpPvuZVC0E1Z52 dMdlYeJ0g/Fy76PSDPP79ZzMv0S6PhiQIBfhccMPC2bCpx0zG2wCZInXoCsGKFdeLPHm 238RRt+Mxu3/jfFEioic33GWQ72pfoEqPG+T/JWpQ//sPBM3jMSaTZmypMxX8e5qskl+ I0tg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hpj8rFpq; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Fixing __get_user() for spectre variant 1 is not sane: we would have to add address space bounds checking in order to validate that the location should be accessed, and then zero the address if found to be invalid. Since __get_user() is supposed to avoid the bounds check, and this is exactly what get_user() does, there's no point having two different implementations that are doing the same thing. So, when the Spectre workarounds are required, make __get_user() an alias of get_user(). Acked-by: Mark Rutland Signed-off-by: Russell King Signed-off-by: David A. Long Signed-off-by: Viresh Kumar --- arch/arm/include/asm/uaccess.h | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm/include/asm/uaccess.h b/arch/arm/include/asm/uaccess.h index 968b50063431..ecd159b45f12 100644 --- a/arch/arm/include/asm/uaccess.h +++ b/arch/arm/include/asm/uaccess.h @@ -314,6 +314,15 @@ static inline void set_fs(mm_segment_t fs) #define user_addr_max() \ (segment_eq(get_fs(), KERNEL_DS) ? ~0UL : get_fs()) +#ifdef CONFIG_CPU_SPECTRE +/* + * When mitigating Spectre variant 1, it is not worth fixing the non- + * verifying accessors, because we need to add verification of the + * address space there. Force these to use the standard get_user() + * version instead. + */ +#define __get_user(x, ptr) get_user(x, ptr) +#else /* * The "__xxx" versions of the user access functions do not verify the * address space - it must have been done previously with a separate @@ -330,12 +339,6 @@ static inline void set_fs(mm_segment_t fs) __gu_err; \ }) -#define __get_user_error(x, ptr, err) \ -({ \ - __get_user_err((x), (ptr), err); \ - (void) 0; \ -}) - #define __get_user_err(x, ptr, err) \ do { \ unsigned long __gu_addr = (unsigned long)(ptr); \ @@ -395,6 +398,7 @@ do { \ #define __get_user_asm_word(x, addr, err) \ __get_user_asm(x, addr, err, ldr) +#endif #define __put_user(x, ptr) \ ({ \ From patchwork Thu Aug 1 08:16:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 170334 Delivered-To: patch@linaro.org Received: by 2002:a92:512:0:0:0:0:0 with SMTP id q18csp5086318ile; Thu, 1 Aug 2019 01:20:48 -0700 (PDT) X-Google-Smtp-Source: APXvYqyGY1DEKdszt4qhCseEze2dJumoO8wBQFMX4VToVApz8RZbzQy51wQ0w5gOciCfwGPboUKF X-Received: by 2002:a63:2026:: with SMTP id g38mr111765916pgg.172.1564647647891; Thu, 01 Aug 2019 01:20:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564647647; cv=none; d=google.com; s=arc-20160816; b=zxeJB3XiiJ439iY3k0Um7M6WBEhczBFcWWa/LEWg6BfI+RmRg4HQYUIfbUvOMs4mk8 OjCXatmKwtw7ZD4+mZQ0YBcY5n7bOnV1PQ0q5sbqN+CWtlCizUbCSuOQLjs/5plafAVr 2c8S/I7HlMFxtS0HSHaN8xEE1zcpYepeZO+wx/7yumimC/KPX/iRM3Rzgpbzt4TpCR7A QAA3SssUi/ATmfYucGbz4W5OfxMKSMYVlHp+hPWNCWb+GNmILOibbbNS+HU/BlvGIbpK /BdLRIrTAFiRHea1m2M1RCJv8JYAbyimlSZaS7ZCbWtuuZNUDmBEtCLDgxGpexUfS/Id Z1zg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=q3Hwoo9R0gf8T8wycN6BweSX3iAbrjmdi48iA1QA7vM=; b=aUusKpfsfuzv21TRDiAfM0FQmZ8EuyhU3IF5Qg/Uw4LR3V5P0KbRlrQRwwqiMzHMCr qIC7YWDmWTsD3ZTSmHE2CtjKBaO8P8BmgTcUCCuZmXl9o/d3NEo1i/sRsLSWIoDcLiep /E6asqisjEcJAVwSKp+v9oTXcD+in/cvxvVqvIQtGGLleRmVCDrYenhS+NEx6MwSeA+Y 0oGkWFz4Bz6LPQllX4XO/taNQKo832qVfNsqAr4RXvumUncSp04DOtVWYAXAhMV6ATJG kHaomsrTzjgDNTNVB+uadaF1EPeckQaM7HnkjhL/rXc9dObftIlXNDo5nczmkeZnX0tA yNrQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=v8tPuBm6; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Spectre variant 1 attacks are about this sequence of pseudo-code: index = load(user-manipulated pointer); access(base + index * stride); In order for the cache side-channel to work, the access() must me made to memory which userspace can detect whether cache lines have been loaded. On 32-bit ARM, this must be either user accessible memory, or a kernel mapping of that same user accessible memory. The problem occurs when the load() speculatively loads privileged data, and the subsequent access() is made to user accessible memory. Any load() which makes use of a user-maniplated pointer is a potential problem if the data it has loaded is used in a subsequent access. This also applies for the access() if the data loaded by that access is used by a subsequent access. Harden the get_user() accessors against Spectre attacks by forcing out of bounds addresses to a NULL pointer. This prevents get_user() being used as the load() step above. As a side effect, put_user() will also be affected even though it isn't implicated. Also harden copy_from_user() by redoing the bounds check within the arm_copy_from_user() code, and NULLing the pointer if out of bounds. Acked-by: Mark Rutland Signed-off-by: Russell King Signed-off-by: David A. Long Signed-off-by: Viresh Kumar --- arch/arm/include/asm/assembler.h | 4 ++++ arch/arm/lib/copy_from_user.S | 9 +++++++++ 2 files changed, 13 insertions(+) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h index 307901f88a1e..483481c6937e 100644 --- a/arch/arm/include/asm/assembler.h +++ b/arch/arm/include/asm/assembler.h @@ -454,6 +454,10 @@ THUMB( orr \reg , \reg , #PSR_T_BIT ) adds \tmp, \addr, #\size - 1 sbcccs \tmp, \tmp, \limit bcs \bad +#ifdef CONFIG_CPU_SPECTRE + movcs \addr, #0 + csdb +#endif #endif .endm diff --git a/arch/arm/lib/copy_from_user.S b/arch/arm/lib/copy_from_user.S index 1512bebfbf1b..d36329cefedc 100644 --- a/arch/arm/lib/copy_from_user.S +++ b/arch/arm/lib/copy_from_user.S @@ -90,6 +90,15 @@ .text ENTRY(arm_copy_from_user) +#ifdef CONFIG_CPU_SPECTRE + get_thread_info r3 + ldr r3, [r3, #TI_ADDR_LIMIT] + adds ip, r1, r2 @ ip=addr+size + sub r3, r3, #1 @ addr_limit - 1 + cmpcc ip, r3 @ if (addr+size > addr_limit - 1) + movcs r1, #0 @ addr = NULL + csdb +#endif #include "copy_template.S" From patchwork Thu Aug 1 08:16:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 170335 Delivered-To: patch@linaro.org Received: by 2002:a92:512:0:0:0:0:0 with SMTP id q18csp5086358ile; Thu, 1 Aug 2019 01:20:50 -0700 (PDT) X-Google-Smtp-Source: APXvYqwAuC5gW1joc/ewBq2F1eXSMfcUwX2HOlv6ez0a+PLKDGqfNI2awvmm+4qVYeEyJXJ5Kadq X-Received: by 2002:a63:f118:: with SMTP id f24mr120510710pgi.322.1564647650109; Thu, 01 Aug 2019 01:20:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564647650; cv=none; d=google.com; s=arc-20160816; b=fRPOBLg3DYeuLMgNNyNYYOGWxzy+Cw5NMmCW1aeX3PTceO88pyNx0OCBbOZhX/HkwI tjAz/ZvVOB5XKVq310BQwWOy+XOWeLEKAseX1whp2pXLK6fbvdXNYPCRXXnN+0SESh1h DupTheIgY6qF/DLHsvoGC9pCgDnFHFUvVNz2xOSTKtjQap6tbmQK9UGYkpn9kmurqH1v 5L7Ruq3NFKSzcN/cJVLo5BxJM2FUMBOIQwguTcql7zQaRsx+wi5Y5zidvu9x/TCPr2J5 Il9kc9X5FDbQgm6FWkivJMvYfke3sy7Z/4NHs5WzAOkmwB0GCWJoOyzn0UQlqkIFrI42 wQHQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=MgdKvQC/PG/qzasZyBmDzAkccfxFwFqJHdwmPruVads=; b=QyFr733lpROKvbGacdaQsZygL/2xkDjMlEOuf8kMlfLlQ6+k8MwjXcq+Z3WPuHGzVU 0XTIcHuhxLR1+dr4lPaXjTjhLKoJlQnCY9j7ifXXM4vCwMH7boE4zOD79CT6+8JGsIBO aPl6VfZQopybO/cSiZCPXD+Tp89FStSa5qGzQf2F6e0JUBtsa8wvkVDf0j1JZo219eOe zPenoDpcSGL3sXswUXXlHfgZV2J7oK5Ljvra6U4jWcgqW3rTtY4pa7T6E9nHi8QFetA2 e174E1zFXhY3SKvbk+pLZaN0i/GWClT/J0RCNUI0nqIPAL/KkXElSCRlPsBWMxYKEpYO m44A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="M/W0Na2Z"; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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When saving the ARM integer registers, use __copy_to_user() to copy them into user signal frame, rather than __put_user_error(). This has the benefit of disabling/enabling PAN once for the whole copy intead of once per write. Signed-off-by: Julien Thierry Signed-off-by: Russell King Signed-off-by: Viresh Kumar --- arch/arm/kernel/signal.c | 49 ++++++++++++++++++++++------------------ 1 file changed, 27 insertions(+), 22 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c index 76f85c38f2b8..98685e2523bf 100644 --- a/arch/arm/kernel/signal.c +++ b/arch/arm/kernel/signal.c @@ -255,30 +255,35 @@ static int setup_sigframe(struct sigframe __user *sf, struct pt_regs *regs, sigset_t *set) { struct aux_sigframe __user *aux; + struct sigcontext context; int err = 0; - __put_user_error(regs->ARM_r0, &sf->uc.uc_mcontext.arm_r0, err); - __put_user_error(regs->ARM_r1, &sf->uc.uc_mcontext.arm_r1, err); - __put_user_error(regs->ARM_r2, &sf->uc.uc_mcontext.arm_r2, err); - __put_user_error(regs->ARM_r3, &sf->uc.uc_mcontext.arm_r3, err); - __put_user_error(regs->ARM_r4, &sf->uc.uc_mcontext.arm_r4, err); - __put_user_error(regs->ARM_r5, &sf->uc.uc_mcontext.arm_r5, err); - __put_user_error(regs->ARM_r6, &sf->uc.uc_mcontext.arm_r6, err); - __put_user_error(regs->ARM_r7, &sf->uc.uc_mcontext.arm_r7, err); - __put_user_error(regs->ARM_r8, &sf->uc.uc_mcontext.arm_r8, err); - __put_user_error(regs->ARM_r9, &sf->uc.uc_mcontext.arm_r9, err); - __put_user_error(regs->ARM_r10, &sf->uc.uc_mcontext.arm_r10, err); - __put_user_error(regs->ARM_fp, &sf->uc.uc_mcontext.arm_fp, err); - __put_user_error(regs->ARM_ip, &sf->uc.uc_mcontext.arm_ip, err); - __put_user_error(regs->ARM_sp, &sf->uc.uc_mcontext.arm_sp, err); - __put_user_error(regs->ARM_lr, &sf->uc.uc_mcontext.arm_lr, err); - __put_user_error(regs->ARM_pc, &sf->uc.uc_mcontext.arm_pc, err); - __put_user_error(regs->ARM_cpsr, &sf->uc.uc_mcontext.arm_cpsr, err); - - __put_user_error(current->thread.trap_no, &sf->uc.uc_mcontext.trap_no, err); - __put_user_error(current->thread.error_code, &sf->uc.uc_mcontext.error_code, err); - __put_user_error(current->thread.address, &sf->uc.uc_mcontext.fault_address, err); - __put_user_error(set->sig[0], &sf->uc.uc_mcontext.oldmask, err); + context = (struct sigcontext) { + .arm_r0 = regs->ARM_r0, + .arm_r1 = regs->ARM_r1, + .arm_r2 = regs->ARM_r2, + .arm_r3 = regs->ARM_r3, + .arm_r4 = regs->ARM_r4, + .arm_r5 = regs->ARM_r5, + .arm_r6 = regs->ARM_r6, + .arm_r7 = regs->ARM_r7, + .arm_r8 = regs->ARM_r8, + .arm_r9 = regs->ARM_r9, + .arm_r10 = regs->ARM_r10, + .arm_fp = regs->ARM_fp, + .arm_ip = regs->ARM_ip, + .arm_sp = regs->ARM_sp, + .arm_lr = regs->ARM_lr, + .arm_pc = regs->ARM_pc, + .arm_cpsr = regs->ARM_cpsr, + + .trap_no = current->thread.trap_no, + .error_code = current->thread.error_code, + .fault_address = current->thread.address, + .oldmask = set->sig[0], + }; + + err |= __copy_to_user(&sf->uc.uc_mcontext, &context, sizeof(context)); err |= __copy_to_user(&sf->uc.uc_sigmask, set, sizeof(*set)); From patchwork Thu Aug 1 08:16:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 170336 Delivered-To: patch@linaro.org Received: by 2002:a92:512:0:0:0:0:0 with SMTP id q18csp5086412ile; Thu, 1 Aug 2019 01:20:53 -0700 (PDT) X-Google-Smtp-Source: APXvYqz3K7DnjnstVP5pEOgBsin9pr8Xx1tWl0luglRzsOV7bZnkw9za31iTmLy/15Mrs/o4suKE X-Received: by 2002:a65:4507:: with SMTP id n7mr10077610pgq.86.1564647653370; Thu, 01 Aug 2019 01:20:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564647653; cv=none; d=google.com; s=arc-20160816; b=ja1vKrHl6wQODui2Io/kIG3dF8TogQUbcU3kzdjHB7RHXgi31s5SAX9BsIc7aUdDF6 WxWHQXwrFy/TCTUeN3P1EcGTCc7IS+YuzSrHKUtoPRh5THEQkcDpSyabOk1hNB2d3n4Q PgCVlKj2KZEtNqNyCbEC4CYQMKqPZ5sm+Zsr6oM4hHy3lcGR1Ptc94DQgHle1Frmy8/a 9NMYa8FE3zinmbVys2/UnmFc1qUHmUMxzvCWk5sXJPdPgSYZWWwjNyKXpzVBASj52Y53 UenDVg3STfZZpN7k4kOpMqb1aUj3cbD2XK999cGCViZduYK4mYBdkyvayqB8VS4NWksW lEuQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Z+TjXjo63OoUiebA/nVcgaugef8flgCeXLGArxWolNY=; b=U4cfUHf8SNUWJIK6XTEm0J0pHXwzvWj5gn8C6C7tmD/qD1RVCqp6DoujGJVfoXBhpL 7KCiwT+H/SqJ4AguL4AWb24gso5BTPJM6CfJlAWYlN6PE/rN6eKlZtuyEqfCkt6CAHdj TEKy6OLOgpCKTtgGZ2o/M+STjdkdT2/eXJZhyU0i9PDx6AovIcSmZPlT3qRMcBZf9IhV lG0yJ6vnAxsppe1KQBAQ3BhhcaJx8zwiuIisN011nRoBS3zy+FItZGhMFTOBud+TT+UE ZufBHyohMman7o/AbT56iDlKdo8C8Sku/gMiRaBlkqrhgof3hC56aGVpyToCDtZ3T0k8 +WLQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=oDNzbpMH; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Use __copy_to_user() rather than __put_user_error() for individual members when saving VFP state. This has the benefit of disabling/enabling PAN once per copied struct intead of once per write. Signed-off-by: Julien Thierry Signed-off-by: Russell King Signed-off-by: Viresh Kumar --- arch/arm/include/asm/thread_info.h | 4 ++-- arch/arm/kernel/signal.c | 13 +++++++------ arch/arm/vfp/vfpmodule.c | 20 ++++++++------------ 3 files changed, 17 insertions(+), 20 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h index 57d2ad9c75ca..df8420672c7e 100644 --- a/arch/arm/include/asm/thread_info.h +++ b/arch/arm/include/asm/thread_info.h @@ -124,8 +124,8 @@ extern void vfp_flush_hwstate(struct thread_info *); struct user_vfp; struct user_vfp_exc; -extern int vfp_preserve_user_clear_hwstate(struct user_vfp __user *, - struct user_vfp_exc __user *); +extern int vfp_preserve_user_clear_hwstate(struct user_vfp *, + struct user_vfp_exc *); extern int vfp_restore_user_hwstate(struct user_vfp *, struct user_vfp_exc *); #endif diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c index 98685e2523bf..6f0bd90f6d93 100644 --- a/arch/arm/kernel/signal.c +++ b/arch/arm/kernel/signal.c @@ -94,17 +94,18 @@ static int restore_iwmmxt_context(struct iwmmxt_sigframe *frame) static int preserve_vfp_context(struct vfp_sigframe __user *frame) { - const unsigned long magic = VFP_MAGIC; - const unsigned long size = VFP_STORAGE_SIZE; + struct vfp_sigframe kframe; int err = 0; - __put_user_error(magic, &frame->magic, err); - __put_user_error(size, &frame->size, err); + memset(&kframe, 0, sizeof(kframe)); + kframe.magic = VFP_MAGIC; + kframe.size = VFP_STORAGE_SIZE; + err = vfp_preserve_user_clear_hwstate(&kframe.ufp, &kframe.ufp_exc); if (err) - return -EFAULT; + return err; - return vfp_preserve_user_clear_hwstate(&frame->ufp, &frame->ufp_exc); + return __copy_to_user(frame, &kframe, sizeof(kframe)); } static int restore_vfp_context(struct vfp_sigframe __user *auxp) diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c index 7aa6366b2a8d..f07567eedd82 100644 --- a/arch/arm/vfp/vfpmodule.c +++ b/arch/arm/vfp/vfpmodule.c @@ -558,12 +558,11 @@ void vfp_flush_hwstate(struct thread_info *thread) * Save the current VFP state into the provided structures and prepare * for entry into a new function (signal handler). */ -int vfp_preserve_user_clear_hwstate(struct user_vfp __user *ufp, - struct user_vfp_exc __user *ufp_exc) +int vfp_preserve_user_clear_hwstate(struct user_vfp *ufp, + struct user_vfp_exc *ufp_exc) { struct thread_info *thread = current_thread_info(); struct vfp_hard_struct *hwstate = &thread->vfpstate.hard; - int err = 0; /* Ensure that the saved hwstate is up-to-date. */ vfp_sync_hwstate(thread); @@ -572,22 +571,19 @@ int vfp_preserve_user_clear_hwstate(struct user_vfp __user *ufp, * Copy the floating point registers. There can be unused * registers see asm/hwcap.h for details. */ - err |= __copy_to_user(&ufp->fpregs, &hwstate->fpregs, - sizeof(hwstate->fpregs)); + memcpy(&ufp->fpregs, &hwstate->fpregs, sizeof(hwstate->fpregs)); + /* * Copy the status and control register. */ - __put_user_error(hwstate->fpscr, &ufp->fpscr, err); + ufp->fpscr = hwstate->fpscr; /* * Copy the exception registers. */ - __put_user_error(hwstate->fpexc, &ufp_exc->fpexc, err); - __put_user_error(hwstate->fpinst, &ufp_exc->fpinst, err); - __put_user_error(hwstate->fpinst2, &ufp_exc->fpinst2, err); - - if (err) - return -EFAULT; + ufp_exc->fpexc = hwstate->fpexc; + ufp_exc->fpinst = hwstate->fpinst; + ufp_exc->fpinst2 = ufp_exc->fpinst2; /* Ensure that VFP is disabled. */ vfp_flush_hwstate(thread); From patchwork Thu Aug 1 08:16:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 170359 Delivered-To: patch@linaro.org Received: by 2002:a92:512:0:0:0:0:0 with SMTP id q18csp5088555ile; Thu, 1 Aug 2019 01:22:53 -0700 (PDT) X-Google-Smtp-Source: APXvYqwuU7tfurhq2Mn/fxTS2caZQ6f1AgXTmJ+BYS86JdxbF/7scUkNtQTF0hhOguumQ23UfIdP X-Received: by 2002:a17:90a:2228:: with SMTP id c37mr7390606pje.9.1564647655107; Thu, 01 Aug 2019 01:20:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564647655; cv=none; d=google.com; s=arc-20160816; b=xf+bwISfzLwMta4TtIhtMA5wTQeg98hhoJovG31hKJK0oLyiHrkh5LcljdtWjyFyP0 rVWPZOUTaLDyjpok+kz8Oq9TrztqXc/bcMGnhj5jNCAtWu+kI62eV314dAx3qY1L7GEC RCIZKbs9topw73gJZjqNB7toVAeoHRsgUBZpX8cZENXbmp1iQDdwLg1wFGTXx3ccGUCp EzwQo/HvKBU1cqfA5fk1+uGoEPohZp0urfZ6OIebipDW0VjGt6S+ZatX+VgYjDFI/miO ApShhgreFvD8+D4auRUjyEtqQRINFDRz7/u1WjsdgfCTxMC6jtAVGgCSqBPiczBaJLAn yYnQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=PM+p9F/paBphnvI0O8YGjV0kMD9bw/jop01RC1tBzqU=; b=EhfMCspiNVkUJZR0krQkVILLuLshDrw32BsylAl3sLcvmjzOPxANbTXdMDXVnC+s5V ezj58aVPqtcjAXS1YOKrrfzR8JjBnvUnCMX4BYhnlK0XoQbjz9U6ncX9QnwPJQ8S81ZM rEZudp59zogPDGBQUr3IVT1wlZUkBfCC9ytaVrbKF8hECewFneQhTiS4tJeYW0iO5YpJ RrhjhENIbSRuh8Y6ZM5pWmKL2woSlzsKzaUaS3tcNqwtwiQIBEvYyDLXCHpKGZUaKm4k pt1TVNZxSN/G7RYUGdGq03hoKUM7vXeMotn4hf6vQ6JU/xd9d+TT0PgS6pLdfNAkgvMq hmEg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=o0bXhyKq; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Copy events to user using __copy_to_user() rather than copy members of individually with __put_user_error(). This has the benefit of disabling/enabling PAN once per event intead of once per event member. Signed-off-by: Julien Thierry Signed-off-by: Russell King Signed-off-by: Viresh Kumar --- arch/arm/kernel/sys_oabi-compat.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm/kernel/sys_oabi-compat.c b/arch/arm/kernel/sys_oabi-compat.c index 640748e27035..d844c5c9364b 100644 --- a/arch/arm/kernel/sys_oabi-compat.c +++ b/arch/arm/kernel/sys_oabi-compat.c @@ -276,6 +276,7 @@ asmlinkage long sys_oabi_epoll_wait(int epfd, int maxevents, int timeout) { struct epoll_event *kbuf; + struct oabi_epoll_event e; mm_segment_t fs; long ret, err, i; @@ -294,8 +295,11 @@ asmlinkage long sys_oabi_epoll_wait(int epfd, set_fs(fs); err = 0; for (i = 0; i < ret; i++) { - __put_user_error(kbuf[i].events, &events->events, err); - __put_user_error(kbuf[i].data, &events->data, err); + e.events = kbuf[i].events; + e.data = kbuf[i].data; + err = __copy_to_user(events, &e, sizeof(e)); + if (err) + break; events++; } kfree(kbuf); From patchwork Thu Aug 1 08:16:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 170337 Delivered-To: patch@linaro.org Received: by 2002:a92:512:0:0:0:0:0 with SMTP id q18csp5086450ile; Thu, 1 Aug 2019 01:20:57 -0700 (PDT) X-Google-Smtp-Source: APXvYqxIqI+dn9lXdY3ovuqa3BVRfyUAO8YgouDwb3n3jYPKtkOgAHrWdybk0cnOGHl+pO64KVfD X-Received: by 2002:a62:5c3:: with SMTP id 186mr5900507pff.144.1564647657312; Thu, 01 Aug 2019 01:20:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564647657; cv=none; d=google.com; s=arc-20160816; b=D8A522R8oimW+HfmvqUJDzEc1I4IS63oSvTWZOSYP9INMEq+fS2BigtnZf4l8wId1X lUraYzafODMJ87U9J82VKU6kKZMGdgOa0+WiphFyE7OskGposLRA7FG5xIZS6iOwoMCu PdtXNepv4KvwZirWsM2Lm4m0Uj/0S4TLB9/46Lj9ZPKHK3nBIfdwfAxLkl7bJo20WnpT BlZiFN333HDPPLzBlWxDz0mGsAnLfUv1tEt++tlTXV2YeQKBdySZqxjb0Md6RwN1Grty 6aIMhdRvrXCO93XdvXaHyBxpek26l4Ylfb1k4sO+LRSZVlwTrf0OHzEJ67JivX2MOlhB Ra2g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=+tEIHvT2/jri72b3g9sp066ia6oUWHcxPpBllqXMUPw=; b=0+x+mzKYClFmoZtV3XZqXBplPZPWOyyIrK/4Y8KHyx1VrLhcpTW3f/Ruv9NVFyfdyw BucmJ/V01qCHc48zH0M5i2zhbIubyEhXpBi6fiVlo95tqtNEQs4vchoCKuFyrE4Z6zBg hFFTaAQky5D2FrTpoHZpDrUuXQZ2zNYWdCUwtg6KRxYXCoTyBPkU+2YrkEqnFdRnVWLc kwcPFGJCc9repAMeGtGulkGnLtxhzJLVkcvJTqJQGOE27pnjgOI87hhEnGK8nFtjmxOQ zyKR1raMaMYPB1jb3AsLMTRF34eAb07gGFt9FqJ3xVrwgG8X7zStrvIkNcfOurARsneQ ehTg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zstarAAh; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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With Spectre-v1.1 mitigations, __put_user_error is pointless. In an attempt to remove it, replace its references in frame setups with __put_user. Signed-off-by: Julien Thierry Signed-off-by: Russell King Signed-off-by: Viresh Kumar --- arch/arm/kernel/signal.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c index 6f0bd90f6d93..4a4ab72d27ba 100644 --- a/arch/arm/kernel/signal.c +++ b/arch/arm/kernel/signal.c @@ -301,7 +301,7 @@ setup_sigframe(struct sigframe __user *sf, struct pt_regs *regs, sigset_t *set) if (err == 0) err |= preserve_vfp_context(&aux->vfp); #endif - __put_user_error(0, &aux->end_magic, err); + err |= __put_user(0, &aux->end_magic); return err; } @@ -433,7 +433,7 @@ setup_frame(struct ksignal *ksig, sigset_t *set, struct pt_regs *regs) /* * Set uc.uc_flags to a value which sc.trap_no would never have. */ - __put_user_error(0x5ac3c35a, &frame->uc.uc_flags, err); + err = __put_user(0x5ac3c35a, &frame->uc.uc_flags); err |= setup_sigframe(frame, regs, set); if (err == 0) @@ -453,8 +453,8 @@ setup_rt_frame(struct ksignal *ksig, sigset_t *set, struct pt_regs *regs) err |= copy_siginfo_to_user(&frame->info, &ksig->info); - __put_user_error(0, &frame->sig.uc.uc_flags, err); - __put_user_error(NULL, &frame->sig.uc.uc_link, err); + err |= __put_user(0, &frame->sig.uc.uc_flags); + err |= __put_user(NULL, &frame->sig.uc.uc_link); err |= __save_altstack(&frame->sig.uc.uc_stack, regs->ARM_sp); err |= setup_sigframe(&frame->sig, regs, set); From patchwork Thu Aug 1 08:16:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 170338 Delivered-To: patch@linaro.org Received: by 2002:a92:512:0:0:0:0:0 with SMTP id q18csp5086500ile; Thu, 1 Aug 2019 01:21:00 -0700 (PDT) X-Google-Smtp-Source: APXvYqyjguQvCpnFmxr3ln2FsrZlLbRz4gIVw1D2dPtYwfKz24vdP3AUJjqs2vy7JwvmYwRK3KMK X-Received: by 2002:a17:902:112c:: with SMTP id d41mr113817851pla.33.1564647659935; Thu, 01 Aug 2019 01:20:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564647659; cv=none; d=google.com; s=arc-20160816; b=Tt5T+V6SOvFIz5YkiYOVjC+9jI1Boo7/Iv1NFAnp/mDPNfDHWU9IRdP+LIVmGosjOM q8JqPZ/JCluUS6wbZAOf1pu3RFzLEGLltUiEZz7QxSBxCn3K2E5Un7AorImwR8DzNtOX SNkuwoEAuSgO2C6xRpD9t3/Cws2blatKKtLb3cSG4kWS3rUNyGGDASTp02oYc7f7T/Ts xgcNt7E8SgU9d/Ejydxg3gWoI+gHJj/xScVoFjMIA/24KxEhEPpDXht090br57F+vJ/n +jxrbGzMz48Z4YIAmIKyHKfxVP47jrzRHz0HImLymKrvHLqRocNpyCw5z7bfVfcBxGAi vl/g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=83Q5DLuQYSva53SfstGNLwQ+WusgochK7tEX54DLnZk=; b=07PL2ry0oyjYJhBKuI9t4trv3dTrj+audNb4VcaqMHBG3GZqOTbOzd3KTPuT1dgckj coCMj4KuPkjM8YXRQhseYZyWsxR6Zen3qmapjDoQ5qprLGjzaJJut/cpySfuGHuA4ojh Zt35vRn5bdb8eBtMk9itgiDrinTp2OoB/C8DSrvc3JnSvnMPR6W9T9xnwSOtu5St6JTN q/HpdeCN+r340zG2GWsMB8TFtd0aQHCnRTmH3l8Y06BP+3e9x8hLpKKVE1BAjpc/MzeP 0H9ptt+6fG+yThFpvWG0kztjqHCmDu1MtE7nffc63uguZmjw29iaH9fMYakvZ6cSStAD KELQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=rI4dN04P; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id v63si6543334pgd.111.2019.08.01.01.20.59; Thu, 01 Aug 2019 01:20:59 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=rI4dN04P; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730656AbfHAIU7 (ORCPT + 14 others); Thu, 1 Aug 2019 04:20:59 -0400 Received: from mail-pf1-f196.google.com ([209.85.210.196]:39185 "EHLO mail-pf1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727171AbfHAIU7 (ORCPT ); Thu, 1 Aug 2019 04:20:59 -0400 Received: by mail-pf1-f196.google.com with SMTP id f17so29614381pfn.6 for ; Thu, 01 Aug 2019 01:20:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=83Q5DLuQYSva53SfstGNLwQ+WusgochK7tEX54DLnZk=; b=rI4dN04PCrS8oEfhhu1FimQvBZ8VBzO1CvaxoGD0C6HzZI6J1xXoWDHX2NESLp/Gu7 7/G8HfBb07K3/rgxPknRTOvB3aLF023teB3bfyIRyAR+J8H4K9LaMWtxu70jFDgK74EX d5yKiB/4rRbxtd1QdEtqb0PY9C3bjQM4DYhFHaErCxKRZDpe+KlfB4THeuDtUHgMKne0 tAcVx3VWyyaYMIEQmAFWy51kwzUYHaZxrC4iPgcfUez/yyp4OS9lBBifrZ0sEM4m2uBe HN9oapm4F9z9UV++zkll/G0/DnOcFJFTYG1xzjUUiBgS5qLQw/8M46c9Qq8EW4MJ4sTk pdDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=83Q5DLuQYSva53SfstGNLwQ+WusgochK7tEX54DLnZk=; b=rTt8gxpf4edvAhgXritg6cCEyyYCghZ9a2rjygmIDWs093v1FHvTgLQ6Wu8kwfZeOF ynU9yJ7bCLCOneKTNh4ReDkMKLejcjBYH++INbgUqfRTwLlZTkLAExU5Q6C50nha56C4 3sft9i5teS18i2kdmvOINOvbUaEoqEwAiyyGgk0gU5aPBWULxySgIg/PEqa4dg0zV2LJ dpGeclXzTSns7omKQRKcyRnAmO0EfSA0POKNzx4cOKAmwWXUInXiRKxYQ5Dlfb/KREO/ Gyuzj6l+mc4mJe6S4dmLuNznEre6KTPiGgVs6NxH8jK1tIPgaBRbT6MGPVyPVLpagRZX vKjw== X-Gm-Message-State: APjAAAWK9Le13+BbAMUJLayscaSA7MVX+n/a8YerXaZdvGipeCElJrNP +Dt8rLhIYRCl6CNBlREfwO6duivIvnk= X-Received: by 2002:a62:14c4:: with SMTP id 187mr50562879pfu.241.1564647658137; Thu, 01 Aug 2019 01:20:58 -0700 (PDT) Received: from localhost ([122.172.28.117]) by smtp.gmail.com with ESMTPSA id j1sm95276210pgl.12.2019.08.01.01.20.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 01 Aug 2019 01:20:57 -0700 (PDT) From: Viresh Kumar To: stable@vger.kernel.org Cc: Viresh Kumar , Julien Thierry , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Marc Zyngier , Mark Rutland , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com, guohanjun@huawei.com Subject: [PATCH ARM32 v4.4 V2 32/47] ARM: 8794/1: uaccess: Prevent speculative use of the current addr_limit Date: Thu, 1 Aug 2019 13:46:16 +0530 Message-Id: <74663c62c712201d35d012eba43ad611b6c5a3fe.1564646727.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Julien Thierry Commit 621afc677465db231662ed126ae1f355bf8eac47 upstream. A mispredicted conditional call to set_fs could result in the wrong addr_limit being forwarded under speculation to a subsequent access_ok check, potentially forming part of a spectre-v1 attack using uaccess routines. This patch prevents this forwarding from taking place, but putting heavy barriers in set_fs after writing the addr_limit. Porting commit c2f0ad4fc089cff8 ("arm64: uaccess: Prevent speculative use of the current addr_limit"). Signed-off-by: Julien Thierry Signed-off-by: Russell King Signed-off-by: Viresh Kumar --- arch/arm/include/asm/uaccess.h | 8 ++++++++ 1 file changed, 8 insertions(+) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm/include/asm/uaccess.h b/arch/arm/include/asm/uaccess.h index ecd159b45f12..a782201a2629 100644 --- a/arch/arm/include/asm/uaccess.h +++ b/arch/arm/include/asm/uaccess.h @@ -99,6 +99,14 @@ extern int __put_user_bad(void); static inline void set_fs(mm_segment_t fs) { current_thread_info()->addr_limit = fs; + + /* + * Prevent a mispredicted conditional call to set_fs from forwarding + * the wrong address limit to access_ok under speculation. + */ + dsb(nsh); + isb(); + modify_domain(DOMAIN_KERNEL, fs ? DOMAIN_CLIENT : DOMAIN_MANAGER); } From patchwork Thu Aug 1 08:16:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 170339 Delivered-To: patch@linaro.org Received: by 2002:a92:512:0:0:0:0:0 with SMTP id q18csp5086552ile; Thu, 1 Aug 2019 01:21:02 -0700 (PDT) X-Google-Smtp-Source: APXvYqyiNstfGcHz0rDopTly/XpSkAKGhfIpe8hp9XVeR8J+JbwcrTBtaA05KPIvBwpRs3TehoJJ X-Received: by 2002:a62:38c6:: with SMTP id f189mr52028197pfa.157.1564647662900; Thu, 01 Aug 2019 01:21:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564647662; cv=none; d=google.com; s=arc-20160816; b=kG9noubWI4KEnXrqscrgzoTul5aDIKtgf96OlTA76tdlZgKAHl4q8vKixio/5XMPLs eHIw38nU2rXZ4jr+A6XmH7184Z8LJwNRhHA5R9/QUWYA6ssCjGJ+17NaT8AMVKOcqlx8 ukboaUy3z76Je974xCvQrNj/q/U3JrRv9NFLJwmNNEJ2N09rexKCExdxMIbxS9GrnINB gKV862j5lwLFIWayL54b72VbhWaXyXvB1N/+l6r+qHdGCnRQG9RcfloYSGAdLAAu83g1 balgpveRFKt9jaW9bH6dXCZdPHVUSZhHNNc7uHUA1LnDN3MT2Rq9iqI13L1KtTfmNxyy bjbg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=wHzU+tsn1pgRkzbIeM8fvpGsFHg5ebHOWm4gu/3Evbs=; b=R1bjLIgDbCps421+/hoEC8wxCeamRyCij0NGhejvNi2LXRn8Wdv0K4C9jyNUE5LJtW USkUUZjB/sj4G2av3nthuEsKyRbX/dCse/3LX4Qrv07HgHLX90+t4aM9+XPF6oKJfs44 F/ahx+BD1VxbaWYrph66vYgRkGt7hAjkBq1eXeI7r3vjuZHZ0GAUnmyNGb74Gk3Et+q2 lxr9pHjm9fp/InxCi4npUKIKboiid6xe7M2UVwzV3e7rvLs5IG0k0eGsbxal9LwVAjaU OoallG553ucVmhEUjuVn8/Wz/rRvQdTlRJZIgA1Yqi+nwtxVi/jUH0tlv28zukyTXs0j bC6A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=rSAt52eg; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Remove the code duplication between put_user() and __put_user(). The code which selected the implementation based upon the pointer size, and declared the local variable to hold the value to be put are common to both implementations. Signed-off-by: Russell King Signed-off-by: Viresh Kumar --- arch/arm/include/asm/uaccess.h | 106 +++++++++++++++------------------ 1 file changed, 49 insertions(+), 57 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm/include/asm/uaccess.h b/arch/arm/include/asm/uaccess.h index a782201a2629..94b1bf53b820 100644 --- a/arch/arm/include/asm/uaccess.h +++ b/arch/arm/include/asm/uaccess.h @@ -253,49 +253,23 @@ extern int __put_user_2(void *, unsigned int); extern int __put_user_4(void *, unsigned int); extern int __put_user_8(void *, unsigned long long); -#define __put_user_x(__r2, __p, __e, __l, __s) \ - __asm__ __volatile__ ( \ - __asmeq("%0", "r0") __asmeq("%2", "r2") \ - __asmeq("%3", "r1") \ - "bl __put_user_" #__s \ - : "=&r" (__e) \ - : "0" (__p), "r" (__r2), "r" (__l) \ - : "ip", "lr", "cc") - -#define __put_user_check(x, p) \ +#define __put_user_check(__pu_val, __ptr, __err, __s) \ ({ \ unsigned long __limit = current_thread_info()->addr_limit - 1; \ - const typeof(*(p)) __user *__tmp_p = (p); \ - register typeof(*(p)) __r2 asm("r2") = (x); \ - register const typeof(*(p)) __user *__p asm("r0") = __tmp_p; \ + register typeof(__pu_val) __r2 asm("r2") = __pu_val; \ + register const void __user *__p asm("r0") = __ptr; \ register unsigned long __l asm("r1") = __limit; \ register int __e asm("r0"); \ - unsigned int __ua_flags = uaccess_save_and_enable(); \ - switch (sizeof(*(__p))) { \ - case 1: \ - __put_user_x(__r2, __p, __e, __l, 1); \ - break; \ - case 2: \ - __put_user_x(__r2, __p, __e, __l, 2); \ - break; \ - case 4: \ - __put_user_x(__r2, __p, __e, __l, 4); \ - break; \ - case 8: \ - __put_user_x(__r2, __p, __e, __l, 8); \ - break; \ - default: __e = __put_user_bad(); break; \ - } \ - uaccess_restore(__ua_flags); \ - __e; \ + __asm__ __volatile__ ( \ + __asmeq("%0", "r0") __asmeq("%2", "r2") \ + __asmeq("%3", "r1") \ + "bl __put_user_" #__s \ + : "=&r" (__e) \ + : "0" (__p), "r" (__r2), "r" (__l) \ + : "ip", "lr", "cc"); \ + __err = __e; \ }) -#define put_user(x, p) \ - ({ \ - might_fault(); \ - __put_user_check(x, p); \ - }) - #else /* CONFIG_MMU */ /* @@ -313,7 +287,7 @@ static inline void set_fs(mm_segment_t fs) } #define get_user(x, p) __get_user(x, p) -#define put_user(x, p) __put_user(x, p) +#define __put_user_check __put_user_nocheck #endif /* CONFIG_MMU */ @@ -408,36 +382,54 @@ do { \ __get_user_asm(x, addr, err, ldr) #endif + +#define __put_user_switch(x, ptr, __err, __fn) \ + do { \ + const __typeof__(*(ptr)) __user *__pu_ptr = (ptr); \ + __typeof__(*(ptr)) __pu_val = (x); \ + unsigned int __ua_flags; \ + might_fault(); \ + __ua_flags = uaccess_save_and_enable(); \ + switch (sizeof(*(ptr))) { \ + case 1: __fn(__pu_val, __pu_ptr, __err, 1); break; \ + case 2: __fn(__pu_val, __pu_ptr, __err, 2); break; \ + case 4: __fn(__pu_val, __pu_ptr, __err, 4); break; \ + case 8: __fn(__pu_val, __pu_ptr, __err, 8); break; \ + default: __err = __put_user_bad(); break; \ + } \ + uaccess_restore(__ua_flags); \ + } while (0) + +#define put_user(x, ptr) \ +({ \ + int __pu_err = 0; \ + __put_user_switch((x), (ptr), __pu_err, __put_user_check); \ + __pu_err; \ +}) + #define __put_user(x, ptr) \ ({ \ long __pu_err = 0; \ - __put_user_err((x), (ptr), __pu_err); \ + __put_user_switch((x), (ptr), __pu_err, __put_user_nocheck); \ __pu_err; \ }) #define __put_user_error(x, ptr, err) \ ({ \ - __put_user_err((x), (ptr), err); \ + __put_user_switch((x), (ptr), (err), __put_user_nocheck); \ (void) 0; \ }) -#define __put_user_err(x, ptr, err) \ -do { \ - unsigned long __pu_addr = (unsigned long)(ptr); \ - unsigned int __ua_flags; \ - __typeof__(*(ptr)) __pu_val = (x); \ - __chk_user_ptr(ptr); \ - might_fault(); \ - __ua_flags = uaccess_save_and_enable(); \ - switch (sizeof(*(ptr))) { \ - case 1: __put_user_asm_byte(__pu_val, __pu_addr, err); break; \ - case 2: __put_user_asm_half(__pu_val, __pu_addr, err); break; \ - case 4: __put_user_asm_word(__pu_val, __pu_addr, err); break; \ - case 8: __put_user_asm_dword(__pu_val, __pu_addr, err); break; \ - default: __put_user_bad(); \ - } \ - uaccess_restore(__ua_flags); \ -} while (0) +#define __put_user_nocheck(x, __pu_ptr, __err, __size) \ + do { \ + unsigned long __pu_addr = (unsigned long)__pu_ptr; \ + __put_user_nocheck_##__size(x, __pu_addr, __err); \ + } while (0) + +#define __put_user_nocheck_1 __put_user_asm_byte +#define __put_user_nocheck_2 __put_user_asm_half +#define __put_user_nocheck_4 __put_user_asm_word +#define __put_user_nocheck_8 __put_user_asm_dword #define __put_user_asm(x, __pu_addr, err, instr) \ __asm__ __volatile__( \ From patchwork Thu Aug 1 08:16:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 170345 Delivered-To: patch@linaro.org Received: by 2002:a92:512:0:0:0:0:0 with SMTP id q18csp5086636ile; Thu, 1 Aug 2019 01:21:06 -0700 (PDT) X-Google-Smtp-Source: APXvYqyr8c0MkI2xMBiBCamS35L/bu9WAak/UPgPLETEvS76XeanLT4dYhkhHbUM3XTBroarL/TG X-Received: by 2002:a17:902:2b8a:: with SMTP id l10mr124349806plb.283.1564647666496; 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When Spectre mitigation is required, __put_user() needs to include check_uaccess. This is already the case for put_user(), so just make __put_user() an alias of put_user(). Signed-off-by: Julien Thierry Signed-off-by: Russell King Signed-off-by: Viresh Kumar --- arch/arm/include/asm/uaccess.h | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm/include/asm/uaccess.h b/arch/arm/include/asm/uaccess.h index 94b1bf53b820..7f96a942d9a0 100644 --- a/arch/arm/include/asm/uaccess.h +++ b/arch/arm/include/asm/uaccess.h @@ -407,6 +407,14 @@ do { \ __pu_err; \ }) +#ifdef CONFIG_CPU_SPECTRE +/* + * When mitigating Spectre variant 1.1, all accessors need to include + * verification of the address space. + */ +#define __put_user(x, ptr) put_user(x, ptr) + +#else #define __put_user(x, ptr) \ ({ \ long __pu_err = 0; \ @@ -414,12 +422,6 @@ do { \ __pu_err; \ }) -#define __put_user_error(x, ptr, err) \ -({ \ - __put_user_switch((x), (ptr), (err), __put_user_nocheck); \ - (void) 0; \ -}) - #define __put_user_nocheck(x, __pu_ptr, __err, __size) \ do { \ unsigned long __pu_addr = (unsigned long)__pu_ptr; \ @@ -499,6 +501,7 @@ do { \ : "r" (x), "i" (-EFAULT) \ : "cc") +#endif /* !CONFIG_CPU_SPECTRE */ #ifdef CONFIG_MMU extern unsigned long __must_check From patchwork Thu Aug 1 08:16:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 170340 Delivered-To: patch@linaro.org Received: by 2002:a92:512:0:0:0:0:0 with SMTP id q18csp5086685ile; Thu, 1 Aug 2019 01:21:08 -0700 (PDT) X-Google-Smtp-Source: APXvYqzG0ME5cQdcJRGn2uMtYKoPDrIX+aRxdl5e0yUxRT07hmeKavTwb+6v0XDZiFN2v3MAlXLf X-Received: by 2002:a17:90a:ac13:: with SMTP id o19mr7261145pjq.143.1564647668407; Thu, 01 Aug 2019 01:21:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564647668; cv=none; d=google.com; s=arc-20160816; b=fShfHAkh1AkdAqQsRn036uLs8RMzvXYB6R0QOKQ9VukC4sdY4sE5MtSd+4Y+0W2hM5 DYuzUuH3p0cMA5nzXyZjD5Oy2cQM9mSMYTNJBZUtf6lbMncZYyDPnqD2MgPBTzTx+bZR hxwrBrf9g0Qqc4weE9de9In9ReZJ41KLrYNneYuAGx31+Abc0C8zIbSDUP1FKhAz5vgw 6Gvfb731smujiEmeTmfIJ3A3GNf69NNRhvipwoiWveSk4K6ysO/WsK4RP4YCuCeBdX/i EWLnRxOl038dpG3RZ4SwauiFVVzWtJk0FBhGDr64WlQwctkdHmzshhmJunBJTb0jG6o8 m5ng== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=QT52cSxWVIebfDc1oGBa7p8CuPEmaq03dkPYlQrFIZw=; b=jn8jT+AVkAnnCOgAxQvLHVG59uA7cKQVSuy0y+tM/fvbIh3694YkB3P2MM25IQ/8CG QCApPvo4C4fiBYjaJtYIaw7Itxb0E2NYe6FvTwGgojq2NDVt4wc/N6WPMq9emI/WGW2V VlrEum9kvNKqz4TvxnBcZrGKkcic0sXnrDPtHgfoFIF4OrKhxr2B5wVvgr4hGuCvniLi kmsk+x9iZNhN178Iu6OVy6V2yl/XpupgWeXIvYr/Vh5moxcy6x2W4iOI8hJboq0zkVmQ 3Q/K6pyWWMcDlClKgGjcF/Scvnkb1w0V5yhVTs7fLdmGESS5Ra6RNJ1hGFDvQaq1+H7s 1tLw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pilV4a1P; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id y21si30526126plp.332.2019.08.01.01.21.08; Thu, 01 Aug 2019 01:21:08 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pilV4a1P; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731131AbfHAIVH (ORCPT + 14 others); Thu, 1 Aug 2019 04:21:07 -0400 Received: from mail-pf1-f194.google.com ([209.85.210.194]:33139 "EHLO mail-pf1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731122AbfHAIVH (ORCPT ); Thu, 1 Aug 2019 04:21:07 -0400 Received: by mail-pf1-f194.google.com with SMTP id g2so33613467pfq.0 for ; Thu, 01 Aug 2019 01:21:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QT52cSxWVIebfDc1oGBa7p8CuPEmaq03dkPYlQrFIZw=; b=pilV4a1PZ7oAn8kiAPyEMpIAXatrnWAY7F56eSYPB9vrKy4dh5U8N9TvLKEbGs/trC gCp08Y6foQq6IHiA6lZOSHoJ6GRRFGq9rri/60LMEZnonPys5z/6SoXnZNJl65mFs7ci JJmSUxzGYnlU1VdgyralvPmw6VwExqh6And5XbOEm19Y4zpQ8SRF02sImAKc6nW5yDiZ GxV3IOIraRaflGL69TuNQCaZhm8vxrZbqpITFaNwdJKixpvFTRCpAsy9bhn2OggnWT/L 3IaRBmLuHoo60PO01b2vc6dsTtslHml6G7AGm53sc8Nrlagct8eYTSp2XXwebHHH3mvI 26dQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QT52cSxWVIebfDc1oGBa7p8CuPEmaq03dkPYlQrFIZw=; b=OVYIOt6/KaGXTGIxeoPYaSE+p+SFWgGZZem3GyQsyUmsCQCtQa5Vc5qP7+vSdZMrm9 F1cQJQKFnOdBCQisdPV8EoTY/0YYchR0e3wWCzoPr7Z+uEeZFa+5vwrhA45CfJR5xka8 +N5AiuezJtzuWV3R0On2gEtu5o/KUQCOiZ51zEGj+q4XJUaPBOnE1TPyg5L1bIBRXEwP 8qZmCqVU27rIKJ2j/lyTM6+FkosDycgC4/Ebb4JpJQSKMAZdx+gKfbjPT+UuWkjL52sJ 2jov647anKrZREwEQaCMRR0M1x81C/XQGvdNFWKqdr7zzlZ/vvZO4LqY9wRKaiqhWkfh ewTg== X-Gm-Message-State: APjAAAXJMHwPC+Vq5hcBfHeOipRohA/qndKArMbIkHAsOnC2plv9dfEM yktdkJxHerfBI3P5kTUXcsSMwES5g24= X-Received: by 2002:a63:a35e:: with SMTP id v30mr57674126pgn.129.1564647665858; Thu, 01 Aug 2019 01:21:05 -0700 (PDT) Received: from localhost ([122.172.28.117]) by smtp.gmail.com with ESMTPSA id p1sm76262663pff.74.2019.08.01.01.21.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 01 Aug 2019 01:21:05 -0700 (PDT) From: Viresh Kumar To: stable@vger.kernel.org Cc: Viresh Kumar , Julien Thierry , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Marc Zyngier , Mark Rutland , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com, guohanjun@huawei.com Subject: [PATCH ARM32 v4.4 V2 35/47] ARM: 8796/1: spectre-v1, v1.1: provide helpers for address sanitization Date: Thu, 1 Aug 2019 13:46:19 +0530 Message-Id: <56d194e7c07733a1cb99457e07067b6db64560ef.1564646727.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Julien Thierry Commit afaf6838f4bc896a711180b702b388b8cfa638fc upstream. Introduce C and asm helpers to sanitize user address, taking the address range they target into account. Use asm helper for existing sanitization in __copy_from_user(). Signed-off-by: Julien Thierry Signed-off-by: Russell King Signed-off-by: Viresh Kumar --- arch/arm/include/asm/assembler.h | 11 +++++++++++ arch/arm/include/asm/uaccess.h | 26 ++++++++++++++++++++++++++ arch/arm/lib/copy_from_user.S | 6 +----- 3 files changed, 38 insertions(+), 5 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h index 483481c6937e..f2624fbd0336 100644 --- a/arch/arm/include/asm/assembler.h +++ b/arch/arm/include/asm/assembler.h @@ -461,6 +461,17 @@ THUMB( orr \reg , \reg , #PSR_T_BIT ) #endif .endm + .macro uaccess_mask_range_ptr, addr:req, size:req, limit:req, tmp:req +#ifdef CONFIG_CPU_SPECTRE + sub \tmp, \limit, #1 + subs \tmp, \tmp, \addr @ tmp = limit - 1 - addr + addhs \tmp, \tmp, #1 @ if (tmp >= 0) { + subhss \tmp, \tmp, \size @ tmp = limit - (addr + size) } + movlo \addr, #0 @ if (tmp < 0) addr = NULL + csdb +#endif + .endm + .macro uaccess_disable, tmp, isb=1 #ifdef CONFIG_CPU_SW_DOMAIN_PAN /* diff --git a/arch/arm/include/asm/uaccess.h b/arch/arm/include/asm/uaccess.h index 7f96a942d9a0..9a3b6de2edac 100644 --- a/arch/arm/include/asm/uaccess.h +++ b/arch/arm/include/asm/uaccess.h @@ -137,6 +137,32 @@ static inline void set_fs(mm_segment_t fs) #define __inttype(x) \ __typeof__(__builtin_choose_expr(sizeof(x) > sizeof(0UL), 0ULL, 0UL)) +/* + * Sanitise a uaccess pointer such that it becomes NULL if addr+size + * is above the current addr_limit. + */ +#define uaccess_mask_range_ptr(ptr, size) \ + ((__typeof__(ptr))__uaccess_mask_range_ptr(ptr, size)) +static inline void __user *__uaccess_mask_range_ptr(const void __user *ptr, + size_t size) +{ + void __user *safe_ptr = (void __user *)ptr; + unsigned long tmp; + + asm volatile( + " sub %1, %3, #1\n" + " subs %1, %1, %0\n" + " addhs %1, %1, #1\n" + " subhss %1, %1, %2\n" + " movlo %0, #0\n" + : "+r" (safe_ptr), "=&r" (tmp) + : "r" (size), "r" (current_thread_info()->addr_limit) + : "cc"); + + csdb(); + return safe_ptr; +} + /* * Single-value transfer routines. They automatically use the right * size if we just have the right pointer type. Note that the functions diff --git a/arch/arm/lib/copy_from_user.S b/arch/arm/lib/copy_from_user.S index d36329cefedc..e32b51838439 100644 --- a/arch/arm/lib/copy_from_user.S +++ b/arch/arm/lib/copy_from_user.S @@ -93,11 +93,7 @@ ENTRY(arm_copy_from_user) #ifdef CONFIG_CPU_SPECTRE get_thread_info r3 ldr r3, [r3, #TI_ADDR_LIMIT] - adds ip, r1, r2 @ ip=addr+size - sub r3, r3, #1 @ addr_limit - 1 - cmpcc ip, r3 @ if (addr+size > addr_limit - 1) - movcs r1, #0 @ addr = NULL - csdb + uaccess_mask_range_ptr r1, r2, r3, ip #endif #include "copy_template.S" From patchwork Thu Aug 1 08:16:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 170341 Delivered-To: patch@linaro.org Received: by 2002:a92:512:0:0:0:0:0 with SMTP id q18csp5086785ile; Thu, 1 Aug 2019 01:21:12 -0700 (PDT) X-Google-Smtp-Source: APXvYqwgo1/mK5GxiH/O4vY7m6HvwaT4FLfLjcCqG9pEK2SHgZL2JcT4AHN5Dn3A9evXyf+ZQcvr X-Received: by 2002:a17:90a:6097:: with SMTP id z23mr7282037pji.75.1564647672431; Thu, 01 Aug 2019 01:21:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564647672; cv=none; d=google.com; s=arc-20160816; b=IgYBzylxGQ6ysRJPFqHY97wAmMVU906SMbPVJOCsynM8OSlGtWZfc3sG3UJnyfELU9 DVzNVvqGpFu6lKkxzNjXVleoQIc3WWIzKEGtypbpwhcDYczgtgXdF2Roe0olc4b6kSc4 ul85L956HPSz/xb/fdEZ6aHMRFYAv+7N5XvmCExiublJV6VJ+zC5T/zHq97Qo8yka2vO cMFVyCxen/Tf3PmhvgeXIKwn7FFg840jNiwaynufV8V4ZrQwR5YoIcFqYpFKalV2Aw1t EmwZwM3jyRhk1fkgtl+cEOu3ehwqC6MncL0vx76SCaJrek14B7xg1E1lPAcKSADpboUw B8LA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=K9TMbtUgLTyiUr1AVMR6X3v/Vfqpdps5jv4IrzU02gI=; b=JQlscMHMB+L4jV0MyShA4067n6NH7sbF0xugft5q+p0jAB848jrWEdu0/E3q8NFePw 7ZcFdnTbuSKW4IRPHhEGgHsKGBIwjObAUisk8b9Qn2+tMp0IBl3NadgRkZO9P/O1HHMP mhhorN1gMyTKMyzm7xYacuWTI6xqSCyelvTZcbBzOuw7UK7uFIdF/sKJ6cyzuZ1ab/lk qDVOkEjax31gQdKiopruEFMXKk0L6rwnGbwrmlxY0g+bi+rWz+KE5KIeIW0F+TlnuJY7 ZwJG1hKIoKxakPK83rQlx/3I9PaNqjGmt+GMxyXGtbPOr+qmMKvrm2lX0Ep5kkw1dCNK NMrw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=u2IY36x0; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id z13si4013236pgj.476.2019.08.01.01.21.12; Thu, 01 Aug 2019 01:21:12 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=u2IY36x0; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731138AbfHAIVK (ORCPT + 14 others); Thu, 1 Aug 2019 04:21:10 -0400 Received: from mail-pf1-f194.google.com ([209.85.210.194]:42886 "EHLO mail-pf1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731106AbfHAIVJ (ORCPT ); Thu, 1 Aug 2019 04:21:09 -0400 Received: by mail-pf1-f194.google.com with SMTP id q10so33593416pff.9 for ; Thu, 01 Aug 2019 01:21:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=K9TMbtUgLTyiUr1AVMR6X3v/Vfqpdps5jv4IrzU02gI=; b=u2IY36x0captMh4lU1M0wOFOAmston0O2MSPdh8WfOWDhEl6wCe1fHWEB302u0RLea ojVO3+6Uw8ngcEcpYwUKq96/4ZNyKwEJSwrmqBpTewb+1cTQJdgIBsGPrIcskcI3D/WE 5Eg2rHSAqdcoxT2Rx0APBgbNWmChW6h+Ch+VfBXwjDUY8xtjNpJh8eZCmXoMtYQOIAnB KDRBkaRJKx2tqjYEejnBltvZKwg1B+mta/JF1UVSfxbYY86SwBJDW+O9haVVpEQ7x9Ou qnTAXeFV4PukhvZIY1cb0Nqw3H7EhNmjHszAQmsiggMC3v6tFdCB8MczrpQKPRwPqCdj P4SQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=K9TMbtUgLTyiUr1AVMR6X3v/Vfqpdps5jv4IrzU02gI=; b=uXREeHs3nbu4pznBONM1vCUnuJwPMyFItWVzFgIA7+sM0v3LsQMbduxGJTh/ASIrju oqhtmWiqPXKU26PsGIJQ9Boz0088rj9EvaQ+BzJq0k9jQt1RUQdUsqDk4SJnJXXMMmig nx6AYVba8FQd8IKn4gqFwXecwe/grpYhvzTyVw6kLSRfCaiIOm7x0xQoYPaZ1RCkN4Q+ vK9QB5+qKrpNpg9tAN4h6ZxlKJ3p77MvU+Ho+vZTfAsPahlN7u2DRqqV9Hv4wmzUPrzg mU1t8UO6akQnkZnAdkWE3/Bdn4XXIO3Uv2a/490gE4k6Lfc+YqHjATmcBow7Eoogb1mA VJGg== X-Gm-Message-State: APjAAAXCHCwgAARu3kiPMqabgyedaEp7f89QZld20+2yad1iT5GB7u19 x0P21EOz6Z6R9/0JNjtwzT6Cz/g1QWs= X-Received: by 2002:a62:e901:: with SMTP id j1mr52916707pfh.189.1564647668335; Thu, 01 Aug 2019 01:21:08 -0700 (PDT) Received: from localhost ([122.172.28.117]) by smtp.gmail.com with ESMTPSA id y194sm47244254pfg.116.2019.08.01.01.21.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 01 Aug 2019 01:21:07 -0700 (PDT) From: Viresh Kumar To: stable@vger.kernel.org Cc: Viresh Kumar , Julien Thierry , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Marc Zyngier , Mark Rutland , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com, guohanjun@huawei.com Subject: [PATCH ARM32 v4.4 V2 36/47] ARM: 8797/1: spectre-v1.1: harden __copy_to_user Date: Thu, 1 Aug 2019 13:46:20 +0530 Message-Id: X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Julien Thierry Commit a1d09e074250fad24f1b993f327b18cc6812eb7a upstream. Sanitize user pointer given to __copy_to_user, both for standard version and memcopy version of the user accessor. Signed-off-by: Julien Thierry Signed-off-by: Russell King Signed-off-by: Viresh Kumar --- arch/arm/lib/copy_to_user.S | 6 +++++- arch/arm/lib/uaccess_with_memcpy.c | 3 ++- 2 files changed, 7 insertions(+), 2 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm/lib/copy_to_user.S b/arch/arm/lib/copy_to_user.S index caf5019d8161..970abe521197 100644 --- a/arch/arm/lib/copy_to_user.S +++ b/arch/arm/lib/copy_to_user.S @@ -94,6 +94,11 @@ ENTRY(__copy_to_user_std) WEAK(arm_copy_to_user) +#ifdef CONFIG_CPU_SPECTRE + get_thread_info r3 + ldr r3, [r3, #TI_ADDR_LIMIT] + uaccess_mask_range_ptr r0, r2, r3, ip +#endif #include "copy_template.S" @@ -108,4 +113,3 @@ ENDPROC(__copy_to_user_std) rsb r0, r0, r2 copy_abort_end .popsection - diff --git a/arch/arm/lib/uaccess_with_memcpy.c b/arch/arm/lib/uaccess_with_memcpy.c index 588bbc288396..0b4fe892d00b 100644 --- a/arch/arm/lib/uaccess_with_memcpy.c +++ b/arch/arm/lib/uaccess_with_memcpy.c @@ -153,7 +153,8 @@ arm_copy_to_user(void __user *to, const void *from, unsigned long n) n = __copy_to_user_std(to, from, n); uaccess_restore(ua_flags); } else { - n = __copy_to_user_memcpy(to, from, n); + n = __copy_to_user_memcpy(uaccess_mask_range_ptr(to, n), + from, n); } return n; } From patchwork Thu Aug 1 08:16:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 170342 Delivered-To: patch@linaro.org Received: by 2002:a92:512:0:0:0:0:0 with SMTP id q18csp5086809ile; Thu, 1 Aug 2019 01:21:14 -0700 (PDT) X-Google-Smtp-Source: APXvYqyygypdpTXp2IzzQG5q2UgRAmvjwu97ZY7/IsZ4gaC75DLRZNJx7YTU82OuybQDf2AOjLe/ X-Received: by 2002:a63:2c8:: with SMTP id 191mr115981734pgc.139.1564647673923; Thu, 01 Aug 2019 01:21:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564647673; cv=none; d=google.com; s=arc-20160816; b=eAOqIy7De47UZ8wwqIY0SopKLjm1Bra6Q220CTywWtGd/zzFrUk2l19rX66KCr0oRm FDgJK8Tfp0CitEcatvZCiF3hT7XPKVo2Wbs3xEWnI1LjEi9NXH99JTcyrK572wGs9sxO IwwoBTRnEg/grN+nmeOHmG7tsJgL/SkFSFj7nfKqoCzWSi1bpW2NMuppu7pzjF2GHIvV HsIocZt8lygcUij/kU8TQ3fPYLEebEZrPnz8kKxMAJZLxKnIdBnp3dXslGeaPLDhO/Kt UJxEuSmve5nd1IP7K7gDBcngbsJ3eZI/mkcuQsrpG3ic/oGazNYDjO5mA0NLEIa+xvl2 /3Ww== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=jbpvQKJEQu6FughKaepmre4Ek2Fg9qHsXyEHlW2kC7A=; b=H6124k/Z5ifIkzRHZUVhc69PazEblvjhb7h0EiMkZrMxds+DJAdZmIY18pmhsTiLnD YU7FIvzvMfwdEZEUQLk1AQE4Y9WTwktFfKk7y007x5lM+LQJd17Gedydj6OmR7Yu40TP HBzljHk8+vyoR44OuPfPHIu30wEligdQfbnE0ZhEmI+OulVqwlhPmudcgD3WCAyNESYq euvyGd4XmjhhR3G1ipR3iTSnnrHHIlW2LRpFfPy8HQuikgCapSfJnsQKDDobPmKE/Q6A 3kyO1N+uqfVGrcPrk/sDUHf98g3x10mk7G8sWhtFkJ7u635sQU+K+coPe4N1PlqzvGGv DPxA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=nuPAxY96; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Due to what appears to be a copy/paste error, the opening ENTRY() of cpu_v7_hvc_switch_mm() lacks a matching ENDPROC(), and instead, the one for cpu_v7_smc_switch_mm() is duplicated. Given that it is ENDPROC() that emits the Thumb annotation, the cpu_v7_hvc_switch_mm() routine will be called in ARM mode on a Thumb2 kernel, resulting in the following splat: Internal error: Oops - undefined instruction: 0 [#1] SMP THUMB2 Modules linked in: CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.18.0-rc1-00030-g4d28ad89189d-dirty #488 Hardware name: QEMU KVM Virtual Machine, BIOS 0.0.0 02/06/2015 PC is at cpu_v7_hvc_switch_mm+0x12/0x18 LR is at flush_old_exec+0x31b/0x570 pc : [] lr : [] psr: 00000013 sp : ee899e50 ip : 00000000 fp : 00000001 r10: eda28f34 r9 : eda31800 r8 : c12470e0 r7 : eda1fc00 r6 : eda53000 r5 : 00000000 r4 : ee88c000 r3 : c0316eec r2 : 00000001 r1 : eda53000 r0 : 6da6c000 Flags: nzcv IRQs on FIQs on Mode SVC_32 ISA ARM Segment none Note the 'ISA ARM' in the last line. Fix this by using the correct name in ENDPROC(). Cc: Fixes: 10115105cb3a ("ARM: spectre-v2: add firmware based hardening") Reviewed-by: Dave Martin Acked-by: Marc Zyngier Signed-off-by: Ard Biesheuvel Signed-off-by: Russell King Signed-off-by: Viresh Kumar --- arch/arm/mm/proc-v7.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index b6359ce39fa7..90cddff176f6 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -106,7 +106,7 @@ ENTRY(cpu_v7_hvc_switch_mm) hvc #0 ldmfd sp!, {r0 - r3} b cpu_v7_switch_mm -ENDPROC(cpu_v7_smc_switch_mm) +ENDPROC(cpu_v7_hvc_switch_mm) #endif ENTRY(cpu_v7_iciallu_switch_mm) mov r3, #0 From patchwork Thu Aug 1 08:16:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 170343 Delivered-To: patch@linaro.org Received: by 2002:a92:512:0:0:0:0:0 with SMTP id q18csp5086842ile; Thu, 1 Aug 2019 01:21:15 -0700 (PDT) X-Google-Smtp-Source: APXvYqxc4rKoUcalIEo8ti5Oxtbpe1+ugYSsmskm6oc8jFycVdUauKmmpjiy/y/fH5w3KiuOmChS X-Received: by 2002:a65:4507:: with SMTP id n7mr10079089pgq.86.1564647675590; Thu, 01 Aug 2019 01:21:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564647675; cv=none; d=google.com; s=arc-20160816; b=FlvjN/Eb/s/cOR+FMpEdEr8hbE0cXSA1qXIs9L6XqRwFKJTaRjcrfSgWBEGQuqS+uM T5XyCAg9rqsQW5LmatnmtrgJy2f7/IOcjD0aCbMN26VHUeok8yr+1PI2/G3blKo6cDk0 gzRLYR1j6jReeP5zDe0Gtv0p01t/+FQT+fnbvzodaiiFlXa++/YDZh0Q3zroigoHfxge 4m430xroQJY/Oq+EdkWNXDf8/FZkQ435CDoDQki1snu/2NL/GB7Qx3J6WSIM0bQrO7TC pWXDbm5UPLiy0hORVbCu4BHpT8EfEl0FEklAVbMLz5q+bd6OOzBMB5iGaOm/g/zay56N 1g6g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=/rNw3tnBxgbMcdBdzBneQcQUsRPBm5GaeGzxs7tkgFw=; b=w7VLwf4p3YhdQV0e3czP+9W1GtbK2/wzpM0Jz1nsl1fR46hbLnfL2ED9o1qfHjAKlq 0dUE8SCSVM7Pp/o1mWIYIDkc45V+PCVeU42iuRfp7aD0PYS+KTuOOBsXASxVliHbipkR yDXqg+1DA1IqKhkMNp+iOmNxWrXMGjoFVXGa4tQ+zj8iC7b6Q3EzPcNsIHyVQ+Tl+v4D p49Z1vrA5SEigfPmEBex9tsOF6d5Nrl6Qa1b0BRT7og4WCE9DklpjQwv/6EHJJiJA8oC /WhM0IQRfk/yCB+cs2x51jBtVazeJYqkUE8nXTakLHZF6cs4PkFmgZHdxW4pvVX8622x XS0g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=oN+aQ42T; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id z13si4013236pgj.476.2019.08.01.01.21.15; Thu, 01 Aug 2019 01:21:15 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=oN+aQ42T; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730700AbfHAIVO (ORCPT + 14 others); Thu, 1 Aug 2019 04:21:14 -0400 Received: from mail-pg1-f196.google.com ([209.85.215.196]:34434 "EHLO mail-pg1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731106AbfHAIVO (ORCPT ); Thu, 1 Aug 2019 04:21:14 -0400 Received: by mail-pg1-f196.google.com with SMTP id n9so27510306pgc.1 for ; Thu, 01 Aug 2019 01:21:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/rNw3tnBxgbMcdBdzBneQcQUsRPBm5GaeGzxs7tkgFw=; b=oN+aQ42TkqS/ZeSiy3PDVQMFYJwaMygZDYjh2qN8hDnDvIcJXJV2xpqOJsfr2J87Vb HeXPSEp5GcxRtJuCXOKlcDE0H84nRUB/twMJAH4jd/ZRQ2XVQgi3URaW62kWUFpPqhvx VWkcO50KK0MHGygwXTdMFgPeTJlYbSSFLDzu1sgoU/zfeXdgQg51br4OgEkEcdJH7Lzk 5i4gx5frWTr2aRqQyJrFvT/4HICocdqzcTYe2qbKmjtEUEJkGpNm+nulY/vpSEPHBKFq F6bqs230Y4TzLP/JVePgx7etwDRWQKZEMwVpsDX3zL1VhLFRyfY4sqoDKQ1VqFNTrw1w JK+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/rNw3tnBxgbMcdBdzBneQcQUsRPBm5GaeGzxs7tkgFw=; b=ulaalJX5sD1HK86DM5Mgohu6ad/EcVCNBOLzIMHqH3bMC7Ei45pfbHcvDU7puRtMM4 CN8orfy1MOFs187RUC28/FM+b0JT3Z8dz/mIU6NypiPPHe2Gh4Rq2gUIM7RTml5hsgzE jf4jfe1gDdFow5DfvEjWz8x9EBM8Nl6e0joYpU72ubAibYYJFGQwgT5ycAj413CSykpr 9dVi0T7KB48fl+ZCJP9XAyOXmkCpb12+/U4fi104+vLCaji42qJchqB/96lzxoBnZ7Xd 2xuVy5or4m3UN1ao95BLs4InaOJdBAnUT7WpshYgBv2UIqAwS6x9D5NjvRk5sYJ+29mM a9VA== X-Gm-Message-State: APjAAAV5Ymsh2AhMSf8G4zjcZhQiQEojMKZTZZV+hOS4n468xWT088KW EvC2WAH9/TBgKjjjBBwKHVbKbejtsb0= X-Received: by 2002:a63:c006:: with SMTP id h6mr83873722pgg.290.1564647673509; Thu, 01 Aug 2019 01:21:13 -0700 (PDT) Received: from localhost ([122.172.28.117]) by smtp.gmail.com with ESMTPSA id f7sm69426237pfd.43.2019.08.01.01.21.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 01 Aug 2019 01:21:13 -0700 (PDT) From: Viresh Kumar To: stable@vger.kernel.org Cc: Viresh Kumar , Julien Thierry , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Marc Zyngier , Mark Rutland , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com, guohanjun@huawei.com Subject: [PATCH ARM32 v4.4 V2 38/47] ARM: 8810/1: vfp: Fix wrong assignement to ufp_exc Date: Thu, 1 Aug 2019 13:46:22 +0530 Message-Id: <17ef1620483a77f70c7c27e64cba3ad1684626c7.1564646727.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Julien Thierry Commit 5df7a99bdd0de4a0480320264c44c04543c29d5a upstream. In vfp_preserve_user_clear_hwstate, ufp_exc->fpinst2 gets assigned to itself. It should actually be hwstate->fpinst2 that gets assigned to the ufp_exc field. Fixes commit 3aa2df6ec2ca6bc143a65351cca4266d03a8bc41 ("ARM: 8791/1: vfp: use __copy_to_user() when saving VFP state"). Reported-by: David Binderman Signed-off-by: Julien Thierry Signed-off-by: Russell King Signed-off-by: Viresh Kumar --- arch/arm/vfp/vfpmodule.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c index f07567eedd82..f9392fb060ea 100644 --- a/arch/arm/vfp/vfpmodule.c +++ b/arch/arm/vfp/vfpmodule.c @@ -583,7 +583,7 @@ int vfp_preserve_user_clear_hwstate(struct user_vfp *ufp, */ ufp_exc->fpexc = hwstate->fpexc; ufp_exc->fpinst = hwstate->fpinst; - ufp_exc->fpinst2 = ufp_exc->fpinst2; + ufp_exc->fpinst2 = hwstate->fpinst2; /* Ensure that VFP is disabled. */ vfp_flush_hwstate(thread); From patchwork Thu Aug 1 08:16:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 170344 Delivered-To: patch@linaro.org Received: by 2002:a92:512:0:0:0:0:0 with SMTP id q18csp5086895ile; Thu, 1 Aug 2019 01:21:18 -0700 (PDT) X-Google-Smtp-Source: APXvYqylzGtX7xGe/RKo0KwGu+pD5SQ8x+s+hiEGUyVTarQ490LLVflgLHMCwzPnGBSKJ9FkTMkB X-Received: by 2002:a17:90a:bc0c:: with SMTP id w12mr6888728pjr.111.1564647678124; Thu, 01 Aug 2019 01:21:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564647678; cv=none; d=google.com; s=arc-20160816; b=wYj3VAOpWSwCyAAwp2uXaPNuR3FKqHPFjhmICDNb5kKH4XEX0rCJrtZ15A0NGQ2oYp oV5bHriST8g3GaKJ4QZZwISgSq23vh/zBX6c24tmSPxa18d6csUhkrwN9T28F2NYrraQ BuB1P05YNuuO/7tSxNLhbXurAVccySCIkEbU+caVwFvgZcVdGJwaxZZZnXxZ1frixqqD 4W2gbI2CkSAGQsr6hWaPXAnMk6oJkiRkHWMaxHBQkotiihywazxJNRAi5sRqi/CHK4S4 WVhcO9f+9yOLzwvJO1gczS7hcS1Kdc2CUIi23L9li16xvPuwgPxyUIgpqdPUsbJVe0N+ 1PpA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Ds/lGPMr1EeNlwL4g2s5u78S6SjnXx7V9zy6A/rndeo=; b=UHZM7xjmeg9Oh+Ax7QpZvp62w51LwMfiXJzacVCQ4kYnrDO356waG06cIz4qFKTxjm DCc8MluM7Y+PZGI3zM9HxjhJqSbPhNBy8wyqHWWMNup1kBTYvxxbxT+bwoviI5/XBKTF IHvPsmCXO/zvT9FhHu6kaAd+dn1GzSQwFZ3o+MaTYOM1mqRYejPrM/mYA9L61mySwwKB UdTeZCgIY3cvgDokE0Eu5Jekd6iUp+XZiEs5UJzIQ0cwLQO4KFfi0ZkjVDHPnu9pTWjw u8MDcRrtV7+PbSy4GZSgDwoT5myLdjWufY7sC1pdWdNRyIb1XfTMuahbqYksenBXcS1t +NLg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=mrBLXFMW; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Move lookup_processor_type() out of the __init section so it is callable from (eg) the secondary startup code during hotplug. Reviewed-by: Julien Thierry Signed-off-by: Russell King Signed-off-by: Viresh Kumar --- arch/arm/kernel/head-common.S | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm/kernel/head-common.S b/arch/arm/kernel/head-common.S index 8733012d231f..7e662bdd5cb3 100644 --- a/arch/arm/kernel/head-common.S +++ b/arch/arm/kernel/head-common.S @@ -122,6 +122,9 @@ ENDPROC(__mmap_switched) .long init_thread_union + THREAD_START_SP @ sp .size __mmap_switched_data, . - __mmap_switched_data + __FINIT + .text + /* * This provides a C-API version of __lookup_processor_type */ @@ -133,9 +136,6 @@ ENTRY(lookup_processor_type) ldmfd sp!, {r4 - r6, r9, pc} ENDPROC(lookup_processor_type) - __FINIT - .text - /* * Read processor ID register (CP#15, CR0), and look up in the linker-built * supported processor list. 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Split out the lookup of the processor type and associated error handling from the rest of setup_processor() - we will need to use this in the secondary CPU bringup path for big.Little Spectre variant 2 mitigation. Reviewed-by: Julien Thierry Signed-off-by: Russell King Signed-off-by: Viresh Kumar --- arch/arm/include/asm/cputype.h | 1 + arch/arm/kernel/setup.c | 31 +++++++++++++++++++------------ 2 files changed, 20 insertions(+), 12 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h index 76bb3bd060d1..53125dad6edd 100644 --- a/arch/arm/include/asm/cputype.h +++ b/arch/arm/include/asm/cputype.h @@ -93,6 +93,7 @@ #define ARM_CPU_PART_SCORPION 0x510002d0 extern unsigned int processor_id; +struct proc_info_list *lookup_processor(u32 midr); #ifdef CONFIG_CPU_CP15 #define read_cpuid(reg) \ diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index 20edd349d379..5aa9c08de410 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -599,22 +599,29 @@ static void __init smp_build_mpidr_hash(void) } #endif -static void __init setup_processor(void) +/* + * locate processor in the list of supported processor types. The linker + * builds this table for us from the entries in arch/arm/mm/proc-*.S + */ +struct proc_info_list *lookup_processor(u32 midr) { - struct proc_info_list *list; + struct proc_info_list *list = lookup_processor_type(midr); - /* - * locate processor in the list of supported processor - * types. The linker builds this table for us from the - * entries in arch/arm/mm/proc-*.S - */ - list = lookup_processor_type(read_cpuid_id()); if (!list) { - pr_err("CPU configuration botched (ID %08x), unable to continue.\n", - read_cpuid_id()); - while (1); + pr_err("CPU%u: configuration botched (ID %08x), CPU halted\n", + smp_processor_id(), midr); + while (1) + /* can't use cpu_relax() here as it may require MMU setup */; } + return list; +} + +static void __init setup_processor(void) +{ + unsigned int midr = read_cpuid_id(); + struct proc_info_list *list = lookup_processor(midr); + cpu_name = list->cpu_name; __cpu_architecture = __get_cpu_architecture(); @@ -632,7 +639,7 @@ static void __init setup_processor(void) #endif pr_info("CPU: %s [%08x] revision %d (ARMv%s), cr=%08lx\n", - cpu_name, read_cpuid_id(), read_cpuid_id() & 15, + list->cpu_name, midr, midr & 15, proc_arch[cpu_architecture()], get_cr()); snprintf(init_utsname()->machine, __NEW_UTS_LEN + 1, "%s%c", From patchwork Thu Aug 1 08:16:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 170347 Delivered-To: patch@linaro.org Received: by 2002:a92:512:0:0:0:0:0 with SMTP id q18csp5086983ile; Thu, 1 Aug 2019 01:21:22 -0700 (PDT) X-Google-Smtp-Source: APXvYqw2T/P5iiYbnn0C9HCUpj8weoQJ5YUTCzyM9XftgX/RM71rnuRBpnMEe4oTuvSQM/V1XAes X-Received: by 2002:a62:2a4d:: with SMTP id q74mr51958938pfq.86.1564647682638; Thu, 01 Aug 2019 01:21:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564647682; cv=none; d=google.com; s=arc-20160816; b=cKv7Z+u7yc4PrW6RBZxPs491wntxlkvFnt0z2amB1rfFrZ5rlbstDFhym6Y27Tud1L O6X0krBn6U8qch6T+hxw1Fy2WcZxA670hamP7El+mHnqcOHVFqtJG6o/u37VCBDnHj2x te6C1Zd0j0FGHeK97vsWLJRwSzk+V87hse0qOyxCTsaiOTq7eh7xgvDdhICWsSu3O1xM MaGKUl2GZrNJ4rzQ8vbsFdykhG88p5ZIiCDS4XObKSGgzhLOUhOlNpTz4KyWNnXeUcKZ ydNbscTWTK92pg3OH+WDqwJ2g9zHbUUCwBAgvgom8S8te7PmptHgvLGFABRkmsNYF7Um t5mw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=gEzBHKM5Yrnew5IgDE9VhKRrkovpTReWWDnzndMpTpo=; b=hUuNje/v9hEcjb/I1XKzwhVvn44gNjGwAxQuUxOf39EMBmRkwcFhOGa7d0JvmWAbU0 Sn+nT3GTriIGSvkKT/WZo4ioCXDTdAB6/4FOodv2oF+rMfxmA/MSn7+vIBgkvOs04txN gne9ZDPdG96nG8f1HYn6sDicFcJZ2OK06BLotqKGKU823ou/K9R1G5mp84dBwQpWMVFl L8+Xi7boNl25NRL0zT9kCRh+TaHQXBbzgKblrGHhiXlpnnA2Yj/iK4/YpkmoYXjQ2y0i UTigaCqoTqhH4YRbR8ve8Hw+r52DKW9lPx5jf2XFXt3COTEFU2XT1q92Wl5DNrNedk2Q EsRg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UN9wbT1c; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Call the per-processor type check_bugs() method in the same way as we do other per-processor functions - move the "processor." detail into proc-fns.h. Reviewed-by: Julien Thierry Signed-off-by: Russell King Signed-off-by: Viresh Kumar --- arch/arm/include/asm/proc-fns.h | 1 + arch/arm/kernel/bugs.c | 4 ++-- 2 files changed, 3 insertions(+), 2 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm/include/asm/proc-fns.h b/arch/arm/include/asm/proc-fns.h index f379f5f849a9..19939e88efca 100644 --- a/arch/arm/include/asm/proc-fns.h +++ b/arch/arm/include/asm/proc-fns.h @@ -99,6 +99,7 @@ extern void cpu_do_suspend(void *); extern void cpu_do_resume(void *); #else #define cpu_proc_init processor._proc_init +#define cpu_check_bugs processor.check_bugs #define cpu_proc_fin processor._proc_fin #define cpu_reset processor.reset #define cpu_do_idle processor._do_idle diff --git a/arch/arm/kernel/bugs.c b/arch/arm/kernel/bugs.c index 7be511310191..d41d3598e5e5 100644 --- a/arch/arm/kernel/bugs.c +++ b/arch/arm/kernel/bugs.c @@ -6,8 +6,8 @@ void check_other_bugs(void) { #ifdef MULTI_CPU - if (processor.check_bugs) - processor.check_bugs(); + if (cpu_check_bugs) + cpu_check_bugs(); #endif } From patchwork Thu Aug 1 08:16:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 170348 Delivered-To: patch@linaro.org Received: by 2002:a92:512:0:0:0:0:0 with SMTP id q18csp5087029ile; Thu, 1 Aug 2019 01:21:25 -0700 (PDT) X-Google-Smtp-Source: APXvYqzR1y7fOg4ODjuu/kD5GtiGPBv5toA30zHe6Ysb24pCIMqU+uefLKswlaVQQGeiOb5KmVtH X-Received: by 2002:a17:90a:2305:: with SMTP id f5mr7609980pje.128.1564647685811; Thu, 01 Aug 2019 01:21:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564647685; cv=none; d=google.com; s=arc-20160816; b=z57HsUN0XORCv3vhDZdnWUu9HyNTmgBfJBEPFHOji9S/xOgrYcNZSo2Skmg+fJCi58 DIaNFKLUHV1gFyltVGPLdxpIiwt1iDmzQM4Kai+jiguzgQof8poTXwvCZwTo8DHigr/6 RucW4vmRS6zxFRGPPRTIqmXZYdYKHP0QTYg50a7MZgXhKJdsGP6VNCWIE2Q7ZGlPLFSK hLT/QyGLcYdxaEgArwYtDzrn0M543iaXZOjsEoYofBEaEQ+0c0v22Qb7ltHdDnjwkUEx gEa/gowB4ACxlrEG3hmgJnBpiKhGyENTfw7prEKyRR+VB1AIJlmR9UV7OxFc5thI8/rk +rbA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=bD+Nn9yJj6UL1BxkfmyNVyFE/Bkgh8dLgfivcvvulBg=; b=cVsOFkj8dvJ2TlRmarZeI6EH7EuxFrEQOdf7vvcHpRXIB85qm4cXszh6DwJpOcWudG eMPfzQ2bUSpnMKl0AK5T6+wRXyYXMtkZVmAn3jadDRdpNS8jvnAWgFleCpYXHZv4Q7CZ /+eyvArSzl5XRmwn8sajr/U7BVhqxzNNtAzK+3LBIEs+rvTbPMAoJEH4i9zPVR3sSqAb PNZmhsR5YAaN/Ok4/5KPR/hT2bWw5QAWiVNwpgSlKCdSMuvTt5z4xcK6DDcHvrVmclYc izp4vlH/kVC5efyIJtsE4HKypBqofLKtr1LqXmu6Vf2HZ/G97mCrO+5ep+V91tux46f+ yvjA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ANFP8g1p; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id z13si4013236pgj.476.2019.08.01.01.21.25; Thu, 01 Aug 2019 01:21:25 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ANFP8g1p; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729116AbfHAIVZ (ORCPT + 14 others); Thu, 1 Aug 2019 04:21:25 -0400 Received: from mail-pf1-f194.google.com ([209.85.210.194]:39225 "EHLO mail-pf1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727460AbfHAIVZ (ORCPT ); Thu, 1 Aug 2019 04:21:25 -0400 Received: by mail-pf1-f194.google.com with SMTP id f17so29615011pfn.6 for ; Thu, 01 Aug 2019 01:21:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bD+Nn9yJj6UL1BxkfmyNVyFE/Bkgh8dLgfivcvvulBg=; b=ANFP8g1p8JFQVKTJYFx6Vw0TW4voibG5DCIASdhkve+IYqSbpJ4pf1CPI/gRJ9yt9S Exd2NJ/005eJrvN/yD3fqP0TfCskg40yqFmckXx7hep+VMMYb4kaUeqZgNxjwXXFeGLC O3Ushag+gGUFO2uvKX4/gXf4FklbrwOHxejkTxQhoge9Yh0YBa9qCcs7TDt/NyGFFi4o gTbulqNmF52VLHNlryHUkhlrggT41FV0BmdZM6Tsypos2QcAO39GpCKgBwmqbDroqaal K618LSh+GSZQjXSoXrvv+ILwOFzCzenhlRDr2gjgi3/ik+gpk9I1T9beafOOAiHqpqDx BioQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bD+Nn9yJj6UL1BxkfmyNVyFE/Bkgh8dLgfivcvvulBg=; b=WCvFRpGo0TSF2za8ocOPPaBKwwIedsgZcEg2JX/ysQNXtquhoXQNi7r2mlsTW43dKY Y9AVvKIWL3HfuKfFjGyxKnHj6lnl92uhmflTs/m+WXVsVQ24Xao1Lsm0rIzE/PYSMgHi ZSb2JJ04L7+nd4BIbbZicixZgLinmjwxZgLPTpBv9fhyUyGgBYA72RqhJS2KcLoYilA+ ZQ6WF+M7alEqj39yOMkjCxeOtBMDFx0Oh30b2o+rusgpSQVnkHHy36Bkn/QtQiGwIehf K8YrNEDxovUWLL8DNAournZicMXtWaywExPRFCNodpG4xQsKmQZe4FNtEc1GNspmyb9L ExlA== X-Gm-Message-State: APjAAAUVaLtCi0Y1LSYgBXeCjdL4jJQd33iPKe5N8CHTy4gUicJNZErS GnGN4eWsajRYXJekOcmjZGZ4eyvEDFs= X-Received: by 2002:a63:e20a:: with SMTP id q10mr115552737pgh.24.1564647683731; Thu, 01 Aug 2019 01:21:23 -0700 (PDT) Received: from localhost ([122.172.28.117]) by smtp.gmail.com with ESMTPSA id p13sm6487461pjb.30.2019.08.01.01.21.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 01 Aug 2019 01:21:23 -0700 (PDT) From: Viresh Kumar To: stable@vger.kernel.org Cc: Viresh Kumar , Julien Thierry , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Marc Zyngier , Mark Rutland , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com, guohanjun@huawei.com Subject: [PATCH ARM32 v4.4 V2 42/47] ARM: add PROC_VTABLE and PROC_TABLE macros Date: Thu, 1 Aug 2019 13:46:26 +0530 Message-Id: <888892dc104d817f590058687946b7f6078d328c.1564646727.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Russell King Commit e209950fdd065d2cc46e6338e47e52841b830cba upstream. Allow the way we access members of the processor vtable to be changed at compile time. We will need to move to per-CPU vtables to fix the Spectre variant 2 issues on big.Little systems. However, we have a couple of calls that do not need the vtable treatment, and indeed cause a kernel warning due to the (later) use of smp_processor_id(), so also introduce the PROC_TABLE macro for these which always use CPU 0's function pointers. Reviewed-by: Julien Thierry Signed-off-by: Russell King Signed-off-by: Viresh Kumar --- arch/arm/include/asm/proc-fns.h | 39 ++++++++++++++++++++++----------- arch/arm/kernel/setup.c | 4 +--- 2 files changed, 27 insertions(+), 16 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm/include/asm/proc-fns.h b/arch/arm/include/asm/proc-fns.h index 19939e88efca..a1a71b068edc 100644 --- a/arch/arm/include/asm/proc-fns.h +++ b/arch/arm/include/asm/proc-fns.h @@ -23,7 +23,7 @@ struct mm_struct; /* * Don't change this structure - ASM code relies on it. */ -extern struct processor { +struct processor { /* MISC * get data abort address/flags */ @@ -79,9 +79,13 @@ extern struct processor { unsigned int suspend_size; void (*do_suspend)(void *); void (*do_resume)(void *); -} processor; +}; #ifndef MULTI_CPU +static inline void init_proc_vtable(const struct processor *p) +{ +} + extern void cpu_proc_init(void); extern void cpu_proc_fin(void); extern int cpu_do_idle(void); @@ -98,18 +102,27 @@ extern void cpu_reset(unsigned long addr) __attribute__((noreturn)); extern void cpu_do_suspend(void *); extern void cpu_do_resume(void *); #else -#define cpu_proc_init processor._proc_init -#define cpu_check_bugs processor.check_bugs -#define cpu_proc_fin processor._proc_fin -#define cpu_reset processor.reset -#define cpu_do_idle processor._do_idle -#define cpu_dcache_clean_area processor.dcache_clean_area -#define cpu_set_pte_ext processor.set_pte_ext -#define cpu_do_switch_mm processor.switch_mm -/* These three are private to arch/arm/kernel/suspend.c */ -#define cpu_do_suspend processor.do_suspend -#define cpu_do_resume processor.do_resume +extern struct processor processor; +#define PROC_VTABLE(f) processor.f +#define PROC_TABLE(f) processor.f +static inline void init_proc_vtable(const struct processor *p) +{ + processor = *p; +} + +#define cpu_proc_init PROC_VTABLE(_proc_init) +#define cpu_check_bugs PROC_VTABLE(check_bugs) +#define cpu_proc_fin PROC_VTABLE(_proc_fin) +#define cpu_reset PROC_VTABLE(reset) +#define cpu_do_idle PROC_VTABLE(_do_idle) +#define cpu_dcache_clean_area PROC_TABLE(dcache_clean_area) +#define cpu_set_pte_ext PROC_TABLE(set_pte_ext) +#define cpu_do_switch_mm PROC_VTABLE(switch_mm) + +/* These two are private to arch/arm/kernel/suspend.c */ +#define cpu_do_suspend PROC_VTABLE(do_suspend) +#define cpu_do_resume PROC_VTABLE(do_resume) #endif extern void cpu_resume(void); diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index 5aa9c08de410..13bda9574e18 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -625,9 +625,7 @@ static void __init setup_processor(void) cpu_name = list->cpu_name; __cpu_architecture = __get_cpu_architecture(); -#ifdef MULTI_CPU - processor = *list->proc; -#endif + init_proc_vtable(list->proc); #ifdef MULTI_TLB cpu_tlb = *list->tlb; #endif From patchwork Thu Aug 1 08:16:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 170349 Delivered-To: patch@linaro.org Received: by 2002:a92:512:0:0:0:0:0 with SMTP id q18csp5087072ile; Thu, 1 Aug 2019 01:21:28 -0700 (PDT) X-Google-Smtp-Source: APXvYqxOTmBjYjOQ/RXWxn/Ugwu4+NZd6jkngHOhW26ExwJlkoKZJ6uwn9HphRup9L42FUauPsiI X-Received: by 2002:a65:6415:: with SMTP id a21mr103210503pgv.98.1564647688184; Thu, 01 Aug 2019 01:21:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564647688; cv=none; d=google.com; s=arc-20160816; b=zDQ3l2Yhcx2H5G5SytM16shYhJG+sO8TB8O6Tu//69z13umJxOy+6UCpnjTWLEiR0G KSIqMWekE2GTX4qEagDCx1FGdq+kd6YrzMHOgjbtugsWMBvzlC7rj1V0XjbIhdL8sRaO DqYm6CmErx+dS6ehrzt3GRzKe/yDSTdV0FKYnc6j5kmGCr9lCnR3Wx9SehuJdiU35CLk 3ajF0BuRz5qZH30m+9fvk/jqvBv6VOXbfShBSjlAaB6QWxT7+NOjj/CSSqIKJZl0HlHz C3W5hZ1p6u5KE7dJ9MMkybfAg5nQ/3yA0OrUqLtvJy5o11/oJR8ZiynbD1vu3fdEsOxN 1/3Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=q2P7nbVondTzzEiUufavLpCtXHz6lnekor7t8KaG36c=; b=fXo5RFWSjA9GFaEQfofF7CkgwAmYhb7gYR4VnYviuY/CUd4fsfVP1DgjFBqk29erft d8piHpDVmFoo6sQ2Y53NswrEpehQBO2ZZjCIvcCg5gdshSo9HJiO5znZly19Bp/EVRgQ qflAgbAibkRyeNDn3DT7cqvAeJNw1ZWHQo0xaGLpnY48NX+nIeH/6DVXv/MewdDemlzW leFnhpKtciN27MNJ0Yf3sIbu8AtJyHr1ewCIBgHZTSn5hPCEk72Vjr/dGNA2N6Ab+fmy I7A8ZzzU13xc0OBjYF3ZxY7YWP2apeQffEJQQMeA/oqVMT6EkoHohX8bngY5NcXkSCQH zkDw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pTRCSsFi; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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One of the easiest ways to protect the kernel from attack is to reduce the internal attack surface exposed when a "write" flaw is available. By making as much of the kernel read-only as possible, we reduce the attack surface. Many things are written to only during __init, and never changed again. These cannot be made "const" since the compiler will do the wrong thing (we do actually need to write to them). Instead, move these items into a memory region that will be made read-only during mark_rodata_ro() which happens after all kernel __init code has finished. This introduces __ro_after_init as a way to mark such memory, and adds some documentation about the existing __read_mostly marking. This improves the security of the Linux kernel by marking formerly read-write memory regions as read-only on a fully booted up system. Based on work by PaX Team and Brad Spengler. Signed-off-by: Kees Cook Cc: Andy Lutomirski Cc: Arnd Bergmann Cc: Borislav Petkov Cc: Brad Spengler Cc: Brian Gerst Cc: David Brown Cc: Denys Vlasenko Cc: Emese Revfy Cc: H. Peter Anvin Cc: Linus Torvalds Cc: Mathias Krause Cc: Michael Ellerman Cc: PaX Team Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: kernel-hardening@lists.openwall.com Cc: linux-arch Link: http://lkml.kernel.org/r/1455748879-21872-5-git-send-email-keescook@chromium.org Signed-off-by: Ingo Molnar Signed-off-by: Viresh Kumar --- arch/parisc/include/asm/cache.h | 3 +++ include/asm-generic/vmlinux.lds.h | 1 + include/linux/cache.h | 14 ++++++++++++++ 3 files changed, 18 insertions(+) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/parisc/include/asm/cache.h b/arch/parisc/include/asm/cache.h index 3d0e17bcc8e9..df0f52bd18b4 100644 --- a/arch/parisc/include/asm/cache.h +++ b/arch/parisc/include/asm/cache.h @@ -22,6 +22,9 @@ #define __read_mostly __attribute__((__section__(".data..read_mostly"))) +/* Read-only memory is marked before mark_rodata_ro() is called. */ +#define __ro_after_init __read_mostly + void parisc_cache_init(void); /* initializes cache-flushing */ void disable_sr_hashing_asm(int); /* low level support for above */ void disable_sr_hashing(void); /* turns off space register hashing */ diff --git a/include/asm-generic/vmlinux.lds.h b/include/asm-generic/vmlinux.lds.h index a461b6604fd9..c63f92150eda 100644 --- a/include/asm-generic/vmlinux.lds.h +++ b/include/asm-generic/vmlinux.lds.h @@ -256,6 +256,7 @@ .rodata : AT(ADDR(.rodata) - LOAD_OFFSET) { \ VMLINUX_SYMBOL(__start_rodata) = .; \ *(.rodata) *(.rodata.*) \ + *(.data..ro_after_init) /* Read only after init */ \ *(__vermagic) /* Kernel version magic */ \ . = ALIGN(8); \ VMLINUX_SYMBOL(__start___tracepoints_ptrs) = .; \ diff --git a/include/linux/cache.h b/include/linux/cache.h index 17e7e82d2aa7..1be04f8c563a 100644 --- a/include/linux/cache.h +++ b/include/linux/cache.h @@ -12,10 +12,24 @@ #define SMP_CACHE_BYTES L1_CACHE_BYTES #endif +/* + * __read_mostly is used to keep rarely changing variables out of frequently + * updated cachelines. If an architecture doesn't support it, ignore the + * hint. + */ #ifndef __read_mostly #define __read_mostly #endif +/* + * __ro_after_init is used to mark things that are read-only after init (i.e. + * after mark_rodata_ro() has been called). These are effectively read-only, + * but may get written to during init, so can't live in .rodata (via "const"). + */ +#ifndef __ro_after_init +#define __ro_after_init __attribute__((__section__(".data..ro_after_init"))) +#endif + #ifndef ____cacheline_aligned #define ____cacheline_aligned __attribute__((__aligned__(SMP_CACHE_BYTES))) #endif From patchwork Thu Aug 1 08:16:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 170350 Delivered-To: patch@linaro.org Received: by 2002:a92:512:0:0:0:0:0 with SMTP id q18csp5087129ile; Thu, 1 Aug 2019 01:21:30 -0700 (PDT) X-Google-Smtp-Source: APXvYqxtJ6O1BINQ/0PJ+KT6ZtXAAokQ1EBlSrhDXkFZu9UjWSeU92MIIh4MHZG3r6F3Pz3SSoDg X-Received: by 2002:a63:69c1:: with SMTP id e184mr113357357pgc.198.1564647690593; Thu, 01 Aug 2019 01:21:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564647690; cv=none; d=google.com; s=arc-20160816; b=e+Fp3vS+UXZgs1QHKyFQYXr2SJB7YNZZtfH1xvEDdKwNMwR3Wbd4cVi6d0FHVqT/OI 6k1eIrozj8R1mvbtFKzO5IayMmzyoAf3GyLKcgeeHoYJABB+9ryp9xkhg9H2+kvo8Qns Cny/URuUXGmHRemPo+pMB/dcRLTG+uWarku/sA+ZLbCWb8wDnoLIWhtYLV1R3rOs7A5l pHBur/NVy+VNwZvWSDnF6t6YKcrpnUgr4lnq0mNiG2vVT6ataW2jubryXW43O8ZJzwbA yF2gyXOgPqYOVe960gG0n/d4ZQkUxB7f4KZPvdD3imQMb1aYwpXmD7wWTn/iaz6VRS/G WcuA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=OQQ7xLa0wSJEVHtnIJUBQOen48CMIup3yNRZI8hCHQM=; b=EgV5k/ZAQU9K0+Bcj70hc7v2WIsAvftffdSWsaR7bMvj58DvFR/s+AjaN1tbeUTTgP FBA4Bw2F07Fpu9t9mrB1hdIbVBURv5GTNs4X3q5oas9jOad5BPFS2a0ThrSJardToUoj rW6EyUb5Ug/CLEHud+65NUlJfx8AIo4ADn4uKN2xdIujuiDw0lveERVGxxW1olJfS8E+ ZDPNckpyq2M3DUAQjp0XqPnuUq13cDj1BAi/9hZZtOWOzf1x77cEhiuHfazxf0Nabv3O zsvGMHfD25EtwNVlzRrwtARwllOoikfdMIttWCW6emnD7O3P5TlgCGTwn1rHlZdTQEy4 75bg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=oUYvAhHh; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Guided by grsecurity's analogous __read_only markings in arch/arm, this applies several uses of __ro_after_init to structures that are only updated during __init. Signed-off-by: Kees Cook Signed-off-by: Russell King Signed-off-by: Viresh Kumar --- arch/arm/kernel/cpuidle.c | 2 +- arch/arm/kernel/setup.c | 10 +++++----- arch/arm/kernel/smp.c | 2 +- arch/arm/lib/delay.c | 2 +- arch/arm/mm/mmu.c | 2 +- 5 files changed, 9 insertions(+), 9 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm/kernel/cpuidle.c b/arch/arm/kernel/cpuidle.c index 318da33465f4..68be7d89141d 100644 --- a/arch/arm/kernel/cpuidle.c +++ b/arch/arm/kernel/cpuidle.c @@ -19,7 +19,7 @@ extern struct of_cpuidle_method __cpuidle_method_of_table[]; static const struct of_cpuidle_method __cpuidle_method_of_table_sentinel __used __section(__cpuidle_method_of_table_end); -static struct cpuidle_ops cpuidle_ops[NR_CPUS]; +static struct cpuidle_ops cpuidle_ops[NR_CPUS] __ro_after_init; /** * arm_cpuidle_simple_enter() - a wrapper to cpu_do_idle() diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index 13bda9574e18..8081f88bf636 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -112,19 +112,19 @@ EXPORT_SYMBOL(elf_hwcap2); #ifdef MULTI_CPU -struct processor processor __read_mostly; +struct processor processor __ro_after_init; #endif #ifdef MULTI_TLB -struct cpu_tlb_fns cpu_tlb __read_mostly; +struct cpu_tlb_fns cpu_tlb __ro_after_init; #endif #ifdef MULTI_USER -struct cpu_user_fns cpu_user __read_mostly; +struct cpu_user_fns cpu_user __ro_after_init; #endif #ifdef MULTI_CACHE -struct cpu_cache_fns cpu_cache __read_mostly; +struct cpu_cache_fns cpu_cache __ro_after_init; #endif #ifdef CONFIG_OUTER_CACHE -struct outer_cache_fns outer_cache __read_mostly; +struct outer_cache_fns outer_cache __ro_after_init; EXPORT_SYMBOL(outer_cache); #endif diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c index bafbd29c6e64..c92abf791aed 100644 --- a/arch/arm/kernel/smp.c +++ b/arch/arm/kernel/smp.c @@ -79,7 +79,7 @@ enum ipi_msg_type { static DECLARE_COMPLETION(cpu_running); -static struct smp_operations smp_ops; +static struct smp_operations smp_ops __ro_after_init; void __init smp_set_ops(const struct smp_operations *ops) { diff --git a/arch/arm/lib/delay.c b/arch/arm/lib/delay.c index 8044591dca72..2cef11884857 100644 --- a/arch/arm/lib/delay.c +++ b/arch/arm/lib/delay.c @@ -29,7 +29,7 @@ /* * Default to the loop-based delay implementation. */ -struct arm_delay_ops arm_delay_ops = { +struct arm_delay_ops arm_delay_ops __ro_after_init = { .delay = __loop_delay, .const_udelay = __loop_const_udelay, .udelay = __loop_udelay, diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c index aead23f15213..36f8c033714f 100644 --- a/arch/arm/mm/mmu.c +++ b/arch/arm/mm/mmu.c @@ -243,7 +243,7 @@ __setup("noalign", noalign_setup); #define PROT_PTE_S2_DEVICE PROT_PTE_DEVICE #define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE -static struct mem_type mem_types[] = { +static struct mem_type mem_types[] __ro_after_init = { [MT_DEVICE] = { /* Strongly ordered / ARMv6 shared device */ .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED | L_PTE_SHARED, From patchwork Thu Aug 1 08:16:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 170351 Delivered-To: patch@linaro.org Received: by 2002:a92:512:0:0:0:0:0 with SMTP id q18csp5087175ile; Thu, 1 Aug 2019 01:21:33 -0700 (PDT) X-Google-Smtp-Source: APXvYqxb9Ysi8+PtKwdydFe+/lHbyI0DruX3IWPgQu0Gk+z53Hex6yy9HzftAgYg48lB2SYhbmg9 X-Received: by 2002:a17:90a:8985:: with SMTP id v5mr7130892pjn.136.1564647693634; Thu, 01 Aug 2019 01:21:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564647693; cv=none; d=google.com; s=arc-20160816; b=kUdK6KNzX7yWtksWhcaEeMuQky7/4ngqZ6mx+dOyeIPA2m6n19TVDTFp7l4T5nzfin Ynkmg8rTjP0vUFj53Q3w2916sY/HbU60XejwUBIUk3meXlWXDV9S/ta3ZLFfkCv1+xxg KwP4y/PU2ElLYh2XUJ+kFLbVBzasdbkSr/yVzEgMQBWAzxEEcNIlLLsVT/55SzXJ2suZ SA0JWdgG7KFOvqqOMCOYdyWikqWk+XxsoR5VNwlVtlgDZw2UU+Q5NfSGUBnlwkkX+731 ra0Yq2YHdUC+w+jrXRt3zdkY3Tgo3bZ2x4DJWTOY1KsqxWU4GQcRvDn6lfuyDQ645BMu uVjw== ARC-Message-Signature: i=1; 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In big.Little systems, some CPUs require the Spectre workarounds in paths such as the context switch, but other CPUs do not. In order to handle these differences, we need per-CPU vtables. We are unable to use the kernel's per-CPU variables to support this as per-CPU is not initialised at times when we need access to the vtables, so we have to use an array indexed by logical CPU number. We use an array-of-pointers to avoid having function pointers in the kernel's read/write .data section. Note: Added include of linux/slab.h in arch/arm/smp.c. Reviewed-by: Julien Thierry Signed-off-by: Russell King Signed-off-by: Viresh Kumar --- arch/arm/include/asm/proc-fns.h | 23 +++++++++++++++++++++++ arch/arm/kernel/setup.c | 5 +++++ arch/arm/kernel/smp.c | 32 ++++++++++++++++++++++++++++++++ arch/arm/mm/proc-v7-bugs.c | 17 ++--------------- 4 files changed, 62 insertions(+), 15 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm/include/asm/proc-fns.h b/arch/arm/include/asm/proc-fns.h index a1a71b068edc..1bfcc3bcfc6d 100644 --- a/arch/arm/include/asm/proc-fns.h +++ b/arch/arm/include/asm/proc-fns.h @@ -104,12 +104,35 @@ extern void cpu_do_resume(void *); #else extern struct processor processor; +#if defined(CONFIG_BIG_LITTLE) && defined(CONFIG_HARDEN_BRANCH_PREDICTOR) +#include +/* + * This can't be a per-cpu variable because we need to access it before + * per-cpu has been initialised. We have a couple of functions that are + * called in a pre-emptible context, and so can't use smp_processor_id() + * there, hence PROC_TABLE(). We insist in init_proc_vtable() that the + * function pointers for these are identical across all CPUs. + */ +extern struct processor *cpu_vtable[]; +#define PROC_VTABLE(f) cpu_vtable[smp_processor_id()]->f +#define PROC_TABLE(f) cpu_vtable[0]->f +static inline void init_proc_vtable(const struct processor *p) +{ + unsigned int cpu = smp_processor_id(); + *cpu_vtable[cpu] = *p; + WARN_ON_ONCE(cpu_vtable[cpu]->dcache_clean_area != + cpu_vtable[0]->dcache_clean_area); + WARN_ON_ONCE(cpu_vtable[cpu]->set_pte_ext != + cpu_vtable[0]->set_pte_ext); +} +#else #define PROC_VTABLE(f) processor.f #define PROC_TABLE(f) processor.f static inline void init_proc_vtable(const struct processor *p) { processor = *p; } +#endif #define cpu_proc_init PROC_VTABLE(_proc_init) #define cpu_check_bugs PROC_VTABLE(check_bugs) diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index 8081f88bf636..f2833d7c5378 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -113,6 +113,11 @@ EXPORT_SYMBOL(elf_hwcap2); #ifdef MULTI_CPU struct processor processor __ro_after_init; +#if defined(CONFIG_BIG_LITTLE) && defined(CONFIG_HARDEN_BRANCH_PREDICTOR) +struct processor *cpu_vtable[NR_CPUS] = { + [0] = &processor, +}; +#endif #endif #ifdef MULTI_TLB struct cpu_tlb_fns cpu_tlb __ro_after_init; diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c index c92abf791aed..03c11e021962 100644 --- a/arch/arm/kernel/smp.c +++ b/arch/arm/kernel/smp.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include @@ -40,6 +41,7 @@ #include #include #include +#include #include #include #include @@ -96,6 +98,30 @@ static unsigned long get_arch_pgd(pgd_t *pgd) #endif } +#if defined(CONFIG_BIG_LITTLE) && defined(CONFIG_HARDEN_BRANCH_PREDICTOR) +static int secondary_biglittle_prepare(unsigned int cpu) +{ + if (!cpu_vtable[cpu]) + cpu_vtable[cpu] = kzalloc(sizeof(*cpu_vtable[cpu]), GFP_KERNEL); + + return cpu_vtable[cpu] ? 0 : -ENOMEM; +} + +static void secondary_biglittle_init(void) +{ + init_proc_vtable(lookup_processor(read_cpuid_id())->proc); +} +#else +static int secondary_biglittle_prepare(unsigned int cpu) +{ + return 0; +} + +static void secondary_biglittle_init(void) +{ +} +#endif + int __cpu_up(unsigned int cpu, struct task_struct *idle) { int ret; @@ -103,6 +129,10 @@ int __cpu_up(unsigned int cpu, struct task_struct *idle) if (!smp_ops.smp_boot_secondary) return -ENOSYS; + ret = secondary_biglittle_prepare(cpu); + if (ret) + return ret; + /* * We need to tell the secondary core where to find * its stack and the page tables. @@ -354,6 +384,8 @@ asmlinkage void secondary_start_kernel(void) struct mm_struct *mm = &init_mm; unsigned int cpu; + secondary_biglittle_init(); + /* * The identity mapping is uncached (strongly ordered), so * switch away from it before attempting any exclusive accesses. diff --git a/arch/arm/mm/proc-v7-bugs.c b/arch/arm/mm/proc-v7-bugs.c index 5544b82a2e7a..9a07916af8dd 100644 --- a/arch/arm/mm/proc-v7-bugs.c +++ b/arch/arm/mm/proc-v7-bugs.c @@ -52,8 +52,6 @@ static void cpu_v7_spectre_init(void) case ARM_CPU_PART_CORTEX_A17: case ARM_CPU_PART_CORTEX_A73: case ARM_CPU_PART_CORTEX_A75: - if (processor.switch_mm != cpu_v7_bpiall_switch_mm) - goto bl_error; per_cpu(harden_branch_predictor_fn, cpu) = harden_branch_predictor_bpiall; spectre_v2_method = "BPIALL"; @@ -61,8 +59,6 @@ static void cpu_v7_spectre_init(void) case ARM_CPU_PART_CORTEX_A15: case ARM_CPU_PART_BRAHMA_B15: - if (processor.switch_mm != cpu_v7_iciallu_switch_mm) - goto bl_error; per_cpu(harden_branch_predictor_fn, cpu) = harden_branch_predictor_iciallu; spectre_v2_method = "ICIALLU"; @@ -88,11 +84,9 @@ static void cpu_v7_spectre_init(void) ARM_SMCCC_ARCH_WORKAROUND_1, &res); if ((int)res.a0 != 0) break; - if (processor.switch_mm != cpu_v7_hvc_switch_mm && cpu) - goto bl_error; per_cpu(harden_branch_predictor_fn, cpu) = call_hvc_arch_workaround_1; - processor.switch_mm = cpu_v7_hvc_switch_mm; + cpu_do_switch_mm = cpu_v7_hvc_switch_mm; spectre_v2_method = "hypervisor"; break; @@ -101,11 +95,9 @@ static void cpu_v7_spectre_init(void) ARM_SMCCC_ARCH_WORKAROUND_1, &res); if ((int)res.a0 != 0) break; - if (processor.switch_mm != cpu_v7_smc_switch_mm && cpu) - goto bl_error; per_cpu(harden_branch_predictor_fn, cpu) = call_smc_arch_workaround_1; - processor.switch_mm = cpu_v7_smc_switch_mm; + cpu_do_switch_mm = cpu_v7_smc_switch_mm; spectre_v2_method = "firmware"; break; @@ -119,11 +111,6 @@ static void cpu_v7_spectre_init(void) if (spectre_v2_method) pr_info("CPU%u: Spectre v2: using %s workaround\n", smp_processor_id(), spectre_v2_method); - return; - -bl_error: - pr_err("CPU%u: Spectre v2: incorrect context switching function, system vulnerable\n", - cpu); } #else static void cpu_v7_spectre_init(void) From patchwork Thu Aug 1 08:16:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 170352 Delivered-To: patch@linaro.org Received: by 2002:a92:512:0:0:0:0:0 with SMTP id q18csp5087274ile; Thu, 1 Aug 2019 01:21:38 -0700 (PDT) X-Google-Smtp-Source: APXvYqwldQWHr9dDQgrY+tcnr7bi5ZbFZ8jO4IBVp9bgFDjQ5Prsjp5y/I+AEjIIVK8baBLBVaEE X-Received: by 2002:a62:2784:: with SMTP id n126mr52774808pfn.61.1564647698671; Thu, 01 Aug 2019 01:21:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564647698; cv=none; d=google.com; s=arc-20160816; b=UMO+7kY7NQ270zGlh19h6vhtShIjNSLMvsRaE9syuzAWa84NeUqNLkOGAD0jpy+UoH 3jADipD8A9UbvqD3gsK9q+FCMqLhtbKKlkfa80+RxTbWRFG0VVJTMrvfq8DT0BGBQI8M YEwMxHQOZ5ff/EYuxsY1WRmShcm6W/ClmpoYNM7ohjtKldUo4qRWMBgizWIQ/dhIhSan l7JpQ7kJG7Ay9Z3drbtYT1ilrwCgT2y7xHaM6Vbm7HLKunQMs2OFL5h0Vmnbx+dHSQGz oaQG3ysrjvDGaKctWC93NQHV09Q2SYm5Lpp163Ug2T10NGy/jOZ02Y2j/9SZGT/OnXLn z3/A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=VcM2nk9n3X98Yf/dvDVr4bULZaEs8I54Pvp1eUOtnUY=; b=DkB2vboCbAfCK0upRTqwsxgyOo+sdO2lv5AlegK6EwlTJJKYaLMfAE5ZfyZG2N7buh 4e7bzCzRCvr6FvCecSZhke9aXMlY1mQaj3LzIIdlKelfFVHe9s3QYN9dUQVUzj88s/b6 MympeomLk+3DjZ/UKQdMLIeXR00OIPuXKjZXe3DZlVYI66IfOt38QueRrAIqiaZ80Rul eTfi3ARdUIg1OCExIpa8Qwomx7izn9QO42n+GGDSktrLSvyfTcakK+AlcFRxXemMu/DW Nxx3gPc4jNNSeJuHWD6pWqBTcJ65j6tupRXozvtF+L8bpS/2nh7pPvvckZ75BA0epOqV g5Jw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="wgago/zp"; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Marek Szyprowski reported problems with CPU hotplug in current kernels. This was tracked down to the processor vtables being located in an init section, and therefore discarded after kernel boot, despite being required after boot to properly initialise the non-boot CPUs. Arrange for these tables to end up in .rodata when required. Reported-by: Marek Szyprowski Tested-by: Krzysztof Kozlowski Fixes: 383fb3ee8024 ("ARM: spectre-v2: per-CPU vtables to work around big.Little systems") Signed-off-by: Russell King Signed-off-by: Viresh Kumar --- arch/arm/mm/proc-macros.S | 10 ++++++++++ 1 file changed, 10 insertions(+) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S index 212147c78f4b..d36a283b4099 100644 --- a/arch/arm/mm/proc-macros.S +++ b/arch/arm/mm/proc-macros.S @@ -259,6 +259,13 @@ .endm .macro define_processor_functions name:req, dabort:req, pabort:req, nommu=0, suspend=0, bugs=0 +/* + * If we are building for big.Little with branch predictor hardening, + * we need the processor function tables to remain available after boot. + */ +#if 1 // defined(CONFIG_BIG_LITTLE) && defined(CONFIG_HARDEN_BRANCH_PREDICTOR) + .section ".rodata" +#endif .type \name\()_processor_functions, #object .align 2 ENTRY(\name\()_processor_functions) @@ -294,6 +301,9 @@ ENTRY(\name\()_processor_functions) .endif .size \name\()_processor_functions, . - \name\()_processor_functions +#if 1 // defined(CONFIG_BIG_LITTLE) && defined(CONFIG_HARDEN_BRANCH_PREDICTOR) + .previous +#endif .endm .macro define_cache_functions name:req From patchwork Thu Aug 1 08:16:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 170353 Delivered-To: patch@linaro.org Received: by 2002:a92:512:0:0:0:0:0 with SMTP id q18csp5087285ile; Thu, 1 Aug 2019 01:21:39 -0700 (PDT) X-Google-Smtp-Source: APXvYqz+AsGp0TRVAPZy5Xd2thCSzVWg1OIxe+om3abQkW7LmirXnXqcR/gxu1zvLb/E0oXOd3RV X-Received: by 2002:a65:4507:: with SMTP id n7mr10080573pgq.86.1564647698995; Thu, 01 Aug 2019 01:21:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564647698; cv=none; d=google.com; s=arc-20160816; b=TP4g8SGtURsYahYWetP7vnfYyFwU/18C5W3qVCzv31NFM0HOwo/L2mAU0YKwxKwOuR L+2VxGIgegyVFvP0CEtM5UoYoxZ29QSR1ty8pYwAcEjvsSLE0tL7+QISBBl1F7hoew3r Oqqagb11lG/NU6Cy1bWAzwPls2LouQySnFDlyieAoprTskMtmfc+HIWplRcaZ1BNXI1u LNJ809gWnEw49V7o9ZqjpTZcqlNL3K92rwBTlY2uymsWbV8gkItKaPCmFdmx0OL/Va7S cEy9zdpePCm+5xXsvXnWXioL4KXcB1yjyMaclqHLrGxE931Hcs3i8Rzg2TU+dVYcIT9E Zgmg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=vRfP6jZwD5k91GsO2EtwWgU9vmyZBDy37/lZXGzi3aU=; b=0h03udlRHXs7bT33YYkTeWmM2g/G1nDJ0VC+1rsJRGPm0J80h35NWgWDeiU6AOOYUt LeahT5If5SHxnPjKWgBEIWQ2pD8qNRyxS//nXM/eC7rjCzqyw1fPDIjkS6ofoVukHCz8 9lX+cXkO2palZbKmGwX24EmoQJjz+YwjAgmVoI/AU2o/YyRt7PaPiE5lWaeAccgtZsKB TFpELlDN+NeEalwu0CNPmMQNe0L3tkXM+45C8hhU64NygFXaOduXu7fNu67bYjGx/JvK ilQw3hYe6cNzxV/RewkBZSUAfJTKVIq1KFh9dsdx2X8qyWhgULu91qQN9MrDBx48EClp 4GEA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=uCU3Z3Dd; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id y3si3395017pjv.50.2019.08.01.01.21.38; Thu, 01 Aug 2019 01:21:38 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=uCU3Z3Dd; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725958AbfHAIVi (ORCPT + 14 others); Thu, 1 Aug 2019 04:21:38 -0400 Received: from mail-pl1-f193.google.com ([209.85.214.193]:36419 "EHLO mail-pl1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730803AbfHAIVh (ORCPT ); Thu, 1 Aug 2019 04:21:37 -0400 Received: by mail-pl1-f193.google.com with SMTP id k8so31881265plt.3 for ; Thu, 01 Aug 2019 01:21:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vRfP6jZwD5k91GsO2EtwWgU9vmyZBDy37/lZXGzi3aU=; b=uCU3Z3Dd1P1FIooMb8g3/Yirwuf5gsToAiV9JYhukWAquCpOpLJOBCMoG93ZDCjBIJ btZaaTRhQMPYjtnilwUJTPxmpmuOa4OSnVouxkTRriItjzbs/k59piXQ+dz0rue37I54 jWgdNzREAD+kvsjZ7QRuA9AOa7zA0MSwjYD1mwFv3fmmirUdTHnq5OC9tDAS3419s9pd +ifs9FqauXsMYjmTt38hWLWb1QTU5UJ0UTt6fYxxN/QGNDipHnlelXreXhCWDUMaVJVU 1I9iNOsaPNQUDjeRv12Z4tcolTbd3/T/jvKxcOy1d/3XVOBwmdPAitFxF3bblCPruDBv yYNQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vRfP6jZwD5k91GsO2EtwWgU9vmyZBDy37/lZXGzi3aU=; b=qIU9QUjNx4ABgSHbYL8v0xz79+x2OvvirK1087rWaN72wrg/UQOUYxMKzJO2kjtqzk eSpXkbV4z1XwrENULhDHvUW1v7HHexI2mfbE3uoPQixQ0N5mcamJeuNUUXSxbs+85bop 4TbtmhlQ5UOxhGE0vo43rCStURO8K+ZJrwubcTtFrfrv2OWZXL1L5J45KKH+FRRMs/73 SUwrfWDqBI/0LQ7WqFcT9bD0svSeHnzJhAs7LkbNHgWKq/n3tpYhqIDFQ6haqcX8qdDB rUlr9jgwlQKD2n7lgQrnw4jTbMIpcz7VQ6ahrXLjgnwACIHYTKFOZTM8O6ZpI15ZdyRg btEA== X-Gm-Message-State: APjAAAWLAvG+hn5uOpGMxaPPEWVlx7GDEtH3mIszkjxy5Ji3u/XKn/N2 ZWiSEthNuLDCU5DUYIQueWLdkmfyvaM= X-Received: by 2002:a17:902:4b:: with SMTP id 69mr123879677pla.89.1564647696697; Thu, 01 Aug 2019 01:21:36 -0700 (PDT) Received: from localhost ([122.172.28.117]) by smtp.gmail.com with ESMTPSA id y194sm47248614pfg.116.2019.08.01.01.21.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 01 Aug 2019 01:21:36 -0700 (PDT) From: Viresh Kumar To: stable@vger.kernel.org Cc: Viresh Kumar , Julien Thierry , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Marc Zyngier , Mark Rutland , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com, guohanjun@huawei.com Subject: [PATCH ARM32 v4.4 V2 47/47] ARM: fix the cockup in the previous patch Date: Thu, 1 Aug 2019 13:46:31 +0530 Message-Id: <455094dcf249c379282166ebbb866fee091d8c9f.1564646727.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Russell King Commit d6951f582cc50ba0ad22ef46b599740966599b14 upstream. The intention in the previous patch was to only place the processor tables in the .rodata section if big.Little was being built and we wanted the branch target hardening, but instead (due to the way it was tested) it ended up always placing the tables into the .rodata section. Although harmless, let's correct this anyway. Fixes: 3a4d0c2172bc ("ARM: ensure that processor vtables is not lost after boot") Signed-off-by: Russell King Signed-off-by: Viresh Kumar --- arch/arm/mm/proc-macros.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S index d36a283b4099..e6bfdcc381f8 100644 --- a/arch/arm/mm/proc-macros.S +++ b/arch/arm/mm/proc-macros.S @@ -263,7 +263,7 @@ * If we are building for big.Little with branch predictor hardening, * we need the processor function tables to remain available after boot. */ -#if 1 // defined(CONFIG_BIG_LITTLE) && defined(CONFIG_HARDEN_BRANCH_PREDICTOR) +#if defined(CONFIG_BIG_LITTLE) && defined(CONFIG_HARDEN_BRANCH_PREDICTOR) .section ".rodata" #endif .type \name\()_processor_functions, #object @@ -301,7 +301,7 @@ ENTRY(\name\()_processor_functions) .endif .size \name\()_processor_functions, . - \name\()_processor_functions -#if 1 // defined(CONFIG_BIG_LITTLE) && defined(CONFIG_HARDEN_BRANCH_PREDICTOR) +#if defined(CONFIG_BIG_LITTLE) && defined(CONFIG_HARDEN_BRANCH_PREDICTOR) .previous #endif .endm