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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id k125-20020a632483000000b005742092c211sm2103096pgk.64.2023.10.18.13.46.08 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 13:46:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 1/2] tcg: Improve expansion of deposit of constant Date: Wed, 18 Oct 2023 13:46:05 -0700 Message-Id: <20231018204606.1545518-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231018204606.1545518-1-richard.henderson@linaro.org> References: <20231018204606.1545518-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The extract2 expansion is too difficult for the optimizer to simplify. If we have an immediate input, use and+or instead, skipping the and if the field becomes all 1's. Signed-off-by: Richard Henderson --- tcg/tcg-op.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 393dbcd01c..2ef4b866e2 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -602,6 +602,7 @@ void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2, { uint32_t mask; TCGv_i32 t1; + TCGTemp *ts; tcg_debug_assert(ofs < 32); tcg_debug_assert(len > 0); @@ -617,6 +618,19 @@ void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2, return; } + /* Deposit of a constant into a value. */ + ts = tcgv_i32_temp(arg2); + if (ts->kind == TEMP_CONST) { + uint32_t mask0 = deposit32(-1, ofs, len, 0); + uint32_t maski = deposit32(0, ofs, len, ts->val); + + if (mask0 != ~maski) { + tcg_gen_andi_i32(ret, arg1, mask0); + } + tcg_gen_ori_i32(ret, ret, maski); + return; + } + t1 = tcg_temp_ebb_new_i32(); if (TCG_TARGET_HAS_extract2_i32) { @@ -2217,6 +2231,7 @@ void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2, { uint64_t mask; TCGv_i64 t1; + TCGTemp *ts; tcg_debug_assert(ofs < 64); tcg_debug_assert(len > 0); @@ -2232,6 +2247,19 @@ void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2, return; } + /* Deposit of a constant into a value. */ + ts = tcgv_i64_temp(arg2); + if (ts->kind == TEMP_CONST) { + uint64_t mask0 = deposit64(-1, ofs, len, 0); + uint64_t maski = deposit64(0, ofs, len, ts->val); + + if (mask0 != ~maski) { + tcg_gen_andi_i64(ret, arg1, mask0); + } + tcg_gen_ori_i64(ret, ret, maski); + return; + } + if (TCG_TARGET_REG_BITS == 32) { if (ofs >= 32) { tcg_gen_deposit_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), From patchwork Wed Oct 18 20:46:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 735074 Delivered-To: patch@linaro.org Received: by 2002:adf:f0cd:0:b0:32d:baff:b0ca with SMTP id x13csp1202712wro; Wed, 18 Oct 2023 13:46:57 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGQ89wrD1xUKnI0+QQpR5vYsLuo0a5tqT2pjGqhzMFEJyLALy3wef91vEUxECmOOrpjnVe+ X-Received: by 2002:a05:622a:14c7:b0:417:f85b:5a5a with SMTP id u7-20020a05622a14c700b00417f85b5a5amr421122qtx.5.1697662017508; Wed, 18 Oct 2023 13:46:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697662017; cv=none; d=google.com; s=arc-20160816; b=QqW6rQwB0by8NDuzfLZ1QVbkMdYJ36QxDVqRPSOkAOuFE9IfssoWIqDlKhF4Wu6+5E iMumbb4EfJsX7dwgDa76UkwFPxqrLgl6hXyfMx1fh+kT2vXrTIe4lbVpcpU4x3O6sb5l 4sr2OEwb94t9LPOTnyZI04LqwqfhYmCZecN6bGF5Wga5JiW6FlrHuwxwBKhxNf4Z0mUT ukUoKErGDhLT7fG/8ygql67xArjp2S+Tz0Gl8tQi/zEsrBvFuBXZHA/wGuZbtoGhA520 4BwOtmkib/cmEA6ZGraMI4oUbArzt/276qOXC5oBRa4Z2/Q+B9QjNu3m8TUR6Tp+6pst uE7A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=2zsMSRhlbZwVzQVen6DKnQDDskBCrZAwA6YeAeDVn/c=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=JuyU6/y1WbQTxnafAIL+4y6GuGdEofyf8s0yL8HOt2DAEBul8zxKbacKPYkp3Q4zYE T3fF+913071e/ABbSC7Y7aSdt2alg22UW6tHyf14IoQoFvLcgNpFvfEcTdRiYm+GnV4H 1uBV+GyWAlkKc6dwJDYL+xUH4OMfd7kwOgQMRR16mAB+9KIJSVPqbx0gnEEawgjotdmO 3FW1MGsi56Z2F8n6ChOkVv5k6PMglR392xxGRrHt/49E7awDcpTUZRq+90fHPXfy8Iar VZGDWJMuCLy7ffbcPjaCIAxrGdl7zLTDKDlKWWuVHUuNiy9Uxhi4Bw0GZkOYTyO6a49I zVxQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ErZWRhpU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id k125-20020a632483000000b005742092c211sm2103096pgk.64.2023.10.18.13.46.09 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 13:46:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 2/2] tcg: Improve expansion of deposit into a constant Date: Wed, 18 Oct 2023 13:46:06 -0700 Message-Id: <20231018204606.1545518-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231018204606.1545518-1-richard.henderson@linaro.org> References: <20231018204606.1545518-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Generalize tcg_gen_deposit_z_* from 0 to any constant. Use this to automatically simplify tcg_gen_deposit_*. Signed-off-by: Richard Henderson --- tcg/tcg-op.c | 295 ++++++++++++++++++++++++++++++--------------------- 1 file changed, 174 insertions(+), 121 deletions(-) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 2ef4b866e2..049b684ccc 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -597,6 +597,70 @@ void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) } } +static void tcg_gen_deposit_i_i32(TCGv_i32 ret, uint32_t i, TCGv_i32 arg, + unsigned int ofs, unsigned int len) +{ + i = deposit32(i, ofs, len, 0); + + if (ofs + len == 32) { + tcg_gen_shli_i32(ret, arg, ofs); + goto finish; + } + if (ofs == 0) { + tcg_gen_andi_i32(ret, arg, (1u << len) - 1); + goto finish; + } + if (TCG_TARGET_HAS_deposit_i32 + && TCG_TARGET_deposit_i32_valid(ofs, len)) { + tcg_gen_op5ii_i32(INDEX_op_deposit_i32, ret, + tcg_constant_i32(i), arg, ofs, len); + return; + } + + /* + * To help two-operand hosts we prefer to zero-extend first, + * which allows ARG to stay live. + */ + switch (len) { + case 16: + if (TCG_TARGET_HAS_ext16u_i32) { + tcg_gen_ext16u_i32(ret, arg); + tcg_gen_shli_i32(ret, ret, ofs); + goto finish; + } + break; + case 8: + if (TCG_TARGET_HAS_ext8u_i32) { + tcg_gen_ext8u_i32(ret, arg); + tcg_gen_shli_i32(ret, ret, ofs); + goto finish; + } + break; + } + /* Otherwise prefer zero-extension over AND for code size. */ + switch (ofs + len) { + case 16: + if (TCG_TARGET_HAS_ext16u_i32) { + tcg_gen_shli_i32(ret, arg, ofs); + tcg_gen_ext16u_i32(ret, ret); + goto finish; + } + break; + case 8: + if (TCG_TARGET_HAS_ext8u_i32) { + tcg_gen_shli_i32(ret, arg, ofs); + tcg_gen_ext8u_i32(ret, ret); + goto finish; + } + break; + } + tcg_gen_andi_i32(ret, arg, (1u << len) - 1); + tcg_gen_shli_i32(ret, ret, ofs); + + finish: + tcg_gen_ori_i32(ret, ret, i); +} + void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2, unsigned int ofs, unsigned int len) { @@ -613,6 +677,14 @@ void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2, tcg_gen_mov_i32(ret, arg2); return; } + + /* Deposit of a value into a constant. */ + ts = tcgv_i32_temp(arg1); + if (ts->kind == TEMP_CONST) { + tcg_gen_deposit_i_i32(ret, ts->val, arg2, ofs, len); + return; + } + if (TCG_TARGET_HAS_deposit_i32 && TCG_TARGET_deposit_i32_valid(ofs, len)) { tcg_gen_op5ii_i32(INDEX_op_deposit_i32, ret, arg1, arg2, ofs, len); return; @@ -667,53 +739,7 @@ void tcg_gen_deposit_z_i32(TCGv_i32 ret, TCGv_i32 arg, tcg_debug_assert(len <= 32); tcg_debug_assert(ofs + len <= 32); - if (ofs + len == 32) { - tcg_gen_shli_i32(ret, arg, ofs); - } else if (ofs == 0) { - tcg_gen_andi_i32(ret, arg, (1u << len) - 1); - } else if (TCG_TARGET_HAS_deposit_i32 - && TCG_TARGET_deposit_i32_valid(ofs, len)) { - TCGv_i32 zero = tcg_constant_i32(0); - tcg_gen_op5ii_i32(INDEX_op_deposit_i32, ret, zero, arg, ofs, len); - } else { - /* To help two-operand hosts we prefer to zero-extend first, - which allows ARG to stay live. */ - switch (len) { - case 16: - if (TCG_TARGET_HAS_ext16u_i32) { - tcg_gen_ext16u_i32(ret, arg); - tcg_gen_shli_i32(ret, ret, ofs); - return; - } - break; - case 8: - if (TCG_TARGET_HAS_ext8u_i32) { - tcg_gen_ext8u_i32(ret, arg); - tcg_gen_shli_i32(ret, ret, ofs); - return; - } - break; - } - /* Otherwise prefer zero-extension over AND for code size. */ - switch (ofs + len) { - case 16: - if (TCG_TARGET_HAS_ext16u_i32) { - tcg_gen_shli_i32(ret, arg, ofs); - tcg_gen_ext16u_i32(ret, ret); - return; - } - break; - case 8: - if (TCG_TARGET_HAS_ext8u_i32) { - tcg_gen_shli_i32(ret, arg, ofs); - tcg_gen_ext8u_i32(ret, ret); - return; - } - break; - } - tcg_gen_andi_i32(ret, arg, (1u << len) - 1); - tcg_gen_shli_i32(ret, ret, ofs); - } + tcg_gen_deposit_i_i32(ret, 0, arg, ofs, len); } void tcg_gen_extract_i32(TCGv_i32 ret, TCGv_i32 arg, @@ -2226,6 +2252,98 @@ void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) } } +static void tcg_gen_deposit_i_i64(TCGv_i64 ret, uint64_t i, TCGv_i64 arg, + unsigned int ofs, unsigned int len) +{ + i = deposit64(i, ofs, len, 0); + + if (ofs + len == 64) { + tcg_gen_shli_i64(ret, arg, ofs); + goto finish; + } + if (ofs == 0) { + tcg_gen_andi_i64(ret, arg, (1ull << len) - 1); + goto finish; + } + if (TCG_TARGET_HAS_deposit_i64 + && TCG_TARGET_deposit_i64_valid(ofs, len)) { + tcg_gen_op5ii_i64(INDEX_op_deposit_i64, ret, + tcg_constant_i64(i), arg, ofs, len); + return; + } + + if (TCG_TARGET_REG_BITS == 32) { + if (ofs >= 32) { + tcg_gen_deposit_i_i32(TCGV_HIGH(ret), i >> 32, + TCGV_LOW(arg), ofs - 32, len); + tcg_gen_movi_i32(TCGV_LOW(ret), i); + return; + } + if (ofs + len <= 32) { + tcg_gen_deposit_i_i32(TCGV_LOW(ret), i, TCGV_LOW(arg), ofs, len); + tcg_gen_movi_i32(TCGV_HIGH(ret), i >> 32); + return; + } + } + + /* + * To help two-operand hosts we prefer to zero-extend first, + * which allows ARG to stay live. + */ + switch (len) { + case 32: + if (TCG_TARGET_HAS_ext32u_i64) { + tcg_gen_ext32u_i64(ret, arg); + tcg_gen_shli_i64(ret, ret, ofs); + goto finish; + } + break; + case 16: + if (TCG_TARGET_HAS_ext16u_i64) { + tcg_gen_ext16u_i64(ret, arg); + tcg_gen_shli_i64(ret, ret, ofs); + goto finish; + } + break; + case 8: + if (TCG_TARGET_HAS_ext8u_i64) { + tcg_gen_ext8u_i64(ret, arg); + tcg_gen_shli_i64(ret, ret, ofs); + goto finish; + } + break; + } + /* Otherwise prefer zero-extension over AND for code size. */ + switch (ofs + len) { + case 32: + if (TCG_TARGET_HAS_ext32u_i64) { + tcg_gen_shli_i64(ret, arg, ofs); + tcg_gen_ext32u_i64(ret, ret); + goto finish; + } + break; + case 16: + if (TCG_TARGET_HAS_ext16u_i64) { + tcg_gen_shli_i64(ret, arg, ofs); + tcg_gen_ext16u_i64(ret, ret); + goto finish; + } + break; + case 8: + if (TCG_TARGET_HAS_ext8u_i64) { + tcg_gen_shli_i64(ret, arg, ofs); + tcg_gen_ext8u_i64(ret, ret); + goto finish; + } + break; + } + tcg_gen_andi_i64(ret, arg, (1ull << len) - 1); + tcg_gen_shli_i64(ret, ret, ofs); + + finish: + tcg_gen_ori_i64(ret, ret, i); +} + void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2, unsigned int ofs, unsigned int len) { @@ -2242,6 +2360,14 @@ void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2, tcg_gen_mov_i64(ret, arg2); return; } + + /* Deposit of a value into a constant. */ + ts = tcgv_i64_temp(arg1); + if (ts->kind == TEMP_CONST) { + tcg_gen_deposit_i_i64(ret, ts->val, arg2, ofs, len); + return; + } + if (TCG_TARGET_HAS_deposit_i64 && TCG_TARGET_deposit_i64_valid(ofs, len)) { tcg_gen_op5ii_i64(INDEX_op_deposit_i64, ret, arg1, arg2, ofs, len); return; @@ -2311,80 +2437,7 @@ void tcg_gen_deposit_z_i64(TCGv_i64 ret, TCGv_i64 arg, tcg_debug_assert(len <= 64); tcg_debug_assert(ofs + len <= 64); - if (ofs + len == 64) { - tcg_gen_shli_i64(ret, arg, ofs); - } else if (ofs == 0) { - tcg_gen_andi_i64(ret, arg, (1ull << len) - 1); - } else if (TCG_TARGET_HAS_deposit_i64 - && TCG_TARGET_deposit_i64_valid(ofs, len)) { - TCGv_i64 zero = tcg_constant_i64(0); - tcg_gen_op5ii_i64(INDEX_op_deposit_i64, ret, zero, arg, ofs, len); - } else { - if (TCG_TARGET_REG_BITS == 32) { - if (ofs >= 32) { - tcg_gen_deposit_z_i32(TCGV_HIGH(ret), TCGV_LOW(arg), - ofs - 32, len); - tcg_gen_movi_i32(TCGV_LOW(ret), 0); - return; - } - if (ofs + len <= 32) { - tcg_gen_deposit_z_i32(TCGV_LOW(ret), TCGV_LOW(arg), ofs, len); - tcg_gen_movi_i32(TCGV_HIGH(ret), 0); - return; - } - } - /* To help two-operand hosts we prefer to zero-extend first, - which allows ARG to stay live. */ - switch (len) { - case 32: - if (TCG_TARGET_HAS_ext32u_i64) { - tcg_gen_ext32u_i64(ret, arg); - tcg_gen_shli_i64(ret, ret, ofs); - return; - } - break; - case 16: - if (TCG_TARGET_HAS_ext16u_i64) { - tcg_gen_ext16u_i64(ret, arg); - tcg_gen_shli_i64(ret, ret, ofs); - return; - } - break; - case 8: - if (TCG_TARGET_HAS_ext8u_i64) { - tcg_gen_ext8u_i64(ret, arg); - tcg_gen_shli_i64(ret, ret, ofs); - return; - } - break; - } - /* Otherwise prefer zero-extension over AND for code size. */ - switch (ofs + len) { - case 32: - if (TCG_TARGET_HAS_ext32u_i64) { - tcg_gen_shli_i64(ret, arg, ofs); - tcg_gen_ext32u_i64(ret, ret); - return; - } - break; - case 16: - if (TCG_TARGET_HAS_ext16u_i64) { - tcg_gen_shli_i64(ret, arg, ofs); - tcg_gen_ext16u_i64(ret, ret); - return; - } - break; - case 8: - if (TCG_TARGET_HAS_ext8u_i64) { - tcg_gen_shli_i64(ret, arg, ofs); - tcg_gen_ext8u_i64(ret, ret); - return; - } - break; - } - tcg_gen_andi_i64(ret, arg, (1ull << len) - 1); - tcg_gen_shli_i64(ret, ret, ofs); - } + tcg_gen_deposit_i_i64(ret, 0, arg, ofs, len); } void tcg_gen_extract_i64(TCGv_i64 ret, TCGv_i64 arg,