From patchwork Fri Aug 9 13:26:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 170917 Delivered-To: patch@linaro.org Received: by 2002:a92:512:0:0:0:0:0 with SMTP id q18csp10005875ile; Fri, 9 Aug 2019 06:26:55 -0700 (PDT) X-Google-Smtp-Source: APXvYqznMACAG86LnNUPD1vVqE3QTzsuQ7rgf5TZ3hBF5fgH7a2BVfVhUIEfcrizN1E1VflR6nhI X-Received: by 2002:a63:e54f:: with SMTP id z15mr17421782pgj.4.1565357215287; Fri, 09 Aug 2019 06:26:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1565357215; cv=none; d=google.com; s=arc-20160816; b=CEW6Dr66jyGWlFHebqhixU0YukivzwLMdsYUwkeni65LUDpkLXcYgrOwgoI3ulw1ma AmLzaJELX6xx5xxedoCqesHtbQLKZP+BBx2oFuB6HU/0RnDA4CpZN7KCVv9Yyu91avcV 6AB6oY8ZwN6PuGfaA0oweB1ahzdjBfIxCoLWHajMAxdzMzBUHmBakvSJ227NTMTKSy7Z 2oLt9B6Xmxwuw6Yc8f6aswtF2iyV+DbykFl/fnoPYgxfh3qQuBbc4fpyn4aitOJwDzYz EvgPJmZkmgAM2TOOozGgqlMPK/OgXFgViYAqhrMnmjVNmB1quNGZsqBiANSVc/9cPvhY 2S2w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=rSFjIk2CuDna3AXJg7IKRglJkXTvsmhX3HKL4CcwO7E=; b=DcPf6hjuqlKRdcWAg9C3+dzqoHvMNnegg5/Fe8HSjcOUYTe58I/zrrsBir1EW83uGV b1nzL87bYvvJnPANxRQwa1DsPfv8QthazURhSVQ7ulkbl/HPRl6+xLe9DvJ2t1LwFQsR TwmKdI1M8in2Jy33ORgXHhFEUDELcLCuVgamgfCn+SMvh04FC0sywJFBIFLY74KjgRxz RnHjIMP1dp2hhDWrinK6yiWgiewp4S6AxuneuPS5n4lEsYlaNFWqcFnMab8I9GfUbl8a 65dSQF+vSame1qKqVZNjF57t9TEjN62/W6mFb3olGwTJYptZYDstR9Sxu7iypXVS4WLZ jTzA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Ri5fm+14; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g4si52475812pgf.383.2019.08.09.06.26.55; Fri, 09 Aug 2019 06:26:55 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Ri5fm+14; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2406273AbfHIN0y (ORCPT + 5 others); Fri, 9 Aug 2019 09:26:54 -0400 Received: from mail-lj1-f194.google.com ([209.85.208.194]:44573 "EHLO mail-lj1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726091AbfHIN0y (ORCPT ); Fri, 9 Aug 2019 09:26:54 -0400 Received: by mail-lj1-f194.google.com with SMTP id k18so92061305ljc.11 for ; Fri, 09 Aug 2019 06:26:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=rSFjIk2CuDna3AXJg7IKRglJkXTvsmhX3HKL4CcwO7E=; b=Ri5fm+14OHJVeYqaTSWgC25bcgo/QJf9T5HfFUsqUghgCmCIoYHUYGgaLzWYZHql6V Q1mVSDZ5Z7TMMNGSiLXS1hHH3CFyOrWe1Q9zieCchUn4Ud7xYj2v8t6VOQ10djYMCb7I RY/DksEAuTH47+rvSruSYxZYElbisDvvaNNn7XK7NyVQwvLLRSQA5q3icUhiKxStxbmb zC06q7qKjUJS4jYQOphQrG6cSI4S6yFOYqY9Cew6nUYlBfpTI0+039fuA6sZguj7EVzA Y8GZZsnCw9XJT60VHbwwwtVZxmYXLYh5OAtEz/5qy1kYQtNofWlXIMTqTHZv8/39NmGT Jn6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=rSFjIk2CuDna3AXJg7IKRglJkXTvsmhX3HKL4CcwO7E=; b=gEWKqFp8nf1jEcygLV53SrlgE/8smOlLZlUVjSrL39HLMCUy3sC0jJ0Q6Gj3B2Tvvj L75Ykz9PQyxYPvJX2lQQdOUOyRXFiHztHDQLSoQzBm8+0iagPPygO504j4sGM6AnmOVS Dw8Nziwyymm9gKORlobIf7SZisx60wi1P2lWuAFsewee0cpODKv1VfHXU8Ppl95pDv+N mcM/J5eis4JVmJt77dlCa31OYF1MykbaLgQNAFrJMgoriTtpvWOXAwhW1GddL8OaolLU KNh72TtjH22x379oyE9Db/fo/VImmPXlpluGWAJ473w0kfbFRo2P0XCmbX1X/VJ0u+wq J9iA== X-Gm-Message-State: APjAAAWzBxbxs6Ks+530mqT/KUtThNq0IGpib2vVkMh5xI4qiBjz3wMV Csd9tWl/AlV90+1vaVyT6AK3DmDmxXQ= X-Received: by 2002:a2e:8455:: with SMTP id u21mr11044489ljh.20.1565357212174; Fri, 09 Aug 2019 06:26:52 -0700 (PDT) Received: from genomnajs.ideon.se ([85.235.10.227]) by smtp.gmail.com with ESMTPSA id d3sm4631190lfj.15.2019.08.09.06.26.50 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 09 Aug 2019 06:26:50 -0700 (PDT) From: Linus Walleij To: linux-gpio@vger.kernel.org Cc: Bartosz Golaszewski , Linus Walleij , Michal Simek , Shubhrajyoti Datta , Thierry Reding Subject: [PATCH] gpio: zynq: Pass irqchip when adding gpiochip Date: Fri, 9 Aug 2019 15:26:49 +0200 Message-Id: <20190809132649.25176-1-linus.walleij@linaro.org> X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org We need to convert all old gpio irqchips to pass the irqchip setup along when adding the gpio_chip. For more info see drivers/gpio/TODO. For chained irqchips this is a pretty straight-forward conversion. Cc: Michal Simek Cc: Shubhrajyoti Datta Cc: Thierry Reding Signed-off-by: Linus Walleij --- drivers/gpio/gpio-zynq.c | 37 +++++++++++++++++++++---------------- 1 file changed, 21 insertions(+), 16 deletions(-) -- 2.21.0 diff --git a/drivers/gpio/gpio-zynq.c b/drivers/gpio/gpio-zynq.c index 86b0bd256c13..cd475ff4bcad 100644 --- a/drivers/gpio/gpio-zynq.c +++ b/drivers/gpio/gpio-zynq.c @@ -830,6 +830,7 @@ static int zynq_gpio_probe(struct platform_device *pdev) int ret, bank_num; struct zynq_gpio *gpio; struct gpio_chip *chip; + struct gpio_irq_chip *girq; const struct of_device_id *match; gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); @@ -885,34 +886,38 @@ static int zynq_gpio_probe(struct platform_device *pdev) if (ret < 0) goto err_pm_dis; - /* report a bug if gpio chip registration fails */ - ret = gpiochip_add_data(chip, gpio); - if (ret) { - dev_err(&pdev->dev, "Failed to add gpio chip\n"); - goto err_pm_put; - } - /* disable interrupts for all banks */ for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr + ZYNQ_GPIO_INTDIS_OFFSET(bank_num)); - ret = gpiochip_irqchip_add(chip, &zynq_gpio_edge_irqchip, 0, - handle_level_irq, IRQ_TYPE_NONE); - if (ret) { - dev_err(&pdev->dev, "Failed to add irq chip\n"); - goto err_rm_gpiochip; + /* Set up the GPIO irqchip */ + girq = &chip->irq; + girq->chip = &zynq_gpio_edge_irqchip; + girq->parent_handler = zynq_gpio_irqhandler; + girq->num_parents = 1; + girq->parents = devm_kcalloc(&pdev->dev, 1, + sizeof(*girq->parents), + GFP_KERNEL); + if (!girq->parents) { + ret = -ENOMEM; + goto err_pm_put; } + girq->parents[0] = gpio->irq; + girq->default_type = IRQ_TYPE_NONE; + girq->handler = handle_level_irq; - gpiochip_set_chained_irqchip(chip, &zynq_gpio_edge_irqchip, gpio->irq, - zynq_gpio_irqhandler); + /* report a bug if gpio chip registration fails */ + ret = gpiochip_add_data(chip, gpio); + if (ret) { + dev_err(&pdev->dev, "Failed to add gpio chip\n"); + goto err_pm_put; + } pm_runtime_put(&pdev->dev); return 0; -err_rm_gpiochip: - gpiochip_remove(chip); err_pm_put: pm_runtime_put(&pdev->dev); err_pm_dis: