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Peter Anvin" CC: , , , , , , Ingo Molnar , "Arnaldo Carvalho de Melo" , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Ian Rogers , Adrian Hunter , "Mario Limonciello" Subject: [PATCH 1/2] x86: Enable x2apic during resume from suspend if used previously Date: Mon, 23 Oct 2023 11:00:17 -0500 Message-ID: <20231023160018.164054-2-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231023160018.164054-1-mario.limonciello@amd.com> References: <20231023160018.164054-1-mario.limonciello@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE3B:EE_|CH3PR12MB9393:EE_ X-MS-Office365-Filtering-Correlation-Id: e01b70fa-002b-4ec0-def6-08dbd3e133cb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: lBLjBHI5BGOdKvZXdg8Gi5EUBXxT3H3FIKxvWkfhYraoXopTCEDrEnS3/6aLULEt6rG9zroJcugVofirMG0VS7uO71tbho6RmpxpcgQgNRr9P2d+dl/MJ/rsqV9zMUwgmLt9PI/vxnwfqeirSzfYvfKww+5Cxg94fe/O5i8Tqv92+hK6Y9kBbxJOca+PvBwhQnYbJbIZDnWfPohHvzjiT1LA/tlp/ptC/hiSfNVcgoKZyUxJvpxqgx2qzRYDVe/wsWhIQeenBHeUzt7AGsdL9wZz1WGNx72eREGszToqrxjth7dtrmgZPEPw44FTuB0oNr69vhOXNnBSnV7MPiwKWr3lOGV7o0sB/A1Yl0SgCexd8U5V7V+jHMvIH36nkjdSiJnZ92eM35P1CA45vbhh8ytBG+U5A54r8cBJJxiNhInVuZNw1qtdItSKdzBQIkPkV7PXQbeJSpA4tNOnPSUs1rPuGZcD8o7wcQTtWI92sHjuAaoczvdwTir9akluWAZxMOgcgGMRqvBpvxrJDIbbxtO2opm0RQiNnAd5xa05AS5j5l3XNAyfjF43Ff0lF5I5U/qG8EKPudDQaI2qGOZoHeDXjPQ+OP3gFgvn3UF2Lze4z8WGlCUftgNfRZbaZCuSshudbiOhaU1TZmun2FTZUNP/WfY8X1/VzwQng8sEcrzgfLhBVug9jxuyzsOkf9WDZK5ui/WV3aVbiJclQNxhtRq1H30npcdM93DSjUY+2m7odn5WkBHj2uH//mLdJQk4YN8bjklfSyyP8ZSaL+gGWw== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230031)(4636009)(346002)(376002)(39860400002)(136003)(396003)(230922051799003)(82310400011)(186009)(64100799003)(1800799009)(451199024)(46966006)(40470700004)(36840700001)(26005)(2906002)(41300700001)(36860700001)(44832011)(40460700003)(86362001)(7416002)(36756003)(5660300002)(8676002)(8936002)(4326008)(15650500001)(2616005)(478600001)(7696005)(16526019)(1076003)(81166007)(110136005)(54906003)(356005)(70586007)(82740400003)(316002)(70206006)(83380400001)(6666004)(336012)(40480700001)(426003)(47076005)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Oct 2023 16:00:39.2220 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e01b70fa-002b-4ec0-def6-08dbd3e133cb X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE3B.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB9393 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org If x2apic was enabled during boot with parallel startup it will be needed during resume from suspend to ram as well. Store whether to enable into the smpboot_control global variable and during startup re-enable it if necessary. Cc: stable@vger.kernel.org # 6.5+ Fixes: 0c7ffa32dbd6 ("x86/smpboot/64: Implement arch_cpuhp_init_parallel_bringup() and enable it") Signed-off-by: Mario Limonciello --- arch/x86/include/asm/smp.h | 1 + arch/x86/kernel/acpi/sleep.c | 12 ++++++++---- arch/x86/kernel/head_64.S | 15 +++++++++++++++ 3 files changed, 24 insertions(+), 4 deletions(-) diff --git a/arch/x86/include/asm/smp.h b/arch/x86/include/asm/smp.h index c31c633419fe..86584ffaebc3 100644 --- a/arch/x86/include/asm/smp.h +++ b/arch/x86/include/asm/smp.h @@ -190,6 +190,7 @@ extern unsigned long apic_mmio_base; #endif /* !__ASSEMBLY__ */ /* Control bits for startup_64 */ +#define STARTUP_ENABLE_X2APIC 0x40000000 #define STARTUP_READ_APICID 0x80000000 /* Top 8 bits are reserved for control */ diff --git a/arch/x86/kernel/acpi/sleep.c b/arch/x86/kernel/acpi/sleep.c index 6dfecb27b846..29734a1299f6 100644 --- a/arch/x86/kernel/acpi/sleep.c +++ b/arch/x86/kernel/acpi/sleep.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -129,11 +130,14 @@ int x86_acpi_suspend_lowlevel(void) */ current->thread.sp = (unsigned long)temp_stack + sizeof(temp_stack); /* - * Ensure the CPU knows which one it is when it comes back, if - * it isn't in parallel mode and expected to work that out for - * itself. + * Ensure x2apic is re-enabled if necessary and the CPU knows which + * one it is when it comes back, if it isn't in parallel mode and + * expected to work that out for itself. */ - if (!(smpboot_control & STARTUP_PARALLEL_MASK)) + if (smpboot_control & STARTUP_PARALLEL_MASK) { + if (x2apic_enabled()) + smpboot_control |= STARTUP_ENABLE_X2APIC; + } else smpboot_control = smp_processor_id(); #endif initial_code = (unsigned long)wakeup_long64; diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S index ea6995920b7a..fcfa79105928 100644 --- a/arch/x86/kernel/head_64.S +++ b/arch/x86/kernel/head_64.S @@ -236,10 +236,15 @@ SYM_INNER_LABEL(secondary_startup_64_no_verify, SYM_L_GLOBAL) * used to look up the CPU number. For booting a single CPU, the * CPU number is encoded in smpboot_control. * + * Bit 30 STARTUP_ENABLE_X2APIC (Enable X2APIC mode) * Bit 31 STARTUP_READ_APICID (Read APICID from APIC) * Bit 0-23 CPU# if STARTUP_xx flags are not set */ movl smpboot_control(%rip), %ecx + + testl $STARTUP_ENABLE_X2APIC, %ecx + jnz .Lenable_x2apic + testl $STARTUP_READ_APICID, %ecx jnz .Lread_apicid /* @@ -249,6 +254,16 @@ SYM_INNER_LABEL(secondary_startup_64_no_verify, SYM_L_GLOBAL) andl $(~STARTUP_PARALLEL_MASK), %ecx jmp .Lsetup_cpu +.Lenable_x2apic: + /* Enable X2APIC if disabled */ + mov $MSR_IA32_APICBASE, %ecx + rdmsr + testl $X2APIC_ENABLE, %eax + jnz .Lread_apicid_msr + orl $X2APIC_ENABLE, %eax + wrmsr + jmp .Lread_apicid_msr + .Lread_apicid: /* Check whether X2APIC mode is already enabled */ mov $MSR_IA32_APICBASE, %ecx From patchwork Mon Oct 23 16:00:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 737456 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 920DDC001E0 for ; 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Peter Anvin" CC: , , , , , , Ingo Molnar , "Arnaldo Carvalho de Melo" , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Ian Rogers , Adrian Hunter , "Mario Limonciello" Subject: [PATCH 2/2] perf/x86/amd: Don't allow pre-emption in amd_pmu_lbr_reset() Date: Mon, 23 Oct 2023 11:00:18 -0500 Message-ID: <20231023160018.164054-3-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231023160018.164054-1-mario.limonciello@amd.com> References: <20231023160018.164054-1-mario.limonciello@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE3C:EE_|MW4PR12MB5666:EE_ X-MS-Office365-Filtering-Correlation-Id: 3a31c1f0-96c5-4c2a-7682-08dbd3e134a3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: qnDU8E0jMpXScECBwwcNfzHnALLCj5smgStDnug8REbs79EYSiTFNtUq0PXn5H4qQd+MC5yMeIeFx6ULyVJlvEr165Wt3NkqYtPzOjhYRNQeCRtCI7/+3TFG1PbUQEFaA2USxl8MRkp6ppVKB7wJtrNO1WxoV1WtlcirVLw5mLc3wsHyL0TnfWPEQeZDADpVP+Wz7x8AMKARotlhlnVBS49XCxtrik9PEtGDPZtPujzNUVClIyVTfBJeC0pfxViz5thLSkjZkkN2GvvgJ90BY0Kl28zstnqvQdCkn5tLRgdYQ960SWoajPXjGHZbAXtTA0GlN3PYN0sm5dJlvySaUksubWJtLiOIKjrMp/8A08OotW9HIffUcZSe+EmXpv3O/kekjlLIoT8LzB7BHACfIU4duRhMRnxUP/C3JyFGOGiiWP8xp8g//Z0NZVixE/m65ewjM7mgJufO6XQNjLWizBh18Mle43l604iPGMFkDuh68KYVhk2T9//xikhcmrzMljtc6pd9Vw71aaclW0dXwmZCjCULpUKzzRQkgekPe7e2OMy3dWbSCDV5NlR2lL3MUM6iP7vG+MZqOVr/9J5ZSOJyCvIHqHCPZrm46w3/PkQ/GujxnHEJp1600MFDs3XgrrFxS3zIcJ8gaYNfmuNw7JPgJF+lpgK7O9cTfoZCfysxw1AnD3ajuqJFFjD62y0Z6N0h8GfnXdZxa/SjNFYp2XbaF+amVDig/SMoX7DtadNjn2n0YvtgPdZa3xNQQjlBXN/Xa5nZk6RfG90IlkuMcg== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230031)(4636009)(39860400002)(396003)(136003)(376002)(346002)(230922051799003)(186009)(82310400011)(451199024)(64100799003)(1800799009)(36840700001)(46966006)(40470700004)(40480700001)(40460700003)(7416002)(36860700001)(5660300002)(82740400003)(2906002)(356005)(41300700001)(16526019)(7696005)(86362001)(1076003)(336012)(83380400001)(81166007)(26005)(426003)(4326008)(8936002)(47076005)(44832011)(2616005)(36756003)(8676002)(6666004)(478600001)(316002)(70586007)(70206006)(110136005)(54906003)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Oct 2023 16:00:40.6349 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3a31c1f0-96c5-4c2a-7682-08dbd3e134a3 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE3C.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB5666 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Fixes a BUG reported during suspend to ram testing. ``` [ 478.274752] BUG: using smp_processor_id() in preemptible [00000000] code: rtcwake/2948 [ 478.274754] caller is amd_pmu_lbr_reset+0x19/0xc0 ``` Cc: stable@vger.kernel.org # 6.1+ Fixes: ca5b7c0d9621 ("perf/x86/amd/lbr: Add LbrExtV2 branch record support") Signed-off-by: Mario Limonciello --- arch/x86/events/amd/lbr.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/x86/events/amd/lbr.c b/arch/x86/events/amd/lbr.c index eb31f850841a..5b98e8c7d8b7 100644 --- a/arch/x86/events/amd/lbr.c +++ b/arch/x86/events/amd/lbr.c @@ -321,7 +321,7 @@ int amd_pmu_lbr_hw_config(struct perf_event *event) void amd_pmu_lbr_reset(void) { - struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); + struct cpu_hw_events *cpuc = get_cpu_ptr(&cpu_hw_events); int i; if (!x86_pmu.lbr_nr) @@ -335,6 +335,7 @@ void amd_pmu_lbr_reset(void) cpuc->last_task_ctx = NULL; cpuc->last_log_id = 0; + put_cpu_ptr(&cpu_hw_events); wrmsrl(MSR_AMD64_LBR_SELECT, 0); }