From patchwork Tue Oct 24 11:37:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Adhemerval Zanella X-Patchwork-Id: 737534 Delivered-To: patch@linaro.org Received: by 2002:adf:dd81:0:b0:32d:baff:b0ca with SMTP id x1csp1978007wrl; Tue, 24 Oct 2023 04:37:35 -0700 (PDT) X-Google-Smtp-Source: AGHT+IG90IiqWO8jtykBXeDIMOC532xrV2ijUL5H3UTQ6BOc8YyNOd62Kc3EIbj1fpvO6fJnjiTt X-Received: by 2002:a05:6808:1586:b0:3ae:5c48:6f41 with SMTP id t6-20020a056808158600b003ae5c486f41mr14774220oiw.28.1698147454834; Tue, 24 Oct 2023 04:37:34 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1698147454; cv=pass; d=google.com; s=arc-20160816; b=CIlY8Gpr1gogYVysI1ROxGh8OJWBhpaXcBkoVgqYnw2WjWx5FdlYferVk5nC3JJiYb JzjZQ1MSZ0rNCIWpC7dv9MX1+KzjJi+P3bDKU7YRa/+Qwv/vI76Vz3ET6ZfssgP8tCFX Tb0d9xTmZIkhXllDEIyaZoDISGE5ycAA2mIXG5sc3+FkMGFNNiVOXT/ITr1aj5DOS2Zc v16JfHsbHnOj+9U4/oZuobDicWtYPNwBPZhZNOIv8+CfbD+MiJlyY6dVOGoCM6GXhdon sk6CbvX/oQEvdOL6fL+qotIceRB7tyzl7Pndt3LfkmnCARsCgDyFtJo/wUYQzrx8UEGJ LjIw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:arc-filter:dmarc-filter:delivered-to; bh=NOvdAysXA05qPpMnEVH8JkFq4y3flQAfl9BCWlDaPAI=; fh=Rk9vnpDApgYog/EhmGDFyutcQpHXbdLZmc0l8HNU7lw=; b=urjpAvsrO5b8TH8EGehE8cSQ/IGRx4pu4lymAqvsChiwupwGcepJMfoxKbctx4Dw1d CsAwH6q9xGH0glJl1U0RKPT1KlYby0WFtGw1yGJOUncsSeppVBgbiJSv74hKe9oBTIoa pofHT0ZtbwtPEwPE/tx3/5KiYKzT2EmIqFCajPesBau3A9QkaNSbWsI4TkJif1nSR6JP b3cAQ5Evp4VRZNHYpIsDlgUw1xtjaeCUHXI+8yeROUJIpYbc4umb81og0chjN8KMJkDW Wg1iFC+wYXrjNEJTX0vEIBBdlIY53Gbl73fcFFV7xpfox9X9Fol2nWMs3obYERGgS/rB pGrw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=unUOqII5; arc=pass (i=1); spf=pass (google.com: domain of libc-alpha-bounces+patch=linaro.org@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="libc-alpha-bounces+patch=linaro.org@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from server2.sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id v9-20020a05622a144900b004181d34928esi7202633qtx.373.2023.10.24.04.37.34 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Oct 2023 04:37:34 -0700 (PDT) Received-SPF: pass (google.com: domain of libc-alpha-bounces+patch=linaro.org@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=unUOqII5; arc=pass (i=1); spf=pass (google.com: domain of libc-alpha-bounces+patch=linaro.org@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="libc-alpha-bounces+patch=linaro.org@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 7B96C3858433 for ; Tue, 24 Oct 2023 11:37:34 +0000 (GMT) X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from mail-pg1-x529.google.com (mail-pg1-x529.google.com [IPv6:2607:f8b0:4864:20::529]) by sourceware.org (Postfix) with ESMTPS id A64823858C50 for ; Tue, 24 Oct 2023 11:37:26 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org A64823858C50 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linaro.org ARC-Filter: OpenARC Filter v1.0.0 sourceware.org A64823858C50 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::529 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698147448; cv=none; b=QpGKTMrpLX/0fswDsb09XUaHBUh3tdUFRCP9XQRaGqPNATIxgyV729vh8bXI9tTxHMc/QYXI3ql2Wwt+RQX4AFgl8tSZshCc8X3X9Hecax8tuOMQACFIYCExuTkmB617R/+8kFZDrWZ4yYXL585iM0q4ulne2/P+CaTQF8ED/7Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698147448; c=relaxed/simple; bh=BoHvN498rhA/tBAAwfSg43+0rL0NtgPiLxrEzE2+mgk=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=L2i2pfy/oK8FpEZyRZ5lBAiFLwowZi6aaucDLfFeCthDLpa/XJMkQ1he4vKjrF+acL3x8Yy8e0UOMmgpMVpmjywYxhMr8p9Zvy5meRYdKd885OapqQsvEMz3EP+yUP6L62PcxFJD1aAfY9cIbIt6PuHDyFO9YUZRsS9D7eYJ6ag= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-pg1-x529.google.com with SMTP id 41be03b00d2f7-5b8f68ba4e5so112844a12.1 for ; Tue, 24 Oct 2023 04:37:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698147445; x=1698752245; darn=sourceware.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NOvdAysXA05qPpMnEVH8JkFq4y3flQAfl9BCWlDaPAI=; b=unUOqII56St3bNkRekE9UyerBJNve2LMk49G1qvwN/d7L4noaopXZJqS8LntdFvDaT zbjx3X5XejjnIS5W/02ZetCPvPHjIwrxEPrM35wKXRn1rmd2vnhvxrncUcCU5qOvhWTA d5JjhnIPv3+vBJnsByaQ1CFMloN4JoqCYH7k4+ga+zzczMjUN2VxIttE83/cCIARCEeq F5WZWIemUITmeYCBy0RvjHrKwt428QzcX8f87Xg/Fy40SLp+Aap00wyIxWmwW9qGe9ue n0SU/6QPPwJnpZrHCkJCIgRs/zyayjCa3De0txPkJo4GWdxekAzzjB2rpYgbUy/HiYkb h8Qg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698147445; x=1698752245; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NOvdAysXA05qPpMnEVH8JkFq4y3flQAfl9BCWlDaPAI=; b=LBN0OrPyVj9jikRZNkUAKhzXbVQAhwvkBxD6Cnr//Cxw+OQuMafnOsKfVqWpaQiAcd mHaf72oCZeoY4BSTkUrq666Nptg5UWxN7iTDzUtldlIsjmyF65I0MEMfZM5WaXbmnS+/ L46QR+kt5yzCw+gnva1q/tdCOHSokBpO932k2A/P7V47yYaWb6CPo3FhvjD9itnrlVIb EIdSlhMahUyXsTchxKIOnMj3jDU1NrhUtKK++EPtyTzRgb0MxTt0DQv7NqVWjsIPeE+H swb7UxcBJhNh9DneLogRfcRw9ZK+p2B6+uhI4OtT2MDx0URn1uTRZ5D4qyDlBUwmIrC9 1EFQ== X-Gm-Message-State: AOJu0YzFAlXs7EaTg58Qdxv/gB9OBl475229z+iEi8y3nIXHV3kN4crX UnD5VMBSzkDkM+lDZ1GLerMlwx0dAeeBcvbscvmviQ== X-Received: by 2002:a05:6a20:7287:b0:17b:2b7e:923c with SMTP id o7-20020a056a20728700b0017b2b7e923cmr2651299pzk.16.1698147445144; Tue, 24 Oct 2023 04:37:25 -0700 (PDT) Received: from mandiga.. ([2804:1b3:a7c3:a647:44d5:84b0:a3f2:fe73]) by smtp.gmail.com with ESMTPSA id k28-20020aa79d1c000000b006bde2480806sm7506663pfp.47.2023.10.24.04.37.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Oct 2023 04:37:24 -0700 (PDT) From: Adhemerval Zanella To: libc-alpha@sourceware.org Cc: Bruno Haible Subject: [PATCH v2 1/3] powerpc: Do not raise exception traps for fesetexcept/fesetexceptflag (BZ 30988) Date: Tue, 24 Oct 2023 08:37:14 -0300 Message-Id: <20231024113716.3911015-2-adhemerval.zanella@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231024113716.3911015-1-adhemerval.zanella@linaro.org> References: <20231024113716.3911015-1-adhemerval.zanella@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: libc-alpha-bounces+patch=linaro.org@sourceware.org According to ISO C23 (7.6.4.4), fesetexcept is supposed to set floating-point exception flags without raising a trap (unlike feraiseexcept, which is supposed to raise a trap if feenableexcept was called with the appropriate argument). This is a side-effect of how we implement the GNU extension feenableexcept, where feenableexcept/fesetenv/fesetmode/feupdateenv might issue prctl (PR_SET_FPEXC, PR_FP_EXC_PRECISE) depending of the argument. And on PR_FP_EXC_PRECISE, setting a floating-point exception flag triggers a trap. To make the both functions follow the C23, fesetexcept and fesetexceptflag now fail if the argument may trigger a trap. The math tests now check for an value different than 0, instead of bail out as unsupported for EXCEPTION_SET_FORCES_TRAP. Checked on powerpc64le-linux-gnu. --- math/test-fesetexcept-traps.c | 11 ++++------- math/test-fexcept-traps.c | 11 ++++------- sysdeps/powerpc/fpu/fesetexcept.c | 5 +++++ sysdeps/powerpc/fpu/fsetexcptflg.c | 9 ++++++++- 4 files changed, 21 insertions(+), 15 deletions(-) diff --git a/math/test-fesetexcept-traps.c b/math/test-fesetexcept-traps.c index 71b6e45b33..96f6c4752f 100644 --- a/math/test-fesetexcept-traps.c +++ b/math/test-fesetexcept-traps.c @@ -39,16 +39,13 @@ do_test (void) return result; } - if (EXCEPTION_SET_FORCES_TRAP) - { - puts ("setting exceptions traps, cannot test on this architecture"); - return 77; - } - /* Verify fesetexcept does not cause exception traps. */ + /* Verify fesetexcept does not cause exception traps. For architectures + where setting the exception might result in traps the function should + return a nonzero value. */ ret = fesetexcept (FE_ALL_EXCEPT); if (ret == 0) puts ("fesetexcept (FE_ALL_EXCEPT) succeeded"); - else + else if (!EXCEPTION_SET_FORCES_TRAP) { puts ("fesetexcept (FE_ALL_EXCEPT) failed"); if (EXCEPTION_TESTS (float)) diff --git a/math/test-fexcept-traps.c b/math/test-fexcept-traps.c index 9701c3c320..9b8f583ae6 100644 --- a/math/test-fexcept-traps.c +++ b/math/test-fexcept-traps.c @@ -63,14 +63,11 @@ do_test (void) result = 1; } - if (EXCEPTION_SET_FORCES_TRAP) - { - puts ("setting exceptions traps, cannot test on this architecture"); - return 77; - } - /* The test is that this does not cause exception traps. */ + /* The test is that this does not cause exception traps. For architectures + where setting the exception might result in traps the function should + return a nonzero value. */ ret = fesetexceptflag (&saved, FE_ALL_EXCEPT); - if (ret != 0) + if (ret != 0 && !EXCEPTION_SET_FORCES_TRAP) { puts ("fesetexceptflag failed"); result = 1; diff --git a/sysdeps/powerpc/fpu/fesetexcept.c b/sysdeps/powerpc/fpu/fesetexcept.c index 609a148a95..2850156d3a 100644 --- a/sysdeps/powerpc/fpu/fesetexcept.c +++ b/sysdeps/powerpc/fpu/fesetexcept.c @@ -31,6 +31,11 @@ fesetexcept (int excepts) & FE_INVALID_SOFTWARE)); if (n.l != u.l) { + if (n.l & fenv_exceptions_to_reg (excepts)) + /* Setting the exception flags may trigger a trap. ISO C 23 § 7.6.4.4 + does not allow it. */ + return -1; + fesetenv_register (n.fenv); /* Deal with FE_INVALID_SOFTWARE not being implemented on some chips. */ diff --git a/sysdeps/powerpc/fpu/fsetexcptflg.c b/sysdeps/powerpc/fpu/fsetexcptflg.c index 2b22f913c0..6517e8ea03 100644 --- a/sysdeps/powerpc/fpu/fsetexcptflg.c +++ b/sysdeps/powerpc/fpu/fsetexcptflg.c @@ -44,7 +44,14 @@ __fesetexceptflag (const fexcept_t *flagp, int excepts) This may cause floating-point exceptions if the restored state requests it. */ if (n.l != u.l) - fesetenv_register (n.fenv); + { + if (n.l & fenv_exceptions_to_reg (excepts)) + /* Setting the exception flags may trigger a trap. ISO C 23 § 7.6.4.4 + does not allow it. */ + return -1; + + fesetenv_register (n.fenv); + } /* Deal with FE_INVALID_SOFTWARE not being implemented on some chips. */ if (flag & FE_INVALID) From patchwork Tue Oct 24 11:37:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adhemerval Zanella X-Patchwork-Id: 737535 Delivered-To: patch@linaro.org Received: by 2002:adf:dd81:0:b0:32d:baff:b0ca with SMTP id x1csp1978019wrl; Tue, 24 Oct 2023 04:37:36 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHe7ZN2f+TRIylmF+8fcRFIYKUpIDKG1aRp+S2Z+PDr4mTDyC1vxExK2yfa5kdGbJopRRSD X-Received: by 2002:a05:622a:24f:b0:41c:e161:c99a with SMTP id c15-20020a05622a024f00b0041ce161c99amr10425645qtx.56.1698147455996; Tue, 24 Oct 2023 04:37:35 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1698147455; cv=pass; d=google.com; s=arc-20160816; b=PlPK5tSF/Tb9/4YrjdtfwKlv7ZzRMDUPg/0fwUAhU2+I/fMPsyUiy/gWEEjkdkMCct HPGhyNl9OmGmpYUwgVweLC5XX1XUWmHa0TGn86cS3YRUshxyEj/8nvNA9FxIzXcwboOy oD5lkTK1Q0XqmIbjMsR+8/m4v+JqVI5RrEyqlagPdgy0br8f+PG1L0jGtKCKZ0Mbs8QY CotsYT7yhzQME5kv+OPQ5vf9ScItvkAprLWIs43H5060pt78ehcavW0MPEAqg0w6/1wl VPn+ewYvAZaXrHG5bLfuqxT4ZHApr1FMHAG10CkThg71DLKcqoJBBdTufcKkLnDSSLXL Cu8A== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:arc-filter:dmarc-filter:delivered-to; bh=xyN0+MPmXPFjdAwhfIEaZ5KCieYNszKZx9zB2QRUtIw=; fh=Rk9vnpDApgYog/EhmGDFyutcQpHXbdLZmc0l8HNU7lw=; b=pCtyw14e1BUPbn1oNTxjaQdps6HP/kQ0juh5RWgmmdSG3fPnBQUw+1vQcrN0Tf6KkW XGgQAUssqDO0EwJHTG0O8BAmaoLioN5pOQP3giPqgQD32Yo4NMYVwcuHVNsy2gpc0dDz EZdMw/+xxG8vpqE1HorgEldKyylDACWtcACuhyomkKYNncl+p752QhcVHSTZ8aYe0z/Q 5sZpbmGXF2VcDE0UrWZ4wKHhRL+cQG8PjcMbVryEmY61p/a8YhCXps1pix9WwsdL1/Lb HOMBVfZaFjv6EjikhQa6cyiITHBFowR1ufyXYab+4PD4Nn4eFM+h0IZP1tC/CKkfICoU St6w== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=YZ7vaKTy; arc=pass (i=1); spf=pass (google.com: domain of libc-alpha-bounces+patch=linaro.org@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="libc-alpha-bounces+patch=linaro.org@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from server2.sourceware.org (server2.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id p8-20020a05622a13c800b0041820c4f419si7059597qtk.782.2023.10.24.04.37.35 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Oct 2023 04:37:35 -0700 (PDT) Received-SPF: pass (google.com: domain of libc-alpha-bounces+patch=linaro.org@sourceware.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=YZ7vaKTy; arc=pass (i=1); spf=pass (google.com: domain of libc-alpha-bounces+patch=linaro.org@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="libc-alpha-bounces+patch=linaro.org@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id A2D5938582B7 for ; Tue, 24 Oct 2023 11:37:35 +0000 (GMT) X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from mail-pg1-x52e.google.com (mail-pg1-x52e.google.com [IPv6:2607:f8b0:4864:20::52e]) by sourceware.org (Postfix) with ESMTPS id B22A93858C2C for ; Tue, 24 Oct 2023 11:37:28 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org B22A93858C2C Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linaro.org ARC-Filter: OpenARC Filter v1.0.0 sourceware.org B22A93858C2C Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::52e ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698147450; cv=none; b=re55Iw+rcc8ITX/ZgqDqfBBsQLw2OIjibeXm1gksWXq4gVZiu6wgeezffZ6hbVyueMm2TASic0fe1n6yZIqPfIdx1wo5UUAVQ2/whMIedLwvEUTqxSOcX4MIIv/jNmR/cXE+2tSoD2+0e0TFS+IfBwumYIkbFfCJ+e/FgvzyCw8= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698147450; c=relaxed/simple; bh=F5dZBtGI0oHO9/8EX6VjjBDGl5NVNM4NeMvraHeIR54=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=Y/895SK40Icb+5HjK8Mjki/NAGwU/GTeriA/iasEoLxGxBRS3CxQxG6mzuoh/JLqp/bzepzeK0aVjmAs0cnv91VETSGP/JatZozpyq0x6kI0RlI+OieRYs6Zknes6JBFXgG2RJNCS8J7rb4gI41zATK015+G5BVU33XPchCVRDE= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-pg1-x52e.google.com with SMTP id 41be03b00d2f7-5ab94fc098cso2522385a12.1 for ; Tue, 24 Oct 2023 04:37:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698147447; x=1698752247; darn=sourceware.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xyN0+MPmXPFjdAwhfIEaZ5KCieYNszKZx9zB2QRUtIw=; b=YZ7vaKTyMmBuiUNCKjknCoYUD+vwgfQss6CooGnYz/CLl8LAh8CVmpDxU3axLr3z1T ghY372hGi5nQs8QeNjtwvIeyiN2yrFjr45U31wHMqtZNo9yeHWvx09nMC+yE8Q/ogL+N N43ann2NiqwXOEhdIc9cNYBPQZJCHFA5Lq0LDvkQWpaTxMUOp15RzUkdjs8coYOcGFeD rvYqcKsPh4pX6PpzVRXDog4rajATnVoBBTECoLBFiqX53fYUNJLKXL4ULiKfZb1BbhAo CH2Ng2ZX1I/oXMGj1nOUGJLiW03m3B1CuNeZ/oxrPVuzEPd/2WHqco4VxXYUrFF/+8X7 Nc+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698147447; x=1698752247; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xyN0+MPmXPFjdAwhfIEaZ5KCieYNszKZx9zB2QRUtIw=; b=nRQnFWr0zB/bQirv7XDe3R9iwHyO6u5BW7/zNZifNwuJ38ULyrx3i2CZyNyMAx8X9R WO9NoYsccLTbyGEXfCH38yk7kbl3/iaeKV7wa/n76eTzTCkTbYdmaR06CW0HOCtk8BfH qQGNnoN/Au8Mz001z5V3FP90ma76LU7IlaDElUc3NoYgtl+t/Ao45bPndQLvau+7/qp+ G5aSk1uRZwtHsLDK0sR3L+LMU68RImFqkPCPC8UOU/4dA3p53QqxzaUq2PwbklnKyxXM v5q66Ec3HVnENOXefi7jJkpRWm/IH9YEV8/9DsohcjgEViZJbfBVcBkO8xG/nSXyPTjM 69Jg== X-Gm-Message-State: AOJu0YwqW8phYrbMMHWuNa6CwOH6kS9QOk64nxNH6APMG7QzLRP72MzI CWSR6OipVkLPeKXLNRLRJ5Wu7GKfQsJ28MOgnz3uwg== X-Received: by 2002:a05:6a20:258a:b0:161:76a4:4f79 with SMTP id k10-20020a056a20258a00b0016176a44f79mr2379434pzd.23.1698147447128; Tue, 24 Oct 2023 04:37:27 -0700 (PDT) Received: from mandiga.. ([2804:1b3:a7c3:a647:44d5:84b0:a3f2:fe73]) by smtp.gmail.com with ESMTPSA id k28-20020aa79d1c000000b006bde2480806sm7506663pfp.47.2023.10.24.04.37.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Oct 2023 04:37:26 -0700 (PDT) From: Adhemerval Zanella To: libc-alpha@sourceware.org Cc: Bruno Haible Subject: [PATCH v2 2/3] i686: Do not raise exception traps on fesetexcept (BZ 30989) Date: Tue, 24 Oct 2023 08:37:15 -0300 Message-Id: <20231024113716.3911015-3-adhemerval.zanella@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231024113716.3911015-1-adhemerval.zanella@linaro.org> References: <20231024113716.3911015-1-adhemerval.zanella@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-12.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: libc-alpha-bounces+patch=linaro.org@sourceware.org According to ISO C23 (7.6.4.4), fesetexcept is supposed to set floating-point exception flags without raising a trap (unlike feraiseexcept, which is supposed to raise a trap if feenableexcept was called with the appropriate argument). The flags can be set in the 387 unit or in the SSE unit. To set a flag, it is sufficient to do it in the SSE unit, because that is guaranteed to not trap. However, on i386 CPUs that have only a 387 unit, set the flags in the 387, as long as this cannot trap. Checked on i686-linux-gnu. --- math/test-fesetexcept-traps.c | 11 +++++++ sysdeps/i386/fpu/fesetexcept.c | 41 +++++++++++++++++++++--- sysdeps/i386/fpu/math-tests-trap-force.h | 29 +++++++++++++++++ 3 files changed, 77 insertions(+), 4 deletions(-) create mode 100644 sysdeps/i386/fpu/math-tests-trap-force.h diff --git a/math/test-fesetexcept-traps.c b/math/test-fesetexcept-traps.c index 96f6c4752f..2f63e9ba23 100644 --- a/math/test-fesetexcept-traps.c +++ b/math/test-fesetexcept-traps.c @@ -19,6 +19,7 @@ #include #include #include +#include static int do_test (void) @@ -43,6 +44,16 @@ do_test (void) where setting the exception might result in traps the function should return a nonzero value. */ ret = fesetexcept (FE_ALL_EXCEPT); + + /* Execute some floating-point operations, since on some CPUs exceptions + triggers a trap only at the next floating-point instruction. */ + volatile double a = 1.0; + volatile double b = a + a; + math_force_eval (b); + volatile long double al = 1.0L; + volatile long double bl = al + al; + math_force_eval (bl); + if (ret == 0) puts ("fesetexcept (FE_ALL_EXCEPT) succeeded"); else if (!EXCEPTION_SET_FORCES_TRAP) diff --git a/sysdeps/i386/fpu/fesetexcept.c b/sysdeps/i386/fpu/fesetexcept.c index 18949e982a..6eeb5ab5b0 100644 --- a/sysdeps/i386/fpu/fesetexcept.c +++ b/sysdeps/i386/fpu/fesetexcept.c @@ -17,15 +17,48 @@ . */ #include +#include int fesetexcept (int excepts) { - fenv_t temp; + /* The flags can be set in the 387 unit or in the SSE unit. To set a flag, + it is sufficient to do it in the SSE unit, because that is guaranteed to + not trap. However, on i386 CPUs that have only a 387 unit, set the flags + in the 387, as long as this cannot trap. */ - __asm__ ("fnstenv %0" : "=m" (*&temp)); - temp.__status_word |= excepts & FE_ALL_EXCEPT; - __asm__ ("fldenv %0" : : "m" (*&temp)); + excepts &= FE_ALL_EXCEPT; + + if (CPU_FEATURE_USABLE (SSE)) + { + /* And now similarly for SSE. */ + unsigned int mxcsr; + __asm__ ("stmxcsr %0" : "=m" (*&mxcsr)); + + /* Set relevant flags. */ + mxcsr |= excepts; + + /* Put the new data in effect. */ + __asm__ ("ldmxcsr %0" : : "m" (*&mxcsr)); + } + else + { + fenv_t temp; + + __asm__ ("fnstenv %0" : "=m" (*&temp)); + + /* Clear or set relevant flags. */ + temp.__status_word |= temp.__status_word & excepts; + + if ((~temp.__control_word) & excepts) + /* Setting the exception flags may trigger a trap (at the next + floating-point instruction, but that does not matter). + ISO C23 (7.6.4.4) does not allow it. */ + return -1; + + /* Store the new status word (along with the rest of the environment). */ + __asm__ ("fldenv %0" : : "m" (*&temp)); + } return 0; } diff --git a/sysdeps/i386/fpu/math-tests-trap-force.h b/sysdeps/i386/fpu/math-tests-trap-force.h new file mode 100644 index 0000000000..20f4ead98d --- /dev/null +++ b/sysdeps/i386/fpu/math-tests-trap-force.h @@ -0,0 +1,29 @@ +/* Configuration for math tests: support for setting exception flags + without causing enabled traps. i686 version. + Copyright (C) 2023 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + . */ + +#ifndef I386_FPU_MATH_TESTS_TRAP_FORCE_H +#define I386_FPU_MATH_TESTS_TRAP_FORCE_H 1 + +#include + +/* Setting exception flags in FPU Status Register results in enabled traps for + those exceptions being taken. */ +#define EXCEPTION_SET_FORCES_TRAP (CPU_FEATURE_USABLE (SSE)) + +#endif /* math-tests-trap-force.h. */ From patchwork Tue Oct 24 11:37:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Adhemerval Zanella X-Patchwork-Id: 737536 Delivered-To: patch@linaro.org Received: by 2002:adf:dd81:0:b0:32d:baff:b0ca with SMTP id x1csp1978513wrl; Tue, 24 Oct 2023 04:38:59 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHaxllRfoNKtxDhTFYVG3yg0c95DJPKSCwD4i8n2pt/5eHLRrIaqBN7q848ZTr0sOnuYhh2 X-Received: by 2002:a05:6214:da7:b0:65a:fcc7:d77 with SMTP id h7-20020a0562140da700b0065afcc70d77mr14035573qvh.55.1698147539636; Tue, 24 Oct 2023 04:38:59 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1698147539; cv=pass; d=google.com; s=arc-20160816; b=GhKQ3LDJ7NK9NEE9SZaeZ2vqIz8nqGHZPh3eRYRLKZl+KWbRZrlhXiq9XSD5kqCuoO W7uhHG0P7iSyc/a1118vl8Z8FguE9ccZHlrv+itC9LyWRr0OrVB8ZNMT3kI1ySn9zAgR 1/12RWyQiUuJMA/shF8aL6EpVVRn/tuNZtFtb+BiTcIRvpfKJsSXB0wQKoE/p3RVgLkp thxTKkgIzS2eAZ86dEFWKh8qVpZ9p+zLbxQCvls9FXaUQcXjX+07uPWJXNuoCefltyLA U0oCHOZFXbvCdiFKUKgB9EA/cL+/KS2VMfTtdQg4cbg3DXMOTrWFjq0W2Kh7cV/Zb9WP /DCA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:arc-filter:dmarc-filter:delivered-to; bh=Gddms76rhRzGJL+ypGhaxMa8z8FDoni+edQVUGF+F0E=; fh=Rk9vnpDApgYog/EhmGDFyutcQpHXbdLZmc0l8HNU7lw=; b=hWFj9y8XTexBQ3jGgDkmJwWiJGH91BxJ6/TsZPy40v2VdLVpSe1QfieZPEJ1Liq+RZ 5f6FfVtbSrtetjAjSt//qPw0GAgLZmXzV0BHmtSwKkzqAG+pHmMgJO1eG3sZUfWQqlHa 0A0attFJxxd0VjUtAGiEq5/Vk9UeJ+RJOlOJdsJKYZezqqKk/EFj+HD8HfoSsbKpZ5dM 6Wo+L514Tk4ug9kQ1gObzIBJhpXcsMbRD9ku+9JRf50T6zvH2ZGrnCDD7Eq3CMxxlfkN +tg8t6nrQvU3uMKJ6cCA5CQ69NqoeusXw5mY/LmHxcztu5grUP4ghD8Ito4N16TT0ANz 42pg== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QhMAr61D; arc=pass (i=1); spf=pass (google.com: domain of libc-alpha-bounces+patch=linaro.org@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="libc-alpha-bounces+patch=linaro.org@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from server2.sourceware.org (server2.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id da18-20020a05621408d200b0065b2d89bd70si6843327qvb.522.2023.10.24.04.38.59 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Oct 2023 04:38:59 -0700 (PDT) Received-SPF: pass (google.com: domain of libc-alpha-bounces+patch=linaro.org@sourceware.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QhMAr61D; arc=pass (i=1); spf=pass (google.com: domain of libc-alpha-bounces+patch=linaro.org@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="libc-alpha-bounces+patch=linaro.org@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 2EA303856DC6 for ; Tue, 24 Oct 2023 11:38:59 +0000 (GMT) X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from mail-pg1-x533.google.com (mail-pg1-x533.google.com [IPv6:2607:f8b0:4864:20::533]) by sourceware.org (Postfix) with ESMTPS id C7C3D3858CDA for ; Tue, 24 Oct 2023 11:38:51 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org C7C3D3858CDA Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linaro.org ARC-Filter: OpenARC Filter v1.0.0 sourceware.org C7C3D3858CDA Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::533 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698147533; cv=none; b=tzwXfXgfgaUZZT8wLPr+0mkrOF06Ug4p+MLP+Lvjsvcj+LpYeKAI8iwX2K+ElDSSIS5OnlKjhdkqPag4IN3euj1HtyTbNbIw0k5Ky4JA+GfoNJ2gbAefAKcu4HFVC5N8xYysndZ2eJ+sytmDWxgpK4Pt1pWzgJV00U3JC0a3mg0= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698147533; c=relaxed/simple; bh=lEwbYBQph18tUUfmlxgyUMDyN+LkoVe3f6Ln9xKesf0=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=BTsW1w/2EF7Dq8FGiXZx0TPMV4SEt3Ohe3gIqqZ/0tlozhmYN8h2y0qG6L9sKzIZNcy6N5jJ7ka8ShfdDfv/92mHB1t42as5iCPBzNBqFMkcHEPVd0A24OeicJ38i+0Xa5+ZUi1wSNi7GFzKA/mGQqpesrftenjYbegMCejd7Qw= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-pg1-x533.google.com with SMTP id 41be03b00d2f7-53fa455cd94so2680728a12.2 for ; Tue, 24 Oct 2023 04:38:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698147530; x=1698752330; darn=sourceware.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Gddms76rhRzGJL+ypGhaxMa8z8FDoni+edQVUGF+F0E=; b=QhMAr61DDaCKgn6OsubtIBpoKmDSUQAtWIgCMn9/5GhfJXkQYJ7bRSHL0I4gB/dQNx 0XVV3AO+oKsa7+xiiRxJBMlZHvGNoUw0s2V0BGEmHU9YCrXFppe7wZrwo21vbhxk1DuA CjJ1qOWU3yvValh8ssmhGvEcPbmnpbiJ1P7ta+R0D1IVrPuzZWPemHfoiS0WcyePQLLx Fvqh4l94HIzlyeBKQpxeORSrbJxufwxBzwrIKlYfS5Sw+15I6Joz/NNsPRQqdexNq6IZ s4O+/kLnrMpmvVaRBc4Rb8e/i/reciy6r55avnI/Rn1ssDyXn9WeWIdFx6wWPJvP21zu 0xQA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698147530; x=1698752330; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Gddms76rhRzGJL+ypGhaxMa8z8FDoni+edQVUGF+F0E=; b=bs1lFCx3V8e+yMijjRppgfA7pjEj9P3H8+aCA6lCcNoKeQNcbivtdEOuJ4oBMxNDWo xUV4yJdtEvJpB+GyXvcvlvmrs+xxPY4ScQmRo1ZSQ8tykgMheqjkoMr3Wh86Q6CWnLnl tnoJSc3x9kaceslKKt4FePKFW9qmQXk+5aXW6ioFZRWeEilnUAx0eWHLc6xFU24iDYvd xq8nYkMQas1V69XrVbAYVlD5V9MSMc5RCdjQxah0YyBUL6yfS+54682mtCmntp++2vy3 0gfVcBXnbp4BaygJhASKvfd6S3AGyLeCmZ2L4X0qCg5wIlvnb8tdmR+YTvRXUb73+GP7 MtcA== X-Gm-Message-State: AOJu0YyBtMHK418s+b6jtuXL+yP2aXvlpxyiqkuF/do0Ded8zJ3TP9mF NwJdDMT/33oClc7K1n/XyV2tZ089QDxgtU8ltNNZ7g== X-Received: by 2002:a05:6a21:35c6:b0:17b:63ce:5b84 with SMTP id ba6-20020a056a2135c600b0017b63ce5b84mr2268222pzc.52.1698147530238; Tue, 24 Oct 2023 04:38:50 -0700 (PDT) Received: from mandiga.. ([2804:1b3:a7c3:a647:44d5:84b0:a3f2:fe73]) by smtp.gmail.com with ESMTPSA id k28-20020aa79d1c000000b006bde2480806sm7506663pfp.47.2023.10.24.04.38.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Oct 2023 04:38:49 -0700 (PDT) From: Adhemerval Zanella To: libc-alpha@sourceware.org Cc: Bruno Haible Subject: [PATCH v2 3/3] x86: Do not raises floating-point exception traps on fesetexceptflag (BZ 30990) Date: Tue, 24 Oct 2023 08:37:16 -0300 Message-Id: <20231024113716.3911015-4-adhemerval.zanella@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231024113716.3911015-1-adhemerval.zanella@linaro.org> References: <20231024113716.3911015-1-adhemerval.zanella@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: libc-alpha-bounces+patch=linaro.org@sourceware.org From: Bruno Haible According to ISO C23 (7.6.4.4), fesetexcept is supposed to set floating-point exception flags without raising a trap (unlike feraiseexcept, which is supposed to raise a trap if feenableexcept was called with the appropriate argument). The flags can be set in the 387 unit or in the SSE unit. When we need to clear a flag, we need to do so in both units, due to the way fetestexcept is implemented. When we need to set a flag, it is sufficient to do it in the SSE unit, because that is guaranteed to not trap. However, on i386 CPUs that have only a 387 unit, set the flags in the 387, as long as this cannot trap. Co-authored-by: Adhemerval Zanella --- math/test-fexcept-traps.c | 11 ++++++ sysdeps/i386/fpu/fsetexcptflg.c | 58 ++++++++++++++++++++----------- sysdeps/x86_64/fpu/fsetexcptflg.c | 24 +++++++------ 3 files changed, 62 insertions(+), 31 deletions(-) diff --git a/math/test-fexcept-traps.c b/math/test-fexcept-traps.c index 9b8f583ae6..f10bf2d9a3 100644 --- a/math/test-fexcept-traps.c +++ b/math/test-fexcept-traps.c @@ -19,6 +19,7 @@ #include #include #include +#include static int do_test (void) @@ -67,6 +68,16 @@ do_test (void) where setting the exception might result in traps the function should return a nonzero value. */ ret = fesetexceptflag (&saved, FE_ALL_EXCEPT); + + /* Execute some floating-point operations, since on some CPUs exceptions + triggers a trap only at the next floating-point instruction. */ + volatile double a = 1.0; + volatile double b = a + a; + math_force_eval (b); + volatile long double al = 1.0L; + volatile long double bl = al + al; + math_force_eval (bl); + if (ret != 0 && !EXCEPTION_SET_FORCES_TRAP) { puts ("fesetexceptflag failed"); diff --git a/sysdeps/i386/fpu/fsetexcptflg.c b/sysdeps/i386/fpu/fsetexcptflg.c index e724b7d6fd..ccbcf35e8e 100644 --- a/sysdeps/i386/fpu/fsetexcptflg.c +++ b/sysdeps/i386/fpu/fsetexcptflg.c @@ -17,42 +17,58 @@ . */ #include -#include -#include #include -#include int __fesetexceptflag (const fexcept_t *flagp, int excepts) { - fenv_t temp; + /* The flags can be set in the 387 unit or in the SSE unit. When we need to + clear a flag, we need to do so in both units, due to the way fetestexcept + is implemented. + When we need to set a flag, it is sufficient to do it in the SSE unit, + because that is guaranteed to not trap. However, on i386 CPUs that have + only a 387 unit, set the flags in the 387, as long as this cannot trap. */ - /* Get the current environment. We have to do this since we cannot - separately set the status word. */ - __asm__ ("fnstenv %0" : "=m" (*&temp)); + fenv_t temp; - temp.__status_word &= ~(excepts & FE_ALL_EXCEPT); - temp.__status_word |= *flagp & excepts & FE_ALL_EXCEPT; + excepts &= FE_ALL_EXCEPT; - /* Store the new status word (along with the rest of the environment. - Possibly new exceptions are set but they won't get executed unless - the next floating-point instruction. */ - __asm__ ("fldenv %0" : : "m" (*&temp)); + /* Get the current x87 FPU environment. We have to do this since we + cannot separately set the status word. */ + __asm__ ("fnstenv %0" : "=m" (*&temp)); - /* If the CPU supports SSE, we set the MXCSR as well. */ if (CPU_FEATURE_USABLE (SSE)) { - unsigned int xnew_exc; + unsigned int mxcsr; + + /* Clear relevant flags. */ + temp.__status_word &= ~(excepts & ~ *flagp); - /* Get the current MXCSR. */ - __asm__ ("stmxcsr %0" : "=m" (*&xnew_exc)); + /* Store the new status word (along with the rest of the environment). */ + __asm__ ("fldenv %0" : : "m" (*&temp)); - /* Set the relevant bits. */ - xnew_exc &= ~(excepts & FE_ALL_EXCEPT); - xnew_exc |= *flagp & excepts & FE_ALL_EXCEPT; + /* And now similarly for SSE. */ + __asm__ ("stmxcsr %0" : "=m" (*&mxcsr)); + + /* Clear or set relevant flags. */ + mxcsr ^= (mxcsr ^ *flagp) & excepts; /* Put the new data in effect. */ - __asm__ ("ldmxcsr %0" : : "m" (*&xnew_exc)); + __asm__ ("ldmxcsr %0" : : "m" (*&mxcsr)); + } + else + { + /* Clear or set relevant flags. */ + temp.__status_word ^= (temp.__status_word ^ *flagp) & excepts; + + if ((~temp.__control_word) & temp.__status_word & excepts) + /* Setting the exception flags may trigger a trap (at the next + floating-point instruction, but that does not matter). + ISO C 23 § 7.6.4.5 does not allow it. */ + return -1; + + /* Store the new status word (along with the rest of the environment). */ + __asm__ ("fldenv %0" : : "m" (*&temp)); } /* Success. */ diff --git a/sysdeps/x86_64/fpu/fsetexcptflg.c b/sysdeps/x86_64/fpu/fsetexcptflg.c index a3ac1dea01..2ce2b509f2 100644 --- a/sysdeps/x86_64/fpu/fsetexcptflg.c +++ b/sysdeps/x86_64/fpu/fsetexcptflg.c @@ -22,30 +22,34 @@ int fesetexceptflag (const fexcept_t *flagp, int excepts) { + /* The flags can be set in the 387 unit or in the SSE unit. + When we need to clear a flag, we need to do so in both units, + due to the way fetestexcept() is implemented. + When we need to set a flag, it is sufficient to do it in the SSE unit, + because that is guaranteed to not trap. */ + fenv_t temp; unsigned int mxcsr; - /* XXX: Do we really need to set both the exception in both units? - Shouldn't it be enough to set only the SSE unit? */ + excepts &= FE_ALL_EXCEPT; /* Get the current x87 FPU environment. We have to do this since we cannot separately set the status word. */ __asm__ ("fnstenv %0" : "=m" (*&temp)); - temp.__status_word &= ~(excepts & FE_ALL_EXCEPT); - temp.__status_word |= *flagp & excepts & FE_ALL_EXCEPT; + /* Clear relevant flags. */ + temp.__status_word &= ~(excepts & ~ *flagp); - /* Store the new status word (along with the rest of the environment. - Possibly new exceptions are set but they won't get executed unless - the next floating-point instruction. */ + /* Store the new status word (along with the rest of the environment). */ __asm__ ("fldenv %0" : : "m" (*&temp)); - /* And now the same for SSE. */ + /* And now similarly for SSE. */ __asm__ ("stmxcsr %0" : "=m" (*&mxcsr)); - mxcsr &= ~(excepts & FE_ALL_EXCEPT); - mxcsr |= *flagp & excepts & FE_ALL_EXCEPT; + /* Clear or set relevant flags. */ + mxcsr ^= (mxcsr ^ *flagp) & excepts; + /* Put the new data in effect. */ __asm__ ("ldmxcsr %0" : : "m" (*&mxcsr)); /* Success. */