From patchwork Thu Oct 26 04:13:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 738314 Delivered-To: patch@linaro.org Received: by 2002:adf:f842:0:b0:32d:baff:b0ca with SMTP id d2csp618133wrq; Wed, 25 Oct 2023 21:15:34 -0700 (PDT) X-Google-Smtp-Source: AGHT+IG/9vFvWJFHSRNiDQvfux6GM+VPkmSBmcJZosC3eSKMhUfSInxXsB0g1GHJa+RGpes9A/+n X-Received: by 2002:a05:6214:418a:b0:66d:327:bf8f with SMTP id ld10-20020a056214418a00b0066d0327bf8fmr1934120qvb.30.1698293733835; Wed, 25 Oct 2023 21:15:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698293733; cv=none; d=google.com; s=arc-20160816; b=bIDd7QQ16cmFlRqH60vyw89cNPbkpZ0cbDpuK7FXxPpA+wc/8xkypklsWdxRY8KN4y oah4kU5iZyusS70LaW2MgC+KmIjIfdcABym+z+XzRavj8b0RCAmXvl+tFOTAAH0HMe2k WmDW5HuO6A1JItEQg5+HZ0KfPhlwnakF0YNwbOqoJlLA5rixdoThk/qTwsw50/OevpUh rmc9DvDkdUFMGJUfu9UuxUZJkbNErJIMerUp4OdMu1nskF+uf3mnjR+fhA/D1JV/Poll FzU/XG/sYEyl482FtRvE3gMOw6zsTLs14GVlnRn4b/pJNViwxZG1o9RtJ1kaYUyBETQH rAXQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=d8cKsWxi6jZjQFiHXDa1qsNnGyql4JqYL/7owK3wgPQ=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=u0yS2a64Bs2IwLE2o88dG3+Bbj9tnClSIvX1umXkGo0CUlZY+Y1qTj0qSutKALH92f AvMrvHc6md/vqnsNsSSl2w3C+aW3+TcB5Xf4qBjoe/OGyAIb9UiPlaHNDs/qPThaoowm MtZXJQELpZ1vbec+lvAFPXx1+IdXBnDs2vpoyfwvsfgBg2b+WHaGQTupgDJ3TP7QwIAc 0UeLvS6JawdpcJ7+7f1u0T9bRfOJVCEEhZquXl+Dag3YZT+Qqdv5CqqHQWOk6NXA1XMO 80ifa3dEK3jAEd1VBe/FODUGGj+jV+xGmBRnH4ZfQAoNUTggBQNV9imjNC2XZg8QQL23 mgNg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iSmAw9Pz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id dw8-20020a0562140a0800b0065b18d336aesi9067607qvb.105.2023.10.25.21.15.33 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 25 Oct 2023 21:15:33 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iSmAw9Pz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qvrl7-0002Vl-R4; Thu, 26 Oct 2023 00:14:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qvrl6-0002V5-3c for qemu-devel@nongnu.org; Thu, 26 Oct 2023 00:14:12 -0400 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qvrl2-0000it-Kk for qemu-devel@nongnu.org; Thu, 26 Oct 2023 00:14:11 -0400 Received: by mail-pl1-x62a.google.com with SMTP id d9443c01a7336-1ca74e77aecso11999975ad.1 for ; Wed, 25 Oct 2023 21:14:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698293646; x=1698898446; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=d8cKsWxi6jZjQFiHXDa1qsNnGyql4JqYL/7owK3wgPQ=; b=iSmAw9Pzd6PQet8+1y1UAwpkHHREY31d5ham6j9c6F0TooNVM44UjkpmgmmttnCayM d8dGieAxcC5vxZjhH6vJEXZbOdS0gCv2yX0kmhK3Tho1NpQfpva5w7Oh7Sco2Vwbk5WV Ro5Z2dIhFxxUqUlZFapS4YqEuOQ3+DtjGfqQNAq3Cx+wrVh3ulynDYr2B5QvCkiSg4gs xxpbBIq24iZM/1DbNAoyel8wYIZ7LOAvIZPdNG9Ix6j1vvKrGTu4ilPCKdOFurlPcSwA PLaU41Gr9/DN1tvfuVpHCNWeaWYKmCpx0Dm1VRMhUWOnzYtnV4XrxBJWAA5zG0acfCxx 4nLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698293646; x=1698898446; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=d8cKsWxi6jZjQFiHXDa1qsNnGyql4JqYL/7owK3wgPQ=; b=GBLRlh7NaY87IAKgIcZ6/ututGbI2vEE9j2q4uEYLSJcBysdysmZRtlEWpxjMTlRYy o+n/IKo5QCnr0gOKIogPdZKWlgnjp5wEzHuZ7Pc3LjJk7S7CKXsvTtCAdK90UGkhq6yW Jp4/VDpQrySslQtclcmUBsHpR86tz0rK/TyOia8wMhMK1V+ieCLs9+6cYvCmCJtRjePl gdxFyTyPRFdolV3iPn1FApmMQXOI3uyq+iui3hvYZ+tj9Nop0R6IlVu2n5dJLd5khEUj cyW/XtnpPViXRthAP+DoKf11M/nsc3LqcpvOqHgOyqAtVTfqEVRPV96YeqKAR/3hU8bK hLWw== X-Gm-Message-State: AOJu0YwHqtBCSqy1Z9wrDke5ly7gBU+qK0Jd/M8DSj52Ol7Ll7cJSEIf 9ftMZL9ysBqgnwr6oVAna5rPevIRNaV1ocv1SpU= X-Received: by 2002:a17:902:f550:b0:1c4:65d5:34ce with SMTP id h16-20020a170902f55000b001c465d534cemr1973773plf.31.1698293646156; Wed, 25 Oct 2023 21:14:06 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id i12-20020a170902eb4c00b001b8b2b95068sm9953929pli.204.2023.10.25.21.14.05 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 21:14:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 1/6] tcg/mips: Split out tcg_out_setcond_int Date: Wed, 25 Oct 2023 21:13:59 -0700 Message-Id: <20231026041404.1229328-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026041404.1229328-1-richard.henderson@linaro.org> References: <20231026041404.1229328-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Return the temp and a set of flags, to be used as a primitive for setcond, brcond, movcond. Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c.inc | 356 ++++++++++++++------------------------ 1 file changed, 132 insertions(+), 224 deletions(-) diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 739a0f60b7..a5e6fe727b 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -871,81 +871,88 @@ static void tcg_out_addsub2(TCGContext *s, TCGReg rl, TCGReg rh, TCGReg al, } } -/* Bit 0 set if inversion required; bit 1 set if swapping required. */ -#define MIPS_CMP_INV 1 -#define MIPS_CMP_SWAP 2 +#define SETCOND_INV TCG_TARGET_NB_REGS +#define SETCOND_NEZ (SETCOND_INV << 1) +#define SETCOND_FLAGS (SETCOND_INV | SETCOND_NEZ) -static const uint8_t mips_cmp_map[16] = { - [TCG_COND_LT] = 0, - [TCG_COND_LTU] = 0, - [TCG_COND_GE] = MIPS_CMP_INV, - [TCG_COND_GEU] = MIPS_CMP_INV, - [TCG_COND_LE] = MIPS_CMP_INV | MIPS_CMP_SWAP, - [TCG_COND_LEU] = MIPS_CMP_INV | MIPS_CMP_SWAP, - [TCG_COND_GT] = MIPS_CMP_SWAP, - [TCG_COND_GTU] = MIPS_CMP_SWAP, -}; +static int tcg_out_setcond_int(TCGContext *s, TCGCond cond, TCGReg ret, + TCGReg arg1, TCGReg arg2) +{ + int flags = 0; + + switch (cond) { + case TCG_COND_EQ: /* -> NE */ + case TCG_COND_GE: /* -> LT */ + case TCG_COND_GEU: /* -> LTU */ + case TCG_COND_LE: /* -> GT */ + case TCG_COND_LEU: /* -> GTU */ + case TCG_COND_TSTEQ: /* -> TSTNE */ + cond = tcg_invert_cond(cond); + flags ^= SETCOND_INV; + break; + default: + break; + } + + switch (cond) { + case TCG_COND_NE: + flags |= SETCOND_NEZ; + if (arg2 == 0) { + return arg1 | flags; + } + tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2); + break; + case TCG_COND_TSTNE: + flags |= SETCOND_NEZ; + tcg_out_opc_reg(s, OPC_AND, ret, arg1, arg2); + break; + case TCG_COND_LT: + tcg_out_opc_reg(s, OPC_SLT, ret, arg1, arg2); + break; + case TCG_COND_LTU: + tcg_out_opc_reg(s, OPC_SLTU, ret, arg1, arg2); + break; + case TCG_COND_GT: + tcg_out_opc_reg(s, OPC_SLT, ret, arg2, arg1); + break; + case TCG_COND_GTU: + tcg_out_opc_reg(s, OPC_SLTU, ret, arg2, arg1); + break; + default: + g_assert_not_reached(); + } + return ret | flags; +} + +static void tcg_out_setcond_end(TCGContext *s, TCGReg ret, int tmpflags) +{ + if (tmpflags != ret) { + TCGReg tmp = tmpflags & ~SETCOND_FLAGS; + + switch (tmpflags & SETCOND_FLAGS) { + case SETCOND_INV: + /* Intermediate result is boolean: simply invert. */ + tcg_out_opc_imm(s, OPC_XORI, ret, tmp, 1); + break; + case SETCOND_NEZ: + /* Intermediate result is zero/non-zero: test != 0. */ + tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, tmp); + break; + case SETCOND_NEZ | SETCOND_INV: + /* Intermediate result is zero/non-zero: test == 0. */ + tcg_out_opc_imm(s, OPC_SLTIU, ret, tmp, 1); + break; + default: + g_assert_not_reached(); + } + } +} static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret, TCGReg arg1, TCGReg arg2) { - MIPSInsn s_opc = OPC_SLTU; - int cmp_map; - - switch (cond) { - case TCG_COND_EQ: - if (arg2 != 0) { - tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2); - arg1 = ret; - } - tcg_out_opc_imm(s, OPC_SLTIU, ret, arg1, 1); - break; - - case TCG_COND_NE: - if (arg2 != 0) { - tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2); - arg1 = ret; - } - tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, arg1); - break; - - case TCG_COND_TSTEQ: - tcg_out_opc_reg(s, OPC_AND, ret, arg1, arg2); - tcg_out_opc_imm(s, OPC_SLTIU, ret, ret, 1); - break; - - case TCG_COND_TSTNE: - tcg_out_opc_reg(s, OPC_AND, ret, arg1, arg2); - tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, ret); - break; - - case TCG_COND_LT: - case TCG_COND_GE: - case TCG_COND_LE: - case TCG_COND_GT: - s_opc = OPC_SLT; - /* FALLTHRU */ - - case TCG_COND_LTU: - case TCG_COND_GEU: - case TCG_COND_LEU: - case TCG_COND_GTU: - cmp_map = mips_cmp_map[cond]; - if (cmp_map & MIPS_CMP_SWAP) { - TCGReg t = arg1; - arg1 = arg2; - arg2 = t; - } - tcg_out_opc_reg(s, s_opc, ret, arg1, arg2); - if (cmp_map & MIPS_CMP_INV) { - tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1); - } - break; - - default: - g_assert_not_reached(); - break; - } + int tmpflags = tcg_out_setcond_int(s, cond, ret, arg1, arg2); + tcg_out_setcond_end(s, ret, tmpflags); } static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1, @@ -958,9 +965,7 @@ static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1, [TCG_COND_GE] = OPC_BGEZ, }; - MIPSInsn s_opc = OPC_SLTU; - MIPSInsn b_opc; - int cmp_map; + MIPSInsn b_opc = 0; switch (cond) { case TCG_COND_EQ: @@ -969,7 +974,6 @@ static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1, case TCG_COND_NE: b_opc = OPC_BNE; break; - case TCG_COND_LT: case TCG_COND_GT: case TCG_COND_LE: @@ -978,156 +982,86 @@ static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1, b_opc = b_zero[cond]; arg2 = arg1; arg1 = 0; - break; } - s_opc = OPC_SLT; - /* FALLTHRU */ - - case TCG_COND_LTU: - case TCG_COND_GTU: - case TCG_COND_LEU: - case TCG_COND_GEU: - cmp_map = mips_cmp_map[cond]; - if (cmp_map & MIPS_CMP_SWAP) { - TCGReg t = arg1; - arg1 = arg2; - arg2 = t; - } - tcg_out_opc_reg(s, s_opc, TCG_TMP0, arg1, arg2); - b_opc = (cmp_map & MIPS_CMP_INV ? OPC_BEQ : OPC_BNE); - arg1 = TCG_TMP0; - arg2 = TCG_REG_ZERO; break; - - case TCG_COND_TSTEQ: - case TCG_COND_TSTNE: - tcg_out_opc_reg(s, OPC_AND, TCG_TMP0, arg1, arg2); - arg1 = TCG_TMP0; - arg2 = TCG_REG_ZERO; - b_opc = cond == TCG_COND_TSTEQ ? OPC_BEQ : OPC_BNE; - break; - default: - g_assert_not_reached(); break; } + if (b_opc == 0) { + int tmpflags = tcg_out_setcond_int(s, cond, TCG_TMP0, arg1, arg2); + + arg2 = 0; + arg1 = tmpflags & ~SETCOND_FLAGS; + b_opc = tmpflags & SETCOND_INV ? OPC_BEQ : OPC_BNE; + } + tcg_out_opc_br(s, b_opc, arg1, arg2); tcg_out_reloc(s, s->code_ptr - 1, R_MIPS_PC16, l, 0); tcg_out_nop(s); } -static TCGReg tcg_out_reduce_eq2(TCGContext *s, TCGReg tmp0, TCGReg tmp1, - TCGReg al, TCGReg ah, - TCGReg bl, TCGReg bh) +static int tcg_out_setcond2_int(TCGContext *s, TCGCond cond, TCGReg ret, + TCGReg al, TCGReg ah, TCGReg bl, TCGReg bh) { - /* Merge highpart comparison into AH. */ - if (bh != 0) { - if (ah != 0) { - tcg_out_opc_reg(s, OPC_XOR, tmp0, ah, bh); - ah = tmp0; - } else { - ah = bh; - } + int flags = 0; + + switch (cond) { + case TCG_COND_EQ: + flags |= SETCOND_INV; + /* fall through */ + case TCG_COND_NE: + flags |= SETCOND_NEZ; + tcg_out_opc_reg(s, OPC_XOR, TCG_TMP0, al, bl); + tcg_out_opc_reg(s, OPC_XOR, TCG_TMP1, ah, bh); + tcg_out_opc_reg(s, OPC_OR, ret, TCG_TMP0, TCG_TMP1); + break; + + case TCG_COND_TSTEQ: + flags |= SETCOND_INV; + /* fall through */ + case TCG_COND_TSTNE: + flags |= SETCOND_NEZ; + tcg_out_opc_reg(s, OPC_AND, TCG_TMP0, al, bl); + tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, ah, bh); + tcg_out_opc_reg(s, OPC_OR, ret, TCG_TMP0, TCG_TMP1); + break; + + default: + tcg_out_setcond(s, TCG_COND_EQ, TCG_TMP0, ah, bh); + tcg_out_setcond(s, tcg_unsigned_cond(cond), TCG_TMP1, al, bl); + tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, TCG_TMP0); + tcg_out_setcond(s, tcg_high_cond(cond), TCG_TMP0, ah, bh); + tcg_out_opc_reg(s, OPC_OR, ret, TCG_TMP0, TCG_TMP1); + break; } - /* Merge lowpart comparison into AL. */ - if (bl != 0) { - if (al != 0) { - tcg_out_opc_reg(s, OPC_XOR, tmp1, al, bl); - al = tmp1; - } else { - al = bl; - } - } - /* Merge high and low part comparisons into AL. */ - if (ah != 0) { - if (al != 0) { - tcg_out_opc_reg(s, OPC_OR, tmp0, ah, al); - al = tmp0; - } else { - al = ah; - } - } - return al; + return ret | flags; } static void tcg_out_setcond2(TCGContext *s, TCGCond cond, TCGReg ret, TCGReg al, TCGReg ah, TCGReg bl, TCGReg bh) { - TCGReg tmp0 = TCG_TMP0; - TCGReg tmp1 = ret; - - tcg_debug_assert(ret != TCG_TMP0); - if (ret == ah || ret == bh) { - tcg_debug_assert(ret != TCG_TMP1); - tmp1 = TCG_TMP1; - } - - switch (cond) { - case TCG_COND_EQ: - case TCG_COND_NE: - tmp1 = tcg_out_reduce_eq2(s, tmp0, tmp1, al, ah, bl, bh); - tcg_out_setcond(s, cond, ret, tmp1, TCG_REG_ZERO); - break; - - case TCG_COND_TSTEQ: - case TCG_COND_TSTNE: - tcg_out_opc_reg(s, OPC_AND, TCG_TMP0, al, bl); - tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, ah, bh); - tcg_out_opc_reg(s, OPC_OR, ret, TCG_TMP0, TCG_TMP1); - tcg_out_setcond(s, tcg_eqne_cond(cond), ret, tmp1, TCG_REG_ZERO); - break; - - default: - tcg_out_setcond(s, TCG_COND_EQ, tmp0, ah, bh); - tcg_out_setcond(s, tcg_unsigned_cond(cond), tmp1, al, bl); - tcg_out_opc_reg(s, OPC_AND, tmp1, tmp1, tmp0); - tcg_out_setcond(s, tcg_high_cond(cond), tmp0, ah, bh); - tcg_out_opc_reg(s, OPC_OR, ret, tmp1, tmp0); - break; - } + int tmpflags = tcg_out_setcond2_int(s, cond, ret, al, ah, bl, bh); + tcg_out_setcond_end(s, ret, tmpflags); } static void tcg_out_brcond2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah, TCGReg bl, TCGReg bh, TCGLabel *l) { - TCGCond b_cond = TCG_COND_NE; - TCGReg tmp = TCG_TMP1; + int tmpflags = tcg_out_setcond2_int(s, cond, TCG_TMP0, al, ah, bl, bh); + TCGReg tmp = tmpflags & ~SETCOND_FLAGS; + MIPSInsn b_opc = tmpflags & SETCOND_INV ? OPC_BEQ : OPC_BNE; - /* With branches, we emit between 4 and 9 insns with 2 or 3 branches. - With setcond, we emit between 3 and 10 insns and only 1 branch, - which ought to get better branch prediction. */ - switch (cond) { - case TCG_COND_EQ: - case TCG_COND_NE: - b_cond = cond; - tmp = tcg_out_reduce_eq2(s, TCG_TMP0, TCG_TMP1, al, ah, bl, bh); - break; - - case TCG_COND_TSTEQ: - case TCG_COND_TSTNE: - tcg_out_opc_reg(s, OPC_AND, TCG_TMP0, al, bl); - tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, ah, bh); - tcg_out_opc_reg(s, OPC_OR, TCG_TMP1, TCG_TMP1, TCG_TMP0); - break; - - default: - /* Minimize code size by preferring a compare not requiring INV. */ - if (mips_cmp_map[cond] & MIPS_CMP_INV) { - cond = tcg_invert_cond(cond); - b_cond = TCG_COND_EQ; - } - tcg_out_setcond2(s, cond, tmp, al, ah, bl, bh); - break; - } - - tcg_out_brcond(s, b_cond, tmp, TCG_REG_ZERO, l); + tcg_out_opc_br(s, b_opc, tmp, TCG_REG_ZERO); + tcg_out_reloc(s, s->code_ptr - 1, R_MIPS_PC16, l, 0); + tcg_out_nop(s); } static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret, TCGReg c1, TCGReg c2, TCGReg v1, TCGReg v2) { - bool eqz = false; + int tmpflags; + bool eqz; /* If one of the values is zero, put it last to match SEL*Z instructions */ if (use_mips32r6_instructions && v1 == 0) { @@ -1136,35 +1070,9 @@ static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret, cond = tcg_invert_cond(cond); } - switch (cond) { - case TCG_COND_EQ: - eqz = true; - /* FALLTHRU */ - case TCG_COND_NE: - if (c2 != 0) { - tcg_out_opc_reg(s, OPC_XOR, TCG_TMP0, c1, c2); - c1 = TCG_TMP0; - } - break; - - case TCG_COND_TSTEQ: - eqz = true; - /* FALLTHRU */ - case TCG_COND_TSTNE: - tcg_out_opc_reg(s, OPC_AND, TCG_TMP0, c1, c2); - c1 = TCG_TMP0; - break; - - default: - /* Minimize code size by preferring a compare not requiring INV. */ - if (mips_cmp_map[cond] & MIPS_CMP_INV) { - cond = tcg_invert_cond(cond); - eqz = true; - } - tcg_out_setcond(s, cond, TCG_TMP0, c1, c2); - c1 = TCG_TMP0; - break; - } + tmpflags = tcg_out_setcond_int(s, cond, TCG_TMP0, c1, c2); + c1 = tmpflags & ~SETCOND_FLAGS; + eqz = tmpflags & SETCOND_INV; if (use_mips32r6_instructions) { MIPSInsn m_opc_t = eqz ? OPC_SELEQZ : OPC_SELNEZ; From patchwork Thu Oct 26 04:14:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 738313 Delivered-To: patch@linaro.org Received: by 2002:adf:f842:0:b0:32d:baff:b0ca with SMTP id d2csp618047wrq; Wed, 25 Oct 2023 21:15:18 -0700 (PDT) X-Google-Smtp-Source: AGHT+IH8+AgT9Fmo7QPxKMGkVCSGoOKo0nSR5cGZ1gW7wXHrI3RJqPr7aknqJz83v7ib16S1Bc7K X-Received: by 2002:a05:6214:519e:b0:66d:140a:18f3 with SMTP id kl30-20020a056214519e00b0066d140a18f3mr20462610qvb.45.1698293717782; Wed, 25 Oct 2023 21:15:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698293717; cv=none; d=google.com; s=arc-20160816; b=eZl2+tGH5Tzh72Da8xy8XQe0VKWYDy5PuCjeVy3jFRczXSavzMDxq4LBP3OBa/XjnP KBhz9wdQllqAiHEQUBe/N1p3QcJx6hLLmFU7b4q6Z6e5MFzNXzRWTnKlGDCyBEMIvt7m QRsaY7nmjIRcXnck1GagurvHW/raxZYa3EoVpS1O8ASUuQwwjABs4pUU14oVj9su8jZl gRgoQgQR+hp/QgqJJqTOwa8X/5DpFM6tU96vXleWb4+nf/9LmhQRVxkXfjBonHfcc6kn o+0pmukhx01pV7sxNujy0PD0nCajRzdMtVWh3t0ueR3wQF7qOldJNe1ysV2XEehpuc5g UGFg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=NWMNJDe+S0+EZdJBo+3dWkXIm0dV/UW0LgPiVtKrpH8=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=jxW4P6PiLFFYFFRVma9npsS38eKUJy+V1gCb84Lu0LORDz3TJNGLrhdzjJR/+ScuWH LYrRKtMbJYaCUjYPVGXz49nMDnUsd0sgMvhM40VrzfUF4kpbbRu8sY0RKVCTshfgVMFh JRBzpJeSKMXwHZUWrJa0CEE6PL+8TR+iEU0++9dHzNOpyRCsx1OwtdA6mrY9AUGA0LSd MMI+khO+lMPchLQsi9NQuyqIeQxZE2odhb0Q1c1sVscwGiLJJRjVXsKCXRAKvA64dL8c Ha9bgsp21UPrfNro1lBguk5oHg+zIc8vR3SSgVZ/CK8Ae2C3xryQAvnibrQP8tsGeFgl 2Guw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WTCHf+hf; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id y11-20020a056214016b00b00668da565494si9059574qvs.162.2023.10.25.21.15.17 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 25 Oct 2023 21:15:17 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WTCHf+hf; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qvrl6-0002Uu-2U; Thu, 26 Oct 2023 00:14:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qvrl4-0002Ub-8v for qemu-devel@nongnu.org; Thu, 26 Oct 2023 00:14:10 -0400 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qvrl2-0000j3-Kt for qemu-devel@nongnu.org; Thu, 26 Oct 2023 00:14:10 -0400 Received: by mail-pl1-x62a.google.com with SMTP id d9443c01a7336-1cab2c24ecdso3328445ad.0 for ; Wed, 25 Oct 2023 21:14:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698293647; x=1698898447; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=NWMNJDe+S0+EZdJBo+3dWkXIm0dV/UW0LgPiVtKrpH8=; b=WTCHf+hf8DmS223zBWjIgTDTxiZFN7FG5muwnZGAPo8g3yy4vYXIj5XssoROy2nknO 5IwgwTon+26AHbpF0bsR1NReewIERr61v2jMS/3dDXZ+HbsVlw4SnLAAub6T4iHOKg4P B9AL1i4kRM/Db5zebjHgDOb4H+OKj4JW6Fl/YZvZu1hW6VgCh6Dkhqjg9qRmDVM/yPVQ 0MDvVd2yeiRRdF7SpaYU200YTP4AKAKilg4gqNjOaZkjKByHmAM37gx82pUY6QK9EDbR GDNAfmFldggSoJfkRl5JuK6HQbP1ymGRSEHGNk+E5bf8NqLKMEbpAkmYGb5vlCsC3QGA CwAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698293647; x=1698898447; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NWMNJDe+S0+EZdJBo+3dWkXIm0dV/UW0LgPiVtKrpH8=; b=keruJ/RdTfWS7Vmnux5qqcuN1QU2t8+ZC834o6k0o3WdKzRJucwZfD0fcW1Akiq3gV V1MrXJHooS+PVyNxr6jWPlyurXjI10mSqZzQzv65HVgwYvenAY/8mlGRzT6D75xGGS5G Y8SLS0GU+3sWbcvdjNkUg9449bnJJk3rvlWnWqZLT6LuaR8vCpmBbP2AI5d19MblomIW IsOHxwwL3DN5tnUNBMuYuHJklI9z6X+KmP0Ef6sDGRaHD2FSev1k86BQNJ1bY2SqXRFg K50wXpB5hcUiUyR6i9m7ywCS7CQrnPHl4+7+luA5ELmef0y0NhiLSOTllAj2GInHRBJo O+Ig== X-Gm-Message-State: AOJu0YwkDLNfoBpVyeejlJl1N3BkrxhhQaVoVfODvyNqbKrcpr8+rpek h2rayQcJW/3P6RszMHjk2bPQxRshPY/h4fxnWgE= X-Received: by 2002:a17:902:ecca:b0:1c7:562d:9b16 with SMTP id a10-20020a170902ecca00b001c7562d9b16mr17295736plh.24.1698293646957; Wed, 25 Oct 2023 21:14:06 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id i12-20020a170902eb4c00b001b8b2b95068sm9953929pli.204.2023.10.25.21.14.06 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 21:14:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 2/6] tcg/mips: Always implement movcond Date: Wed, 25 Oct 2023 21:14:00 -0700 Message-Id: <20231026041404.1229328-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026041404.1229328-1-richard.henderson@linaro.org> References: <20231026041404.1229328-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Expand as branch over move if not supported in the ISA. Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.h | 4 ++-- tcg/mips/tcg-target.c.inc | 19 ++++++++++++++----- 2 files changed, 16 insertions(+), 7 deletions(-) diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index c0576f66d7..0a4083f0d9 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -154,7 +154,7 @@ extern bool use_mips32r2_instructions; #endif /* optional instructions detected at runtime */ -#define TCG_TARGET_HAS_movcond_i32 use_movnz_instructions +#define TCG_TARGET_HAS_movcond_i32 1 #define TCG_TARGET_HAS_bswap16_i32 use_mips32r2_instructions #define TCG_TARGET_HAS_deposit_i32 use_mips32r2_instructions #define TCG_TARGET_HAS_extract_i32 use_mips32r2_instructions @@ -169,7 +169,7 @@ extern bool use_mips32r2_instructions; #define TCG_TARGET_HAS_qemu_st8_i32 0 #if TCG_TARGET_REG_BITS == 64 -#define TCG_TARGET_HAS_movcond_i64 use_movnz_instructions +#define TCG_TARGET_HAS_movcond_i64 1 #define TCG_TARGET_HAS_bswap16_i64 use_mips32r2_instructions #define TCG_TARGET_HAS_bswap32_i64 use_mips32r2_instructions #define TCG_TARGET_HAS_bswap64_i64 use_mips32r2_instructions diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index a5e6fe727b..f9b790ed8a 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -1085,13 +1085,22 @@ static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret, if (v2 != 0) { tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP1); } - } else { + return; + } + + /* This should be guaranteed via constraints */ + tcg_debug_assert(v2 == ret); + + if (use_movnz_instructions) { MIPSInsn m_opc = eqz ? OPC_MOVZ : OPC_MOVN; - tcg_out_opc_reg(s, m_opc, ret, v1, c1); - - /* This should be guaranteed via constraints */ - tcg_debug_assert(v2 == ret); + } else { + /* Invert the condition in order to branch over the move. */ + MIPSInsn b_opc = eqz ? OPC_BNE : OPC_BEQ; + tcg_out_opc_imm(s, b_opc, c1, TCG_REG_ZERO, 2); + tcg_out_nop(s); + /* Open-code tcg_out_mov, without the nop-move check. */ + tcg_out_opc_reg(s, OPC_OR, ret, v1, TCG_REG_ZERO); } } From patchwork Thu Oct 26 04:14:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 738312 Delivered-To: patch@linaro.org Received: by 2002:adf:f842:0:b0:32d:baff:b0ca with SMTP id d2csp618025wrq; Wed, 25 Oct 2023 21:15:12 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGKv0VSirinShicADm1Tblom4nRL17CF+As432kSY+PGz35wppuANYw3jXMnbmGf7VpZz22 X-Received: by 2002:ac8:5886:0:b0:40f:f0e0:a008 with SMTP id t6-20020ac85886000000b0040ff0e0a008mr21180051qta.53.1698293711719; Wed, 25 Oct 2023 21:15:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698293711; cv=none; d=google.com; s=arc-20160816; b=dSeVN+YPqexIZ6g/Py75n94j5oVK9fc603a/18JPsP8xj51EG7/YJhcC3PJlIBgJsY cKIYLXBcR3h+dnfK2EWiCrPSiju9luDQ8NZm+JW0XAeeqa9BZKdwSIzymwrYWG2o94V1 Z+EnNGT3q9ng9OcdthmJPwZddelIneD4hLqUM/5dquc9Cfrg+yx2+2ZGJ9c6g7pydKOv bQWTpzDVMc3wwzEWjbrDqKfz/PA/eFyLHo2EdrBwvlIdE5ua8T9qXaPCaQd5D7DItF5g 6U7mEwf3xb8+s3Zj4BYVl/lOZeqnXp5/tMfV7RtVh0SCgURxJnvrzn2tde4gjUi8WVcP vIxA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=mlppooNW1d2qtQucki4AZw1DSpXcW2IllcDyJOYGRCQ=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=QIvzTmk5xbZJ2KL3Uxouw/kMih15OXJUoBAT5ixJlmHfhtzFBUuwws2XN/7ZDOXNaK J7JKGfrV4bOs+lKkvOGiwYsYKpMyM4gf6zhYtTeWkWyqnLByARzabhmWLLGykUUZcMCY LOsAnu+p6Rwp2saJP5HqF7zbS7MhwFYzGdylOPPUmSJFX5+wKchp8tfuXiuUj9rsKLb4 xDokzTlqO7T5yXga4hGUrgWao1W2hSfwl4zggCZwT+tu1Xn3rCjahK+6MMPq2Re750DQ HJXlpOSd2hj8WuNr9AIS5ZavsXQI7/EV4jR4o9mJHiUka2/e5JlZFUCH1ZwocuWpjVMn 85bg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="bX/OO3dk"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id u24-20020a05622a199800b0040538e3e2e4si8817864qtc.266.2023.10.25.21.15.11 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 25 Oct 2023 21:15:11 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="bX/OO3dk"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qvrl8-0002WQ-Lv; Thu, 26 Oct 2023 00:14:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qvrl6-0002VD-FV for qemu-devel@nongnu.org; Thu, 26 Oct 2023 00:14:12 -0400 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qvrl3-0000jA-FP for qemu-devel@nongnu.org; Thu, 26 Oct 2023 00:14:12 -0400 Received: by mail-pl1-x630.google.com with SMTP id d9443c01a7336-1c9a1762b43so3475885ad.1 for ; Wed, 25 Oct 2023 21:14:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698293648; x=1698898448; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=mlppooNW1d2qtQucki4AZw1DSpXcW2IllcDyJOYGRCQ=; b=bX/OO3dkkA2tJbvYma2G1KSZbCkFCEChFYceTvzjA8sSMNgQOZwsFOWyjx74tdbOnO IPWNRLzq+oOBd+t65NQ4uGWlMEueMaFN8dLBffiRFZ6i+YVRQAPpWdR6DkDzQSmT8rNb Z8Vf/htrTbJsQolnsrtzMltDr/1rESgjY+3zTYPj7Lujj1JnPZPGaTumfDgxTKIGuKZK /dklHcMf/9zagPL2FqfZ2adxeGckxelP+qBM0/im71TFH9Gc/Rvt4wmt+oQqPINVDtJQ Q23Jg7n3HffuudN8ohFaOOz5t9q/TRRCaDt4zWiNkRTB234+C28T9IA331tJdcbU8DRH bI1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698293648; x=1698898448; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mlppooNW1d2qtQucki4AZw1DSpXcW2IllcDyJOYGRCQ=; b=diImRtq6kXrr2SzR1ZrwpPsPsauASx62+uyRZ6iLUDkJ8WNHHsWG+wM15SUYeB2KCT kIUjYfBGoqhb7GcSJgStIaCIiEClM24syGNIUeBoz8hJ61vhbxuVgg65sudhFaaswFDg efFnConr0THiep21VXdLGIqLS0NzDpW5PnWTBlBDuR6Lxl09yBpxnEWXxVBSsUeMtYYO WEBgtmSClERF2GhaI84sbr8jXPRSmYoH6rjF25IRCGj4h7kSsN0enZXT2rVx128TpCCh xfhQZQ7pKkfWHE1wdJVzbj7krjbTU2p1wF5tx+P3lNk1BayAj/AgmRIZkPH26ok3nrP5 z06A== X-Gm-Message-State: AOJu0Ywh6FdSt7bi1P4LREoH5kRxM8SFO6XxhDB10ocR2lpXz4rn3Oi8 n9IJOBqJjnHIhetYkXa8cV2mlsQ77EpTHBwA0B8= X-Received: by 2002:a17:902:d4cf:b0:1c3:92de:1b23 with SMTP id o15-20020a170902d4cf00b001c392de1b23mr20015716plg.59.1698293647800; Wed, 25 Oct 2023 21:14:07 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id i12-20020a170902eb4c00b001b8b2b95068sm9953929pli.204.2023.10.25.21.14.07 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 21:14:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 3/6] tcg: Remove TCG_TARGET_HAS_movcond_{i32,i64} Date: Wed, 25 Oct 2023 21:14:01 -0700 Message-Id: <20231026041404.1229328-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026041404.1229328-1-richard.henderson@linaro.org> References: <20231026041404.1229328-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The movcond opcode is now mandatory for backends to implement. Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h | 4 +-- include/tcg/tcg.h | 1 - tcg/aarch64/tcg-target.h | 2 -- tcg/arm/tcg-target.h | 1 - tcg/i386/tcg-target.h | 2 -- tcg/loongarch64/tcg-target.h | 2 -- tcg/mips/tcg-target.h | 2 -- tcg/ppc/tcg-target.h | 2 -- tcg/riscv/tcg-target.h | 2 -- tcg/s390x/tcg-target.h | 2 -- tcg/sparc64/tcg-target.h | 2 -- tcg/tci/tcg-target.h | 2 -- tcg/tcg-op.c | 50 ++++++++---------------------------- tcg/tcg.c | 6 ++--- 14 files changed, 14 insertions(+), 66 deletions(-) diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h index 6eff3d9106..ecd08db0de 100644 --- a/include/tcg/tcg-opc.h +++ b/include/tcg/tcg-opc.h @@ -47,7 +47,7 @@ DEF(mb, 0, 0, 1, 0) DEF(mov_i32, 1, 1, 0, TCG_OPF_NOT_PRESENT) DEF(setcond_i32, 1, 2, 1, 0) DEF(negsetcond_i32, 1, 2, 1, IMPL(TCG_TARGET_HAS_negsetcond_i32)) -DEF(movcond_i32, 1, 4, 1, IMPL(TCG_TARGET_HAS_movcond_i32)) +DEF(movcond_i32, 1, 4, 1, 0) /* load/store */ DEF(ld8u_i32, 1, 1, 1, 0) DEF(ld8s_i32, 1, 1, 1, 0) @@ -113,7 +113,7 @@ DEF(ctpop_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ctpop_i32)) DEF(mov_i64, 1, 1, 0, TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT) DEF(setcond_i64, 1, 2, 1, IMPL64) DEF(negsetcond_i64, 1, 2, 1, IMPL64 | IMPL(TCG_TARGET_HAS_negsetcond_i64)) -DEF(movcond_i64, 1, 4, 1, IMPL64 | IMPL(TCG_TARGET_HAS_movcond_i64)) +DEF(movcond_i64, 1, 4, 1, IMPL64) /* load/store */ DEF(ld8u_i64, 1, 1, 1, IMPL64) DEF(ld8s_i64, 1, 1, 1, IMPL64) diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index a9282cdcc6..bb522a865c 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -96,7 +96,6 @@ typedef uint64_t TCGRegSet; #define TCG_TARGET_HAS_extract_i64 0 #define TCG_TARGET_HAS_sextract_i64 0 #define TCG_TARGET_HAS_extract2_i64 0 -#define TCG_TARGET_HAS_movcond_i64 0 #define TCG_TARGET_HAS_negsetcond_i64 0 #define TCG_TARGET_HAS_add2_i64 0 #define TCG_TARGET_HAS_sub2_i64 0 diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 98727ea53b..352e19aba8 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -85,7 +85,6 @@ typedef enum { #define TCG_TARGET_HAS_extract_i32 1 #define TCG_TARGET_HAS_sextract_i32 1 #define TCG_TARGET_HAS_extract2_i32 1 -#define TCG_TARGET_HAS_movcond_i32 1 #define TCG_TARGET_HAS_negsetcond_i32 1 #define TCG_TARGET_HAS_add2_i32 1 #define TCG_TARGET_HAS_sub2_i32 1 @@ -122,7 +121,6 @@ typedef enum { #define TCG_TARGET_HAS_extract_i64 1 #define TCG_TARGET_HAS_sextract_i64 1 #define TCG_TARGET_HAS_extract2_i64 1 -#define TCG_TARGET_HAS_movcond_i64 1 #define TCG_TARGET_HAS_negsetcond_i64 1 #define TCG_TARGET_HAS_add2_i64 1 #define TCG_TARGET_HAS_sub2_i64 1 diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 311a985209..439898efb3 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -115,7 +115,6 @@ extern bool use_neon_instructions; #define TCG_TARGET_HAS_extract_i32 use_armv7_instructions #define TCG_TARGET_HAS_sextract_i32 use_armv7_instructions #define TCG_TARGET_HAS_extract2_i32 1 -#define TCG_TARGET_HAS_movcond_i32 1 #define TCG_TARGET_HAS_negsetcond_i32 1 #define TCG_TARGET_HAS_mulu2_i32 1 #define TCG_TARGET_HAS_muls2_i32 1 diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 8417ea4899..7522ce7575 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -149,7 +149,6 @@ typedef enum { #define TCG_TARGET_HAS_extract_i32 1 #define TCG_TARGET_HAS_sextract_i32 1 #define TCG_TARGET_HAS_extract2_i32 1 -#define TCG_TARGET_HAS_movcond_i32 1 #define TCG_TARGET_HAS_negsetcond_i32 1 #define TCG_TARGET_HAS_add2_i32 1 #define TCG_TARGET_HAS_sub2_i32 1 @@ -186,7 +185,6 @@ typedef enum { #define TCG_TARGET_HAS_extract_i64 1 #define TCG_TARGET_HAS_sextract_i64 0 #define TCG_TARGET_HAS_extract2_i64 1 -#define TCG_TARGET_HAS_movcond_i64 1 #define TCG_TARGET_HAS_negsetcond_i64 1 #define TCG_TARGET_HAS_add2_i64 1 #define TCG_TARGET_HAS_sub2_i64 1 diff --git a/tcg/loongarch64/tcg-target.h b/tcg/loongarch64/tcg-target.h index 03017672f6..bebb2c6a05 100644 --- a/tcg/loongarch64/tcg-target.h +++ b/tcg/loongarch64/tcg-target.h @@ -97,7 +97,6 @@ extern bool use_lsx_instructions; #define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL /* optional instructions */ -#define TCG_TARGET_HAS_movcond_i32 1 #define TCG_TARGET_HAS_negsetcond_i32 0 #define TCG_TARGET_HAS_div_i32 1 #define TCG_TARGET_HAS_rem_i32 1 @@ -134,7 +133,6 @@ extern bool use_lsx_instructions; #define TCG_TARGET_HAS_qemu_st8_i32 0 /* 64-bit operations */ -#define TCG_TARGET_HAS_movcond_i64 1 #define TCG_TARGET_HAS_negsetcond_i64 0 #define TCG_TARGET_HAS_div_i64 1 #define TCG_TARGET_HAS_rem_i64 1 diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index 0a4083f0d9..5b3fdcc726 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -154,7 +154,6 @@ extern bool use_mips32r2_instructions; #endif /* optional instructions detected at runtime */ -#define TCG_TARGET_HAS_movcond_i32 1 #define TCG_TARGET_HAS_bswap16_i32 use_mips32r2_instructions #define TCG_TARGET_HAS_deposit_i32 use_mips32r2_instructions #define TCG_TARGET_HAS_extract_i32 use_mips32r2_instructions @@ -169,7 +168,6 @@ extern bool use_mips32r2_instructions; #define TCG_TARGET_HAS_qemu_st8_i32 0 #if TCG_TARGET_REG_BITS == 64 -#define TCG_TARGET_HAS_movcond_i64 1 #define TCG_TARGET_HAS_bswap16_i64 use_mips32r2_instructions #define TCG_TARGET_HAS_bswap32_i64 use_mips32r2_instructions #define TCG_TARGET_HAS_bswap64_i64 use_mips32r2_instructions diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index 8bfb14998e..a2856afd4d 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -96,7 +96,6 @@ typedef enum { #define TCG_TARGET_HAS_extract_i32 1 #define TCG_TARGET_HAS_sextract_i32 0 #define TCG_TARGET_HAS_extract2_i32 0 -#define TCG_TARGET_HAS_movcond_i32 1 #define TCG_TARGET_HAS_negsetcond_i32 1 #define TCG_TARGET_HAS_mulu2_i32 0 #define TCG_TARGET_HAS_muls2_i32 0 @@ -134,7 +133,6 @@ typedef enum { #define TCG_TARGET_HAS_extract_i64 1 #define TCG_TARGET_HAS_sextract_i64 0 #define TCG_TARGET_HAS_extract2_i64 0 -#define TCG_TARGET_HAS_movcond_i64 1 #define TCG_TARGET_HAS_negsetcond_i64 1 #define TCG_TARGET_HAS_add2_i64 1 #define TCG_TARGET_HAS_sub2_i64 1 diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index c1132d178f..f3644a8bc1 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -87,7 +87,6 @@ extern bool have_zbb; #endif /* optional instructions */ -#define TCG_TARGET_HAS_movcond_i32 1 #define TCG_TARGET_HAS_negsetcond_i32 1 #define TCG_TARGET_HAS_div_i32 1 #define TCG_TARGET_HAS_rem_i32 1 @@ -123,7 +122,6 @@ extern bool have_zbb; #define TCG_TARGET_HAS_setcond2 1 #define TCG_TARGET_HAS_qemu_st8_i32 0 -#define TCG_TARGET_HAS_movcond_i64 1 #define TCG_TARGET_HAS_negsetcond_i64 1 #define TCG_TARGET_HAS_div_i64 1 #define TCG_TARGET_HAS_rem_i64 1 diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h index 50e12ef9d6..2c936c1bcb 100644 --- a/tcg/s390x/tcg-target.h +++ b/tcg/s390x/tcg-target.h @@ -95,7 +95,6 @@ extern uint64_t s390_facilities[3]; #define TCG_TARGET_HAS_extract_i32 1 #define TCG_TARGET_HAS_sextract_i32 0 #define TCG_TARGET_HAS_extract2_i32 0 -#define TCG_TARGET_HAS_movcond_i32 1 #define TCG_TARGET_HAS_negsetcond_i32 1 #define TCG_TARGET_HAS_add2_i32 1 #define TCG_TARGET_HAS_sub2_i32 1 @@ -131,7 +130,6 @@ extern uint64_t s390_facilities[3]; #define TCG_TARGET_HAS_extract_i64 1 #define TCG_TARGET_HAS_sextract_i64 0 #define TCG_TARGET_HAS_extract2_i64 0 -#define TCG_TARGET_HAS_movcond_i64 1 #define TCG_TARGET_HAS_negsetcond_i64 1 #define TCG_TARGET_HAS_add2_i64 1 #define TCG_TARGET_HAS_sub2_i64 1 diff --git a/tcg/sparc64/tcg-target.h b/tcg/sparc64/tcg-target.h index 5cfc4b4679..4c286c6006 100644 --- a/tcg/sparc64/tcg-target.h +++ b/tcg/sparc64/tcg-target.h @@ -105,7 +105,6 @@ extern bool use_vis3_instructions; #define TCG_TARGET_HAS_extract_i32 0 #define TCG_TARGET_HAS_sextract_i32 0 #define TCG_TARGET_HAS_extract2_i32 0 -#define TCG_TARGET_HAS_movcond_i32 1 #define TCG_TARGET_HAS_negsetcond_i32 1 #define TCG_TARGET_HAS_add2_i32 1 #define TCG_TARGET_HAS_sub2_i32 1 @@ -142,7 +141,6 @@ extern bool use_vis3_instructions; #define TCG_TARGET_HAS_extract_i64 0 #define TCG_TARGET_HAS_sextract_i64 0 #define TCG_TARGET_HAS_extract2_i64 0 -#define TCG_TARGET_HAS_movcond_i64 1 #define TCG_TARGET_HAS_negsetcond_i64 1 #define TCG_TARGET_HAS_add2_i64 1 #define TCG_TARGET_HAS_sub2_i64 1 diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 91ca33b616..3503fc4a4c 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -69,7 +69,6 @@ #define TCG_TARGET_HAS_not_i32 1 #define TCG_TARGET_HAS_orc_i32 1 #define TCG_TARGET_HAS_rot_i32 1 -#define TCG_TARGET_HAS_movcond_i32 1 #define TCG_TARGET_HAS_negsetcond_i32 0 #define TCG_TARGET_HAS_muls2_i32 1 #define TCG_TARGET_HAS_muluh_i32 0 @@ -104,7 +103,6 @@ #define TCG_TARGET_HAS_not_i64 1 #define TCG_TARGET_HAS_orc_i64 1 #define TCG_TARGET_HAS_rot_i64 1 -#define TCG_TARGET_HAS_movcond_i64 1 #define TCG_TARGET_HAS_negsetcond_i64 0 #define TCG_TARGET_HAS_muls2_i64 1 #define TCG_TARGET_HAS_add2_i32 1 diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 828eb9ee46..51de796769 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -864,17 +864,8 @@ void tcg_gen_movcond_i32(TCGCond cond, TCGv_i32 ret, TCGv_i32 c1, tcg_gen_mov_i32(ret, v1); } else if (cond == TCG_COND_NEVER) { tcg_gen_mov_i32(ret, v2); - } else if (TCG_TARGET_HAS_movcond_i32) { - tcg_gen_op6i_i32(INDEX_op_movcond_i32, ret, c1, c2, v1, v2, cond); } else { - TCGv_i32 t0 = tcg_temp_ebb_new_i32(); - TCGv_i32 t1 = tcg_temp_ebb_new_i32(); - tcg_gen_negsetcond_i32(cond, t0, c1, c2); - tcg_gen_and_i32(t1, v1, t0); - tcg_gen_andc_i32(ret, v2, t0); - tcg_gen_or_i32(ret, ret, t1); - tcg_temp_free_i32(t0); - tcg_temp_free_i32(t1); + tcg_gen_op6i_i32(INDEX_op_movcond_i32, ret, c1, c2, v1, v2, cond); } } @@ -2600,43 +2591,22 @@ void tcg_gen_movcond_i64(TCGCond cond, TCGv_i64 ret, TCGv_i64 c1, tcg_gen_mov_i64(ret, v1); } else if (cond == TCG_COND_NEVER) { tcg_gen_mov_i64(ret, v2); - } else if (TCG_TARGET_REG_BITS == 32) { + } else if (TCG_TARGET_REG_BITS == 64) { + tcg_gen_op6i_i64(INDEX_op_movcond_i64, ret, c1, c2, v1, v2, cond); + } else { TCGv_i32 t0 = tcg_temp_ebb_new_i32(); - TCGv_i32 t1 = tcg_temp_ebb_new_i32(); + TCGv_i32 zero = tcg_constant_i32(0); + tcg_gen_op6i_i32(INDEX_op_setcond2_i32, t0, TCGV_LOW(c1), TCGV_HIGH(c1), TCGV_LOW(c2), TCGV_HIGH(c2), cond); - if (TCG_TARGET_HAS_movcond_i32) { - tcg_gen_movi_i32(t1, 0); - tcg_gen_movcond_i32(TCG_COND_NE, TCGV_LOW(ret), t0, t1, - TCGV_LOW(v1), TCGV_LOW(v2)); - tcg_gen_movcond_i32(TCG_COND_NE, TCGV_HIGH(ret), t0, t1, - TCGV_HIGH(v1), TCGV_HIGH(v2)); - } else { - tcg_gen_neg_i32(t0, t0); + tcg_gen_movcond_i32(TCG_COND_NE, TCGV_LOW(ret), t0, zero, + TCGV_LOW(v1), TCGV_LOW(v2)); + tcg_gen_movcond_i32(TCG_COND_NE, TCGV_HIGH(ret), t0, zero, + TCGV_HIGH(v1), TCGV_HIGH(v2)); - tcg_gen_and_i32(t1, TCGV_LOW(v1), t0); - tcg_gen_andc_i32(TCGV_LOW(ret), TCGV_LOW(v2), t0); - tcg_gen_or_i32(TCGV_LOW(ret), TCGV_LOW(ret), t1); - - tcg_gen_and_i32(t1, TCGV_HIGH(v1), t0); - tcg_gen_andc_i32(TCGV_HIGH(ret), TCGV_HIGH(v2), t0); - tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(ret), t1); - } tcg_temp_free_i32(t0); - tcg_temp_free_i32(t1); - } else if (TCG_TARGET_HAS_movcond_i64) { - tcg_gen_op6i_i64(INDEX_op_movcond_i64, ret, c1, c2, v1, v2, cond); - } else { - TCGv_i64 t0 = tcg_temp_ebb_new_i64(); - TCGv_i64 t1 = tcg_temp_ebb_new_i64(); - tcg_gen_negsetcond_i64(cond, t0, c1, c2); - tcg_gen_and_i64(t1, v1, t0); - tcg_gen_andc_i64(ret, v2, t0); - tcg_gen_or_i64(ret, ret, t1); - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); } } diff --git a/tcg/tcg.c b/tcg/tcg.c index 57d0583fe7..5da03ba11d 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1874,6 +1874,7 @@ bool tcg_op_supported(TCGOpcode op) case INDEX_op_mov_i32: case INDEX_op_setcond_i32: case INDEX_op_brcond_i32: + case INDEX_op_movcond_i32: case INDEX_op_ld8u_i32: case INDEX_op_ld8s_i32: case INDEX_op_ld16u_i32: @@ -1895,8 +1896,6 @@ bool tcg_op_supported(TCGOpcode op) case INDEX_op_negsetcond_i32: return TCG_TARGET_HAS_negsetcond_i32; - case INDEX_op_movcond_i32: - return TCG_TARGET_HAS_movcond_i32; case INDEX_op_div_i32: case INDEX_op_divu_i32: return TCG_TARGET_HAS_div_i32; @@ -1969,6 +1968,7 @@ bool tcg_op_supported(TCGOpcode op) case INDEX_op_mov_i64: case INDEX_op_setcond_i64: case INDEX_op_brcond_i64: + case INDEX_op_movcond_i64: case INDEX_op_ld8u_i64: case INDEX_op_ld8s_i64: case INDEX_op_ld16u_i64: @@ -1995,8 +1995,6 @@ bool tcg_op_supported(TCGOpcode op) case INDEX_op_negsetcond_i64: return TCG_TARGET_HAS_negsetcond_i64; - case INDEX_op_movcond_i64: - return TCG_TARGET_HAS_movcond_i64; case INDEX_op_div_i64: case INDEX_op_divu_i64: return TCG_TARGET_HAS_div_i64; From patchwork Thu Oct 26 04:14:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 738310 Delivered-To: patch@linaro.org Received: by 2002:adf:f842:0:b0:32d:baff:b0ca with SMTP id d2csp618026wrq; Wed, 25 Oct 2023 21:15:12 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGdhc4p6znRXOJYjz2zscJx8Pkc2k32Bmsp/aVogKI0hRrQuwEoqs/TxQn7Xi9Rr+13d9mo X-Received: by 2002:a05:620a:4888:b0:76f:1f8c:cc1b with SMTP id ea8-20020a05620a488800b0076f1f8ccc1bmr14223631qkb.78.1698293711677; Wed, 25 Oct 2023 21:15:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698293711; cv=none; d=google.com; s=arc-20160816; b=j0bPURxqLjRz3CVxcIWHbbE8OQLu0Ls4D+gzZWvKTE+IsggE6ZAj/V/Nox+dnCuidj M26Hm83VzWkgZWHgdNhoB3ew/8iSejIsynCypp0wgDyrgCiuWWkK+YxXcgDuKxbGGgVr 4x276JQTE+UseeUDz6MdZm7n36vHu5Mq2UKyUfib3rbBuajCxWyraqr6wybDoOKYCql+ O9tkBVrsgMZampMrrSJy+qyl5IN6UqzyzxVvyUObsJ+RepEYwBXiNorBEil6asx/l2fL SVqsnjEPeRbdOnnsct6CmFOuSFu0tXhw4LqpfRK3dvAlHjmj0670WmQ6ZnMi2jkfz8W1 bMgw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=lPY9mxzDBbOf1owj0FOY1MUzjClJ3s1wsYFvJx2toV4=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=jzQy1LpemID6ZwtGTelBSncxPVJtu05kqFYyC6et+rzTjhxPG//7lReGXMEfliDWkz pYmeI3U+PcPG6Yh5EL8XW6XintmOevc99wGCzWw5ZIirXk4fExuWYiOytmYPDHAvkN4A XYFrk8aivWYA9BOIQDWjMPbatrhehDRUQ6JQ8QJpqPu8cYYovWSCbar4urNBG2ecgemk kPpz5lwn3P/kzCgzHCcYkCU8OQwbpUdD6ZTfcCwmpYBYJWr7K44LFez+9Qlh2awu/JtV Tgj2ibmanvJu2baggY1Cm2vN+QLZC8Qo80iBlY4Pd/uFRPoul8mZbnW4mok5lAjSd0wf zbyQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SKkv3jNE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id g24-20020a05620a109800b0076db4dfa8a9si8780486qkk.44.2023.10.25.21.15.11 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 25 Oct 2023 21:15:11 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SKkv3jNE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qvrlB-0002XI-BI; Thu, 26 Oct 2023 00:14:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qvrl7-0002VW-BW for qemu-devel@nongnu.org; Thu, 26 Oct 2023 00:14:13 -0400 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qvrl5-0000jK-3M for qemu-devel@nongnu.org; Thu, 26 Oct 2023 00:14:13 -0400 Received: by mail-pl1-x634.google.com with SMTP id d9443c01a7336-1c5cd27b1acso3602135ad.2 for ; Wed, 25 Oct 2023 21:14:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698293648; x=1698898448; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=lPY9mxzDBbOf1owj0FOY1MUzjClJ3s1wsYFvJx2toV4=; b=SKkv3jNEnzmbGHw48dQoUIRneJTwcrut1YGwQpz6az5vbuLLYPEgEO2HGhScAZSXU7 bwVlf/dzW7OwuWJAE0Ylrf6cvf887oQBMULo820B3En945VvrSLxtl4DZ1qKnswZxki1 pSt6XDjgqVzbwoz2bTJpXSqBpShUoq1w8znSJLAqiaNhYdy9nC6V9Yj6DiD0UVPOEdJO DebZyXBh+wFvod4eGqfaMfYfzfUEo7jHn6CO+6FU+BcgEmXjB+jl6pMJc/E+QFORn66k Rf/WP8oiox1XeNO1wDPlzjbw/2clKpAeXgNN3d7VUiTyop0t1nZZi2y7u5S//oH7gyuI jpfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698293648; x=1698898448; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lPY9mxzDBbOf1owj0FOY1MUzjClJ3s1wsYFvJx2toV4=; b=VQJ1dKwP/JObWAvuPCJoZDsgxeJ+uCJE/yCx6Xb2AIfi+70HZviYTifyURjb1ffeQx BbwxMlZT+h2vsv3+gqVIFJGpmXtjxUWK0tTjatFrhMUQj5XkV3zceSiaEsVEBqppcyTV wHaEEaI+MR8cwipWz0oPMnbFnpIi+9av0ofQz+8tyeDqSlsWpvn0sNB9ozq9mDjfRaW2 YV/FTib0IvcB/6ASodAtNartSjiFrgCKZnr9iIAgH0xLUKAJvGQSDJZSIDJvngrj9LpD pBfLM9U6iaR+ysoU24WgmkuK3ZlaIdJaLuCz8/FqHaXNB77u8Oow/BGfa8SUwPh66I7S pf8A== X-Gm-Message-State: AOJu0YwbfdklVsnWi8USNn3JKSbIMLurHAo3ci3rzpVKhxIgn2lXrykl 6E6KZx++C4UoMjB0S7ScXNsHCAEXjxSQpSvCRvk= X-Received: by 2002:a17:902:f686:b0:1c7:5f03:8562 with SMTP id l6-20020a170902f68600b001c75f038562mr19992779plg.30.1698293648581; Wed, 25 Oct 2023 21:14:08 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id i12-20020a170902eb4c00b001b8b2b95068sm9953929pli.204.2023.10.25.21.14.08 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 21:14:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 4/6] tcg/mips: Implement neg opcodes Date: Wed, 25 Oct 2023 21:14:02 -0700 Message-Id: <20231026041404.1229328-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026041404.1229328-1-richard.henderson@linaro.org> References: <20231026041404.1229328-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.h | 4 ++-- tcg/mips/tcg-target.c.inc | 8 ++++++++ 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index 5b3fdcc726..20c14224fb 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -184,12 +184,12 @@ extern bool use_mips32r2_instructions; #endif /* optional instructions automatically implemented */ -#define TCG_TARGET_HAS_neg_i32 0 /* sub rd, zero, rt */ +#define TCG_TARGET_HAS_neg_i32 1 #define TCG_TARGET_HAS_ext8u_i32 0 /* andi rt, rs, 0xff */ #define TCG_TARGET_HAS_ext16u_i32 0 /* andi rt, rs, 0xffff */ #if TCG_TARGET_REG_BITS == 64 -#define TCG_TARGET_HAS_neg_i64 0 /* sub rd, zero, rt */ +#define TCG_TARGET_HAS_neg_i64 1 #define TCG_TARGET_HAS_ext8u_i64 0 /* andi rt, rs, 0xff */ #define TCG_TARGET_HAS_ext16u_i64 0 /* andi rt, rs, 0xffff */ #endif diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index f9b790ed8a..c38f5c9450 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -1935,6 +1935,12 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_opc_reg(s, OPC_MFHI, a1, 0, 0); break; + case INDEX_op_neg_i32: + i1 = OPC_SUBU; + goto do_unary; + case INDEX_op_neg_i64: + i1 = OPC_DSUBU; + goto do_unary; case INDEX_op_not_i32: case INDEX_op_not_i64: i1 = OPC_NOR; @@ -2159,6 +2165,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_ld16u_i32: case INDEX_op_ld16s_i32: case INDEX_op_ld_i32: + case INDEX_op_neg_i32: case INDEX_op_not_i32: case INDEX_op_bswap16_i32: case INDEX_op_bswap32_i32: @@ -2172,6 +2179,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_ld32s_i64: case INDEX_op_ld32u_i64: case INDEX_op_ld_i64: + case INDEX_op_neg_i64: case INDEX_op_not_i64: case INDEX_op_bswap16_i64: case INDEX_op_bswap32_i64: From patchwork Thu Oct 26 04:14:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 738311 Delivered-To: patch@linaro.org Received: by 2002:adf:f842:0:b0:32d:baff:b0ca with SMTP id d2csp618022wrq; Wed, 25 Oct 2023 21:15:11 -0700 (PDT) X-Google-Smtp-Source: AGHT+IF5LgIYTlayN9+uGAfcTmdza6larZUyrYalSrWIRhU3A82t2FLRSh8cdx6GxzPwIW8BCEno X-Received: by 2002:a05:6214:21ce:b0:66d:1256:6dbc with SMTP id d14-20020a05621421ce00b0066d12566dbcmr21867499qvh.44.1698293711667; Wed, 25 Oct 2023 21:15:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698293711; cv=none; d=google.com; s=arc-20160816; b=W7L3lXl7/EUFz1HGlkYx3w1fA+asni/gQW22GrlyGj911i0IWgKq6FWcaIKTm9p3ld bSoZg339JZk8TDva3Di4HYH91jDykXXYZkZT8dIZKkV9k0poWRQDisiUJ3u5mK0sTyCP dndj1PkSIRBK/GRyF2N4wOK+Ityq9IBrRNHaBn+ae8s0eX2YPEWVEJSR+UMN97zQlccu X1Y7jlIpqoh4eVNp6rw3xEjlyErmlm0XSxF7ouSMjQb83OsRSKoijHnU38teq7worad7 38JI6PRYI3eCA7uR/6xUiUBeegyUZ//saPiS+WM5Q5frm7CoRdOgrznT8QDiacMy9rkq kang== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=kfOTc+047DdEYqk8cfseEawf9Tt5uNnX6caSwYhD9Rk=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=TfYXMKKeGENm8lQanbs6IG305AIoMWLMXkv2pfe4wCMUnIBzvUld/BpCz/+k/MWpGg qzeNuMiDDbev9uKK4XUaNIG0gJ/m+UzLwk7WXMzL+s2Z6CNIg/16qa8fUH1/a7T0hvp9 V32P9NXkE6WyndO9P/y13ps616E9vM1WeKf+HZWNKX94C6WRDxtGuT86Thmq+N2Y4BRe HLpJHF6vc1rzfLWc+wyx9v9OWwOeGzPnrefKHZWNcPXIRxosu1zswnn+ny7lLvlO1Op2 ZC7hIHRUVXTXBqJB43AryC7sOBCrQmDwl69JRGiLlY6L3fi+jmlisvzioAXT2nwdSABz v2PA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="gSTe/COK"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d14-20020a0cfe8e000000b0065b26faf108si9134350qvs.406.2023.10.25.21.15.11 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 25 Oct 2023 21:15:11 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="gSTe/COK"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qvrl8-0002W9-FK; Thu, 26 Oct 2023 00:14:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qvrl6-0002VG-J9 for qemu-devel@nongnu.org; Thu, 26 Oct 2023 00:14:12 -0400 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qvrl4-0000jS-RO for qemu-devel@nongnu.org; Thu, 26 Oct 2023 00:14:12 -0400 Received: by mail-pl1-x631.google.com with SMTP id d9443c01a7336-1cc0e78ec92so432895ad.3 for ; Wed, 25 Oct 2023 21:14:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698293649; x=1698898449; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=kfOTc+047DdEYqk8cfseEawf9Tt5uNnX6caSwYhD9Rk=; b=gSTe/COKmGRO5lx48JaHInzlEZUstmLneCzzQOQ+85+4FFWyx4UpANg0/i2f86ieFX lvp9Skwne7ckO4R6taoy4dcEKSUORJe+Fi9I0nMFbHa8sxum1wbpNr4rjDvxU68hfVtp Gx2GIg7JsTWq22Gn2kBSIkyrZa6rjKB3p9X/HTtVNeUxHwAiFGgBvX1xITLm7vIcpaYP UqW7niBA0HTswfezGlCUVw80FQHtzMtLpSAL6s971TPVznNmJuuQXkTzFSGO22OOT8IC MVSuUGeqWcPx7E95iQurYI7g9CEusQD3M8S4yQW9SHAYG0AWrc0MIUPzjMcTgiK8HFij 9vHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698293649; x=1698898449; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kfOTc+047DdEYqk8cfseEawf9Tt5uNnX6caSwYhD9Rk=; b=V58jEyR+WpZqd2RJ3muC85ugT2jvOplpi1DQ1bL5qfDV9dSLQOoMCwORjEsyTUU1ta TVpqGc0BNMKWPHwov+rP+bqtfa+9tSg/pfhiD7NGxAzHbG4i3TvUj+sBGEMA2c9Qy7kI TEjHQl62bEPhmoWH1g6xxiybcNLWhWlEjm66+Q3LREfxmjBGOTD092VSSmiabqX7DqpD ZSoFX/Qync9XZ8o4n/d7gSRnzS/urov896zP52e4L/kiFBqhavgX7J35uZlxiFVcProF ZBNZOH/HcXKriyJeI5oxGURQKUw+HmGoXH9CK0yySzj5G7JUu2GuSIjZoQwJuH4hONE/ J7sA== X-Gm-Message-State: AOJu0YzXBAJ7gpiAnT0LeNSDGJoicjVwUHNTbR+K+O5HnqrtFH9ki6H3 GTFCrpYUpFqPnRyCXeVy9l0279y1P7jG+RT+ovk= X-Received: by 2002:a17:902:da92:b0:1c7:4f87:3dbe with SMTP id j18-20020a170902da9200b001c74f873dbemr17411696plx.31.1698293649413; Wed, 25 Oct 2023 21:14:09 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id i12-20020a170902eb4c00b001b8b2b95068sm9953929pli.204.2023.10.25.21.14.08 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 21:14:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 5/6] tcg/loongarch64: Implement neg opcodes Date: Wed, 25 Oct 2023 21:14:03 -0700 Message-Id: <20231026041404.1229328-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026041404.1229328-1-richard.henderson@linaro.org> References: <20231026041404.1229328-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- tcg/loongarch64/tcg-target.h | 4 ++-- tcg/loongarch64/tcg-target.c.inc | 9 +++++++++ 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/tcg/loongarch64/tcg-target.h b/tcg/loongarch64/tcg-target.h index bebb2c6a05..d1c8e6d341 100644 --- a/tcg/loongarch64/tcg-target.h +++ b/tcg/loongarch64/tcg-target.h @@ -119,7 +119,7 @@ extern bool use_lsx_instructions; #define TCG_TARGET_HAS_bswap16_i32 1 #define TCG_TARGET_HAS_bswap32_i32 1 #define TCG_TARGET_HAS_not_i32 1 -#define TCG_TARGET_HAS_neg_i32 0 +#define TCG_TARGET_HAS_neg_i32 1 #define TCG_TARGET_HAS_andc_i32 1 #define TCG_TARGET_HAS_orc_i32 1 #define TCG_TARGET_HAS_eqv_i32 0 @@ -153,7 +153,7 @@ extern bool use_lsx_instructions; #define TCG_TARGET_HAS_bswap32_i64 1 #define TCG_TARGET_HAS_bswap64_i64 1 #define TCG_TARGET_HAS_not_i64 1 -#define TCG_TARGET_HAS_neg_i64 0 +#define TCG_TARGET_HAS_neg_i64 1 #define TCG_TARGET_HAS_andc_i64 1 #define TCG_TARGET_HAS_orc_i64 1 #define TCG_TARGET_HAS_eqv_i64 0 diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc index 4e850a29e5..f21fba9f66 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -1458,6 +1458,13 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, } break; + case INDEX_op_neg_i32: + tcg_out_opc_sub_w(s, a0, TCG_REG_ZERO, a1); + break; + case INDEX_op_neg_i64: + tcg_out_opc_sub_d(s, a0, TCG_REG_ZERO, a1); + break; + case INDEX_op_mul_i32: tcg_out_opc_mul_w(s, a0, a1, a2); break; @@ -2093,6 +2100,8 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_extrl_i64_i32: case INDEX_op_extrh_i64_i32: case INDEX_op_ext_i32_i64: + case INDEX_op_neg_i32: + case INDEX_op_neg_i64: case INDEX_op_not_i32: case INDEX_op_not_i64: case INDEX_op_extract_i32: From patchwork Thu Oct 26 04:14:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 738315 Delivered-To: patch@linaro.org Received: by 2002:adf:f842:0:b0:32d:baff:b0ca with SMTP id d2csp618249wrq; Wed, 25 Oct 2023 21:15:54 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFROCTqL/aVgc7i5eC+ZEKgFfHGNsLAo9xZlfpNB0hd/+dRHgxDaAjB+sb4CcYvU46xhTGb X-Received: by 2002:a05:6214:76c:b0:66c:fd11:14dd with SMTP id f12-20020a056214076c00b0066cfd1114ddmr21136129qvz.29.1698293754059; Wed, 25 Oct 2023 21:15:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698293754; cv=none; d=google.com; s=arc-20160816; b=PghMUe0qS0Qa3zi7ZSVTgyVG5/JEPxbup9q1HaIiwmDdbbUTOjS+xVJE79iVL+6Cup v8lrJ1hu3FCCmTLRx2laKx2rDK9NQIFU9Hp3eS1hUQ0v8SsIY6qjCV0uw9rssT8zNhgv 6qZFUnrw/DOCmjz9mKTYXGU0zWpsjRYB2bvvrh6Cg3Ydn25GX0LnurUOwFhFhS+fy+/Z IsmeqOmmOQrgKuaOzW1mXC+PdHpBVL8bP943POqws8N8hXwmfMdjNLg71SrFKSEaYLFr c54HjqBI2+ssowBsdJmRbkHV+36h7L/aMmCwE0/FIj2cgjtPSneE5Oh0AA8Zl30Kn2+j QuDg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=bjZedkK0rhWtjOU1AHgb9FN6j8665Di15JYAcbx3Fw8=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=Wn2scW1W4Tgqemo8bZ8/vBkHHEDSw2205F7GirocZRlDFwxLhFV/HggxT0bC3LRmSl VfK45SDz1ewWxg+tLkGl/9cdIam2RJCCvuwHKqQqVkT4UZFTarL9W0XX08Ml/WZm1qWZ AjRIXwQ5EfiU9Qss9itL8zlTvG7DOD7WFyQaFRMbS46t0u7KajtxD26CEPKBqHlZHmTJ riemYMrWrp85RhPaUNeWEKaCp1ZhMbvgbJkU2IlS93fBFjjuUxQQSCMo7o4zDRU2VYiw vrfDXrmyax3GBylJLoaiSH0iVuCL5eViDZ3/bMq1zdiJRZ8/dEJxkzhbrT6LC/A2ijcF sAOA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=bwcKXZBd; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id fo8-20020ad45f08000000b006593aafe254si9842713qvb.97.2023.10.25.21.15.53 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 25 Oct 2023 21:15:54 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=bwcKXZBd; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qvrl9-0002X0-PA; Thu, 26 Oct 2023 00:14:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qvrl8-0002WK-Fl for qemu-devel@nongnu.org; Thu, 26 Oct 2023 00:14:14 -0400 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qvrl5-0000jp-MX for qemu-devel@nongnu.org; Thu, 26 Oct 2023 00:14:14 -0400 Received: by mail-pl1-x629.google.com with SMTP id d9443c01a7336-1ca816f868fso3144165ad.1 for ; Wed, 25 Oct 2023 21:14:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698293650; x=1698898450; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=bjZedkK0rhWtjOU1AHgb9FN6j8665Di15JYAcbx3Fw8=; b=bwcKXZBdmZFp7/Vrz6NK9sRwAtjiNXDVZC5eGN51Ipjzgr4vRz/MGLZcPe2Q/cszFV J++wJHGdpCSgqIj/xzyM6uznLM3UnE/akUCwX4FR6LgNYgwPaOsgghaFgI4CujuVLPbM K/AzZzyqlWyqDNizDIDSUhxmrCtM9ZuGaKY4u+OUhwhMc9aC5hjkx7cilNh/KMu+c+Wq 9V+Vk9S26EtsQZ2etqR+jUW/74MF5A88pUUCzeHI5sANY4c8PGzsNvG8HOta6duLGxpf 8WImPVU4C/42mmjo/zbwjpomFZC2DqOalHjN0KCJHRLlwB17rBCqQjN24xF3IodTPVrW AMNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698293650; x=1698898450; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bjZedkK0rhWtjOU1AHgb9FN6j8665Di15JYAcbx3Fw8=; b=WaElmJIPC4HJ5RPHtv6MZYOB85uVK7QCHH2tPoYrKiDfwkRl0m/s8NnJQ4K5tUrtmg 0QLlCJLzct0IBRDl2anpZO1aGLIuvD5pSnM+MZnSrfwn//TYi3NMXTG5QC3m5gCD3CMU 9R0ZpZS0xtDft5Y7HpOIXF7u9ZPULiyFWPTOxu3AL92PUv7TimRSq+mYNb2bWp0jWTvb h4OC+RnFfZz3trR/w8CXeqW3Vt8Jn8Myos3ZcHtJvE2IOEZHdrTJ4j5a5SqEtYDU+yF0 PWHYYe2fjHcNA/7zpTTFl4Mjjl0EbC+2gc7C8K8cndjiSgY3rnqiUq/rY6eenGMvTvZc sA8g== X-Gm-Message-State: AOJu0YyH5U2NF5QydiBpw9sqf6uxvIV9ufT25IMr70wEkd9hW64A0JfK p2cyN86YV9kEg/GKwaRA+0Pv47cz3fkJpNMftHA= X-Received: by 2002:a17:902:f9c3:b0:1c9:d948:33ea with SMTP id kz3-20020a170902f9c300b001c9d94833eamr12101303plb.21.1698293650186; Wed, 25 Oct 2023 21:14:10 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id i12-20020a170902eb4c00b001b8b2b95068sm9953929pli.204.2023.10.25.21.14.09 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 21:14:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 6/6] tcg: Remove TCG_TARGET_HAS_neg_{i32,i64} Date: Wed, 25 Oct 2023 21:14:04 -0700 Message-Id: <20231026041404.1229328-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026041404.1229328-1-richard.henderson@linaro.org> References: <20231026041404.1229328-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The movcond opcode is now mandatory for backends to implement. Signed-off-by: Richard Henderson --- include/tcg/tcg-op-common.h | 12 ++---------- include/tcg/tcg-opc.h | 4 ++-- include/tcg/tcg.h | 1 - tcg/aarch64/tcg-target.h | 2 -- tcg/arm/tcg-target.h | 1 - tcg/i386/tcg-target.h | 2 -- tcg/loongarch64/tcg-target.h | 2 -- tcg/mips/tcg-target.h | 2 -- tcg/ppc/tcg-target.h | 2 -- tcg/riscv/tcg-target.h | 2 -- tcg/s390x/tcg-target.h | 2 -- tcg/sparc64/tcg-target.h | 2 -- tcg/tci/tcg-target.h | 2 -- tcg/optimize.c | 15 +++++---------- tcg/tcg-op.c | 10 ++++------ tcg/tcg.c | 6 ++---- tcg/tci.c | 2 -- 17 files changed, 15 insertions(+), 54 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index 677aea6dd1..7dc1184ba6 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -481,11 +481,7 @@ static inline void tcg_gen_mul_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) static inline void tcg_gen_neg_i32(TCGv_i32 ret, TCGv_i32 arg) { - if (TCG_TARGET_HAS_neg_i32) { - tcg_gen_op2_i32(INDEX_op_neg_i32, ret, arg); - } else { - tcg_gen_subfi_i32(ret, 0, arg); - } + tcg_gen_op2_i32(INDEX_op_neg_i32, ret, arg); } static inline void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg) @@ -732,11 +728,7 @@ void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); static inline void tcg_gen_neg_i64(TCGv_i64 ret, TCGv_i64 arg) { - if (TCG_TARGET_HAS_neg_i64) { - tcg_gen_op2_i64(INDEX_op_neg_i64, ret, arg); - } else { - tcg_gen_subfi_i64(ret, 0, arg); - } + tcg_gen_op2_i64(INDEX_op_neg_i64, ret, arg); } /* Size changing operations. */ diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h index ecd08db0de..b80227fa1c 100644 --- a/include/tcg/tcg-opc.h +++ b/include/tcg/tcg-opc.h @@ -100,7 +100,7 @@ DEF(ext16u_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext16u_i32)) DEF(bswap16_i32, 1, 1, 1, IMPL(TCG_TARGET_HAS_bswap16_i32)) DEF(bswap32_i32, 1, 1, 1, IMPL(TCG_TARGET_HAS_bswap32_i32)) DEF(not_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_not_i32)) -DEF(neg_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_i32)) +DEF(neg_i32, 1, 1, 0, 0) DEF(andc_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_andc_i32)) DEF(orc_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_orc_i32)) DEF(eqv_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_eqv_i32)) @@ -171,7 +171,7 @@ DEF(bswap16_i64, 1, 1, 1, IMPL64 | IMPL(TCG_TARGET_HAS_bswap16_i64)) DEF(bswap32_i64, 1, 1, 1, IMPL64 | IMPL(TCG_TARGET_HAS_bswap32_i64)) DEF(bswap64_i64, 1, 1, 1, IMPL64 | IMPL(TCG_TARGET_HAS_bswap64_i64)) DEF(not_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_not_i64)) -DEF(neg_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_neg_i64)) +DEF(neg_i64, 1, 1, 0, IMPL64) DEF(andc_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_andc_i64)) DEF(orc_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_orc_i64)) DEF(eqv_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_eqv_i64)) diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index bb522a865c..2a0893e0f7 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -82,7 +82,6 @@ typedef uint64_t TCGRegSet; #define TCG_TARGET_HAS_bswap16_i64 0 #define TCG_TARGET_HAS_bswap32_i64 0 #define TCG_TARGET_HAS_bswap64_i64 0 -#define TCG_TARGET_HAS_neg_i64 0 #define TCG_TARGET_HAS_not_i64 0 #define TCG_TARGET_HAS_andc_i64 0 #define TCG_TARGET_HAS_orc_i64 0 diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 352e19aba8..33f15a564a 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -71,7 +71,6 @@ typedef enum { #define TCG_TARGET_HAS_bswap16_i32 1 #define TCG_TARGET_HAS_bswap32_i32 1 #define TCG_TARGET_HAS_not_i32 1 -#define TCG_TARGET_HAS_neg_i32 1 #define TCG_TARGET_HAS_rot_i32 1 #define TCG_TARGET_HAS_andc_i32 1 #define TCG_TARGET_HAS_orc_i32 1 @@ -107,7 +106,6 @@ typedef enum { #define TCG_TARGET_HAS_bswap32_i64 1 #define TCG_TARGET_HAS_bswap64_i64 1 #define TCG_TARGET_HAS_not_i64 1 -#define TCG_TARGET_HAS_neg_i64 1 #define TCG_TARGET_HAS_rot_i64 1 #define TCG_TARGET_HAS_andc_i64 1 #define TCG_TARGET_HAS_orc_i64 1 diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 439898efb3..a712cc80ad 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -101,7 +101,6 @@ extern bool use_neon_instructions; #define TCG_TARGET_HAS_bswap16_i32 1 #define TCG_TARGET_HAS_bswap32_i32 1 #define TCG_TARGET_HAS_not_i32 1 -#define TCG_TARGET_HAS_neg_i32 1 #define TCG_TARGET_HAS_rot_i32 1 #define TCG_TARGET_HAS_andc_i32 1 #define TCG_TARGET_HAS_orc_i32 0 diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 7522ce7575..fa34deec47 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -135,7 +135,6 @@ typedef enum { #define TCG_TARGET_HAS_ext16u_i32 1 #define TCG_TARGET_HAS_bswap16_i32 1 #define TCG_TARGET_HAS_bswap32_i32 1 -#define TCG_TARGET_HAS_neg_i32 1 #define TCG_TARGET_HAS_not_i32 1 #define TCG_TARGET_HAS_andc_i32 have_bmi1 #define TCG_TARGET_HAS_orc_i32 0 @@ -171,7 +170,6 @@ typedef enum { #define TCG_TARGET_HAS_bswap16_i64 1 #define TCG_TARGET_HAS_bswap32_i64 1 #define TCG_TARGET_HAS_bswap64_i64 1 -#define TCG_TARGET_HAS_neg_i64 1 #define TCG_TARGET_HAS_not_i64 1 #define TCG_TARGET_HAS_andc_i64 have_bmi1 #define TCG_TARGET_HAS_orc_i64 0 diff --git a/tcg/loongarch64/tcg-target.h b/tcg/loongarch64/tcg-target.h index d1c8e6d341..428098cbc0 100644 --- a/tcg/loongarch64/tcg-target.h +++ b/tcg/loongarch64/tcg-target.h @@ -119,7 +119,6 @@ extern bool use_lsx_instructions; #define TCG_TARGET_HAS_bswap16_i32 1 #define TCG_TARGET_HAS_bswap32_i32 1 #define TCG_TARGET_HAS_not_i32 1 -#define TCG_TARGET_HAS_neg_i32 1 #define TCG_TARGET_HAS_andc_i32 1 #define TCG_TARGET_HAS_orc_i32 1 #define TCG_TARGET_HAS_eqv_i32 0 @@ -153,7 +152,6 @@ extern bool use_lsx_instructions; #define TCG_TARGET_HAS_bswap32_i64 1 #define TCG_TARGET_HAS_bswap64_i64 1 #define TCG_TARGET_HAS_not_i64 1 -#define TCG_TARGET_HAS_neg_i64 1 #define TCG_TARGET_HAS_andc_i64 1 #define TCG_TARGET_HAS_orc_i64 1 #define TCG_TARGET_HAS_eqv_i64 0 diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index 20c14224fb..b98ffae1d0 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -184,12 +184,10 @@ extern bool use_mips32r2_instructions; #endif /* optional instructions automatically implemented */ -#define TCG_TARGET_HAS_neg_i32 1 #define TCG_TARGET_HAS_ext8u_i32 0 /* andi rt, rs, 0xff */ #define TCG_TARGET_HAS_ext16u_i32 0 /* andi rt, rs, 0xffff */ #if TCG_TARGET_REG_BITS == 64 -#define TCG_TARGET_HAS_neg_i64 1 #define TCG_TARGET_HAS_ext8u_i64 0 /* andi rt, rs, 0xff */ #define TCG_TARGET_HAS_ext16u_i64 0 /* andi rt, rs, 0xffff */ #endif diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index a2856afd4d..5295e4f9ab 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -83,7 +83,6 @@ typedef enum { #define TCG_TARGET_HAS_bswap16_i32 1 #define TCG_TARGET_HAS_bswap32_i32 1 #define TCG_TARGET_HAS_not_i32 1 -#define TCG_TARGET_HAS_neg_i32 1 #define TCG_TARGET_HAS_andc_i32 1 #define TCG_TARGET_HAS_orc_i32 1 #define TCG_TARGET_HAS_eqv_i32 1 @@ -120,7 +119,6 @@ typedef enum { #define TCG_TARGET_HAS_bswap32_i64 1 #define TCG_TARGET_HAS_bswap64_i64 1 #define TCG_TARGET_HAS_not_i64 1 -#define TCG_TARGET_HAS_neg_i64 1 #define TCG_TARGET_HAS_andc_i64 1 #define TCG_TARGET_HAS_orc_i64 1 #define TCG_TARGET_HAS_eqv_i64 1 diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index f3644a8bc1..a4edc3dc74 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -109,7 +109,6 @@ extern bool have_zbb; #define TCG_TARGET_HAS_bswap16_i32 have_zbb #define TCG_TARGET_HAS_bswap32_i32 have_zbb #define TCG_TARGET_HAS_not_i32 1 -#define TCG_TARGET_HAS_neg_i32 1 #define TCG_TARGET_HAS_andc_i32 have_zbb #define TCG_TARGET_HAS_orc_i32 have_zbb #define TCG_TARGET_HAS_eqv_i32 have_zbb @@ -142,7 +141,6 @@ extern bool have_zbb; #define TCG_TARGET_HAS_bswap32_i64 have_zbb #define TCG_TARGET_HAS_bswap64_i64 have_zbb #define TCG_TARGET_HAS_not_i64 1 -#define TCG_TARGET_HAS_neg_i64 1 #define TCG_TARGET_HAS_andc_i64 have_zbb #define TCG_TARGET_HAS_orc_i64 have_zbb #define TCG_TARGET_HAS_eqv_i64 have_zbb diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h index 2c936c1bcb..e69b0d2ddd 100644 --- a/tcg/s390x/tcg-target.h +++ b/tcg/s390x/tcg-target.h @@ -82,7 +82,6 @@ extern uint64_t s390_facilities[3]; #define TCG_TARGET_HAS_bswap16_i32 1 #define TCG_TARGET_HAS_bswap32_i32 1 #define TCG_TARGET_HAS_not_i32 HAVE_FACILITY(MISC_INSN_EXT3) -#define TCG_TARGET_HAS_neg_i32 1 #define TCG_TARGET_HAS_andc_i32 HAVE_FACILITY(MISC_INSN_EXT3) #define TCG_TARGET_HAS_orc_i32 HAVE_FACILITY(MISC_INSN_EXT3) #define TCG_TARGET_HAS_eqv_i32 HAVE_FACILITY(MISC_INSN_EXT3) @@ -117,7 +116,6 @@ extern uint64_t s390_facilities[3]; #define TCG_TARGET_HAS_bswap32_i64 1 #define TCG_TARGET_HAS_bswap64_i64 1 #define TCG_TARGET_HAS_not_i64 HAVE_FACILITY(MISC_INSN_EXT3) -#define TCG_TARGET_HAS_neg_i64 1 #define TCG_TARGET_HAS_andc_i64 HAVE_FACILITY(MISC_INSN_EXT3) #define TCG_TARGET_HAS_orc_i64 HAVE_FACILITY(MISC_INSN_EXT3) #define TCG_TARGET_HAS_eqv_i64 HAVE_FACILITY(MISC_INSN_EXT3) diff --git a/tcg/sparc64/tcg-target.h b/tcg/sparc64/tcg-target.h index 4c286c6006..f8cf145266 100644 --- a/tcg/sparc64/tcg-target.h +++ b/tcg/sparc64/tcg-target.h @@ -91,7 +91,6 @@ extern bool use_vis3_instructions; #define TCG_TARGET_HAS_ext16u_i32 0 #define TCG_TARGET_HAS_bswap16_i32 0 #define TCG_TARGET_HAS_bswap32_i32 0 -#define TCG_TARGET_HAS_neg_i32 1 #define TCG_TARGET_HAS_not_i32 1 #define TCG_TARGET_HAS_andc_i32 1 #define TCG_TARGET_HAS_orc_i32 1 @@ -127,7 +126,6 @@ extern bool use_vis3_instructions; #define TCG_TARGET_HAS_bswap16_i64 0 #define TCG_TARGET_HAS_bswap32_i64 0 #define TCG_TARGET_HAS_bswap64_i64 0 -#define TCG_TARGET_HAS_neg_i64 1 #define TCG_TARGET_HAS_not_i64 1 #define TCG_TARGET_HAS_andc_i64 1 #define TCG_TARGET_HAS_orc_i64 1 diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 3503fc4a4c..2a13816c8e 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -65,7 +65,6 @@ #define TCG_TARGET_HAS_clz_i32 1 #define TCG_TARGET_HAS_ctz_i32 1 #define TCG_TARGET_HAS_ctpop_i32 1 -#define TCG_TARGET_HAS_neg_i32 1 #define TCG_TARGET_HAS_not_i32 1 #define TCG_TARGET_HAS_orc_i32 1 #define TCG_TARGET_HAS_rot_i32 1 @@ -99,7 +98,6 @@ #define TCG_TARGET_HAS_clz_i64 1 #define TCG_TARGET_HAS_ctz_i64 1 #define TCG_TARGET_HAS_ctpop_i64 1 -#define TCG_TARGET_HAS_neg_i64 1 #define TCG_TARGET_HAS_not_i64 1 #define TCG_TARGET_HAS_orc_i64 1 #define TCG_TARGET_HAS_rot_i64 1 diff --git a/tcg/optimize.c b/tcg/optimize.c index 27b1eaaa8d..5e16800cfa 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -1930,7 +1930,7 @@ static void fold_setcond_tst_pow2(OptContext *ctx, TCGOp *op, bool neg) sub_opc = INDEX_op_sub_i32; xor_opc = INDEX_op_xor_i32; shr_opc = INDEX_op_shr_i32; - neg_opc = TCG_TARGET_HAS_neg_i32 ? INDEX_op_neg_i32 : 0; + neg_opc = INDEX_op_neg_i32; uext_opc = TCG_TARGET_HAS_extract_i32 ? INDEX_op_extract_i32 : 0; sext_opc = TCG_TARGET_HAS_sextract_i32 ? INDEX_op_sextract_i32 : 0; break; @@ -1939,7 +1939,7 @@ static void fold_setcond_tst_pow2(OptContext *ctx, TCGOp *op, bool neg) sub_opc = INDEX_op_sub_i64; xor_opc = INDEX_op_xor_i64; shr_opc = INDEX_op_shr_i64; - neg_opc = TCG_TARGET_HAS_neg_i64 ? INDEX_op_neg_i64 : 0; + neg_opc = INDEX_op_neg_i64; uext_opc = TCG_TARGET_HAS_extract_i64 ? INDEX_op_extract_i64 : 0; sext_opc = TCG_TARGET_HAS_sextract_i64 ? INDEX_op_sextract_i64 : 0; break; @@ -1986,15 +1986,10 @@ static void fold_setcond_tst_pow2(OptContext *ctx, TCGOp *op, bool neg) op2->args[0] = ret; op2->args[1] = ret; op2->args[2] = arg_new_constant(ctx, 1); - } else if (neg && neg_opc) { + } else if (neg) { op2 = tcg_op_insert_after(ctx->tcg, op, neg_opc, 2); op2->args[0] = ret; op2->args[1] = ret; - } else if (neg) { - op2 = tcg_op_insert_after(ctx->tcg, op, sub_opc, 3); - op2->args[0] = ret; - op2->args[1] = arg_new_constant(ctx, 0); - op2->args[2] = ret; } } @@ -2205,11 +2200,11 @@ static bool fold_sub_to_neg(OptContext *ctx, TCGOp *op) switch (ctx->type) { case TCG_TYPE_I32: neg_op = INDEX_op_neg_i32; - have_neg = TCG_TARGET_HAS_neg_i32; + have_neg = true; break; case TCG_TYPE_I64: neg_op = INDEX_op_neg_i64; - have_neg = TCG_TARGET_HAS_neg_i64; + have_neg = true; break; case TCG_TYPE_V64: case TCG_TYPE_V128: diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 51de796769..59deb3cbbb 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -138,9 +138,8 @@ void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2) { - if (arg1 == 0 && TCG_TARGET_HAS_neg_i32) { - /* Don't recurse with tcg_gen_neg_i32. */ - tcg_gen_op2_i32(INDEX_op_neg_i32, ret, arg2); + if (arg1 == 0) { + tcg_gen_neg_i32(ret, arg2); } else { tcg_gen_sub_i32(ret, tcg_constant_i32(arg1), arg2); } @@ -1342,9 +1341,8 @@ void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2) { - if (arg1 == 0 && TCG_TARGET_HAS_neg_i64) { - /* Don't recurse with tcg_gen_neg_i64. */ - tcg_gen_op2_i64(INDEX_op_neg_i64, ret, arg2); + if (arg1 == 0) { + tcg_gen_neg_i64(ret, arg2); } else if (TCG_TARGET_REG_BITS == 64) { tcg_gen_sub_i64(ret, tcg_constant_i64(arg1), arg2); } else { diff --git a/tcg/tcg.c b/tcg/tcg.c index 5da03ba11d..a507c111cf 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1885,6 +1885,7 @@ bool tcg_op_supported(TCGOpcode op) case INDEX_op_st_i32: case INDEX_op_add_i32: case INDEX_op_sub_i32: + case INDEX_op_neg_i32: case INDEX_op_mul_i32: case INDEX_op_and_i32: case INDEX_op_or_i32: @@ -1942,8 +1943,6 @@ bool tcg_op_supported(TCGOpcode op) return TCG_TARGET_HAS_bswap32_i32; case INDEX_op_not_i32: return TCG_TARGET_HAS_not_i32; - case INDEX_op_neg_i32: - return TCG_TARGET_HAS_neg_i32; case INDEX_op_andc_i32: return TCG_TARGET_HAS_andc_i32; case INDEX_op_orc_i32: @@ -1982,6 +1981,7 @@ bool tcg_op_supported(TCGOpcode op) case INDEX_op_st_i64: case INDEX_op_add_i64: case INDEX_op_sub_i64: + case INDEX_op_neg_i64: case INDEX_op_mul_i64: case INDEX_op_and_i64: case INDEX_op_or_i64: @@ -2038,8 +2038,6 @@ bool tcg_op_supported(TCGOpcode op) return TCG_TARGET_HAS_bswap64_i64; case INDEX_op_not_i64: return TCG_TARGET_HAS_not_i64; - case INDEX_op_neg_i64: - return TCG_TARGET_HAS_neg_i64; case INDEX_op_andc_i64: return TCG_TARGET_HAS_andc_i64; case INDEX_op_orc_i64: diff --git a/tcg/tci.c b/tcg/tci.c index 5e1c4a491d..39adcb7d82 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -745,12 +745,10 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, regs[r0] = ~regs[r1]; break; #endif -#if TCG_TARGET_HAS_neg_i32 || TCG_TARGET_HAS_neg_i64 CASE_32_64(neg) tci_args_rr(insn, &r0, &r1); regs[r0] = -regs[r1]; break; -#endif #if TCG_TARGET_REG_BITS == 64 /* Load/store operations (64 bit). */