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Wysocki" , Shyam Sundar S K , "open list:PCI SUBSYSTEM" , "open list:X86 PLATFORM DRIVERS" , Lukas Wunner , Kai-Heng Feng , Mario Limonciello Subject: [PATCH 1/4] PCI: Make d3cold_allowed sysfs attribute read only Date: Tue, 24 Oct 2023 21:05:43 -0500 Message-ID: <20231025020546.504-2-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231025020546.504-1-mario.limonciello@amd.com> References: <20231025020546.504-1-mario.limonciello@amd.com> X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-OrganizationHeadersPreserved: SATLEXMB04.amd.com X-EOPAttributedMessage: 0 X-CrossPremisesHeadersPromoted: CO1PEPF000044EE.namprd05.prod.outlook.com X-CrossPremisesHeadersFiltered: CO1PEPF000044EE.namprd05.prod.outlook.com X-MS-TrafficTypeDiagnostic: CO1PEPF000044EE:EE_|BL1PR12MB5174:EE_|MN0PR12MB6101:EE_|SJ2PR12MB9007:EE_ X-MS-Office365-Filtering-Correlation-Id: aef36bd4-f8ba-4c9c-a556-08dbd64d6307 X-Microsoft-Antispam: BCL:0; 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Userspace was able to opt PCIe devices into d3cold support by using the `d3cold_allowed` sysfs attribute. The policy changed to default to enabled with commit 4f9c1397e2e8 ("PCI/PM: Enable D3/D3cold by default for most devices"). The sysfs file remains however and can potentially allow userspace to prevent the SoC from getting into the deepest sleep state on modern systems. For debugging purposes `pcie_port_pm=` can be used to control whether a PCI port will go into D3cold and runtime PM can be turned off by `/sys/bus/pci/devices/*/power/control` on PCI end points. Change the sysfs attribute to a noop that ignores the input when written and shows a warning. Simplify the internal kernel logic to drop `d3cold_allowed`. Link: https://lore.kernel.org/linux-pci/20230918132424.GA11357@wunner.de/ Signed-off-by: Mario Limonciello --- Changes from previous submission: * Update commit message * Roll into series for D3 related handling --- Documentation/ABI/testing/sysfs-bus-pci | 4 ++-- drivers/pci/pci-acpi.c | 2 +- drivers/pci/pci-sysfs.c | 14 ++------------ drivers/pci/pci.c | 3 +-- include/linux/pci.h | 1 - 5 files changed, 6 insertions(+), 18 deletions(-) diff --git a/Documentation/ABI/testing/sysfs-bus-pci b/Documentation/ABI/testing/sysfs-bus-pci index ecf47559f495..b5db141dfee6 100644 --- a/Documentation/ABI/testing/sysfs-bus-pci +++ b/Documentation/ABI/testing/sysfs-bus-pci @@ -283,8 +283,8 @@ Description: device will never be put into D3Cold state. If it is set, the device may be put into D3Cold state if other requirements are satisfied too. Reading this attribute will show the current - value of d3cold_allowed bit. Writing this attribute will set - the value of d3cold_allowed bit. + value of no_d3cold bit. + Writing to this attribute is deprecated and will do nothing. What: /sys/bus/pci/devices/.../sriov_totalvfs Date: November 2012 diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c index 05b7357bd258..a05350a4e49c 100644 --- a/drivers/pci/pci-acpi.c +++ b/drivers/pci/pci-acpi.c @@ -911,7 +911,7 @@ pci_power_t acpi_pci_choose_state(struct pci_dev *pdev) { int acpi_state, d_max; - if (pdev->no_d3cold || !pdev->d3cold_allowed) + if (pdev->no_d3cold) d_max = ACPI_STATE_D3_HOT; else d_max = ACPI_STATE_D3_COLD; diff --git a/drivers/pci/pci-sysfs.c b/drivers/pci/pci-sysfs.c index 5e741a05cf2c..52ed5a55a371 100644 --- a/drivers/pci/pci-sysfs.c +++ b/drivers/pci/pci-sysfs.c @@ -523,17 +523,7 @@ static ssize_t d3cold_allowed_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { - struct pci_dev *pdev = to_pci_dev(dev); - unsigned long val; - - if (kstrtoul(buf, 0, &val) < 0) - return -EINVAL; - - pdev->d3cold_allowed = !!val; - pci_bridge_d3_update(pdev); - - pm_runtime_resume(dev); - + dev_warn_once(dev, "pci: writing to d3cold_allowed is deprecated\n"); return count; } @@ -541,7 +531,7 @@ static ssize_t d3cold_allowed_show(struct device *dev, struct device_attribute *attr, char *buf) { struct pci_dev *pdev = to_pci_dev(dev); - return sysfs_emit(buf, "%u\n", pdev->d3cold_allowed); + return sysfs_emit(buf, "%u\n", !pdev->no_d3cold); } static DEVICE_ATTR_RW(d3cold_allowed); #endif diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 59c01d68c6d5..8c5a6f68f63d 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -3067,7 +3067,7 @@ static int pci_dev_check_d3cold(struct pci_dev *dev, void *data) bool *d3cold_ok = data; if (/* The device needs to be allowed to go D3cold ... */ - dev->no_d3cold || !dev->d3cold_allowed || + dev->no_d3cold || /* ... and if it is wakeup capable to do so from D3cold. */ (device_may_wakeup(&dev->dev) && @@ -3204,7 +3204,6 @@ void pci_pm_init(struct pci_dev *dev) dev->d3hot_delay = PCI_PM_D3HOT_WAIT; dev->d3cold_delay = PCI_PM_D3COLD_WAIT; dev->bridge_d3 = pci_bridge_d3_possible(dev); - dev->d3cold_allowed = true; dev->d1_support = false; dev->d2_support = false; diff --git a/include/linux/pci.h b/include/linux/pci.h index 8c7c2c3c6c65..5f4ed71d31f5 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -376,7 +376,6 @@ struct pci_dev { unsigned int no_d1d2:1; /* D1 and D2 are forbidden */ unsigned int no_d3cold:1; /* D3cold is forbidden */ unsigned int bridge_d3:1; /* Allow D3 for bridge */ - unsigned int d3cold_allowed:1; /* D3cold is allowed by user */ unsigned int mmio_always_on:1; /* Disallow turning off io/mem decoding during BAR sizing */ unsigned int wakeup_prepared:1; From patchwork Wed Oct 25 02:05:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 739512 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0E6CAC25B67 for ; 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Wysocki" , Shyam Sundar S K , "open list:PCI SUBSYSTEM" , "open list:X86 PLATFORM DRIVERS" , Lukas Wunner , Kai-Heng Feng , Mario Limonciello Subject: [PATCH 2/4] PCI: Refresh root ports in pci_bridge_d3_update() Date: Tue, 24 Oct 2023 21:05:44 -0500 Message-ID: <20231025020546.504-3-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231025020546.504-1-mario.limonciello@amd.com> References: <20231025020546.504-1-mario.limonciello@amd.com> X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-OrganizationHeadersPreserved: SATLEXMB04.amd.com X-EOPAttributedMessage: 0 X-CrossPremisesHeadersPromoted: CO1PEPF000044F2.namprd05.prod.outlook.com X-CrossPremisesHeadersFiltered: CO1PEPF000044F2.namprd05.prod.outlook.com X-MS-TrafficTypeDiagnostic: CO1PEPF000044F2:EE_|DM4PR12MB7695:EE_|MN0PR12MB6101:EE_|SJ2PR12MB9007:EE_ X-MS-Office365-Filtering-Correlation-Id: 788c1f59-8068-4e6b-07c8-08dbd64d630a X-Microsoft-Antispam: BCL:0; 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If called on a root port, use `no_d3cold` variable to decide policy and also immediately refresh whether D3 is possible. Signed-off-by: Mario Limonciello --- Changes from RFC v1: * New patch --- drivers/pci/pci.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 8c5a6f68f63d..28f70e8ea478 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -3021,6 +3021,9 @@ bool pci_bridge_d3_possible(struct pci_dev *bridge) if (pci_bridge_d3_disable) return false; + if (bridge->no_d3cold) + return false; + /* * Hotplug ports handled by firmware in System Management Mode * may not be put into D3 by the OS (Thunderbolt on non-Macs). @@ -3096,7 +3099,11 @@ void pci_bridge_d3_update(struct pci_dev *dev) bool d3cold_ok = true; bridge = pci_upstream_bridge(dev); - if (!bridge || !pci_bridge_d3_possible(bridge)) + if (!bridge) { + dev->bridge_d3 = pci_bridge_d3_possible(dev); + return; + } + if (!pci_bridge_d3_possible(bridge)) return; /* From patchwork Wed Oct 25 02:05:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 739511 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CC0C5C25B6E for ; Thu, 26 Oct 2023 18:00:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230146AbjJZSAQ (ORCPT ); Thu, 26 Oct 2023 14:00:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60798 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230330AbjJZSAP (ORCPT ); Thu, 26 Oct 2023 14:00:15 -0400 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2056.outbound.protection.outlook.com [40.107.92.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BBD5B194; Thu, 26 Oct 2023 11:00:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=RfPGze8CFknUAidbc2UPJuuVpNgiELx/WgMfOoRF/IolpME1SLPcbppdGSwxA/yGCtoTY6oe5vSM/1Sf3B2EL+cGT4ttC++OXC1F4EswY0DhNS61SjTcQveRwbsVB6BOLKGx7vnQx24uBC/ZsZsT8KI8BaheGvBx8B5w2kcLjpBlF5Tkg7atcmdB51oYJfhLwPLOKiJlfY4Pe7dGkHrn35XPZc3of27o0mWP9UhqHZlM1pboQZ5woZw2w84NoK596gIL6J0xFM4lc14Zb/FXTTYZn+cUPKqs3e9PD0VVhDl138+NljlvzK6UoBVbEcPVJnWGxzNg3lsNTju8fN0AEg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=TeMEEDA0o/xz+YB5OAwmFUl9k7FxdNparpTFBxGlRcE=; b=gJJUV3NC1WM8zLxOsehXyAYQrS22SbksIARrO+YIe4PJ2w1gGa61VTxnz9lUK5FTGvp/NIidPF/AWAwQh8AR7ZVmLoxtQWbKdGU3SfEJqsJ0/XxPi6oUQeBEGwo6pZTdbHFZHNplyFJt3ji9eNJPB+6/dmKIrpSuHRMy0VIQKJCmKB0jkNHypstdB7wOpL4IrUdJwmX4JWeJ8iLapXfd6kCLybq2A107k9tIaN7H/hHbtueeBOqA4Sts1eZY/CDPq6TU1jt13GO1O9z9BR2BeCuqW3tYIZyk06sHZJC8XBZ6cin1LtuvzHXXT23HSpvPaFLd/UEObSX6NPTo0oS6Dg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=amd.com; dmarc=pass action=none header.from=amd.com; dkim=pass header.d=amd.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=TeMEEDA0o/xz+YB5OAwmFUl9k7FxdNparpTFBxGlRcE=; b=H4zmO76hEKeEdGHk/bAWcEeA4yLSSF4oY/a1yK+Fo/Wkglerw7s9jgSVVLkylNF9UVkmYYCMO7+6ScOOJp2rXS/XRstBYN6xZnzPslfeDwC602QHzV7CLJTdCO8vkVqPUpOwHdxXooP6QDdAOM/d/VgMRlXQaYmJa8QSkF2jQZE= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=amd.com; Received: from MN0PR12MB6101.namprd12.prod.outlook.com (2603:10b6:208:3cb::10) by SJ2PR12MB9007.namprd12.prod.outlook.com (2603:10b6:a03:541::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6907.29; Thu, 26 Oct 2023 18:00:09 +0000 Received: from MN0PR12MB6101.namprd12.prod.outlook.com ([fe80::83d7:9c4f:4d9b:1f2a]) by MN0PR12MB6101.namprd12.prod.outlook.com ([fe80::83d7:9c4f:4d9b:1f2a%4]) with mapi id 15.20.6907.022; Thu, 26 Oct 2023 18:00:08 +0000 Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=amd.com; pr=C From: Mario Limonciello To: Bjorn Helgaas , Hans de Goede , =?utf-8?q?Ilpo_J=C3=A4rvinen?= CC: "Rafael J . Wysocki" , Shyam Sundar S K , "open list:PCI SUBSYSTEM" , "open list:X86 PLATFORM DRIVERS" , Lukas Wunner , Kai-Heng Feng , Mario Limonciello , "Rafael J. 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This driver can be compiled as a module, so export the symbol for when it is a module. Acked-by: "Rafael J. Wysocki" Signed-off-by: Mario Limonciello --- drivers/acpi/x86/s2idle.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/acpi/x86/s2idle.c b/drivers/acpi/x86/s2idle.c index 08f7c6708206..de9c313c21fa 100644 --- a/drivers/acpi/x86/s2idle.c +++ b/drivers/acpi/x86/s2idle.c @@ -322,6 +322,7 @@ int acpi_get_lps0_constraint(struct acpi_device *adev) return ACPI_STATE_UNKNOWN; } +EXPORT_SYMBOL_GPL(acpi_get_lps0_constraint); static void lpi_check_constraints(void) { From patchwork Wed Oct 25 02:05:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 739219 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C411EC25B67 for ; Thu, 26 Oct 2023 18:00:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230330AbjJZSAS (ORCPT ); Thu, 26 Oct 2023 14:00:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59256 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230309AbjJZSAR (ORCPT ); Thu, 26 Oct 2023 14:00:17 -0400 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2056.outbound.protection.outlook.com [40.107.92.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E0457AC; Thu, 26 Oct 2023 11:00:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=FVkyrgovUGxajXJwX9hgWrO6Qa/R6CD/H9xjbwXDMw6tTG/wp2rGVb9uIt68JNoFwnAH8niblsW4yTx5jKQOhLk8HNE2cKM9fHKyOoxxY96kkBVAYrbREL57TTU7aHf4LCKo8ckGJHBsHMcX/60kBOpHGesbavqnxijDr/gu8M6GbiWyWhNwSBJnRLBsV+6x76KQOSGjXSxcFpJ97/cGGmjL3v+AeZ7UGj27SwHLyQxnto/sreC494Q5RTdIGSGUN5ly/eixxtTwBJA2+Mg8IJMO+q3M9RcMNOv7EXPgxOML2Ues2ObX53PwmXM/c4EXylw47G5MEAQh6RTIoC1BXg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=+F3uO+5IWBcf7q6yTe2ZhI9rXKBglfqAeJ41mJytnzo=; b=OGnkPX2fjxgeAmFyvYAJ6JUnrX2h0B99HRYxeZd5jDZAUivcWq++dgbukf1QU8LiR5/+3OXQl9NEw/+JZYk47+tgnIOpR3ErlYs9EJAlUWonqtQ+l5sEfNWuT4l/kPQICGJhjPuKAZ/FGKKy1weinxS6FXz3J0kVkPDDcssdaT47SzEmzWdIHlayalHEoFsPFLMy8cpi6ub12YdMu/QP3T7gQFe9rkXr2owKaKF/Shhe8+CnisrOCNNlugsCuOk6rte8ZAaLfxLo/e0ALOilLrabd0J+Zid1OGkdIEG4jezFFru8yK0RKwEgikKsxXpD0jwPk8zXGuE1GQM5WXTPFg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=amd.com; dmarc=pass action=none header.from=amd.com; dkim=pass header.d=amd.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=+F3uO+5IWBcf7q6yTe2ZhI9rXKBglfqAeJ41mJytnzo=; b=Re41GFkRETwo0vzHdyHGBzWRaOafIBR6pIxj9vCP2pX9TePkW9hrtFrRivCSY5s36VaeFsuAd1OIlR/1j1UpWJexyIiHKFH47CZzvIGcwqntVHJojoG1fsrovDccUVOBR0NH1rRflTetkABbxzXi2vbye+JyBpECQMbEd8CZrJI= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=amd.com; Received: from MN0PR12MB6101.namprd12.prod.outlook.com (2603:10b6:208:3cb::10) by SJ2PR12MB9007.namprd12.prod.outlook.com (2603:10b6:a03:541::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6907.29; Thu, 26 Oct 2023 18:00:11 +0000 Received: from MN0PR12MB6101.namprd12.prod.outlook.com ([fe80::83d7:9c4f:4d9b:1f2a]) by MN0PR12MB6101.namprd12.prod.outlook.com ([fe80::83d7:9c4f:4d9b:1f2a%4]) with mapi id 15.20.6907.022; Thu, 26 Oct 2023 18:00:11 +0000 Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=amd.com; pr=C From: Mario Limonciello To: Bjorn Helgaas , Hans de Goede , =?utf-8?q?Ilpo_J=C3=A4rvinen?= CC: "Rafael J . Wysocki" , Shyam Sundar S K , "open list:PCI SUBSYSTEM" , "open list:X86 PLATFORM DRIVERS" , Lukas Wunner , Kai-Heng Feng , Mario Limonciello Subject: [PATCH 4/4] platform/x86/amd: pmc: Add support for using constraints to decide D3 policy Date: Tue, 24 Oct 2023 21:05:46 -0500 Message-ID: <20231025020546.504-5-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231025020546.504-1-mario.limonciello@amd.com> References: <20231025020546.504-1-mario.limonciello@amd.com> X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-OrganizationHeadersPreserved: SATLEXMB04.amd.com X-EOPAttributedMessage: 0 X-CrossPremisesHeadersPromoted: CO1PEPF000044F3.namprd05.prod.outlook.com X-CrossPremisesHeadersFiltered: CO1PEPF000044F3.namprd05.prod.outlook.com X-MS-TrafficTypeDiagnostic: CO1PEPF000044F3:EE_|MN6PR12MB8591:EE_|MN0PR12MB6101:EE_|SJ2PR12MB9007:EE_ X-MS-Office365-Filtering-Correlation-Id: b86bee8d-d6c4-4faf-1802-08dbd64d635b X-Microsoft-Antispam: BCL:0; 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This policy doesn't match what Windows uses. In Windows the driver stack includes a "Power Engine Plugin" (uPEP driver) to decide the policy for integrated devices using PEP device constraints. Device constraints are expressed as a number in the _DSM of the PNP0D80 device and exported by the kernel in acpi_get_lps0_constraint(). Add support for SoCs to use constraints on Linux as well for deciding target state for integrated PCI bridges. Disable existing production SoCs by default with this change. Link: https://learn.microsoft.com/en-us/windows-hardware/design/device-experiences/platform-design-for-modern-standby#low-power-core-silicon-cpu-soc-dram Signed-off-by: Mario Limonciello --- Changes from RFC v1: * Use pci_d3cold_*able() instead --- drivers/platform/x86/amd/pmc/pmc.c | 57 ++++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/drivers/platform/x86/amd/pmc/pmc.c b/drivers/platform/x86/amd/pmc/pmc.c index c1e788b67a74..346564517667 100644 --- a/drivers/platform/x86/amd/pmc/pmc.c +++ b/drivers/platform/x86/amd/pmc/pmc.c @@ -741,6 +741,61 @@ static int amd_pmc_czn_wa_irq1(struct amd_pmc_dev *pdev) return 0; } +static inline void amd_pmc_apply_constraint(struct pci_dev *pci_dev, bool apply) +{ + if (apply) + pci_d3cold_disable(pci_dev); + else + pci_d3cold_enable(pci_dev); +} + +/* + * Constraints are specified in the ACPI LPS0 device and specify what the + * platform intended for devices that are internal to the SoC. + * + * If a constraint is present and >= to ACPI_STATE_D3, then enable D3. + * If a constraint is not present or < ACPI_STATE_D3, then disable D3. + */ +static void amd_pmc_check_constraints(struct amd_pmc_dev *pdev, bool apply) +{ + struct pci_dev *pci_dev = NULL; + struct acpi_device *adev; + int constraint; + + switch (pdev->cpu_id) { + case AMD_CPU_ID_RV: + case AMD_CPU_ID_RN: + case AMD_CPU_ID_YC: + case AMD_CPU_ID_CB: + case AMD_CPU_ID_PS: + case AMD_CPU_ID_SP: + return; + default: + break; + } + + while ((pci_dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, pci_dev))) { + adev = ACPI_COMPANION(&pci_dev->dev); + if (!adev) + continue; + constraint = acpi_get_lps0_constraint(adev); + dev_dbg(&pci_dev->dev, "constraint is %d\n", constraint); + + switch (constraint) { + case ACPI_STATE_UNKNOWN: + case ACPI_STATE_D0: + case ACPI_STATE_D1: + case ACPI_STATE_D2: + amd_pmc_apply_constraint(pci_dev, apply); + continue; + /* use the logic pci_bridge_d3_possible() to decide */ + case ACPI_STATE_D3: + default: + continue; + } + } +} + static int amd_pmc_verify_czn_rtc(struct amd_pmc_dev *pdev, u32 *arg) { struct rtc_device *rtc_device; @@ -1074,6 +1129,7 @@ static int amd_pmc_probe(struct platform_device *pdev) amd_pmc_quirks_init(dev); } + amd_pmc_check_constraints(dev, TRUE); amd_pmc_dbgfs_register(dev); pm_report_max_hw_sleep(U64_MAX); return 0; @@ -1089,6 +1145,7 @@ static void amd_pmc_remove(struct platform_device *pdev) if (IS_ENABLED(CONFIG_SUSPEND)) acpi_unregister_lps0_dev(&amd_pmc_s2idle_dev_ops); + amd_pmc_check_constraints(dev, FALSE); amd_pmc_dbgfs_unregister(dev); pci_dev_put(dev->rdev); mutex_destroy(&dev->lock);