From patchwork Fri Nov 3 16:25:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan O'Donoghue X-Patchwork-Id: 742350 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 135EDC0018C for ; Fri, 3 Nov 2023 16:25:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343554AbjKCQZT (ORCPT ); Fri, 3 Nov 2023 12:25:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36932 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230121AbjKCQZR (ORCPT ); Fri, 3 Nov 2023 12:25:17 -0400 Received: from mail-wr1-x434.google.com (mail-wr1-x434.google.com [IPv6:2a00:1450:4864:20::434]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B348DD45 for ; Fri, 3 Nov 2023 09:25:08 -0700 (PDT) Received: by mail-wr1-x434.google.com with SMTP id ffacd0b85a97d-32f78dcf036so2055301f8f.0 for ; Fri, 03 Nov 2023 09:25:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699028707; x=1699633507; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=KzXkSGua52mfDZp2DkUv0+KW6F6b7LlJDY38k2KiigI=; b=H6461LuPQaPdJJymvEd8cLeb3V9fghIeRd05NL/Si2cKKLKafCLx0MFeFToOHMm92c AUyc+5XwoIkzL09UCk/lCCBqpIlHLxZyKUQbITjWKkHRPAbb0orrWHAo0L0t71NMDpAM skok1huEO0GIgaZSJwWIpS4bsMT8kAOWllXpHsabp3E1HFrCDJfMfBC+3APfODtP3Owa rG5FKPS473TjtiF3UIBR6z0G2eP6urajh5BXRnRkIiih23AU9yxC+F/CfqvvG2FOjklL NZD9Byr1xbAjnZaFy5gQjgqFsnl9qvcnfEt8I5yt723wn8Y64pLeXaIJcsI9W1N9vbLJ W0Wg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699028707; x=1699633507; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KzXkSGua52mfDZp2DkUv0+KW6F6b7LlJDY38k2KiigI=; b=s/xFzNby01e6NsfoPNyuHg1bTCiBBiEIYOqPRawCMZoJaLxPN4iPKgzy/6vdfldc9O d2DnsccY+kEpwqM4IeEewNZNF7mcxxitYo6L1fppQN5Cv32VugPGBa/R5omyYe1Dn2kQ rrX+JkYpE5PphzOfaxiHbGjY5zwpL85+r4/6HM9SgIJKi5e8t6vJUirEIJQIX6BeROuX Q3S02jzNOMi1Hk6zuUzUppPkL0308taxcdv9jlUjzyVwEXpEUg5jjyzj+nTS7MOrl+oZ 3UPdgPDESuJ4dHZhcBowEENnJBdVkFAEM7VwJIXH76XtTWSavSkbCOtAwla33L3C3XzH WcHw== X-Gm-Message-State: AOJu0YzLqGXXP3/ZT+cDK1nGtg8iH1mwJ6PHAG0B5TKAqfoc93C6pczz IXYEBsZxifhC1wLYre87euS7Ng== X-Google-Smtp-Source: AGHT+IF7Bc9i7BQ/TGY4nIIawPLpBHEaEXHI8Rgu+HFqkPoxbu6ORDttK5FRpzZKdGhmSgPmWIpiXw== X-Received: by 2002:a5d:648b:0:b0:32f:8bbb:fc00 with SMTP id o11-20020a5d648b000000b0032f8bbbfc00mr3496585wri.12.1699028707025; Fri, 03 Nov 2023 09:25:07 -0700 (PDT) Received: from [127.0.0.1] ([37.228.218.3]) by smtp.gmail.com with ESMTPSA id x13-20020a5d650d000000b003142e438e8csm2219972wru.26.2023.11.03.09.25.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Nov 2023 09:25:06 -0700 (PDT) From: Bryan O'Donoghue Date: Fri, 03 Nov 2023 16:25:04 +0000 Subject: [PATCH v2 1/6] media: dt-bindings: media: camss: Add qcom,sc8280xp-camss binding MIME-Version: 1.0 Message-Id: <20231103-b4-camss-sc8280xp-v2-1-b7af4d253a20@linaro.org> References: <20231103-b4-camss-sc8280xp-v2-0-b7af4d253a20@linaro.org> In-Reply-To: <20231103-b4-camss-sc8280xp-v2-0-b7af4d253a20@linaro.org> To: hverkuil-cisco@xs4all.nl, laurent.pinchart@ideasonboard.com, Andy Gross , Bjorn Andersson , Konrad Dybcio , Robert Foss , Todor Tomov , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , vincent.knecht@mailoo.org, matti.lehtimaki@gmail.com, quic_grosikop@quicinc.com Cc: linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Bryan O'Donoghue , Krzysztof Kozlowski X-Mailer: b4 0.13-dev-26615 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add bindings for qcom,sc8280xp-camss in order to support the camera subsystem for sc8280xp as found in the Lenovo x13s Laptop. This patch depends on: https://lore.kernel.org/linux-arm-msm/20231026105345.3376-2-bryan.odonoghue@linaro.org/ https://lore.kernel.org/linux-arm-msm/20231026105345.3376-3-bryan.odonoghue@linaro.org/ Signed-off-by: Bryan O'Donoghue Reviewed-by: Krzysztof Kozlowski --- .../bindings/media/qcom,sc8280xp-camss.yaml | 581 +++++++++++++++++++++ 1 file changed, 581 insertions(+) diff --git a/Documentation/devicetree/bindings/media/qcom,sc8280xp-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sc8280xp-camss.yaml new file mode 100644 index 0000000000000..88216c1a37709 --- /dev/null +++ b/Documentation/devicetree/bindings/media/qcom,sc8280xp-camss.yaml @@ -0,0 +1,581 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/qcom,sc8280xp-camss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SC8280XP Camera Subsystem (CAMSS) + +maintainers: + - Bryan O'Donoghue + +description: | + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms. + +properties: + compatible: + const: qcom,sc8280xp-camss + + clocks: + maxItems: 63 + + clock-names: + items: + - const: camnoc_axi + - const: camnoc_axi_src + - const: cpas_ahb + - const: cphy_rx_src + - const: csiphy0 + - const: csiphy0_timer_src + - const: csiphy0_timer + - const: csiphy1 + - const: csiphy1_timer_src + - const: csiphy1_timer + - const: csiphy2 + - const: csiphy2_timer_src + - const: csiphy2_timer + - const: csiphy3 + - const: csiphy3_timer_src + - const: csiphy3_timer + - const: vfe0_axi + - const: vfe0_src + - const: vfe0 + - const: vfe0_cphy_rx + - const: vfe0_csid_src + - const: vfe0_csid + - const: vfe1_axi + - const: vfe1_src + - const: vfe1 + - const: vfe1_cphy_rx + - const: vfe1_csid_src + - const: vfe1_csid + - const: vfe2_axi + - const: vfe2_src + - const: vfe2 + - const: vfe2_cphy_rx + - const: vfe2_csid_src + - const: vfe2_csid + - const: vfe3_axi + - const: vfe3_src + - const: vfe3 + - const: vfe3_cphy_rx + - const: vfe3_csid_src + - const: vfe3_csid + - const: vfe_lite0_src + - const: vfe_lite0 + - const: vfe_lite0_cphy_rx + - const: vfe_lite0_csid_src + - const: vfe_lite0_csid + - const: vfe_lite1_src + - const: vfe_lite1 + - const: vfe_lite1_cphy_rx + - const: vfe_lite1_csid_src + - const: vfe_lite1_csid + - const: vfe_lite2_src + - const: vfe_lite2 + - const: vfe_lite2_cphy_rx + - const: vfe_lite2_csid_src + - const: vfe_lite2_csid + - const: vfe_lite3_src + - const: vfe_lite3 + - const: vfe_lite3_cphy_rx + - const: vfe_lite3_csid_src + - const: vfe_lite3_csid + - const: gcc_axi_hf + - const: gcc_axi_sf + - const: slow_ahb_src + + interrupts: + maxItems: 20 + + interrupt-names: + items: + - const: csid1_lite + - const: vfe_lite1 + - const: csiphy3 + - const: csid0 + - const: vfe0 + - const: csid1 + - const: vfe1 + - const: csid0_lite + - const: vfe_lite0 + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: csid2 + - const: vfe2 + - const: csid3_lite + - const: csid2_lite + - const: vfe_lite3 + - const: vfe_lite2 + - const: csid3 + - const: vfe3 + + iommus: + maxItems: 16 + + interconnects: + maxItems: 4 + + interconnect-names: + items: + - const: cam_ahb + - const: cam_hf_mnoc + - const: cam_sf_mnoc + - const: cam_sf_icp_mnoc + + power-domains: + items: + - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller. + - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller. + - description: IFE2 GDSC - Image Front End, Global Distributed Switch Controller. + - description: IFE3 GDSC - Image Front End, Global Distributed Switch Controller. + - description: Titan Top GDSC - Titan ISP Block, Global Distributed Switch Controller. + + power-domain-names: + items: + - const: ife0 + - const: ife1 + - const: ife2 + - const: ife3 + - const: top + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + description: + CSI input ports. + + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data from CSIPHY0. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - clock-lanes + - data-lanes + + port@1: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data from CSIPHY1. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - clock-lanes + - data-lanes + + port@2: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data from CSIPHY2. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - clock-lanes + - data-lanes + + port@3: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data from CSIPHY3. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - clock-lanes + - data-lanes + + reg: + maxItems: 20 + + reg-names: + items: + - const: csiphy2 + - const: csiphy3 + - const: csiphy0 + - const: csiphy1 + - const: vfe0 + - const: csid0 + - const: vfe1 + - const: csid1 + - const: vfe2 + - const: csid2 + - const: vfe_lite0 + - const: csid0_lite + - const: vfe_lite1 + - const: csid1_lite + - const: vfe_lite2 + - const: csid2_lite + - const: vfe_lite3 + - const: csid3_lite + - const: vfe3 + - const: csid3 + + vdda-phy-supply: + description: + Phandle to a regulator supply to PHY core block. + + vdda-pll-supply: + description: + Phandle to 1.8V regulator supply to PHY refclk pll block. + +required: + - clock-names + - clocks + - compatible + - interconnects + - interconnect-names + - interrupts + - interrupt-names + - iommus + - power-domains + - power-domain-names + - reg + - reg-names + - vdda-phy-supply + - vdda-pll-supply + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + camss: camss@ac5a000 { + compatible = "qcom,sc8280xp-camss"; + + reg = <0 0x0ac5a000 0 0x2000>, + <0 0x0ac5c000 0 0x2000>, + <0 0x0ac65000 0 0x2000>, + <0 0x0ac67000 0 0x2000>, + <0 0x0acaf000 0 0x4000>, + <0 0x0acb3000 0 0x1000>, + <0 0x0acb6000 0 0x4000>, + <0 0x0acba000 0 0x1000>, + <0 0x0acbd000 0 0x4000>, + <0 0x0acc1000 0 0x1000>, + <0 0x0acc4000 0 0x4000>, + <0 0x0acc8000 0 0x1000>, + <0 0x0accb000 0 0x4000>, + <0 0x0accf000 0 0x1000>, + <0 0x0acd2000 0 0x4000>, + <0 0x0acd6000 0 0x1000>, + <0 0x0acd9000 0 0x4000>, + <0 0x0acdd000 0 0x1000>, + <0 0x0ace0000 0 0x4000>, + <0 0x0ace4000 0 0x1000>; + + reg-names = "csiphy2", + "csiphy3", + "csiphy0", + "csiphy1", + "vfe0", + "csid0", + "vfe1", + "csid1", + "vfe2", + "csid2", + "vfe_lite0", + "csid0_lite", + "vfe_lite1", + "csid1_lite", + "vfe_lite2", + "csid2_lite", + "vfe_lite3", + "csid3_lite", + "vfe3", + "csid3"; + + vdda-phy-supply = <&vreg_l6d>; + vdda-pll-supply = <&vreg_l4d>; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + interrupt-names = "csid1_lite", + "vfe_lite1", + "csiphy3", + "csid0", + "vfe0", + "csid1", + "vfe1", + "csid0_lite", + "vfe_lite0", + "csiphy0", + "csiphy1", + "csiphy2", + "csid2", + "vfe2", + "csid3_lite", + "csid2_lite", + "vfe_lite3", + "vfe_lite2", + "csid3", + "vfe3"; + + power-domains = <&camcc IFE_0_GDSC>, + <&camcc IFE_1_GDSC>, + <&camcc IFE_2_GDSC>, + <&camcc IFE_3_GDSC>, + <&camcc TITAN_TOP_GDSC>; + + power-domain-names = "ife0", + "ife1", + "ife2", + "ife3", + "top"; + + clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, + <&camcc CAMCC_CAMNOC_AXI_CLK_SRC>, + <&camcc CAMCC_CPAS_AHB_CLK>, + <&camcc CAMCC_CPHY_RX_CLK_SRC>, + <&camcc CAMCC_CSIPHY0_CLK>, + <&camcc CAMCC_CSI0PHYTIMER_CLK_SRC>, + <&camcc CAMCC_CSI0PHYTIMER_CLK>, + <&camcc CAMCC_CSIPHY1_CLK>, + <&camcc CAMCC_CSI1PHYTIMER_CLK_SRC>, + <&camcc CAMCC_CSI1PHYTIMER_CLK>, + <&camcc CAMCC_CSIPHY2_CLK>, + <&camcc CAMCC_CSI2PHYTIMER_CLK_SRC>, + <&camcc CAMCC_CSI2PHYTIMER_CLK>, + <&camcc CAMCC_CSIPHY3_CLK>, + <&camcc CAMCC_CSI3PHYTIMER_CLK_SRC>, + <&camcc CAMCC_CSI3PHYTIMER_CLK>, + <&camcc CAMCC_IFE_0_AXI_CLK>, + <&camcc CAMCC_IFE_0_CLK_SRC>, + <&camcc CAMCC_IFE_0_CLK>, + <&camcc CAMCC_IFE_0_CPHY_RX_CLK>, + <&camcc CAMCC_IFE_0_CSID_CLK_SRC>, + <&camcc CAMCC_IFE_0_CSID_CLK>, + <&camcc CAMCC_IFE_1_AXI_CLK>, + <&camcc CAMCC_IFE_1_CLK_SRC>, + <&camcc CAMCC_IFE_1_CLK>, + <&camcc CAMCC_IFE_1_CPHY_RX_CLK>, + <&camcc CAMCC_IFE_1_CSID_CLK_SRC>, + <&camcc CAMCC_IFE_1_CSID_CLK>, + <&camcc CAMCC_IFE_2_AXI_CLK>, + <&camcc CAMCC_IFE_2_CLK_SRC>, + <&camcc CAMCC_IFE_2_CLK>, + <&camcc CAMCC_IFE_2_CPHY_RX_CLK>, + <&camcc CAMCC_IFE_2_CSID_CLK_SRC>, + <&camcc CAMCC_IFE_2_CSID_CLK>, + <&camcc CAMCC_IFE_3_AXI_CLK>, + <&camcc CAMCC_IFE_3_CLK_SRC>, + <&camcc CAMCC_IFE_3_CLK>, + <&camcc CAMCC_IFE_3_CPHY_RX_CLK>, + <&camcc CAMCC_IFE_3_CSID_CLK_SRC>, + <&camcc CAMCC_IFE_3_CSID_CLK>, + <&camcc CAMCC_IFE_LITE_0_CLK_SRC>, + <&camcc CAMCC_IFE_LITE_0_CLK>, + <&camcc CAMCC_IFE_LITE_0_CPHY_RX_CLK>, + <&camcc CAMCC_IFE_LITE_0_CSID_CLK_SRC>, + <&camcc CAMCC_IFE_LITE_0_CSID_CLK>, + <&camcc CAMCC_IFE_LITE_1_CLK_SRC>, + <&camcc CAMCC_IFE_LITE_1_CLK>, + <&camcc CAMCC_IFE_LITE_1_CPHY_RX_CLK>, + <&camcc CAMCC_IFE_LITE_1_CSID_CLK_SRC>, + <&camcc CAMCC_IFE_LITE_1_CSID_CLK>, + <&camcc CAMCC_IFE_LITE_2_CLK_SRC>, + <&camcc CAMCC_IFE_LITE_2_CLK>, + <&camcc CAMCC_IFE_LITE_2_CPHY_RX_CLK>, + <&camcc CAMCC_IFE_LITE_2_CSID_CLK_SRC>, + <&camcc CAMCC_IFE_LITE_2_CSID_CLK>, + <&camcc CAMCC_IFE_LITE_3_CLK_SRC>, + <&camcc CAMCC_IFE_LITE_3_CLK>, + <&camcc CAMCC_IFE_LITE_3_CPHY_RX_CLK>, + <&camcc CAMCC_IFE_LITE_3_CSID_CLK_SRC>, + <&camcc CAMCC_IFE_LITE_3_CSID_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&gcc GCC_CAMERA_SF_AXI_CLK>, + <&camcc CAMCC_SLOW_AHB_CLK_SRC>; + + clock-names = "camnoc_axi", + "camnoc_axi_src", + "cpas_ahb", + "cphy_rx_src", + "csiphy0", + "csiphy0_timer_src", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer_src", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer_src", + "csiphy2_timer", + "csiphy3", + "csiphy3_timer_src", + "csiphy3_timer", + "vfe0_axi", + "vfe0_src", + "vfe0", + "vfe0_cphy_rx", + "vfe0_csid_src", + "vfe0_csid", + "vfe1_axi", + "vfe1_src", + "vfe1", + "vfe1_cphy_rx", + "vfe1_csid_src", + "vfe1_csid", + "vfe2_axi", + "vfe2_src", + "vfe2", + "vfe2_cphy_rx", + "vfe2_csid_src", + "vfe2_csid", + "vfe3_axi", + "vfe3_src", + "vfe3", + "vfe3_cphy_rx", + "vfe3_csid_src", + "vfe3_csid", + "vfe_lite0_src", + "vfe_lite0", + "vfe_lite0_cphy_rx", + "vfe_lite0_csid_src", + "vfe_lite0_csid", + "vfe_lite1_src", + "vfe_lite1", + "vfe_lite1_cphy_rx", + "vfe_lite1_csid_src", + "vfe_lite1_csid", + "vfe_lite2_src", + "vfe_lite2", + "vfe_lite2_cphy_rx", + "vfe_lite2_csid_src", + "vfe_lite2_csid", + "vfe_lite3_src", + "vfe_lite3", + "vfe_lite3_cphy_rx", + "vfe_lite3_csid_src", + "vfe_lite3_csid", + "gcc_axi_hf", + "gcc_axi_sf", + "slow_ahb_src"; + + + iommus = <&apps_smmu 0x2000 0x4e0>, + <&apps_smmu 0x2020 0x4e0>, + <&apps_smmu 0x2040 0x4e0>, + <&apps_smmu 0x2060 0x4e0>, + <&apps_smmu 0x2080 0x4e0>, + <&apps_smmu 0x20e0 0x4e0>, + <&apps_smmu 0x20c0 0x4e0>, + <&apps_smmu 0x20a0 0x4e0>, + <&apps_smmu 0x2400 0x4e0>, + <&apps_smmu 0x2420 0x4e0>, + <&apps_smmu 0x2440 0x4e0>, + <&apps_smmu 0x2460 0x4e0>, + <&apps_smmu 0x2480 0x4e0>, + <&apps_smmu 0x24e0 0x4e0>, + <&apps_smmu 0x24c0 0x4e0>, + <&apps_smmu 0x24a0 0x4e0>; + + interconnects = <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_CAMERA_CFG 0>, + <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI1 0>, + <&mmss_noc MASTER_CAMNOC_SF 0 &mc_virt SLAVE_EBI1 0>, + <&mmss_noc MASTER_CAMNOC_ICP 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "cam_ahb", + "cam_hf_mnoc", + "cam_sf_mnoc", + "cam_sf_icp_mnoc"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + csiphy_ep0: endpoint@0 { + reg = <0>; + clock-lanes = <7>; + data-lanes = <0 1>; + remote-endpoint = <&sensor_ep>; + }; + }; + }; + }; + }; From patchwork Fri Nov 3 16:25:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan O'Donoghue X-Patchwork-Id: 740783 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 417F6C4332F for ; Fri, 3 Nov 2023 16:25:21 +0000 (UTC) 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References: <20231103-b4-camss-sc8280xp-v2-0-b7af4d253a20@linaro.org> In-Reply-To: <20231103-b4-camss-sc8280xp-v2-0-b7af4d253a20@linaro.org> To: hverkuil-cisco@xs4all.nl, laurent.pinchart@ideasonboard.com, Andy Gross , Bjorn Andersson , Konrad Dybcio , Robert Foss , Todor Tomov , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , vincent.knecht@mailoo.org, matti.lehtimaki@gmail.com, quic_grosikop@quicinc.com Cc: linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Bryan O'Donoghue X-Mailer: b4 0.13-dev-26615 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Adds a CAMSS SoC identifier for the SC8280XP. Signed-off-by: Bryan O'Donoghue --- drivers/media/platform/qcom/camss/camss.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/platform/qcom/camss/camss.h index a0c2dcc779f05..ac15fe23a702e 100644 --- a/drivers/media/platform/qcom/camss/camss.h +++ b/drivers/media/platform/qcom/camss/camss.h @@ -77,6 +77,7 @@ enum camss_version { CAMSS_660, CAMSS_845, CAMSS_8250, + CAMSS_8280XP, }; enum icc_count { From patchwork Fri Nov 3 16:25:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan O'Donoghue X-Patchwork-Id: 740782 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DF367C4332F for ; Fri, 3 Nov 2023 16:25:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234377AbjKCQZY (ORCPT ); Fri, 3 Nov 2023 12:25:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37006 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345199AbjKCQZW (ORCPT ); Fri, 3 Nov 2023 12:25:22 -0400 Received: from mail-wr1-x436.google.com (mail-wr1-x436.google.com [IPv6:2a00:1450:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6AB83D57 for ; Fri, 3 Nov 2023 09:25:11 -0700 (PDT) Received: by mail-wr1-x436.google.com with SMTP id ffacd0b85a97d-32faea0fa1fso1140995f8f.1 for ; Fri, 03 Nov 2023 09:25:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699028710; x=1699633510; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=vbWYJQhIsB+Tb1jwxwFcUUflIu3DiRZ3/+WTM6wt7Zk=; b=eTYPT0rVRkdPg5jdUU8WtO+irykmstrT9IJKuMIwwE5ntUli7bk/npvYE2G9U03g8e 0aTJR035Hst4SJZsqq1djnBzCjJBf+8dJgIjoSu1b3cgFT37kOPKeiafiTlNG0dKG2fN GCBox8ls90ZO2jS615bXINKf/njwAAmZG7FxwsxsNl9zU8R5etE85xzwCzu3WmwRoW5r RirtI2qVS7hPLWOfpS2UQQd8fm6OyvYUH7z7NeuASQcJQ5HyStGcYqM16pYiGr2bi5JM 0wGcm98TCAAAC0nlMwqPhpQUe1/+iqkcNMVQQhRTHY1am5zurh9QAfe2vDGVuv9vBGv9 jDLw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699028710; x=1699633510; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vbWYJQhIsB+Tb1jwxwFcUUflIu3DiRZ3/+WTM6wt7Zk=; b=jZVWewdTpDzGbLKzxkvlXT1BEaW+lxyRZTtrKdcFeXAGAuz+Pn+hj1yh3dV8vyjxhv 2kNVPwAmIdYmfvapCpH2s7Q7uJ58wxg1PTFr2AjKvlcGrsWSnqYns4W5eNdX+95W2u2Z 1RwL0fVSD71BbNZuU3HCKW4dpe/TJjiIOzFFuuJK/k51Eerth6OQrP5AS1su9LLZ4OB0 Z4FEHlEWz9lHve+b6Rc+YQtWltuM+EflOq8SwiimT4VHjgztaODapcvkwTIZ9H1V0/zi JTVYQcUYiTkS8dAWsyrCY5kwQoNi0t1toQkv4Pg5JO1dmwRzDOEUAbGB7P1VpTdvIMtH tg1g== X-Gm-Message-State: AOJu0YyVrV3lSsSbAUpEirBnwhGZvQxDnAvcJgICrpPOIymwP22HxLql rwByXT2NN8F4KEEqTBLfFO+/Zw== X-Google-Smtp-Source: AGHT+IF+CW/nMUNPdHn4nVYyH4zTlYe6CmQodryEHsXQLgJ3RMqO7l+zdqDk4D22Q/+Q+0SV4RGG6Q== X-Received: by 2002:a5d:6da7:0:b0:32f:952f:c51c with SMTP id u7-20020a5d6da7000000b0032f952fc51cmr3690212wrs.18.1699028709763; Fri, 03 Nov 2023 09:25:09 -0700 (PDT) Received: from [127.0.0.1] ([37.228.218.3]) by smtp.gmail.com with ESMTPSA id x13-20020a5d650d000000b003142e438e8csm2219972wru.26.2023.11.03.09.25.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Nov 2023 09:25:09 -0700 (PDT) From: Bryan O'Donoghue Date: Fri, 03 Nov 2023 16:25:06 +0000 Subject: [PATCH v2 3/6] media: qcom: camss: csiphy-3ph: Add Gen2 v1.1 two-phase MIPI CSI-2 DPHY init MIME-Version: 1.0 Message-Id: <20231103-b4-camss-sc8280xp-v2-3-b7af4d253a20@linaro.org> References: <20231103-b4-camss-sc8280xp-v2-0-b7af4d253a20@linaro.org> In-Reply-To: <20231103-b4-camss-sc8280xp-v2-0-b7af4d253a20@linaro.org> To: hverkuil-cisco@xs4all.nl, laurent.pinchart@ideasonboard.com, Andy Gross , Bjorn Andersson , Konrad Dybcio , Robert Foss , Todor Tomov , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , vincent.knecht@mailoo.org, matti.lehtimaki@gmail.com, quic_grosikop@quicinc.com Cc: linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Bryan O'Donoghue X-Mailer: b4 0.13-dev-26615 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add a PHY configuration sequence for the sc8280xp which uses a Qualcomm Gen 2 version 1.1 CSI-2 PHY. The PHY can be configured as two phase or three phase in C-PHY or D-PHY mode. This configuration supports two-phase D-PHY mode. Signed-off-by: Bryan O'Donoghue --- .../platform/qcom/camss/camss-csiphy-3ph-1-0.c | 85 ++++++++++++++++++++++ 1 file changed, 85 insertions(+) diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c index f50e2235c37fc..2eb3531ffd00b 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c @@ -148,6 +148,91 @@ csiphy_reg_t lane_regs_sdm845[5][14] = { }, }; +/* GEN2 1.1 2PH */ +static const struct +csiphy_reg_t lane_regs_sc8280xp[5][14] = { + { + {0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0034, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x001C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0028, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0000, 0x90, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0008, 0x0E, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x000c, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0010, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0060, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0064, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x0704, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x072C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0734, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x071C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0714, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0728, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x073C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0700, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0708, 0x0E, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x070C, 0xA5, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0710, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0738, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0760, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0764, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x0204, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x022C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0234, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x021C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0214, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0228, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x023C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0200, 0x90, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0208, 0x0E, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x020C, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0210, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0238, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0260, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0264, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0434, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x041C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0428, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0400, 0x90, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0408, 0x0E, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x040C, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0410, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0460, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0464, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x0604, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x062C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0634, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x061C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0614, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0628, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x063C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0600, 0x90, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0608, 0x0E, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x060C, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0610, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0638, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0660, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0664, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, +}; + /* GEN2 1.2.1 2PH */ static const struct csiphy_reg_t lane_regs_sm8250[5][20] = { From patchwork Fri Nov 3 16:25:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan O'Donoghue X-Patchwork-Id: 742348 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E1F5CC001B2 for ; Fri, 3 Nov 2023 16:25:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345370AbjKCQZZ (ORCPT ); Fri, 3 Nov 2023 12:25:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36974 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345311AbjKCQZW (ORCPT ); Fri, 3 Nov 2023 12:25:22 -0400 Received: from mail-wr1-x436.google.com (mail-wr1-x436.google.com [IPv6:2a00:1450:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C482F194 for ; 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+static const struct camss_subdev_resources csiphy_res_sc8280xp[] = { + /* CSIPHY0 */ + { + .regulators = {}, + .clock = { "csiphy0", "csiphy0_timer" }, + .clock_rate = { { 400000000 }, + { 300000000 } }, + .reg = { "csiphy0" }, + .interrupt = { "csiphy0" }, + .ops = &csiphy_ops_3ph_1_0 + }, + /* CSIPHY1 */ + { + .regulators = {}, + .clock = { "csiphy1", "csiphy1_timer" }, + .clock_rate = { { 400000000 }, + { 300000000 } }, + .reg = { "csiphy1" }, + .interrupt = { "csiphy1" }, + .ops = &csiphy_ops_3ph_1_0 + }, + /* CSIPHY2 */ + { + .regulators = {}, + .clock = { "csiphy2", "csiphy2_timer" }, + .clock_rate = { { 400000000 }, + { 300000000 } }, + .reg = { "csiphy2" }, + .interrupt = { "csiphy2" }, + .ops = &csiphy_ops_3ph_1_0 + }, + /* CSIPHY3 */ + { + .regulators = {}, + .clock = { "csiphy3", "csiphy3_timer" }, + .clock_rate = { { 400000000 }, + { 300000000 } }, + .reg = { "csiphy3" }, + .interrupt = { "csiphy3" }, + .ops = &csiphy_ops_3ph_1_0 + }, +}; + +static const struct camss_subdev_resources csid_res_sc8280xp[] = { + /* CSID0 */ + { + .regulators = { "vdda-phy", "vdda-pll" }, + .clock = { "vfe0_csid_src", "vfe0_csid", "cphy_rx_src", + "vfe0_cphy_rx", "vfe0_src", "vfe0", "vfe0_axi" }, + .clock_rate = { { 400000000, 400000000, 480000000, 600000000, 600000000, 600000000 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 } }, + .reg = { "csid0" }, + .interrupt = { "csid0" }, + .ops = &csid_ops_gen2 + }, + /* CSID1 */ + { + .regulators = { "vdda-phy", "vdda-pll" }, + .clock = { "vfe1_csid_src", "vfe1_csid", "cphy_rx_src", + "vfe1_cphy_rx", "vfe1_src", "vfe1", "vfe1_axi" }, + .clock_rate = { { 400000000, 400000000, 480000000, 600000000, 600000000, 600000000 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 } }, + .reg = { "csid1" }, + .interrupt = { "csid1" }, + .ops = &csid_ops_gen2 + }, + /* CSID2 */ + { + .regulators = { "vdda-phy", "vdda-pll" }, + .clock = { "vfe2_csid_src", "vfe2_csid", "cphy_rx_src", + "vfe2_cphy_rx", "vfe2_src", "vfe2", "vfe2_axi" }, + .clock_rate = { { 400000000, 400000000, 480000000, 600000000, 600000000, 600000000 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 } }, + .reg = { "csid2" }, + .interrupt = { "csid2" }, + .ops = &csid_ops_gen2 + }, + /* CSID3 */ + { + .regulators = { "vdda-phy", "vdda-pll" }, + .clock = { "vfe3_csid_src", "vfe3_csid", "cphy_rx_src", + "vfe3_cphy_rx", "vfe3_src", "vfe3", "vfe3_axi" }, + .clock_rate = { { 400000000, 400000000, 480000000, 600000000, 600000000, 600000000 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 } }, + .reg = { "csid3" }, + .interrupt = { "csid3" }, + .ops = &csid_ops_gen2 + }, + /* CSID_LITE0 */ + { + .regulators = { "vdda-phy", "vdda-pll" }, + .clock = { "vfe_lite0_csid_src", "vfe_lite0_csid", + "cphy_rx_src", "vfe_lite0_cphy_rx", "vfe_lite0_src", + "vfe_lite0" }, + .clock_rate = { { 400000000, 400000000, 480000000, 600000000, 600000000, 600000000 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, }, + .reg = { "csid0_lite" }, + .interrupt = { "csid0_lite" }, + .is_lite = true, + .ops = &csid_ops_gen2 + }, + /* CSID_LITE1 */ + { + .regulators = { "vdda-phy", "vdda-pll" }, + .clock = { "vfe_lite1_csid_src", "vfe_lite1_csid", + "cphy_rx_src", "vfe_lite1_cphy_rx", "vfe_lite1_src", + "vfe_lite1" }, + .clock_rate = { { 400000000, 400000000, 480000000, 600000000, 600000000, 600000000 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, }, + .reg = { "csid1_lite" }, + .interrupt = { "csid1_lite" }, + .is_lite = true, + .ops = &csid_ops_gen2 + }, + /* CSID_LITE2 */ + { + .regulators = { "vdda-phy", "vdda-pll" }, + .clock = { "vfe_lite2_csid_src", "vfe_lite2_csid", + "cphy_rx_src", "vfe_lite2_cphy_rx", "vfe_lite2_src", + "vfe_lite2" }, + .clock_rate = { { 400000000, 400000000, 480000000, 600000000, 600000000, 600000000 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, }, + .reg = { "csid2_lite" }, + .interrupt = { "csid2_lite" }, + .is_lite = true, + .ops = &csid_ops_gen2 + }, + /* CSID_LITE3 */ + { + .regulators = { "vdda-phy", "vdda-pll" }, + .clock = { "vfe_lite3_csid_src", "vfe_lite3_csid", + "cphy_rx_src", "vfe_lite3_cphy_rx", "vfe_lite3_src", + "vfe_lite3" }, + .clock_rate = { { 400000000, 400000000, 480000000, 600000000, 600000000, 600000000 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, }, + .reg = { "csid3_lite" }, + .interrupt = { "csid3_lite" }, + .is_lite = true, + .ops = &csid_ops_gen2 + } +}; + +static const struct camss_subdev_resources vfe_res_sc8280xp[] = { + /* IFE0 */ + { + .regulators = {}, + .clock = { "gcc_axi_hf", "gcc_axi_sf", "slow_ahb_src", + "cpas_ahb", "camnoc_axi", "camnoc_axi_src", + "vfe0_src", "vfe0", "vfe0_axi" }, + .clock_rate = { { 0 }, + { 0 }, + { 19200000, 80000000, 80000000, 80000000, 80000000}, + { 80000000 }, + { 0 }, + { 19200000, 150000000, 266666667, 320000000, 400000000, 480000000 }, + { 0 }, + { 400000000, 558000000, 637000000, 760000000 }, + { 0 }, }, + .reg = { "vfe0" }, + .interrupt = { "vfe0" }, + .pd_name = "ife0", + .line_num = 4, + .ops = &vfe_ops_170 + }, + /* IFE1 */ + { + .regulators = {}, + .clock = { "gcc_axi_hf", "gcc_axi_sf", "slow_ahb_src", + "cpas_ahb", "camnoc_axi", "camnoc_axi_src", + "vfe1_src", "vfe1", "vfe1_axi" }, + .clock_rate = { { 0 }, + { 0 }, + { 19200000, 80000000, 80000000, 80000000, 80000000}, + { 80000000 }, + { 0 }, + { 19200000, 150000000, 266666667, 320000000, 400000000, 480000000 }, + { 0 }, + { 400000000, 558000000, 637000000, 760000000 }, + { 0 }, }, + .reg = { "vfe1" }, + .interrupt = { "vfe1" }, + .pd_name = "ife1", + .line_num = 4, + .ops = &vfe_ops_170 + }, + /* IFE2 */ + { + .regulators = {}, + .clock = { "gcc_axi_hf", "gcc_axi_sf", "slow_ahb_src", + "cpas_ahb", "camnoc_axi", "camnoc_axi_src", + "vfe2_src", "vfe2", "vfe2_axi" }, + .clock_rate = { { 0 }, + { 0 }, + { 19200000, 80000000, 80000000, 80000000, 80000000}, + { 80000000 }, + { 0 }, + { 19200000, 150000000, 266666667, 320000000, 400000000, 480000000 }, + { 0 }, + { 400000000, 558000000, 637000000, 760000000 }, + { 0 }, }, + .reg = { "vfe2" }, + .interrupt = { "vfe2" }, + .pd_name = "ife2", + .line_num = 4, + .ops = &vfe_ops_170 + }, + /* VFE3 */ + { + .regulators = {}, + .clock = { "gcc_axi_hf", "gcc_axi_sf", "slow_ahb_src", + "cpas_ahb", "camnoc_axi", "camnoc_axi_src", + "vfe3_src", "vfe3", "vfe3_axi" }, + .clock_rate = { { 0 }, + { 0 }, + { 19200000, 80000000, 80000000, 80000000, 80000000}, + { 80000000 }, + { 0 }, + { 19200000, 150000000, 266666667, 320000000, 400000000, 480000000 }, + { 0 }, + { 400000000, 558000000, 637000000, 760000000 }, + { 0 }, }, + .reg = { "vfe3" }, + .interrupt = { "vfe3" }, + .pd_name = "ife3", + .line_num = 4, + .ops = &vfe_ops_170 + }, + /* IFE_LITE_0 */ + { + .regulators = {}, + .clock = { "gcc_axi_hf", "gcc_axi_sf", "slow_ahb_src", + "cpas_ahb", "camnoc_axi", "camnoc_axi_src", + "vfe_lite0_src", "vfe_lite0" }, + .clock_rate = { { 0 }, + { 0 }, + { 19200000, 80000000, 80000000, 80000000, 80000000}, + { 80000000 }, + { 0 }, + { 19200000, 150000000, 266666667, 320000000, 400000000, 480000000 }, + { 0 }, + { 320000000, 400000000, 480000000, 600000000 }, }, + .reg = { "vfe_lite0" }, + .interrupt = { "vfe_lite0" }, + .is_lite = true, + .line_num = 4, + .ops = &vfe_ops_170 + }, + /* IFE_LITE_1 */ + { + .regulators = {}, + .clock = { "gcc_axi_hf", "gcc_axi_sf", "slow_ahb_src", + "cpas_ahb", "camnoc_axi", "camnoc_axi_src", + "vfe_lite1_src", "vfe_lite1" }, + .clock_rate = { { 0 }, + { 0 }, + { 19200000, 80000000, 80000000, 80000000, 80000000}, + { 80000000 }, + { 0 }, + { 19200000, 150000000, 266666667, 320000000, 400000000, 480000000 }, + { 0 }, + { 320000000, 400000000, 480000000, 600000000 }, }, + .reg = { "vfe_lite1" }, + .interrupt = { "vfe_lite1" }, + .is_lite = true, + .line_num = 4, + .ops = &vfe_ops_170 + }, + /* IFE_LITE_2 */ + { + .regulators = {}, + .clock = { "gcc_axi_hf", "gcc_axi_sf", "slow_ahb_src", + "cpas_ahb", "camnoc_axi", "camnoc_axi_src", + "vfe_lite2_src", "vfe_lite2" }, + .clock_rate = { { 0 }, + { 0 }, + { 19200000, 80000000, 80000000, 80000000, 80000000}, + { 80000000 }, + { 0 }, + { 19200000, 150000000, 266666667, 320000000, 400000000, 480000000 }, + { 0 }, + { 320000000, 400000000, 480000000, 600000000, }, }, + .reg = { "vfe_lite2" }, + .interrupt = { "vfe_lite2" }, + .is_lite = true, + .line_num = 4, + .ops = &vfe_ops_170 + }, + /* VFE_LITE_3 */ + { + .regulators = {}, + .clock = { "gcc_axi_hf", "gcc_axi_sf", "slow_ahb_src", + "cpas_ahb", "camnoc_axi", "camnoc_axi_src", + "vfe_lite3_src", "vfe_lite3" }, + .clock_rate = { { 0 }, + { 0 }, + { 19200000, 80000000, 80000000, 80000000, 80000000}, + { 80000000 }, + { 0 }, + { 19200000, 150000000, 266666667, 320000000, 400000000, 480000000 }, + { 0 }, + { 320000000, 400000000, 480000000, 600000000 }, }, + .reg = { "vfe_lite3" }, + .interrupt = { "vfe_lite3" }, + .is_lite = true, + .line_num = 4, + .ops = &vfe_ops_170 + }, +}; + +static const struct resources_icc icc_res_sc8280xp[] = { + { + .name = "cam_ahb", + .icc_bw_tbl.avg = 150000, + .icc_bw_tbl.peak = 300000, + }, + { + .name = "cam_hf_mnoc", + .icc_bw_tbl.avg = 2097152, + .icc_bw_tbl.peak = 2097152, + }, + { + .name = "cam_sf_mnoc", + .icc_bw_tbl.avg = 2097152, + .icc_bw_tbl.peak = 2097152, + }, + { + .name = "cam_sf_icp_mnoc", + .icc_bw_tbl.avg = 2097152, + .icc_bw_tbl.peak = 2097152, + }, +}; + /* * camss_add_clock_margin - Add margin to clock frequency rate * @rate: Clock frequency rate @@ -1824,12 +2192,27 @@ static const struct camss_resources sm8250_resources = { .vfe_num = ARRAY_SIZE(vfe_res_8250), }; +static const struct camss_resources sc8280xp_resources = { + .version = CAMSS_8280XP, + .pd_name = "top", + .csiphy_res = csiphy_res_sc8280xp, + .csid_res = csid_res_sc8280xp, + .ispif_res = NULL, + .vfe_res = vfe_res_sc8280xp, + .icc_res = icc_res_sc8280xp, + .icc_path_num = ARRAY_SIZE(icc_res_sc8280xp), + .csiphy_num = ARRAY_SIZE(csiphy_res_sc8280xp), + .csid_num = ARRAY_SIZE(csid_res_sc8280xp), + .vfe_num = ARRAY_SIZE(vfe_res_sc8280xp), +}; + static const struct of_device_id camss_dt_match[] = { { .compatible = "qcom,msm8916-camss", .data = &msm8916_resources }, { .compatible = "qcom,msm8996-camss", .data = &msm8996_resources }, { .compatible = "qcom,sdm660-camss", .data = &sdm660_resources }, { .compatible = "qcom,sdm845-camss", .data = &sdm845_resources }, { .compatible = "qcom,sm8250-camss", .data = &sm8250_resources }, + { .compatible = "qcom,sc8280xp-camss", .data = &sc8280xp_resources }, { } }; From patchwork Fri Nov 3 16:25:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan O'Donoghue X-Patchwork-Id: 742349 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2114BC4167B for ; Fri, 3 Nov 2023 16:25:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345349AbjKCQZX (ORCPT ); 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Fri, 03 Nov 2023 09:25:11 -0700 (PDT) From: Bryan O'Donoghue Date: Fri, 03 Nov 2023 16:25:08 +0000 Subject: [PATCH v2 5/6] media: qcom: camss: Add sc8280xp support MIME-Version: 1.0 Message-Id: <20231103-b4-camss-sc8280xp-v2-5-b7af4d253a20@linaro.org> References: <20231103-b4-camss-sc8280xp-v2-0-b7af4d253a20@linaro.org> In-Reply-To: <20231103-b4-camss-sc8280xp-v2-0-b7af4d253a20@linaro.org> To: hverkuil-cisco@xs4all.nl, laurent.pinchart@ideasonboard.com, Andy Gross , Bjorn Andersson , Konrad Dybcio , Robert Foss , Todor Tomov , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , vincent.knecht@mailoo.org, matti.lehtimaki@gmail.com, quic_grosikop@quicinc.com Cc: linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Bryan O'Donoghue X-Mailer: b4 0.13-dev-26615 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add in functional logic throughout the code to support the sc8280xp. Signed-off-by: Bryan O'Donoghue --- .../platform/qcom/camss/camss-csiphy-3ph-1-0.c | 23 +++++++++++++++++--- drivers/media/platform/qcom/camss/camss-csiphy.c | 1 + drivers/media/platform/qcom/camss/camss-vfe.c | 25 +++++++++++++++++----- drivers/media/platform/qcom/camss/camss-video.c | 1 + 4 files changed, 42 insertions(+), 8 deletions(-) diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c index 2eb3531ffd00b..2810d0fa06c13 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c @@ -513,6 +513,10 @@ static void csiphy_gen2_config_lanes(struct csiphy_device *csiphy, r = &lane_regs_sm8250[0][0]; array_size = ARRAY_SIZE(lane_regs_sm8250[0]); break; + case CAMSS_8280XP: + r = &lane_regs_sc8280xp[0][0]; + array_size = ARRAY_SIZE(lane_regs_sc8280xp[0]); + break; default: WARN(1, "unknown cspi version\n"); return; @@ -548,13 +552,26 @@ static u8 csiphy_get_lane_mask(struct csiphy_lanes_cfg *lane_cfg) return lane_mask; } +static bool csiphy_is_gen2(u32 version) +{ + bool ret = false; + + switch (version) { + case CAMSS_845: + case CAMSS_8250: + case CAMSS_8280XP: + ret = true; + break; + } + + return ret; +} + static void csiphy_lanes_enable(struct csiphy_device *csiphy, struct csiphy_config *cfg, s64 link_freq, u8 lane_mask) { struct csiphy_lanes_cfg *c = &cfg->csi2->lane_cfg; - bool is_gen2 = (csiphy->camss->res->version == CAMSS_845 || - csiphy->camss->res->version == CAMSS_8250); u8 settle_cnt; u8 val; int i; @@ -576,7 +593,7 @@ static void csiphy_lanes_enable(struct csiphy_device *csiphy, val = 0x00; writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(0)); - if (is_gen2) + if (csiphy_is_gen2(csiphy->camss->res->version)) csiphy_gen2_config_lanes(csiphy, settle_cnt); else csiphy_gen1_config_lanes(csiphy, cfg, settle_cnt); diff --git a/drivers/media/platform/qcom/camss/camss-csiphy.c b/drivers/media/platform/qcom/camss/camss-csiphy.c index edd573606a6ae..8241acf789865 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy.c @@ -579,6 +579,7 @@ int msm_csiphy_subdev_init(struct camss *camss, break; case CAMSS_845: case CAMSS_8250: + case CAMSS_8280XP: csiphy->formats = csiphy_formats_sdm845; csiphy->nformats = ARRAY_SIZE(csiphy_formats_sdm845); break; diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/platform/qcom/camss/camss-vfe.c index 50929c3cbb831..28cf63af1ec08 100644 --- a/drivers/media/platform/qcom/camss/camss-vfe.c +++ b/drivers/media/platform/qcom/camss/camss-vfe.c @@ -225,6 +225,7 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 sink_code, case CAMSS_660: case CAMSS_845: case CAMSS_8250: + case CAMSS_8280XP: switch (sink_code) { case MEDIA_BUS_FMT_YUYV8_1X16: { @@ -1522,6 +1523,7 @@ int msm_vfe_subdev_init(struct camss *camss, struct vfe_device *vfe, break; case CAMSS_845: case CAMSS_8250: + case CAMSS_8280XP: l->formats = formats_rdi_845; l->nformats = ARRAY_SIZE(formats_rdi_845); break; @@ -1600,6 +1602,23 @@ static const struct media_entity_operations vfe_media_ops = { .link_validate = v4l2_subdev_link_validate, }; +static int vfe_bpl_align(struct vfe_device *vfe) +{ + int ret = 8; + + switch (vfe->camss->res->version) { + case CAMSS_845: + case CAMSS_8250: + case CAMSS_8280XP: + ret = 16; + break; + default: + break; + } + + return ret; +} + /* * msm_vfe_register_entities - Register subdev node for VFE module * @vfe: VFE device @@ -1666,11 +1685,7 @@ int msm_vfe_register_entities(struct vfe_device *vfe, } video_out->ops = &vfe->video_ops; - if (vfe->camss->res->version == CAMSS_845 || - vfe->camss->res->version == CAMSS_8250) - video_out->bpl_alignment = 16; - else - video_out->bpl_alignment = 8; + video_out->bpl_alignment = vfe_bpl_align(vfe); video_out->line_based = 0; if (i == VFE_LINE_PIX) { video_out->bpl_alignment = 16; diff --git a/drivers/media/platform/qcom/camss/camss-video.c b/drivers/media/platform/qcom/camss/camss-video.c index a89da5ef47109..54cd82f741154 100644 --- a/drivers/media/platform/qcom/camss/camss-video.c +++ b/drivers/media/platform/qcom/camss/camss-video.c @@ -1028,6 +1028,7 @@ int msm_video_register(struct camss_video *video, struct v4l2_device *v4l2_dev, break; case CAMSS_845: case CAMSS_8250: + case CAMSS_8280XP: video->formats = formats_rdi_845; video->nformats = ARRAY_SIZE(formats_rdi_845); break; From patchwork Fri Nov 3 16:25:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan O'Donoghue X-Patchwork-Id: 740781 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 349D0C4167B for ; Fri, 3 Nov 2023 16:25:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345190AbjKCQZ3 (ORCPT ); Fri, 3 Nov 2023 12:25:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37086 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345411AbjKCQZ0 (ORCPT ); Fri, 3 Nov 2023 12:25:26 -0400 Received: from mail-wr1-x42c.google.com (mail-wr1-x42c.google.com [IPv6:2a00:1450:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7C583D64 for ; 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Lets rename the file to capture its wider scope than vfe-170 only. Signed-off-by: Bryan O'Donoghue --- drivers/media/platform/qcom/camss/Makefile | 2 +- drivers/media/platform/qcom/camss/{camss-vfe-170.c => camss-vfe-17x.c} | 0 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/platform/qcom/camss/Makefile b/drivers/media/platform/qcom/camss/Makefile index 4e22223589739..0d4389ab312d1 100644 --- a/drivers/media/platform/qcom/camss/Makefile +++ b/drivers/media/platform/qcom/camss/Makefile @@ -14,7 +14,7 @@ qcom-camss-objs += \ camss-vfe-4-1.o \ camss-vfe-4-7.o \ camss-vfe-4-8.o \ - camss-vfe-170.o \ + camss-vfe-17x.o \ camss-vfe-480.o \ camss-vfe-gen1.o \ camss-vfe.o \ diff --git a/drivers/media/platform/qcom/camss/camss-vfe-170.c b/drivers/media/platform/qcom/camss/camss-vfe-17x.c similarity index 100% rename from drivers/media/platform/qcom/camss/camss-vfe-170.c rename to drivers/media/platform/qcom/camss/camss-vfe-17x.c