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([2804:1b3:a7c0:a715:c1a0:7281:6384:2ee9]) by smtp.gmail.com with ESMTPSA id k3-20020a05620a142300b0076f12fcb0easm3272722qkj.2.2023.11.06.05.27.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Nov 2023 05:27:18 -0800 (PST) From: Adhemerval Zanella To: libc-alpha@sourceware.org, Bruno Haible Subject: [PATCH v2 1/7] powerpc: Do not raise exception traps for fesetexcept/fesetexceptflag (BZ 30988) Date: Mon, 6 Nov 2023 10:27:07 -0300 Message-Id: <20231106132713.953501-2-adhemerval.zanella@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231106132713.953501-1-adhemerval.zanella@linaro.org> References: <20231106132713.953501-1-adhemerval.zanella@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: libc-alpha-bounces+patch=linaro.org@sourceware.org According to ISO C23 (7.6.4.4), fesetexcept is supposed to set floating-point exception flags without raising a trap (unlike feraiseexcept, which is supposed to raise a trap if feenableexcept was called with the appropriate argument). This is a side-effect of how we implement the GNU extension feenableexcept, where feenableexcept/fesetenv/fesetmode/feupdateenv might issue prctl (PR_SET_FPEXC, PR_FP_EXC_PRECISE) depending of the argument. And on PR_FP_EXC_PRECISE, setting a floating-point exception flag triggers a trap. To make the both functions follow the C23, fesetexcept and fesetexceptflag now fail if the argument may trigger a trap. The math tests now check for an value different than 0, instead of bail out as unsupported for EXCEPTION_SET_FORCES_TRAP. Checked on powerpc64le-linux-gnu. Reviewed-by: Carlos O'Donell --- math/test-fesetexcept-traps.c | 11 ++++------- math/test-fexcept-traps.c | 11 ++++------- sysdeps/powerpc/fpu/fesetexcept.c | 5 +++++ sysdeps/powerpc/fpu/fsetexcptflg.c | 9 ++++++++- 4 files changed, 21 insertions(+), 15 deletions(-) diff --git a/math/test-fesetexcept-traps.c b/math/test-fesetexcept-traps.c index 71b6e45b33..96f6c4752f 100644 --- a/math/test-fesetexcept-traps.c +++ b/math/test-fesetexcept-traps.c @@ -39,16 +39,13 @@ do_test (void) return result; } - if (EXCEPTION_SET_FORCES_TRAP) - { - puts ("setting exceptions traps, cannot test on this architecture"); - return 77; - } - /* Verify fesetexcept does not cause exception traps. */ + /* Verify fesetexcept does not cause exception traps. For architectures + where setting the exception might result in traps the function should + return a nonzero value. */ ret = fesetexcept (FE_ALL_EXCEPT); if (ret == 0) puts ("fesetexcept (FE_ALL_EXCEPT) succeeded"); - else + else if (!EXCEPTION_SET_FORCES_TRAP) { puts ("fesetexcept (FE_ALL_EXCEPT) failed"); if (EXCEPTION_TESTS (float)) diff --git a/math/test-fexcept-traps.c b/math/test-fexcept-traps.c index 9701c3c320..9b8f583ae6 100644 --- a/math/test-fexcept-traps.c +++ b/math/test-fexcept-traps.c @@ -63,14 +63,11 @@ do_test (void) result = 1; } - if (EXCEPTION_SET_FORCES_TRAP) - { - puts ("setting exceptions traps, cannot test on this architecture"); - return 77; - } - /* The test is that this does not cause exception traps. */ + /* The test is that this does not cause exception traps. For architectures + where setting the exception might result in traps the function should + return a nonzero value. */ ret = fesetexceptflag (&saved, FE_ALL_EXCEPT); - if (ret != 0) + if (ret != 0 && !EXCEPTION_SET_FORCES_TRAP) { puts ("fesetexceptflag failed"); result = 1; diff --git a/sysdeps/powerpc/fpu/fesetexcept.c b/sysdeps/powerpc/fpu/fesetexcept.c index 609a148a95..2850156d3a 100644 --- a/sysdeps/powerpc/fpu/fesetexcept.c +++ b/sysdeps/powerpc/fpu/fesetexcept.c @@ -31,6 +31,11 @@ fesetexcept (int excepts) & FE_INVALID_SOFTWARE)); if (n.l != u.l) { + if (n.l & fenv_exceptions_to_reg (excepts)) + /* Setting the exception flags may trigger a trap. ISO C 23 § 7.6.4.4 + does not allow it. */ + return -1; + fesetenv_register (n.fenv); /* Deal with FE_INVALID_SOFTWARE not being implemented on some chips. */ diff --git a/sysdeps/powerpc/fpu/fsetexcptflg.c b/sysdeps/powerpc/fpu/fsetexcptflg.c index 2b22f913c0..6517e8ea03 100644 --- a/sysdeps/powerpc/fpu/fsetexcptflg.c +++ b/sysdeps/powerpc/fpu/fsetexcptflg.c @@ -44,7 +44,14 @@ __fesetexceptflag (const fexcept_t *flagp, int excepts) This may cause floating-point exceptions if the restored state requests it. */ if (n.l != u.l) - fesetenv_register (n.fenv); + { + if (n.l & fenv_exceptions_to_reg (excepts)) + /* Setting the exception flags may trigger a trap. ISO C 23 § 7.6.4.4 + does not allow it. */ + return -1; + + fesetenv_register (n.fenv); + } /* Deal with FE_INVALID_SOFTWARE not being implemented on some chips. */ if (flag & FE_INVALID) From patchwork Mon Nov 6 13:27:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adhemerval Zanella Netto X-Patchwork-Id: 741392 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1083602wrr; Mon, 6 Nov 2023 05:27:30 -0800 (PST) X-Google-Smtp-Source: AGHT+IEY8HZcNdEpF/mujO6sazTjP3pEvAIGBSAgzdvFIKos/NzKcO//D3DA9skO+gy9UlE4ULwi X-Received: by 2002:a05:6214:c4b:b0:66d:9f6e:ab4d with SMTP id r11-20020a0562140c4b00b0066d9f6eab4dmr30818462qvj.14.1699277249932; Mon, 06 Nov 2023 05:27:29 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1699277249; cv=pass; d=google.com; s=arc-20160816; b=X2cme09hlHOpzDPLmuCMSeJNy7sgD1uPBbD0flNwUNHlpOj+8tCmRYx+3fH/DM9Fcr CkbIM6RxLtvAB+JNEQYiQFTYzhCFktO8URMqnytKZ+Mok6QcfUvMcSKCnPcEPm84eUkR +PhhAW7xx++tYqr9oKvBb52KNZ9CBBNCIZ1t0c+iPUZmasdpSZaCsaT/v/Q4Vib0+vhp XDypy5H9SxrG95vZXGnryJNvKoJ4Qy3fXHKp3Bzzr5PDblIQ9+fplYHQ0w275SxK/6TP 5t16X+FMLEFOfFl04PmN9csFTRpk85WdHbXswnqYW7+nh2q6pq4GeU/tAVXzgubq6Gns jmjQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature:arc-filter:dmarc-filter:delivered-to; bh=DU7GVADg99Hwk54vw+9Jf7Krbt2jfsYfpsChaj/RuNI=; fh=01HD8dtuIqmy9rV/eMJuvD8dAGq4TXBqBjIxWaMzNQI=; b=fog7M2v71ctB4LHRZcJP24C7w7/EoinmyLTHaQUZmblrgDAmaNGRl9UGysQKdTfAcU lnIwPbqgnoNV9r7kGTPGVQGy469S/R2pa28l1PEALJNYJKPnODhqVPfeBg+sJWJorbaM DQMrJgHL9aNh7NlpxcnPote5vZwXc7U/ySGgKHeztf9ZX81scQzWzGTQBYiBTVNBbpjF bAzh6O9rOojp1zC7x4niDWlVDg6TrkqzRvi5GW4NLGhyGKVOsoEz/21/2HMHvgizTP8D F/j37p/B6An7Kr3OSnbbr+DWpKI2wptyuPzJEK2DDMAbh3nFvCa24AgVh9yi9V+iE2ta JbNg== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TZ3WPlrx; arc=pass (i=1); spf=pass (google.com: domain of libc-alpha-bounces+patch=linaro.org@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="libc-alpha-bounces+patch=linaro.org@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from server2.sourceware.org (server2.sourceware.org. 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([2804:1b3:a7c0:a715:c1a0:7281:6384:2ee9]) by smtp.gmail.com with ESMTPSA id k3-20020a05620a142300b0076f12fcb0easm3272722qkj.2.2023.11.06.05.27.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Nov 2023 05:27:19 -0800 (PST) From: Adhemerval Zanella To: libc-alpha@sourceware.org, Bruno Haible Subject: [PATCH v2 2/7] i686: Do not raise exception traps on fesetexcept (BZ 30989) Date: Mon, 6 Nov 2023 10:27:08 -0300 Message-Id: <20231106132713.953501-3-adhemerval.zanella@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231106132713.953501-1-adhemerval.zanella@linaro.org> References: <20231106132713.953501-1-adhemerval.zanella@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-12.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: libc-alpha-bounces+patch=linaro.org@sourceware.org According to ISO C23 (7.6.4.4), fesetexcept is supposed to set floating-point exception flags without raising a trap (unlike feraiseexcept, which is supposed to raise a trap if feenableexcept was called with the appropriate argument). The flags can be set in the 387 unit or in the SSE unit. To set a flag, it is sufficient to do it in the SSE unit, because that is guaranteed to not trap. However, on i386 CPUs that have only a 387 unit, set the flags in the 387, as long as this cannot trap. Checked on i686-linux-gnu. Reviewed-by: Carlos O'Donell --- math/test-fesetexcept-traps.c | 28 ++++++++++++--- sysdeps/i386/fpu/fesetexcept.c | 46 +++++++++++++++++++++--- sysdeps/i386/fpu/math-tests-trap-force.h | 29 +++++++++++++++ sysdeps/x86/fpu/test-fenv-sse-2.c | 23 +++--------- 4 files changed, 100 insertions(+), 26 deletions(-) create mode 100644 sysdeps/i386/fpu/math-tests-trap-force.h diff --git a/math/test-fesetexcept-traps.c b/math/test-fesetexcept-traps.c index 96f6c4752f..8a5c0bca80 100644 --- a/math/test-fesetexcept-traps.c +++ b/math/test-fesetexcept-traps.c @@ -19,6 +19,7 @@ #include #include #include +#include static int do_test (void) @@ -41,8 +42,28 @@ do_test (void) /* Verify fesetexcept does not cause exception traps. For architectures where setting the exception might result in traps the function should - return a nonzero value. */ - ret = fesetexcept (FE_ALL_EXCEPT); + return a nonzero value. + Also check if the function does not alter the exception mask. */ + { + int exc_before = fegetexcept (); + ret = fesetexcept (FE_ALL_EXCEPT); + int exc_after = fegetexcept (); + if (exc_before != exc_after) + { + puts ("fesetexcept (FE_ALL_EXCEPT) changed the exceptions mask"); + return 1; + } + } + + /* Execute some floating-point operations, since on some CPUs exceptions + triggers a trap only at the next floating-point instruction. */ + volatile double a = 1.0; + volatile double b = a + a; + math_force_eval (b); + volatile long double al = 1.0L; + volatile long double bl = al + al; + math_force_eval (bl); + if (ret == 0) puts ("fesetexcept (FE_ALL_EXCEPT) succeeded"); else if (!EXCEPTION_SET_FORCES_TRAP) @@ -61,5 +82,4 @@ do_test (void) return result; } -#define TEST_FUNCTION do_test () -#include "../test-skeleton.c" +#include diff --git a/sysdeps/i386/fpu/fesetexcept.c b/sysdeps/i386/fpu/fesetexcept.c index 18949e982a..58f577d93d 100644 --- a/sysdeps/i386/fpu/fesetexcept.c +++ b/sysdeps/i386/fpu/fesetexcept.c @@ -17,15 +17,53 @@ . */ #include +#include int fesetexcept (int excepts) { - fenv_t temp; + /* The flags can be set in the 387 unit or in the SSE unit. To set a flag, + it is sufficient to do it in the SSE unit, because that is guaranteed to + not trap. However, on i386 CPUs that have only a 387 unit, set the flags + in the 387, as long as this cannot trap. */ - __asm__ ("fnstenv %0" : "=m" (*&temp)); - temp.__status_word |= excepts & FE_ALL_EXCEPT; - __asm__ ("fldenv %0" : : "m" (*&temp)); + excepts &= FE_ALL_EXCEPT; + + if (CPU_FEATURE_USABLE (SSE)) + { + /* Get the control word of the SSE unit. */ + unsigned int mxcsr; + __asm__ ("stmxcsr %0" : "=m" (*&mxcsr)); + + /* Set relevant flags. */ + mxcsr |= excepts; + + /* Put the new data in effect. */ + __asm__ ("ldmxcsr %0" : : "m" (*&mxcsr)); + } + else + { + fenv_t temp; + + /* Note: fnstenv masks all floating-point exceptions until the fldenv + or fldcw below. */ + __asm__ ("fnstenv %0" : "=m" (*&temp)); + + /* Set relevant flags. */ + temp.__status_word |= excepts; + + if ((~temp.__control_word) & excepts) + { + /* Setting the exception flags may trigger a trap (at the next + floating-point instruction, but that does not matter). + ISO C23 (7.6.4.4) does not allow it. */ + __asm__ volatile ("fldcw %0" : : "m" (*&temp.__control_word)); + return -1; + } + + /* Store the new status word (along with the rest of the environment). */ + __asm__ ("fldenv %0" : : "m" (*&temp)); + } return 0; } diff --git a/sysdeps/i386/fpu/math-tests-trap-force.h b/sysdeps/i386/fpu/math-tests-trap-force.h new file mode 100644 index 0000000000..f41e1ffc2d --- /dev/null +++ b/sysdeps/i386/fpu/math-tests-trap-force.h @@ -0,0 +1,29 @@ +/* Configuration for math tests: support for setting exception flags + without causing enabled traps. i686 version. + Copyright (C) 2023 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + . */ + +#ifndef I386_FPU_MATH_TESTS_TRAP_FORCE_H +#define I386_FPU_MATH_TESTS_TRAP_FORCE_H 1 + +#include + +/* Setting exception flags in FPU Status Register results in enabled traps for + those exceptions being taken. */ +#define EXCEPTION_SET_FORCES_TRAP !CPU_FEATURE_USABLE (SSE) + +#endif /* math-tests-trap-force.h. */ diff --git a/sysdeps/x86/fpu/test-fenv-sse-2.c b/sysdeps/x86/fpu/test-fenv-sse-2.c index f3e820b6ed..7a0503790f 100644 --- a/sysdeps/x86/fpu/test-fenv-sse-2.c +++ b/sysdeps/x86/fpu/test-fenv-sse-2.c @@ -22,17 +22,8 @@ #include #include #include - -static bool -have_sse2 (void) -{ - unsigned int eax, ebx, ecx, edx; - - if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx)) - return false; - - return (edx & bit_SSE2) != 0; -} +#include +#include static uint32_t get_sse_mxcsr (void) @@ -164,13 +155,9 @@ sse_tests (void) static int do_test (void) { - if (!have_sse2 ()) - { - puts ("CPU does not support SSE2, cannot test"); - return 0; - } + if (!CPU_FEATURE_USABLE (SSE2)) + FAIL_UNSUPPORTED ("CPU does not support SSE2"); return sse_tests (); } -#define TEST_FUNCTION do_test () -#include +#include From patchwork Mon Nov 6 13:27:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Adhemerval Zanella Netto X-Patchwork-Id: 741395 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1083792wrr; Mon, 6 Nov 2023 05:27:54 -0800 (PST) X-Google-Smtp-Source: AGHT+IHbuL85flrXB0k6HGKd4OyzI85ePfE+Nu5CQaS/k4b8vU0EvfCCHXscYJU8Zz1+4eTOXch0 X-Received: by 2002:ac8:5d06:0:b0:41b:7759:2a9a with SMTP id f6-20020ac85d06000000b0041b77592a9amr39074169qtx.13.1699277274514; Mon, 06 Nov 2023 05:27:54 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1699277274; cv=pass; d=google.com; s=arc-20160816; b=lBUJFmDpsEs/7Y7EzAkrSlFdhcYINlqZyzL5pZ7+3OAOR8GMwqdS9/3sdo5Lgh90L8 2m9Ot2xMGudS9TYe3vaKJPEhlvhFTNCMcm293H3wUS8HUiZHlq/QqkLpAvEmA0zI9zUg QZjIWNfjYDBQfwKudqCwdbscWCw/rmJwUfFZfX43ZqRQIH9Jb1M02gED0D2fmA7x0onr g6PtpIAuILkkgw4qVRgaWZQ1s/mWnv/LQr3zsWsXUgG7/waYRiIqKScUxMg8Bys+CYUk hZlHWwx52bGgbA2nTmzVdnJhI+TCIHQF09UApB2QIWS67f7QV0wtEknnzeutiLZT2n4t fA6g== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature:arc-filter:dmarc-filter:delivered-to; bh=OsJVfrzuJQEStROxTkYGHeK2o8XwhP+5e/BtTCdJZcc=; fh=01HD8dtuIqmy9rV/eMJuvD8dAGq4TXBqBjIxWaMzNQI=; b=tEV0vTY99z6JCPZhtJUhNd00tQfNZZO8GJnhFMZYJWpy4FKIb+zpSClg5n6zKqk1++ DV7hOeTwKSvGA5INeEDxrN0TG5wCxd+WZZdjJL1dKkp77rmhPX0cb7bKiiKGvkM9qKnC M9/gW0oft7N04Eh1kBnUNyvy407Ng4JsqClEQ+ljOd10yqhRQXZv4T2AhBQUi1zbx0te 7MevcIex2bv1W6Haw/HMv65JOjb98sTPI/mZDPtdBLhMsAjWLl0Msf79p19UjJU/8Jlb wlMyYMgfe4ob/lihvWLQlZY946/Am5m+2GvATStaabDsR/GQUEdj8byK0U0GNMFwjgBV anfQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VxFuMLfb; arc=pass (i=1); spf=pass (google.com: domain of libc-alpha-bounces+patch=linaro.org@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="libc-alpha-bounces+patch=linaro.org@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from server2.sourceware.org (server2.sourceware.org. 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([2804:1b3:a7c0:a715:c1a0:7281:6384:2ee9]) by smtp.gmail.com with ESMTPSA id k3-20020a05620a142300b0076f12fcb0easm3272722qkj.2.2023.11.06.05.27.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Nov 2023 05:27:22 -0800 (PST) From: Adhemerval Zanella To: libc-alpha@sourceware.org, Bruno Haible Subject: [PATCH v2 3/7] x86: Do not raises floating-point exception traps on fesetexceptflag (BZ 30990) Date: Mon, 6 Nov 2023 10:27:09 -0300 Message-Id: <20231106132713.953501-4-adhemerval.zanella@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231106132713.953501-1-adhemerval.zanella@linaro.org> References: <20231106132713.953501-1-adhemerval.zanella@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: libc-alpha-bounces+patch=linaro.org@sourceware.org From: Bruno Haible According to ISO C23 (7.6.4.4), fesetexcept is supposed to set floating-point exception flags without raising a trap (unlike feraiseexcept, which is supposed to raise a trap if feenableexcept was called with the appropriate argument). The flags can be set in the 387 unit or in the SSE unit. When we need to clear a flag, we need to do so in both units, due to the way fetestexcept is implemented. When we need to set a flag, it is sufficient to do it in the SSE unit, because that is guaranteed to not trap. However, on i386 CPUs that have only a 387 unit, set the flags in the 387, as long as this cannot trap. Co-authored-by: Adhemerval Zanella Reviewed-by: Carlos O'Donell --- math/test-fexcept-traps.c | 25 +++++++++++- sysdeps/i386/fpu/fsetexcptflg.c | 63 ++++++++++++++++++++----------- sysdeps/x86_64/fpu/fsetexcptflg.c | 24 +++++++----- 3 files changed, 79 insertions(+), 33 deletions(-) diff --git a/math/test-fexcept-traps.c b/math/test-fexcept-traps.c index 9b8f583ae6..6bfb5124da 100644 --- a/math/test-fexcept-traps.c +++ b/math/test-fexcept-traps.c @@ -19,6 +19,7 @@ #include #include #include +#include static int do_test (void) @@ -65,8 +66,28 @@ do_test (void) /* The test is that this does not cause exception traps. For architectures where setting the exception might result in traps the function should - return a nonzero value. */ - ret = fesetexceptflag (&saved, FE_ALL_EXCEPT); + return a nonzero value. + Also check if the function does not alter the exception mask. */ + { + int exc_before = fegetexcept (); + ret = fesetexceptflag (&saved, FE_ALL_EXCEPT); + int exc_after = fegetexcept (); + if (exc_before != exc_after) + { + puts ("fesetexceptflag (FE_ALL_EXCEPT) changed the exceptions mask"); + return 1; + } + } + + /* Execute some floating-point operations, since on some CPUs exceptions + triggers a trap only at the next floating-point instruction. */ + volatile double a = 1.0; + volatile double b = a + a; + math_force_eval (b); + volatile long double al = 1.0L; + volatile long double bl = al + al; + math_force_eval (bl); + if (ret != 0 && !EXCEPTION_SET_FORCES_TRAP) { puts ("fesetexceptflag failed"); diff --git a/sysdeps/i386/fpu/fsetexcptflg.c b/sysdeps/i386/fpu/fsetexcptflg.c index e724b7d6fd..480165cff9 100644 --- a/sysdeps/i386/fpu/fsetexcptflg.c +++ b/sysdeps/i386/fpu/fsetexcptflg.c @@ -17,42 +17,63 @@ . */ #include -#include -#include #include -#include int __fesetexceptflag (const fexcept_t *flagp, int excepts) { - fenv_t temp; + /* The flags can be set in the 387 unit or in the SSE unit. When we need to + clear a flag, we need to do so in both units, due to the way fetestexcept + is implemented. + When we need to set a flag, it is sufficient to do it in the SSE unit, + because that is guaranteed to not trap. However, on i386 CPUs that have + only a 387 unit, set the flags in the 387, as long as this cannot trap. */ - /* Get the current environment. We have to do this since we cannot - separately set the status word. */ - __asm__ ("fnstenv %0" : "=m" (*&temp)); + fenv_t temp; - temp.__status_word &= ~(excepts & FE_ALL_EXCEPT); - temp.__status_word |= *flagp & excepts & FE_ALL_EXCEPT; + excepts &= FE_ALL_EXCEPT; - /* Store the new status word (along with the rest of the environment. - Possibly new exceptions are set but they won't get executed unless - the next floating-point instruction. */ - __asm__ ("fldenv %0" : : "m" (*&temp)); + /* Get the current x87 FPU environment. We have to do this since we + cannot separately set the status word. + Note: fnstenv masks all floating-point exceptions until the fldenv + or fldcw below. */ + __asm__ ("fnstenv %0" : "=m" (*&temp)); - /* If the CPU supports SSE, we set the MXCSR as well. */ if (CPU_FEATURE_USABLE (SSE)) { - unsigned int xnew_exc; + unsigned int mxcsr; + + /* Clear relevant flags. */ + temp.__status_word &= ~(excepts & ~ *flagp); - /* Get the current MXCSR. */ - __asm__ ("stmxcsr %0" : "=m" (*&xnew_exc)); + /* Store the new status word (along with the rest of the environment). */ + __asm__ ("fldenv %0" : : "m" (*&temp)); - /* Set the relevant bits. */ - xnew_exc &= ~(excepts & FE_ALL_EXCEPT); - xnew_exc |= *flagp & excepts & FE_ALL_EXCEPT; + /* And now similarly for SSE. */ + __asm__ ("stmxcsr %0" : "=m" (*&mxcsr)); + + /* Clear or set relevant flags. */ + mxcsr ^= (mxcsr ^ *flagp) & excepts; /* Put the new data in effect. */ - __asm__ ("ldmxcsr %0" : : "m" (*&xnew_exc)); + __asm__ ("ldmxcsr %0" : : "m" (*&mxcsr)); + } + else + { + /* Clear or set relevant flags. */ + temp.__status_word ^= (temp.__status_word ^ *flagp) & excepts; + + if ((~temp.__control_word) & temp.__status_word & excepts) + { + /* Setting the exception flags may trigger a trap (at the next + floating-point instruction, but that does not matter). + ISO C 23 § 7.6.4.5 does not allow it. */ + __asm__ volatile ("fldcw %0" : : "m" (*&temp.__control_word)); + return -1; + } + + /* Store the new status word (along with the rest of the environment). */ + __asm__ ("fldenv %0" : : "m" (*&temp)); } /* Success. */ diff --git a/sysdeps/x86_64/fpu/fsetexcptflg.c b/sysdeps/x86_64/fpu/fsetexcptflg.c index a3ac1dea01..2ce2b509f2 100644 --- a/sysdeps/x86_64/fpu/fsetexcptflg.c +++ b/sysdeps/x86_64/fpu/fsetexcptflg.c @@ -22,30 +22,34 @@ int fesetexceptflag (const fexcept_t *flagp, int excepts) { + /* The flags can be set in the 387 unit or in the SSE unit. + When we need to clear a flag, we need to do so in both units, + due to the way fetestexcept() is implemented. + When we need to set a flag, it is sufficient to do it in the SSE unit, + because that is guaranteed to not trap. */ + fenv_t temp; unsigned int mxcsr; - /* XXX: Do we really need to set both the exception in both units? - Shouldn't it be enough to set only the SSE unit? */ + excepts &= FE_ALL_EXCEPT; /* Get the current x87 FPU environment. We have to do this since we cannot separately set the status word. */ __asm__ ("fnstenv %0" : "=m" (*&temp)); - temp.__status_word &= ~(excepts & FE_ALL_EXCEPT); - temp.__status_word |= *flagp & excepts & FE_ALL_EXCEPT; + /* Clear relevant flags. */ + temp.__status_word &= ~(excepts & ~ *flagp); - /* Store the new status word (along with the rest of the environment. - Possibly new exceptions are set but they won't get executed unless - the next floating-point instruction. */ + /* Store the new status word (along with the rest of the environment). */ __asm__ ("fldenv %0" : : "m" (*&temp)); - /* And now the same for SSE. */ + /* And now similarly for SSE. */ __asm__ ("stmxcsr %0" : "=m" (*&mxcsr)); - mxcsr &= ~(excepts & FE_ALL_EXCEPT); - mxcsr |= *flagp & excepts & FE_ALL_EXCEPT; + /* Clear or set relevant flags. */ + mxcsr ^= (mxcsr ^ *flagp) & excepts; + /* Put the new data in effect. */ __asm__ ("ldmxcsr %0" : : "m" (*&mxcsr)); /* Success. */ From patchwork Mon Nov 6 13:27:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adhemerval Zanella Netto X-Patchwork-Id: 741393 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1083736wrr; Mon, 6 Nov 2023 05:27:48 -0800 (PST) X-Google-Smtp-Source: AGHT+IEpybXng7VqhUWFAoNAMOUdW+ebfmIcJ2zUT+WIRmoBO37GwjmLN5K9BZgNJ0OnhA941Df4 X-Received: by 2002:a1f:9bc9:0:b0:49a:6dc0:5a89 with SMTP id d192-20020a1f9bc9000000b0049a6dc05a89mr26419283vke.5.1699277268254; Mon, 06 Nov 2023 05:27:48 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1699277268; cv=pass; d=google.com; s=arc-20160816; b=Pri91hktqUjQRDEVoayWLLksY6dBHBefTzdVoIdGjPEB3LUBEXXrwCVmkdmXUlEEej KIE35JFH91lcm2l0FN6J6/yJGJamN7GEWhB4+3xbD79smZrF1KZcbmyngt8dvJjHkryi OpfjMfZw+K7trOIPAXIaxQtjdVD8WdC/0CqjVc8tqfL/CScsL8c77s1NIQKx2FOtXUyC j6Ly6/ds2q7l2i8FWzEeKCMvdS17DjyyrcW0+cMIrAjcZ55BvH4r2605YIuZS47AxdfJ zGGIfI9THG1DI7yBjR9DgfEvDujaivwP/zTYvMafGbArnQSOOWrDAS7331Jg3yr9MvLr ZOtg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature:arc-filter:dmarc-filter:delivered-to; bh=dAGhyw5HHu+H6+bHRnW8EePkEXjIB3hBIAUm3XJpJj4=; fh=01HD8dtuIqmy9rV/eMJuvD8dAGq4TXBqBjIxWaMzNQI=; b=Bp3ixns8rir0yrHofQKdEgssHRXAME03IIGsHQxUQcl9b/xJqLSgm183YfIBBC7Fa8 eewDokNHdR9vlxxkezTJvewpiJWBQlzcTVanN1j8fU4pA/m8lGpbyTeUsE04nVLY/oNr uDFHNnOEjLqycVz7i+X1wcFhtWvVrEmNZpgYzZXp/VFsVtgfyDrKGw3w6hEXJb7HPvI/ Enyh//ZDw+dA0XqRKHRRbx/KKB8RENMKioeeSHlGm1rTDUWUnnbLnz4tSqR6sACIXlaT 6OOWK+ElaD8ZV8+o2nFtRFdCppFfVvqlX1QnexeDhUf9fVtRQzAFm6shAswpix6BlKFN okIw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=rdRGpfUQ; arc=pass (i=1); spf=pass (google.com: domain of libc-alpha-bounces+patch=linaro.org@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="libc-alpha-bounces+patch=linaro.org@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from server2.sourceware.org (server2.sourceware.org. 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([2804:1b3:a7c0:a715:c1a0:7281:6384:2ee9]) by smtp.gmail.com with ESMTPSA id k3-20020a05620a142300b0076f12fcb0easm3272722qkj.2.2023.11.06.05.27.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Nov 2023 05:27:24 -0800 (PST) From: Adhemerval Zanella To: libc-alpha@sourceware.org, Bruno Haible Subject: [PATCH v2 4/7] manual: Clarify undefined behavior of feenableexcept (BZ 31019) Date: Mon, 6 Nov 2023 10:27:10 -0300 Message-Id: <20231106132713.953501-5-adhemerval.zanella@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231106132713.953501-1-adhemerval.zanella@linaro.org> References: <20231106132713.953501-1-adhemerval.zanella@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: libc-alpha-bounces+patch=linaro.org@sourceware.org From: Bruno Haible Explain undefined behavior of feenableexcept in a special case. Reviewed-by: Carlos O'Donell --- manual/arith.texi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/manual/arith.texi b/manual/arith.texi index fa7110e992..be24c20493 100644 --- a/manual/arith.texi +++ b/manual/arith.texi @@ -1176,6 +1176,12 @@ enabled, the status of the other exceptions is not changed. The function returns the previous enabled exceptions in case the operation was successful, @code{-1} otherwise. + +Note: Enabling traps for an exception for which the exception flag is +currently already set (@pxref{Status bit operations}) has unspecified +consequences: it may or may not trigger a trap immediately. +@c It triggers a trap immediately on powerpc*, at the next floating- +@c instruction on i386, and not at all on the other CPUs. @end deftypefun @deftypefun int fedisableexcept (int @var{excepts}) From patchwork Mon Nov 6 13:27:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adhemerval Zanella Netto X-Patchwork-Id: 741394 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1083789wrr; Mon, 6 Nov 2023 05:27:54 -0800 (PST) X-Google-Smtp-Source: AGHT+IGIdAe1DppNYoC0VDJWdGjLf0pcYkc8oGSxH9LNrbwgdOHv13JomhYT7U+RpXf4S2NtnMMe X-Received: by 2002:a05:6214:1949:b0:655:935b:ca85 with SMTP id q9-20020a056214194900b00655935bca85mr37114823qvk.48.1699277273861; Mon, 06 Nov 2023 05:27:53 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1699277273; cv=pass; d=google.com; s=arc-20160816; b=wh6NInsvwe6Qos8JY7HCenNiKuS9/p5As+zlju9OZArDntQkx5JUUxB+I7sAmLqvqf 2NhUmaOUtO17QPzwk+UBYGIBECh0U9KMRpfVGmTKNCF8JvAIF1hcLdtj8Ipl2M8ILx3Z UvYzf8KSeCVXWLk7zFdqmb1SAtBsY7qeOMgBslZxb2xRhXyewD6gE0Pox1FTW8JFwcO5 +nts/kWcI3KT1Je1PYrSvrflszoFqWcrl+jyFT6Nc15X2d2KmqHO7tDHKfI/Bs9b+BP3 OVd4bf6VBp1JTyI2cSMDlUH3amIYqZPXA0rU0T/zrWJzm1UTaKI3jYd4VYgro/JfAh/d atcw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature:arc-filter:dmarc-filter:delivered-to; bh=LHNjnkOvSbJeqaH29rBAWg6tdAoqLI2jG+IbFLY4Wo8=; fh=01HD8dtuIqmy9rV/eMJuvD8dAGq4TXBqBjIxWaMzNQI=; b=pa9pxOHme2YxCRx/TGpd4ocKwTrSQlDnqyd1IDnpTKUyWx6VzcAOGP85yt89UwRurY TUF7cOf/VXc196fJ0Spurnjvz/9HcjKVI5GsgYHr056+JW/VC7FSZ4fF15k4kXo+WuUC /Aq4LdnwPKAZmzDO9i6syJZELwPwlDkRjBAOzNK+oofyeFKC3rAMn8AK9ili9esyiTMR dCR3gZb+Sd737WGUE7qJp+dU/7y3xCrn/qNYA63dEcw4TQ4V/wXGpXUrGa7MWnPlQLLn o0iXN7ptkcrg4WepFHSYvdnXlPODtPWKaeby+J7xSdDWuHzmxUZITjAwkkkgX6ylfZRM 0Rew== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=LRzOLYVk; arc=pass (i=1); spf=pass (google.com: domain of libc-alpha-bounces+patch=linaro.org@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="libc-alpha-bounces+patch=linaro.org@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from server2.sourceware.org (server2.sourceware.org. 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([2804:1b3:a7c0:a715:c1a0:7281:6384:2ee9]) by smtp.gmail.com with ESMTPSA id k3-20020a05620a142300b0076f12fcb0easm3272722qkj.2.2023.11.06.05.27.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Nov 2023 05:27:26 -0800 (PST) From: Adhemerval Zanella To: libc-alpha@sourceware.org, Bruno Haible Subject: [PATCH v2 5/7] riscv: Fix feenvupdate with FE_DFL_ENV (BZ 31022) Date: Mon, 6 Nov 2023 10:27:11 -0300 Message-Id: <20231106132713.953501-6-adhemerval.zanella@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231106132713.953501-1-adhemerval.zanella@linaro.org> References: <20231106132713.953501-1-adhemerval.zanella@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: libc-alpha-bounces+patch=linaro.org@sourceware.org libc_feupdateenv_riscv should check for FE_DFL_ENV, similar to libc_fesetenv_riscv. Also extend the test-fenv.c to test fenvupdate. Checked on riscv under qemu-system. Reviewed-by: Carlos O'Donell --- math/test-fenv.c | 131 ++++++++++++++++++++++++++++--- sysdeps/riscv/rvf/fenv_private.h | 8 +- 2 files changed, 124 insertions(+), 15 deletions(-) diff --git a/math/test-fenv.c b/math/test-fenv.c index 0af7141ba7..63dceddb10 100644 --- a/math/test-fenv.c +++ b/math/test-fenv.c @@ -196,6 +196,30 @@ set_single_exc (const char *test_name, int fe_exc, fexcept_t exception) feclearexcept (exception); test_exceptions (str, ALL_EXC ^ fe_exc, 0); } + +static void +update_single_exc (const char *test_name, const fenv_t *envp, int fe_exc, + int fe_exc_clear, int exception) +{ + char str[200]; + /* The standard allows the inexact exception to be set together with the + underflow and overflow exceptions. So ignore the inexact flag if the + others are raised. */ + int ignore_inexact = (fe_exc & (UNDERFLOW_EXC | OVERFLOW_EXC)) != 0; + + strcpy (str, test_name); + strcat (str, ": set flag, with rest not set"); + feclearexcept (FE_ALL_EXCEPT); + feraiseexcept (exception); + feupdateenv (envp); + test_exceptions (str, fe_exc, ignore_inexact); + + strcpy (str, test_name); + strcat (str, ": clear flag, rest also unset"); + feclearexcept (exception); + feupdateenv (envp); + test_exceptions (str, fe_exc_clear, ignore_inexact); +} #endif static void @@ -233,22 +257,32 @@ fe_tests (void) } #if FE_ALL_EXCEPT +static const char * +funcname (int (*func)(const fenv_t *)) +{ + if (func == fesetenv) + return "fesetenv"; + else if (func == feupdateenv) + return "feupdateenv"; + __builtin_unreachable (); +} + /* Test that program aborts with no masked interrupts */ static void -feenv_nomask_test (const char *flag_name, int fe_exc) +feenv_nomask_test (const char *flag_name, int fe_exc, int (*func)(const fenv_t *)) { # if defined FE_NOMASK_ENV int status; pid_t pid; if (!EXCEPTION_ENABLE_SUPPORTED (FE_ALL_EXCEPT) - && fesetenv (FE_NOMASK_ENV) != 0) + && func (FE_NOMASK_ENV) != 0) { printf ("Test: not testing FE_NOMASK_ENV, it isn't implemented.\n"); return; } - printf ("Test: after fesetenv (FE_NOMASK_ENV) processes will abort\n"); + printf ("Test: after %s (FE_NOMASK_ENV) processes will abort\n", funcname (func)); printf (" when feraiseexcept (%s) is called.\n", flag_name); pid = fork (); if (pid == 0) @@ -295,12 +329,12 @@ feenv_nomask_test (const char *flag_name, int fe_exc) /* Test that program doesn't abort with default environment */ static void -feenv_mask_test (const char *flag_name, int fe_exc) +feenv_mask_test (const char *flag_name, int fe_exc, int (*func)(const fenv_t *)) { int status; pid_t pid; - printf ("Test: after fesetenv (FE_DFL_ENV) processes will not abort\n"); + printf ("Test: after %s (FE_DFL_ENV) processes will not abort\n", funcname (func)); printf (" when feraiseexcept (%s) is called.\n", flag_name); pid = fork (); if (pid == 0) @@ -313,7 +347,7 @@ feenv_mask_test (const char *flag_name, int fe_exc) setrlimit (RLIMIT_CORE, &core_limit); #endif - fesetenv (FE_DFL_ENV); + func (FE_DFL_ENV); feraiseexcept (fe_exc); exit (2); } @@ -615,10 +649,18 @@ feenable_test (const char *flag_name, int fe_exc) static void fe_single_test (const char *flag_name, int fe_exc) { - feenv_nomask_test (flag_name, fe_exc); - feenv_mask_test (flag_name, fe_exc); + feenv_nomask_test (flag_name, fe_exc, fesetenv); + feenv_mask_test (flag_name, fe_exc, fesetenv); feenable_test (flag_name, fe_exc); } + + +static void +feupdate_single_test (const char *flag_name, int fe_exc) +{ + feenv_nomask_test (flag_name, fe_exc, feupdateenv); + feenv_mask_test (flag_name, fe_exc, feupdateenv); +} #endif @@ -646,6 +688,72 @@ feenv_tests (void) fesetenv (FE_DFL_ENV); } +#if FE_ALL_EXCEPT +static void +feupdateenv_single_test (const char *test_name, int fe_exc, int exception) +{ + char str[100]; + fenv_t env; + int res; + + snprintf (str, sizeof str, "feupdateenv %s and FL_DFL_ENV", test_name); + update_single_exc (str, FE_DFL_ENV, fe_exc, NO_EXC, exception); + + feraiseexcept (FE_ALL_EXCEPT); + res = fegetenv (&env); + if (res != 0) + { + printf ("fegetenv failed: %d\n", res); + ++count_errors; + return; + } + + snprintf (str, sizeof str, "feupdateenv %s and FE_ALL_EXCEPT", test_name); + update_single_exc (str, &env, ALL_EXC, ALL_EXC, exception); +} +#endif + +static void +feupdateenv_tests (void) +{ + /* We might have some exceptions still set. */ + feclearexcept (FE_ALL_EXCEPT); + +#ifdef FE_DIVBYZERO + feupdate_single_test ("FE_DIVBYZERO", FE_DIVBYZERO); +#endif +#ifdef FE_INVALID + feupdate_single_test ("FE_INVALID", FE_INVALID); +#endif +#ifdef FE_INEXACT + feupdate_single_test ("FE_INEXACT", FE_INEXACT); +#endif +#ifdef FE_UNDERFLOW + feupdate_single_test ("FE_UNDERFLOW", FE_UNDERFLOW); +#endif +#ifdef FE_OVERFLOW + feupdate_single_test ("FE_OVERFLOW", FE_OVERFLOW); +#endif + +#ifdef FE_DIVBYZERO + feupdateenv_single_test ("DIVBYZERO", DIVBYZERO_EXC, FE_DIVBYZERO); +#endif +#ifdef FE_INVALID + feupdateenv_single_test ("INVALID", INVALID_EXC, FE_INVALID); +#endif +#ifdef FE_INEXACT + feupdateenv_single_test ("INEXACT", INEXACT_EXC, FE_INEXACT); +#endif +#ifdef FE_UNDERFLOW + feupdateenv_single_test ("UNDERFLOW", UNDERFLOW_EXC, FE_UNDERFLOW); +#endif +#ifdef FE_OVERFLOW + feupdateenv_single_test ("OVERFLOW", OVERFLOW_EXC, FE_OVERFLOW); +#endif + + feupdateenv (FE_DFL_ENV); +} + static void feholdexcept_tests (void) @@ -766,13 +874,14 @@ initial_tests (void) #endif } -int -main (void) +static int +do_test (void) { initial_tests (); fe_tests (); feenv_tests (); feholdexcept_tests (); + feupdateenv_tests (); if (count_errors) { @@ -782,3 +891,5 @@ main (void) printf ("\n All tests passed successfully.\n"); return 0; } + +#include diff --git a/sysdeps/riscv/rvf/fenv_private.h b/sysdeps/riscv/rvf/fenv_private.h index 40e23661b7..d8d65458b2 100644 --- a/sysdeps/riscv/rvf/fenv_private.h +++ b/sysdeps/riscv/rvf/fenv_private.h @@ -93,10 +93,7 @@ libc_fetestexcept_riscv (int ex) static __always_inline void libc_fesetenv_riscv (const fenv_t *envp) { - long int env = (long int) envp - (long int) FE_DFL_ENV; - if (env != 0) - env = *envp; - + long int env = (envp != FE_DFL_ENV ? *envp : 0); _FPU_SETCW (env); } @@ -123,7 +120,8 @@ libc_feupdateenv_test_riscv (const fenv_t *envp, int ex) static __always_inline void libc_feupdateenv_riscv (const fenv_t *envp) { - _FPU_SETCW (*envp | riscv_getflags ()); + long int env = (envp != FE_DFL_ENV ? *envp : 0); + _FPU_SETCW (env | riscv_getflags ()); } #define libc_feupdateenv libc_feupdateenv_riscv From patchwork Mon Nov 6 13:27:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adhemerval Zanella Netto X-Patchwork-Id: 741396 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1083810wrr; Mon, 6 Nov 2023 05:27:56 -0800 (PST) X-Google-Smtp-Source: AGHT+IGi01c6ABlTJwsTvYvlDnK9JpLdhD7v4GtrZcYiDk8I411jaJOD07SicQzqs4T+HetH6UzQ X-Received: by 2002:a0c:f1ca:0:b0:66d:28a5:d153 with SMTP id u10-20020a0cf1ca000000b0066d28a5d153mr27236186qvl.47.1699277276272; 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([2804:1b3:a7c0:a715:c1a0:7281:6384:2ee9]) by smtp.gmail.com with ESMTPSA id k3-20020a05620a142300b0076f12fcb0easm3272722qkj.2.2023.11.06.05.27.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Nov 2023 05:27:28 -0800 (PST) From: Adhemerval Zanella To: libc-alpha@sourceware.org, Bruno Haible Subject: [PATCH v2 6/7] alpha: Fix fesetexceptflag (BZ 30998) Date: Mon, 6 Nov 2023 10:27:12 -0300 Message-Id: <20231106132713.953501-7-adhemerval.zanella@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231106132713.953501-1-adhemerval.zanella@linaro.org> References: <20231106132713.953501-1-adhemerval.zanella@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: libc-alpha-bounces+patch=linaro.org@sourceware.org From: Bruno Haible It clears some exception flags that are outside the EXCEPTS argument. It fixes math/test-fexcept on qemu-user. Reviewed-by: Carlos O'Donell --- sysdeps/alpha/fpu/fsetexcptflg.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sysdeps/alpha/fpu/fsetexcptflg.c b/sysdeps/alpha/fpu/fsetexcptflg.c index 70f3666a6e..63eb06845d 100644 --- a/sysdeps/alpha/fpu/fsetexcptflg.c +++ b/sysdeps/alpha/fpu/fsetexcptflg.c @@ -27,7 +27,7 @@ __fesetexceptflag (const fexcept_t *flagp, int excepts) tmp = __ieee_get_fp_control (); /* Set all the bits that were called for. */ - tmp = (tmp & ~SWCR_STATUS_MASK) | (*flagp & excepts & SWCR_STATUS_MASK); + tmp ^= (tmp ^ *flagp) & excepts & SWCR_STATUS_MASK; /* And store it back. */ __ieee_set_fp_control (tmp); From patchwork Mon Nov 6 13:27:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adhemerval Zanella Netto X-Patchwork-Id: 741397 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1083955wrr; Mon, 6 Nov 2023 05:28:18 -0800 (PST) X-Google-Smtp-Source: AGHT+IGFDCC0NByMIlyc6Kiv1j5/BkwBH/SR4PE3g6OOqfz0ulI+aEN8d+rtFUwsw/A0JisKTqky X-Received: by 2002:a05:620a:191c:b0:767:ff8e:74ff with SMTP id bj28-20020a05620a191c00b00767ff8e74ffmr14533395qkb.25.1699277297870; Mon, 06 Nov 2023 05:28:17 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1699277297; cv=pass; d=google.com; s=arc-20160816; b=uUkSl9Gdou/eSuiFq5XXmIuBCZpiPTncsZhdE2xAhnBGZIshY6SvWBdV2CadN4aYOc wO2txBHZCz8mKAIdGIx0QaKroxP5oQD/4ag2e9G6R3gG022r3hAOXLPPowaTSFkhA5Yt 3ietJCeuQQB5PfszfQtdSLa6MqlAB2NqDJ3+Ke7xuJJ5lST3jIMn1iDNF4FcaGoISVKy 9yj/Y0Lq1cdAqM9f+xUCd2imJNuuUKvN8t7bQpDPb39ghCe+fJ9tLAgURvVn29sUdBIU bEeIDtUXi7FU/RrFueYoIyuuuCx7Qgfm8zomjP3lgaAeUFSo4TZn2QtwG6EkLjqbGOKi DO9A== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature:arc-filter:dmarc-filter:delivered-to; bh=6jWpJtYgU4AupWiGBpR3CkeP70iQINh300sZdk4guoA=; fh=01HD8dtuIqmy9rV/eMJuvD8dAGq4TXBqBjIxWaMzNQI=; b=xW7RHs977BbZHam67QRSiyk4BchftpNVz5bXxRwyiO7WHaFJRByBZ6CSMjhxwMaJHk wWBJspX6d1jUg43nqsLUfXQEBKxywUttPRnaHhSexZXoOEK//bFIpC8O3g2D3hSyRhXR 5C2LmWDuVzpkcMALfkvRLa5G/APHZ8CSPATcXCjWjhot24Gt1+GvPqbbdXFMKQJgh0eH vCM5hyKbXJodLEg/0wMjJLf6i470e//PuL11TUbvGAbuN3CjYOY2H36eVOZwsK2ixHhQ htgVaUoOaIrezftFBmjn+WVsWtlNG/kBdHov4P8piLlUMvcWbTtsdP7Cxof3LvNyJC+/ 1r5w== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WifGkwAM; arc=pass (i=1); spf=pass (google.com: domain of libc-alpha-bounces+patch=linaro.org@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="libc-alpha-bounces+patch=linaro.org@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from server2.sourceware.org (server2.sourceware.org. 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([2804:1b3:a7c0:a715:c1a0:7281:6384:2ee9]) by smtp.gmail.com with ESMTPSA id k3-20020a05620a142300b0076f12fcb0easm3272722qkj.2.2023.11.06.05.27.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Nov 2023 05:27:29 -0800 (PST) From: Adhemerval Zanella To: libc-alpha@sourceware.org, Bruno Haible Subject: [PATCH v2 7/7] hppa: Fix undefined behaviour in feclearexcept (BZ 30983) Date: Mon, 6 Nov 2023 10:27:13 -0300 Message-Id: <20231106132713.953501-8-adhemerval.zanella@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231106132713.953501-1-adhemerval.zanella@linaro.org> References: <20231106132713.953501-1-adhemerval.zanella@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: libc-alpha-bounces+patch=linaro.org@sourceware.org From: Bruno Haible The expression (excepts & FE_ALL_EXCEPT) << 27 produces a signed integer overflow when 'excepts' is specified as FE_INVALID (= 0x10), because - excepts is of type 'int', - FE_ALL_EXCEPT is of type 'int', - thus (excepts & FE_ALL_EXCEPT) is (int) 0x10, - 'int' is 32 bits wide. The patched code produces the same instruction sequence as previosuly. Reviewed-by: Carlos O'Donell --- sysdeps/hppa/fpu/fclrexcpt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sysdeps/hppa/fpu/fclrexcpt.c b/sysdeps/hppa/fpu/fclrexcpt.c index 055fb04ccc..46caf39ec1 100644 --- a/sysdeps/hppa/fpu/fclrexcpt.c +++ b/sysdeps/hppa/fpu/fclrexcpt.c @@ -26,7 +26,7 @@ feclearexcept (int excepts) /* Get the current status word. */ __asm__ ("fstd %%fr0,0(%1)" : "=m" (s.l) : "r" (&s.l) : "%r0"); /* Clear all the relevant bits. */ - s.sw[0] &= ~((excepts & FE_ALL_EXCEPT) << 27); + s.sw[0] &= ~(((unsigned int) excepts & FE_ALL_EXCEPT) << 27); __asm__ ("fldd 0(%0),%%fr0" : : "r" (&s.l), "m" (s.l) : "%r0"); /* Success. */