From patchwork Mon Nov 13 13:44:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 743692 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6AEDA208D3 for ; Mon, 13 Nov 2023 13:45:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="MLCaTwro" Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.88]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 73E7D10E2 for ; Mon, 13 Nov 2023 05:45:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1699883105; x=1731419105; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=dSRoGLNGkzB/cewjB4rN6vNiiKu4LDQf2s9zKDElRU0=; b=MLCaTwroFXWx4J1+ebE72904UHBfgdMT+tOSd1oEX3tsfvQUGa+lJKwi yRcUUROyFUNVQKtdtNjo2D7seNGsFVx4VQMVvew1QvOR4eG+HmFny3DVX Otk+qgvARt3lmu38HMDnvMccWEfY3yW/SjuPw0kxbKdfDxLXJcJ9hxAxn ahvVSbeFmPKge118QZ8xJaVJKW+McPAFxMYMOjKGwaIoyckR3krbDHJAI trGbfQBH4KFHfet+vthekSfphJM1d07e90c0AqZ08blMC5CYOLMglQWGN CXOy8VfkrfAYDrveU2JArhXevaDj6GJa69JjhM6wVlTbiMyYBr00vQrFn Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10893"; a="421531262" X-IronPort-AV: E=Sophos;i="6.03,299,1694761200"; d="scan'208";a="421531262" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Nov 2023 05:45:04 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10893"; a="793440933" X-IronPort-AV: E=Sophos;i="6.03,299,1694761200"; d="scan'208";a="793440933" Received: from turnipsi.fi.intel.com (HELO kekkonen.fi.intel.com) ([10.237.72.44]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Nov 2023 05:45:03 -0800 Received: from svinhufvud.ger.corp.intel.com (localhost [IPv6:::1]) by kekkonen.fi.intel.com (Postfix) with ESMTP id 46307120BA7; Mon, 13 Nov 2023 15:45:00 +0200 (EET) From: Sakari Ailus To: linux-media@vger.kernel.org Cc: laurent.pinchart@ideasonboard.com, hdegoede@redhat.com Subject: [PATCH v2 2/6] media: v4l: cci: Add driver-private bit definitions Date: Mon, 13 Nov 2023 15:44:54 +0200 Message-Id: <20231113134458.1423754-3-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231113134458.1423754-1-sakari.ailus@linux.intel.com> References: <20231113134458.1423754-1-sakari.ailus@linux.intel.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Provide a few bits for drivers to store private information on register definitions. Signed-off-by: Sakari Ailus Reviewed-by: Hans de Goede --- include/media/v4l2-cci.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/media/v4l2-cci.h b/include/media/v4l2-cci.h index f2c2962e936b..ee469f03e440 100644 --- a/include/media/v4l2-cci.h +++ b/include/media/v4l2-cci.h @@ -33,6 +33,11 @@ struct cci_reg_sequence { #define CCI_REG_ADDR_MASK GENMASK(15, 0) #define CCI_REG_WIDTH_SHIFT 16 #define CCI_REG_WIDTH_MASK GENMASK(19, 16) +/* + * Private CCI register flags, for the use of drivers. + */ +#define CCI_REG_PRIVATE_SHIFT 28U +#define CCI_REG_PRIVATE_MASK GENMASK(31U, CCI_REG_PRIVATE_SHIFT) #define CCI_REG8(x) ((1 << CCI_REG_WIDTH_SHIFT) | (x)) #define CCI_REG16(x) ((2 << CCI_REG_WIDTH_SHIFT) | (x)) From patchwork Mon Nov 13 13:44:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 743691 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 933BF208A8 for ; Mon, 13 Nov 2023 13:45:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="P0o+IvYl" Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.88]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 395A810FB for ; Mon, 13 Nov 2023 05:45:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1699883106; x=1731419106; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=9eDGvWq7eNETl+uBlWVa9nAB3RTCFgKJKyc5vM2rbrg=; b=P0o+IvYlTNnMl5zBILIPuwvm0NHzYlYVSUZaOp46xB8m+HQTHLwgUy6c YSraCqF1e765MNdb68+fNtjJ3J8XXKWmOHZsC5IO3+G6y5GqPCvEEH1w8 ApVPZ8XxlvPg6W8uuit9r8fOdyLAQ/AeRevrt/5MpUNwo0RboUj3gPgYz CIWD7dR76NLXqgk/LnDvNgZetbOwl+EbPic+W1oD+PnfiNo6eHoQz6Ng5 n+58MqNxfHSEHSw8AoLxEviIRhGQmRe01Tm7XOV6VBwvqs4SINnyisEkF U+ayvTkU5MYBTKo7peKqdfiyjW0uQbNPOugi9gHDUIqCyJGrYJcw8Q1D0 Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10893"; a="421531266" X-IronPort-AV: E=Sophos;i="6.03,299,1694761200"; d="scan'208";a="421531266" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Nov 2023 05:45:04 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10893"; a="793440936" X-IronPort-AV: E=Sophos;i="6.03,299,1694761200"; d="scan'208";a="793440936" Received: from turnipsi.fi.intel.com (HELO kekkonen.fi.intel.com) ([10.237.72.44]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Nov 2023 05:45:03 -0800 Received: from svinhufvud.ger.corp.intel.com (localhost [IPv6:::1]) by kekkonen.fi.intel.com (Postfix) with ESMTP id C4015120BDC; Mon, 13 Nov 2023 15:45:00 +0200 (EET) From: Sakari Ailus To: linux-media@vger.kernel.org Cc: laurent.pinchart@ideasonboard.com, hdegoede@redhat.com Subject: [PATCH v2 3/6] media: v4l: cci: Add macros to obtain register width and address Date: Mon, 13 Nov 2023 15:44:55 +0200 Message-Id: <20231113134458.1423754-4-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231113134458.1423754-1-sakari.ailus@linux.intel.com> References: <20231113134458.1423754-1-sakari.ailus@linux.intel.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add CCI_REG_WIDTH() macro to obtain register width in bits and similarly, CCI_REG_WIDTH_BYTES() to obtain it in bytes. Also add CCI_REG_ADDR() macro to obtain the address of a register. Use both macros in v4l2-cci.c, too. Signed-off-by: Sakari Ailus Reviewed-by: Hans de Goede --- drivers/media/v4l2-core/v4l2-cci.c | 8 ++++---- include/media/v4l2-cci.h | 9 +++++++-- 2 files changed, 11 insertions(+), 6 deletions(-) diff --git a/drivers/media/v4l2-core/v4l2-cci.c b/drivers/media/v4l2-core/v4l2-cci.c index bc2dbec019b0..3179160abde3 100644 --- a/drivers/media/v4l2-core/v4l2-cci.c +++ b/drivers/media/v4l2-core/v4l2-cci.c @@ -25,8 +25,8 @@ int cci_read(struct regmap *map, u32 reg, u64 *val, int *err) if (err && *err) return *err; - len = FIELD_GET(CCI_REG_WIDTH_MASK, reg); - reg = FIELD_GET(CCI_REG_ADDR_MASK, reg); + len = CCI_REG_WIDTH_BYTES(reg); + reg = CCI_REG_ADDR(reg); ret = regmap_bulk_read(map, reg, buf, len); if (ret) { @@ -75,8 +75,8 @@ int cci_write(struct regmap *map, u32 reg, u64 val, int *err) if (err && *err) return *err; - len = FIELD_GET(CCI_REG_WIDTH_MASK, reg); - reg = FIELD_GET(CCI_REG_ADDR_MASK, reg); + len = CCI_REG_WIDTH_BYTES(reg); + reg = CCI_REG_ADDR(reg); switch (len) { case 1: diff --git a/include/media/v4l2-cci.h b/include/media/v4l2-cci.h index ee469f03e440..50df3aa4af1d 100644 --- a/include/media/v4l2-cci.h +++ b/include/media/v4l2-cci.h @@ -7,6 +7,7 @@ #ifndef _V4L2_CCI_H #define _V4L2_CCI_H +#include #include #include @@ -36,8 +37,12 @@ struct cci_reg_sequence { /* * Private CCI register flags, for the use of drivers. */ -#define CCI_REG_PRIVATE_SHIFT 28U -#define CCI_REG_PRIVATE_MASK GENMASK(31U, CCI_REG_PRIVATE_SHIFT) +#define CCI_REG_PRIVATE_SHIFT 28 +#define CCI_REG_PRIVATE_MASK GENMASK(31, CCI_REG_PRIVATE_SHIFT) + +#define CCI_REG_WIDTH_BYTES(x) FIELD_GET(CCI_REG_WIDTH_MASK, x) +#define CCI_REG_WIDTH(x) (CCI_REG_WIDTH_BYTES(x) << 3) +#define CCI_REG_ADDR(x) FIELD_GET(CCI_REG_ADDR_MASK, x) #define CCI_REG8(x) ((1 << CCI_REG_WIDTH_SHIFT) | (x)) #define CCI_REG16(x) ((2 << CCI_REG_WIDTH_SHIFT) | (x)) From patchwork Mon Nov 13 13:44:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 743690 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 217BB2033A for ; Mon, 13 Nov 2023 13:45:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="GTpHrOJu" Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.88]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7B6D2D53 for ; Mon, 13 Nov 2023 05:45:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1699883107; x=1731419107; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=vEOsHOoQFbDjx/fMXgU7+lcn6jtLvfAt8wSFkJ5LgXQ=; b=GTpHrOJu1ItI+bd0k77bo/+ST7CalS53Cm1SzYiiGwjOEUKxLce6Lrtk Ehlhuc5PxijQ1x+2jrRl3k11jiVY5I96NQPGDBNxljD98uKn0xlSKzdUF EbxH+lrpff25d4tni8MsmoXwiyLoQL2UzA+4sDXNEBvQ4QyWl0fBc1tDf 1oSucCRQNvcRqwtMmVCYferPBdplEeKXQj2MsvK3qxwesLds7t+wHi1Lh KMXqNXmP+AQxKPyvFhc6TUBqlmcIHeDZRy/FF+v6KQC54iBvNqysHfION jD2AfzzxoolMefXnFCNWq9BQTHupS75kbp2XD8NhK5I/BVaZ5T2mB16mE w==; X-IronPort-AV: E=McAfee;i="6600,9927,10893"; a="421531273" X-IronPort-AV: E=Sophos;i="6.03,299,1694761200"; d="scan'208";a="421531273" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Nov 2023 05:45:07 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10893"; a="793440942" X-IronPort-AV: E=Sophos;i="6.03,299,1694761200"; d="scan'208";a="793440942" Received: from turnipsi.fi.intel.com (HELO kekkonen.fi.intel.com) ([10.237.72.44]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Nov 2023 05:45:05 -0800 Received: from svinhufvud.ger.corp.intel.com (localhost [IPv6:::1]) by kekkonen.fi.intel.com (Postfix) with ESMTP id 58182120E18; Mon, 13 Nov 2023 15:45:02 +0200 (EET) From: Sakari Ailus To: linux-media@vger.kernel.org Cc: laurent.pinchart@ideasonboard.com, hdegoede@redhat.com Subject: [PATCH v2 5/6] media: ccs: Better separate CCS static data access Date: Mon, 13 Nov 2023 15:44:57 +0200 Message-Id: <20231113134458.1423754-6-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231113134458.1423754-1-sakari.ailus@linux.intel.com> References: <20231113134458.1423754-1-sakari.ailus@linux.intel.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Separate CCS static data read-only register access in ccs-reg-access.c by naming them differently. The code in this file generally deals with reading and writing registers where as static data (when it comes to ccs_static_read_only()) contains the read-only register values but no hardware registers are accessed in that case. Signed-off-by: Sakari Ailus --- .../driver-api/media/drivers/ccs/mk-ccs-regs | 2 +- drivers/media/i2c/ccs/ccs-reg-access.c | 20 +++++++++---------- 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/Documentation/driver-api/media/drivers/ccs/mk-ccs-regs b/Documentation/driver-api/media/drivers/ccs/mk-ccs-regs index 01252ee6062b..3d3152b45821 100755 --- a/Documentation/driver-api/media/drivers/ccs/mk-ccs-regs +++ b/Documentation/driver-api/media/drivers/ccs/mk-ccs-regs @@ -136,7 +136,7 @@ if (! defined $kernel) { print $H "#define CCS_FL_FLOAT_IREAL " . flag_str(\$flag, \$all_flags) . "\n"; print $H "#define CCS_FL_IREAL " . flag_str(\$flag, \$all_flags) . "\n"; -print $H "#define CCS_BUILD_BUG \ +print $H "#define CCS_BUILD_BUG \\ BUILD_BUG_ON(~CCI_REG_PRIVATE_MASK & ($all_flags))\n" if defined $kernel; diff --git a/drivers/media/i2c/ccs/ccs-reg-access.c b/drivers/media/i2c/ccs/ccs-reg-access.c index 25993445f4fe..652d705a2ef5 100644 --- a/drivers/media/i2c/ccs/ccs-reg-access.c +++ b/drivers/media/i2c/ccs/ccs-reg-access.c @@ -197,8 +197,8 @@ static int __ccs_read_addr(struct ccs_sensor *sensor, u32 reg, u32 *val, return 0; } -static int __ccs_read_data(struct ccs_reg *regs, size_t num_regs, - u32 reg, u32 *val) +static int __ccs_static_read_only(struct ccs_reg *regs, size_t num_regs, + u32 reg, u32 *val) { unsigned int width = ccs_reg_width(reg); size_t i; @@ -235,16 +235,16 @@ static int __ccs_read_data(struct ccs_reg *regs, size_t num_regs, return -ENOENT; } -static int ccs_read_data(struct ccs_sensor *sensor, u32 reg, u32 *val) +static int ccs_static_read_only(struct ccs_sensor *sensor, u32 reg, u32 *val) { - if (!__ccs_read_data(sensor->sdata.sensor_read_only_regs, - sensor->sdata.num_sensor_read_only_regs, - reg, val)) + if (!__ccs_static_read_only(sensor->sdata.sensor_read_only_regs, + sensor->sdata.num_sensor_read_only_regs, + reg, val)) return 0; - return __ccs_read_data(sensor->mdata.module_read_only_regs, - sensor->mdata.num_module_read_only_regs, - reg, val); + return __ccs_static_read_only(sensor->mdata.module_read_only_regs, + sensor->mdata.num_module_read_only_regs, + reg, val); } static int ccs_read_addr_raw(struct ccs_sensor *sensor, u32 reg, u32 *val, @@ -253,7 +253,7 @@ static int ccs_read_addr_raw(struct ccs_sensor *sensor, u32 reg, u32 *val, int rval; if (data) { - rval = ccs_read_data(sensor, reg, val); + rval = ccs_static_read_only(sensor, reg, val); if (!rval) return 0; }