From patchwork Wed Nov 15 09:51:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jai Luthra X-Patchwork-Id: 744141 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7C4037E for ; Wed, 15 Nov 2023 09:52:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="Af4LcLhL" Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3FC6711C; Wed, 15 Nov 2023 01:52:24 -0800 (PST) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 3AF9q92b104991; Wed, 15 Nov 2023 03:52:09 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1700041929; bh=LLGGCOQ7unGDSmJmEvT2dCwuXArAIgSDeOPgzN9Q4Ec=; h=From:Date:Subject:References:In-Reply-To:To:CC; b=Af4LcLhLLJaAvc5OGBYF2ljSURLSPbirtXj15P5eoVxQDs7gUirl1XdLH1hfKsEK3 UkanFSUVM37mlyo7XRkI836Ou53UGScDTTVWEcnhJIcJcqYr4RNOkVoJJ+1FPk+1u0 pVEib10FGJYKktcXyEmNu3BkiPwVOgbR4/qniRYU= Received: from DLEE110.ent.ti.com (dlee110.ent.ti.com [157.170.170.21]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 3AF9q9bs109154 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 15 Nov 2023 03:52:09 -0600 Received: from DLEE100.ent.ti.com (157.170.170.30) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 15 Nov 2023 03:52:09 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 15 Nov 2023 03:52:09 -0600 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 3AF9q8gA009683; Wed, 15 Nov 2023 03:52:08 -0600 From: Jai Luthra Date: Wed, 15 Nov 2023 15:21:09 +0530 Subject: [PATCH 1/8] arm64: defconfig: Enable AM62 CSI2RX Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20231115-csi_dts-v1-1-99fc535b2bde@ti.com> References: <20231115-csi_dts-v1-0-99fc535b2bde@ti.com> In-Reply-To: <20231115-csi_dts-v1-0-99fc535b2bde@ti.com> To: Catalin Marinas , Will Deacon , Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Aradhya Bhatia , Devarsh Thakkar , Vaishnav Achath , Julien Massot , Martyn Welch , Jai Luthra X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=1229; i=j-luthra@ti.com; h=from:subject:message-id; bh=8U3EQOnnnQs+YWq5bKXi7ppSCeJNZ30pVpHqlXgkXMA=; b=owEBbQKS/ZANAwAIAUPekfkkmnFFAcsmYgBlVJS5ClHbIj0PBE9t2b/G0B5Dhzy9g7A5MYJcm tCTl4pBhJmJAjMEAAEIAB0WIQRN4NgY5dV16NRar8VD3pH5JJpxRQUCZVSUuQAKCRBD3pH5JJpx RXC/D/45/M7qdoBGBRU7UODDT0uKAMafjqTYos26JFwLBx0via4aA1DvTFzE/r/Q5lgDnZY7CJH LFGDJv1AtRQAC4ZRCqT6Bx/nuFhj6w5hR/ac8Hi6YEPiX8IoGo0Lg+nkb81rN1yyV0VMa+5oA+M IaN5F9kPQohyeQk4yFWbmPB8DxMb7Y9EdNrV0GAQSty49XtMqNAZ7wMi1L3OjJl4mtUuKDh1m7f WjLarCc0DKjltP3dC7zRyf8vqEroh16+1K4dW2U4jqK2tsIwaBOqOLrhLaigxCuQ3e+q1JxMSyj g01XlNmI4O7GVXAooQugG7XYncnzaEmqIgL8vlQykvNYeoU6fTozPvYCSj/IWoCfexdS6JVYNzW 6ymcPCeZBMrz9QcQrsEKeSLDKi89w/jHE+Z5MN578PWI5FhCpyvN5OeZKkQO2aa/c5L+/mDWZe1 PDegbnR6EYYOftTRCjYBg8NN2/g/3znXAKa3oslrvXWcP+FDzrxp1C2yYHJC4JQQmxDfrW06B5e J/v99C24yEo1Bu6+jKu3jLMnPFJMNMJgUSTf5iiyV+6LyFH3tEmEdF+2dJn1ajlpIoZF41cb/q4 yZpW9Cwr/RgcO/RvRtkxDmrfaSYA/qXcDCBTAz2zvc4TC37MpXCYI1jdewMuJY5jJRAFzXHuQlK IhctqwmWIOyhRlg== X-Developer-Key: i=j-luthra@ti.com; a=openpgp; fpr=4DE0D818E5D575E8D45AAFC543DE91F9249A7145 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 AM62 and other K3 based SoCs use Cadence DPHY and CSI-RX bridge drivers, along with a DMA wrapper CSI IP for the camera pipeline. Signed-off-by: Jai Luthra --- arch/arm64/configs/defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index b60aa1f89343..aa2df39d072e 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -783,6 +783,7 @@ CONFIG_USB_VIDEO_CLASS=m CONFIG_V4L_PLATFORM_DRIVERS=y CONFIG_SDR_PLATFORM_DRIVERS=y CONFIG_V4L_MEM2MEM_DRIVERS=y +CONFIG_VIDEO_CADENCE_CSI2RX=m CONFIG_VIDEO_MEDIATEK_JPEG=m CONFIG_VIDEO_MEDIATEK_VCODEC=m CONFIG_VIDEO_IMX7_CSI=m @@ -804,6 +805,7 @@ CONFIG_VIDEO_SAMSUNG_EXYNOS_GSC=m CONFIG_VIDEO_SAMSUNG_S5P_JPEG=m CONFIG_VIDEO_SAMSUNG_S5P_MFC=m CONFIG_VIDEO_SUN6I_CSI=m +CONFIG_VIDEO_TI_J721E_CSI2RX=m CONFIG_VIDEO_HANTRO=m CONFIG_VIDEO_IMX219=m CONFIG_VIDEO_IMX412=m @@ -1421,6 +1423,7 @@ CONFIG_PHY_XGENE=y CONFIG_PHY_CAN_TRANSCEIVER=m CONFIG_PHY_SUN4I_USB=y CONFIG_PHY_CADENCE_TORRENT=m +CONFIG_PHY_CADENCE_DPHY_RX=m CONFIG_PHY_CADENCE_SIERRA=m CONFIG_PHY_MIXEL_MIPI_DPHY=m CONFIG_PHY_FSL_IMX8M_PCIE=y From patchwork Wed Nov 15 09:51:10 2023 Content-Type: text/plain; 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Wed, 15 Nov 2023 03:52:10 -0600 From: Jai Luthra Date: Wed, 15 Nov 2023 15:21:10 +0530 Subject: [PATCH 2/8] arm64: dts: ti: Enable CSI-RX on AM62 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20231115-csi_dts-v1-2-99fc535b2bde@ti.com> References: <20231115-csi_dts-v1-0-99fc535b2bde@ti.com> In-Reply-To: <20231115-csi_dts-v1-0-99fc535b2bde@ti.com> To: Catalin Marinas , Will Deacon , Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Aradhya Bhatia , Devarsh Thakkar , Vaishnav Achath , Julien Massot , Martyn Welch , Jai Luthra X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=2175; i=j-luthra@ti.com; h=from:subject:message-id; bh=Ygo3DMdffwbzu3W24FhQXSDCuiW/4zp9AmLaS/aTiyk=; b=owEBbQKS/ZANAwAIAUPekfkkmnFFAcsmYgBlVJS5K58USh8mBD3DC3jzqtI6iwmtg6IcPoD/W 2rgL9AGiLeJAjMEAAEIAB0WIQRN4NgY5dV16NRar8VD3pH5JJpxRQUCZVSUuQAKCRBD3pH5JJpx RaqmD/9rxFCqMJtUlFUV/4S/uzP/3qTmJag8aliPz2OXZivPWQ7uLxDniA+osdaRrlg32f8cSAd YJeWfANcBTRFi6qxAcuYA7ln+yklxL+sVq1ubsm7kqFXop2R+gDcEB2zLEsT28+R0tPH+z0QmsO pn8HqRb/1sjuwUYZJEhaaASAghwUmwQ9ACS0KKXq9aWcRl9rgAwZwF7leF47Pg+USvjc5Dt9AE2 ZhXeB2MOe4hd2NOy7Od+Q/T0OpRKPWWvw6mzWWAfozIWGrx8W1bONRWuvD5iAV0wDbEpPPIf0rm aU7IOmGZFy54Obr6vcTkSz+AH/CgzsxrtD6S9Uvl5F8PpXCjus+kvYAeWEho2SNf4OCWVw0CnkW Wwug4wIgG4yn/j2j2/vg2FjiI2JYd8o7lwA7MNlUBfOUAx+OdT5IgTG+EfMrYe8XlLq6cw0yFXf nTmRR6RP/rfzrTz4/AQmjlbQhswktVP8QuWTPEJt95RBbgLIxqKNlMmEqVaNKQB402sCQGjrZBi 7IsSCqh/8TkYQeMaaGCJPlMhi7QkM+yFBQNrO/UZ/aGc+dPNSAzoPW7nR9k40CTrakcGofbflrs KpfXWD0uSB0uTw5R/ppHPI/3U3sU+KKDZCYYY5OEWLiD35TddRJEkIDReUJngoRiLofMyXucQQh g5rjSKKa2JsbdhQ== X-Developer-Key: i=j-luthra@ti.com; a=openpgp; fpr=4DE0D818E5D575E8D45AAFC543DE91F9249A7145 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 The CSI2RX subsystem can be used to capture video frames from CSI-2 cameras. Add nodes for the CSI core, SHIM layer, and the DPHY. Signed-off-by: Jai Luthra --- arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 62 ++++++++++++++++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi index e5c64c86d1d5..c0a95f6aff5e 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -965,4 +965,66 @@ mcasp2: audio-controller@2b20000 { power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; status = "disabled"; }; + + ti_csi2rx0: ticsi2rx@30102000 { + compatible = "ti,j721e-csi2rx-shim"; + dmas = <&main_bcdma 0 0x4700 0>; + dma-names = "rx0"; + reg = <0x00 0x30102000 0x00 0x1000>; + power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + cdns_csi2rx0: csi-bridge@30101000 { + compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; + reg = <0x00 0x30101000 0x00 0x1000>; + clocks = <&k3_clks 182 0>, <&k3_clks 182 3>, <&k3_clks 182 0>, + <&k3_clks 182 0>, <&k3_clks 182 4>, <&k3_clks 182 4>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy0>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + csi0_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi0_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi0_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi0_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; + }; + }; + + dphy0: phy@30110000 { + compatible = "cdns,dphy-rx"; + reg = <0x00 0x30110000 0x00 0x1100>; + #phy-cells = <0>; + power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + }; From patchwork Wed Nov 15 09:51:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jai Luthra X-Patchwork-Id: 744139 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E04249465 for ; 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Wed, 15 Nov 2023 03:52:16 -0600 Received: from DLEE113.ent.ti.com (157.170.170.24) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 15 Nov 2023 03:52:16 -0600 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 15 Nov 2023 03:52:16 -0600 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 3AF9qFAY015928; Wed, 15 Nov 2023 03:52:16 -0600 From: Jai Luthra Date: Wed, 15 Nov 2023 15:21:14 +0530 Subject: [PATCH 6/8] arm64: dts: ti: k3-am62x: Add overlays for OV5640 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20231115-csi_dts-v1-6-99fc535b2bde@ti.com> References: <20231115-csi_dts-v1-0-99fc535b2bde@ti.com> In-Reply-To: <20231115-csi_dts-v1-0-99fc535b2bde@ti.com> To: Catalin Marinas , Will Deacon , Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Aradhya Bhatia , Devarsh Thakkar , Vaishnav Achath , Julien Massot , Martyn Welch , Jai Luthra X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; 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a=openpgp; fpr=4DE0D818E5D575E8D45AAFC543DE91F9249A7145 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Three different OV5640 modules are supported using the 15-pin FFC connector on SK-AM62: - Digilent PCam 5C - ALINX AN5641 - TEVI-OV5640-*-RPI The Digilent and ALINX modules supply a 12Mhz XCLK to the sensor, while the TEVI module supplies a 24Mhz XCLK, thus requiring a separate overlay. These overlays can be used on other boards of the SK-AM62* family that have a 15/22-pin FFC connector, so we name the overlays with the prefix k3-am62x-. Signed-off-by: Jai Luthra --- arch/arm64/boot/dts/ti/Makefile | 6 ++ .../arm64/boot/dts/ti/k3-am62x-sk-csi2-ov5640.dtso | 74 ++++++++++++++++++++++ .../boot/dts/ti/k3-am62x-sk-csi2-tevi-ov5640.dtso | 74 ++++++++++++++++++++++ 3 files changed, 154 insertions(+) diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index e49e32414560..a09b16cbefb4 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -13,6 +13,10 @@ k3-am625-beagleplay-csi2-ov5640-dtbs := k3-am625-beagleplay.dtb \ k3-am625-beagleplay-csi2-ov5640.dtbo k3-am625-beagleplay-csi2-tevi-ov5640-dtbs := k3-am625-beagleplay.dtb \ k3-am625-beagleplay-csi2-tevi-ov5640.dtbo +k3-am625-sk-csi2-ov5640-dtbs := k3-am625-sk.dtb \ + k3-am62x-sk-csi2-ov5640.dtbo +k3-am625-sk-csi2-tevi-ov5640-dtbs := k3-am625-sk.dtb \ + k3-am62x-sk-csi2-tevi-ov5640.dtbo k3-am625-sk-hdmi-audio-dtbs := k3-am625-sk.dtb k3-am62x-sk-hdmi-audio.dtbo k3-am62-lp-sk-hdmi-audio-dtbs := k3-am62-lp-sk.dtb k3-am62x-sk-hdmi-audio.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am625-beagleplay.dtb @@ -20,6 +24,8 @@ dtb-$(CONFIG_ARCH_K3) += k3-am625-beagleplay-csi2-ov5640.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-beagleplay-csi2-tevi-ov5640.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-phyboard-lyra-rdk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-sk.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am625-sk-csi2-ov5640.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am625-sk-csi2-tevi-ov5640.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-dahlia.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-dev.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-yavia.dtb diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-csi2-ov5640.dtso b/arch/arm64/boot/dts/ti/k3-am62x-sk-csi2-ov5640.dtso new file mode 100644 index 000000000000..790340673094 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-csi2-ov5640.dtso @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * ALINX AN5641 & Digilent PCam 5C - OV5640 camera module + * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + clk_ov5640_fixed: ov5640-xclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12000000>; + }; +}; + +&main_i2c2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + i2c-switch@71 { + compatible = "nxp,pca9543"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x71>; + + /* CAM port */ + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + ov5640: camera@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + + clocks = <&clk_ov5640_fixed>; + clock-names = "xclk"; + powerdown-gpios = <&exp1 13 GPIO_ACTIVE_LOW>; + + port { + csi2_cam0: endpoint { + remote-endpoint = <&csi2rx0_in_sensor>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; + }; +}; + +&cdns_csi2rx0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2rx0_in_sensor: endpoint { + remote-endpoint = <&csi2_cam0>; + bus-type = <4>; /* CSI2 DPHY. */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-csi2-tevi-ov5640.dtso b/arch/arm64/boot/dts/ti/k3-am62x-sk-csi2-tevi-ov5640.dtso new file mode 100644 index 000000000000..d7772767f49d --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-csi2-tevi-ov5640.dtso @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Technexion TEVI-OV5640-*-RPI - OV5640 camera module + * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + clk_ov5640_fixed: ov5640-xclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; +}; + +&main_i2c2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + i2c-switch@71 { + compatible = "nxp,pca9543"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x71>; + + /* CAM port */ + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + ov5640: camera@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + + clocks = <&clk_ov5640_fixed>; + clock-names = "xclk"; + powerdown-gpios = <&exp1 13 GPIO_ACTIVE_LOW>; + + port { + csi2_cam0: endpoint { + remote-endpoint = <&csi2rx0_in_sensor>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; + }; +}; + +&cdns_csi2rx0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2rx0_in_sensor: endpoint { + remote-endpoint = <&csi2_cam0>; + bus-type = <4>; /* CSI2 DPHY. */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; From patchwork Wed Nov 15 09:51:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jai Luthra X-Patchwork-Id: 744138 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1A8419477 for ; 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Wed, 15 Nov 2023 03:52:19 -0600 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 15 Nov 2023 03:52:19 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 15 Nov 2023 03:52:19 -0600 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 3AF9qI9o009800; Wed, 15 Nov 2023 03:52:19 -0600 From: Jai Luthra Date: Wed, 15 Nov 2023 15:21:16 +0530 Subject: [PATCH 8/8] arm64: dts: ti: k3-am62x: Add overlay for IMX219 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20231115-csi_dts-v1-8-99fc535b2bde@ti.com> References: <20231115-csi_dts-v1-0-99fc535b2bde@ti.com> In-Reply-To: <20231115-csi_dts-v1-0-99fc535b2bde@ti.com> To: Catalin Marinas , Will Deacon , Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Aradhya Bhatia , Devarsh Thakkar , Vaishnav Achath , Julien Massot , Martyn Welch , Jai Luthra X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; 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a=openpgp; fpr=4DE0D818E5D575E8D45AAFC543DE91F9249A7145 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 RPi v2 Camera (IMX219) is an 8MP camera that can be used with SK-AM62A through the 22-pin CSI-RX connector. Same overlay can be used across SK-AM62* boards that have a 15/22-pin FFC connector, so we name it with the k3-am62x- prefix. Signed-off-by: Jai Luthra --- arch/arm64/boot/dts/ti/Makefile | 4 ++ .../arm64/boot/dts/ti/k3-am62x-sk-csi2-imx219.dtso | 76 ++++++++++++++++++++++ 2 files changed, 80 insertions(+) diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index a09b16cbefb4..f89dcbe3c635 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -37,7 +37,10 @@ dtb-$(CONFIG_ARCH_K3) += k3-am625-sk-hdmi-audio.dtb dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk-hdmi-audio.dtb # Boards with AM62Ax SoC +k3-am62a7-sk-csi2-imx219-dtbs := k3-am62a7-sk.dtb \ + k3-am62x-sk-csi2-imx219.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am62a7-sk.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am62a7-sk-csi2-imx219.dtb # Boards with AM62Px SoC dtb-$(CONFIG_ARCH_K3) += k3-am62p5-sk.dtb @@ -96,6 +99,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm.dtb DTC_FLAGS_k3-am625-beagleplay += -@ DTC_FLAGS_k3-am625-sk += -@ DTC_FLAGS_k3-am62-lp-sk += -@ +DTC_FLAGS_k3-am62a7-sk += -@ DTC_FLAGS_k3-am6548-iot2050-advanced-m2 += -@ DTC_FLAGS_k3-j721e-common-proc-board += -@ DTC_FLAGS_k3-j721s2-common-proc-board += -@ diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-csi2-imx219.dtso b/arch/arm64/boot/dts/ti/k3-am62x-sk-csi2-imx219.dtso new file mode 100644 index 000000000000..84d08bfda469 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-csi2-imx219.dtso @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * IMX219 (RPi v2) Camera Module + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + clk_imx219_fixed: imx219-xclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; +}; + +&main_i2c2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + i2c-switch@71 { + compatible = "nxp,pca9543"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x71>; + + /* CAM port */ + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + ov5640: camera@10 { + compatible = "sony,imx219"; + reg = <0x10>; + + clocks = <&clk_imx219_fixed>; + clock-names = "xclk"; + + reset-gpios = <&exp1 13 GPIO_ACTIVE_HIGH>; + + port { + csi2_cam0: endpoint { + remote-endpoint = <&csi2rx0_in_sensor>; + link-frequencies = /bits/ 64 <456000000>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; + }; +}; + +&cdns_csi2rx0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2rx0_in_sensor: endpoint { + remote-endpoint = <&csi2_cam0>; + bus-type = <4>; /* CSI2 DPHY. */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +};