From patchwork Fri Nov 17 11:39:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sibi Sankar X-Patchwork-Id: 745003 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="X8/AeSYB" Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C2180D79; Fri, 17 Nov 2023 03:40:37 -0800 (PST) Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3AHBTaCK019477; Fri, 17 Nov 2023 11:40:16 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=u15VP7wvrbUbzwSp4NHedWJkBZeqVju776PukXoCsfk=; b=X8/AeSYBbJSlu2yhjkQ2yyhA2NvGrv1WCyMOVPYSaCuZo0R3NDGXY/WNqL0ZJJzRRHsR e8FOvknWtUxdNvmGTLIcelMPmKXwIHXLmUGfVGqE7FmNfWJ94Spw2ZEmVXZ+KP9aBWEF w5EESgLt645Km603PRpfRPfWPIsK14LZgVGJme9Vin8qosWlHYlvUh7ZKHb4EoRXDnFm 5m371s2kT2iIbpyfZGZseh4eLLPWVSXb+taP1O0uwAfc4c4gMQV1SBs+r9CkE0WigQq+ qFboCF1TQV3DBQS3tVhzJwZJ2dMbmkKme/2GPwuef7gPeQ5Zo8DP+ndjk5Rb1oJhkBWV zQ== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3ue2na0nnf-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 17 Nov 2023 11:40:15 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3AHBeEFO003314 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 17 Nov 2023 11:40:14 GMT Received: from blr-ubuntu-87.ap.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Fri, 17 Nov 2023 03:40:06 -0800 From: Sibi Sankar To: , , , , , CC: , , , , , , , , , , , , , , , , , , Sibi Sankar Subject: [PATCH V2 2/5] dt-bindings: arm: qcom: Document X1E80100 SoC and boards Date: Fri, 17 Nov 2023 17:09:28 +0530 Message-ID: <20231117113931.26660-3-quic_sibis@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231117113931.26660-1-quic_sibis@quicinc.com> References: <20231117113931.26660-1-quic_sibis@quicinc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: Zb8Tl6TbTfxZbQlhxPxbcyKTH1YyTHZT X-Proofpoint-ORIG-GUID: Zb8Tl6TbTfxZbQlhxPxbcyKTH1YyTHZT X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-17_09,2023-11-16_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 priorityscore=1501 malwarescore=0 mlxscore=0 lowpriorityscore=0 mlxlogscore=999 phishscore=0 suspectscore=0 clxscore=1015 adultscore=0 impostorscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311170087 From: Rajendra Nayak Document the X1E80100 SoC binding and also the boards using it. Also document the new board id qcp (Qualcomm Compute Platform). Signed-off-by: Rajendra Nayak Co-developed-by: Sibi Sankar Signed-off-by: Sibi Sankar --- v2: * Update the part number from sc8380xp to x1e80100. * Fixup ordering in the SoC/board bindings. [Krzysztof] Documentation/devicetree/bindings/arm/qcom.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 88b84035e7b1..6458ed828819 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -87,6 +87,7 @@ description: | sm8350 sm8450 sm8550 + x1e80100 The 'board' element must be one of the following strings: @@ -110,6 +111,7 @@ description: | liquid rdp432-c2 mtp + qcp qrd rb2 ride @@ -1044,6 +1046,12 @@ properties: - qcom,sm8550-qrd - const: qcom,sm8550 + - items: + - enum: + - qcom,x1e80100-crd + - qcom,x1e80100-qcp + - const: qcom,x1e80100 + # Board compatibles go above qcom,msm-id: From patchwork Fri Nov 17 11:39:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sibi Sankar X-Patchwork-Id: 745002 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="EVS3d1nO" Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 51724D55; Fri, 17 Nov 2023 03:40:56 -0800 (PST) Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3AH96wPG012168; Fri, 17 Nov 2023 11:40:40 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=mriFY7XDxu/1AMciRVOz/h02yTrXaVQLAHsegrJsVaw=; b=EVS3d1nOrYNt8KPcqN+T8oCopJHskJRVW1yYpWEvPh1zvtNA0Jyl+5w8CleluVXzsijT cgQBaWPmJq8NWlsuwwv3HNvhurEVGwd8bAN0e7sBsZnztmkqfwM9oOZd9PTRerCJ5EoH IEybQc5OU4SkjEVijETJm+ZzcyP7HGIFMLtTfCGMlCnNQrcIbRdraJczruYqKHTKtWwX 6ycV6/eU1KHh/M5W1Q9E+vlu1gw/Yep2VHnSb9xAWpmdhbnGNRQUNmfvVz+L9nfbkFN5 b/ZBgmba3+NNoUTNP398L1kGODj893EqIEY45udyLH4Us/ybkxwZ9+C3KU/JmGDefsLd qA== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3udkkutpxc-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 17 Nov 2023 11:40:39 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3AHBecFt016614 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 17 Nov 2023 11:40:38 GMT Received: from blr-ubuntu-87.ap.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Fri, 17 Nov 2023 03:40:30 -0800 From: Sibi Sankar To: , , , , , CC: , , , , , , , , , , , , , , , , , , Sibi Sankar Subject: [PATCH V2 5/5] arm64: defconfig: Enable X1E80100 SoC base configs Date: Fri, 17 Nov 2023 17:09:31 +0530 Message-ID: <20231117113931.26660-6-quic_sibis@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231117113931.26660-1-quic_sibis@quicinc.com> References: <20231117113931.26660-1-quic_sibis@quicinc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: RkXU7MzJCFmApnfWnLFJRREqvCm2eznZ X-Proofpoint-ORIG-GUID: RkXU7MzJCFmApnfWnLFJRREqvCm2eznZ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-17_09,2023-11-16_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 malwarescore=0 mlxlogscore=856 clxscore=1015 spamscore=0 impostorscore=0 lowpriorityscore=0 phishscore=0 adultscore=0 bulkscore=0 suspectscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311170087 From: Rajendra Nayak Enable GCC, Pinctrl and Interconnect configs for Qualcomm's X1E80100 SoC which is required to boot X1E80100 QCP/CRD boards to a console shell. The configs are required to be marked as builtin and not modules due to the console driver dependencies. Signed-off-by: Rajendra Nayak Co-developed-by: Sibi Sankar Signed-off-by: Sibi Sankar --- v2: * Update the part number from sc8380xp to x1e80100. * Add additional details to patch 5 commit message. [Konrad/Krzysztof] arch/arm64/configs/defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index b60aa1f89343..013b22dd12c9 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -614,6 +614,7 @@ CONFIG_PINCTRL_SM8450_LPASS_LPI=m CONFIG_PINCTRL_SC8280XP_LPASS_LPI=m CONFIG_PINCTRL_SM8550=y CONFIG_PINCTRL_SM8550_LPASS_LPI=m +CONFIG_PINCTRL_X1E80100=y CONFIG_PINCTRL_LPASS_LPI=m CONFIG_GPIO_AGGREGATOR=m CONFIG_GPIO_ALTERA=m @@ -1266,6 +1267,7 @@ CONFIG_SM_GPUCC_6115=m CONFIG_SM_GPUCC_8150=y CONFIG_SM_GPUCC_8250=y CONFIG_SM_VIDEOCC_8250=y +CONFIG_X1E_GCC_80100=y CONFIG_QCOM_HFPLL=y CONFIG_CLK_GFM_LPASS_SM8250=m CONFIG_CLK_RCAR_USB2_CLOCK_SEL=y @@ -1524,6 +1526,7 @@ CONFIG_INTERCONNECT_QCOM_SM8250=m CONFIG_INTERCONNECT_QCOM_SM8350=m CONFIG_INTERCONNECT_QCOM_SM8450=y CONFIG_INTERCONNECT_QCOM_SM8550=y +CONFIG_INTERCONNECT_QCOM_X1E80100=y CONFIG_COUNTER=m CONFIG_RZ_MTU3_CNT=m CONFIG_HTE=y