From patchwork Sat Nov 18 03:38:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 745136 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D18D7C54E76 for ; Sat, 18 Nov 2023 03:39:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346426AbjKRDjj (ORCPT ); Fri, 17 Nov 2023 22:39:39 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49594 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233029AbjKRDji (ORCPT ); Fri, 17 Nov 2023 22:39:38 -0500 Received: from mail-pj1-x102c.google.com (mail-pj1-x102c.google.com [IPv6:2607:f8b0:4864:20::102c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3B3CAD79 for ; Fri, 17 Nov 2023 19:39:35 -0800 (PST) Received: by mail-pj1-x102c.google.com with SMTP id 98e67ed59e1d1-28398d6c9f3so1206944a91.0 for ; Fri, 17 Nov 2023 19:39:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1700278775; x=1700883575; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rUH3sN/jANNMbAvxiLE+FR6QScUT3piYF3Fp6n0y2EI=; b=JB96zYtXcwC6xFXzykj3V+MKnG4qCBTaBH+IWV8wFYK+dc1sfUyf2W5SSK3oVVny9F VWQlOetAR8ENiS/FdhGNOib5JBWu5MUNpcYAQbDDPJyRDc3oi67JIFGmZQUIw55qWTvj diYd3f6YOpdms8avA8DNQqtu33VHTLeJmXVqLkJTJjRFT5SoDrrGkC1BjqEgOzU7edWy WeRGJopCYaraDpmSs/HI2mBoeOWGD3YS0ZNCbaFueMu8TLlPBwFRtpaYlP7ksJV6zhs2 SmzO1hLRBChDXvwQIzmuo9+USt/t3ZXVXZxEK3FelS2NBUaefga+W9NyG+Fk49A541IZ Bvkg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700278775; x=1700883575; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rUH3sN/jANNMbAvxiLE+FR6QScUT3piYF3Fp6n0y2EI=; b=p2DijITZVss4ZqyyToKv02/ozpKVFSCIrtnGiLIe4v//eUJPA4bdlIGOuczO9ymZSy LRN77947E9H/EWqGAMeu7JLLsQTlSyM2gghhl1a4zRWbULF9DPBQE/hdIvuNWxYfjl3K e69+cQAp1FFNNshO72jLdrKe0BaxedExIOmzTBPi6xjk+fSoyPUD6UfUQkwGGrVhAwZH sa8yXuDy649r33CIAx8x6nPFPi7VD+AuleZJQ9BZDSqIoCZqWdTiKvG65WdItx0rbIUb hzHmQuYeaOap/69u3yLI20LulipYXQ0GcbziK2htTaGIo9VKfSc7L0mnL249Ip7C2JP7 1qRA== X-Gm-Message-State: AOJu0YzF1t905tL3FJ062TGEMMRfAt3Re08TP+0er8qnbgZmSiMPA50k foObMhHnkwagfUfNMqiE3gQ52Q== X-Google-Smtp-Source: AGHT+IFL/vhOEv9SFr5vahVonbYDfe/rMF/KgPJfyv64wzi2WyOjQ+a4xtQ3OlsfO5O9XMpJ2UxSgA== X-Received: by 2002:a17:90b:3b45:b0:280:29cd:4802 with SMTP id ot5-20020a17090b3b4500b0028029cd4802mr1636773pjb.3.1700278774537; Fri, 17 Nov 2023 19:39:34 -0800 (PST) Received: from anup-ubuntu-vm.localdomain ([171.76.80.108]) by smtp.gmail.com with ESMTPSA id cz8-20020a17090ad44800b00280fcbbe774sm2053823pjb.10.2023.11.17.19.39.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Nov 2023 19:39:33 -0800 (PST) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Greg Kroah-Hartman , Jiri Slaby Cc: Conor Dooley , Andrew Jones , linux-riscv@lists.infradead.org, linux-serial@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v4 1/5] RISC-V: Add stubs for sbi_console_putchar/getchar() Date: Sat, 18 Nov 2023 09:08:55 +0530 Message-Id: <20231118033859.726692-2-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231118033859.726692-1-apatel@ventanamicro.com> References: <20231118033859.726692-1-apatel@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org The functions sbi_console_putchar() and sbi_console_getchar() are not defined when CONFIG_RISCV_SBI_V01 is disabled so let us add stub of these functions to avoid "#ifdef" on user side. Signed-off-by: Anup Patel Reviewed-by: Andrew Jones --- arch/riscv/include/asm/sbi.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 0892f4421bc4..66f3933c14f6 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -271,8 +271,13 @@ struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0, unsigned long arg3, unsigned long arg4, unsigned long arg5); +#ifdef CONFIG_RISCV_SBI_V01 void sbi_console_putchar(int ch); int sbi_console_getchar(void); +#else +static inline void sbi_console_putchar(int ch) { } +static inline int sbi_console_getchar(void) { return -ENOENT; } +#endif long sbi_get_mvendorid(void); long sbi_get_marchid(void); long sbi_get_mimpid(void); From patchwork Sat Nov 18 03:38:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 745343 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 87493C47071 for ; Sat, 18 Nov 2023 03:39:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346440AbjKRDjn (ORCPT ); Fri, 17 Nov 2023 22:39:43 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37096 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346433AbjKRDjl (ORCPT ); Fri, 17 Nov 2023 22:39:41 -0500 Received: from mail-pg1-x52a.google.com (mail-pg1-x52a.google.com [IPv6:2607:f8b0:4864:20::52a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9CC85D7A for ; Fri, 17 Nov 2023 19:39:38 -0800 (PST) Received: by mail-pg1-x52a.google.com with SMTP id 41be03b00d2f7-5c184b3bbc4so2022520a12.1 for ; Fri, 17 Nov 2023 19:39:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1700278778; x=1700883578; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lUknxwWYXkt9C2M9pb/Z3CUGPfJIBZQMgmHAhH/xaf8=; b=IHinz0gC9R+tzPymiH/JYDJhkA1wbhQAUTXtmV8pyHSzPlZAcwIeDTK5Fi0FYCDuFY BPf7XkCaBf4DpJeDsDjEEyjA6mxsD7olqrLUy63PqC8wKgBRbjQhJ+U3dC0EXS5Dj/6n OHsJFVQFL1HfPjTBhISf7TH4K/0T1eJX1ZuZn/VUggTkINKUWUuljbxT9/E39owHOTJl 6wcinfSZw9yz+cAX28qCKoGn54+4TpNa0HwpYgtOpgNnKwRWJPRiJA5lF8du9u/jpLeN id4pvq9Ju4CZfzrqJZQ1tBRXiELsF4fxDCVm/h798hhGQo6dFnUJx2fbUclpc/0jQjxv e69w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700278778; x=1700883578; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lUknxwWYXkt9C2M9pb/Z3CUGPfJIBZQMgmHAhH/xaf8=; b=PTyQ0dg9XlLpw3tOFZD3DNxyLECppdMPIaeVBZD0pSUUGQbeCOE2dqQgsvDgiqEICh 1yoYGvuEBpVc96ZMFTitsTxYRNp31/dbww9iWz7St02EwKpuk4Y95aU3QxF3jBpyixOR r07QtrSacPJdet5dd/CSMfHC7//1r1qcum4GYKj8rObNPGw8uSEm0Nocv2G0usptdrf+ byLzIxOrHFkR4VH3ox3yXLShqRScSZFf0itvqekwqdaMZb7HtXTcEU1r6Sy8IUWSKSe3 mZrEocmPpj1nUrzHByaBWTVFDGQ0Qb1mvX9theDxBsw54fMgN9sHMFopihKH2HFORya4 A98Q== X-Gm-Message-State: AOJu0YxomGBp+0NwHPK2ahuQ/Hbv2HyfkYMU4nzIj3+8ECDIrSR1PWov iw1EgceDPq1saaNyoTMK3ymv/A== X-Google-Smtp-Source: AGHT+IGETYioNALUjNhz6JIS+eO7DP/jwO69X1kH6NZN6oXPpq2gEGKYxgt01iCN0WIJkFYPAiCO9A== X-Received: by 2002:a17:90b:1e02:b0:27d:7887:ddc5 with SMTP id pg2-20020a17090b1e0200b0027d7887ddc5mr1729418pjb.32.1700278778017; Fri, 17 Nov 2023 19:39:38 -0800 (PST) Received: from anup-ubuntu-vm.localdomain ([171.76.80.108]) by smtp.gmail.com with ESMTPSA id cz8-20020a17090ad44800b00280fcbbe774sm2053823pjb.10.2023.11.17.19.39.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Nov 2023 19:39:37 -0800 (PST) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Greg Kroah-Hartman , Jiri Slaby Cc: Conor Dooley , Andrew Jones , linux-riscv@lists.infradead.org, linux-serial@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v4 2/5] RISC-V: Add SBI debug console helper routines Date: Sat, 18 Nov 2023 09:08:56 +0530 Message-Id: <20231118033859.726692-3-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231118033859.726692-1-apatel@ventanamicro.com> References: <20231118033859.726692-1-apatel@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org Let us provide SBI debug console helper routines which can be shared by serial/earlycon-riscv-sbi.c and hvc/hvc_riscv_sbi.c. Signed-off-by: Anup Patel Reviewed-by: Andrew Jones --- arch/riscv/include/asm/sbi.h | 5 +++++ arch/riscv/kernel/sbi.c | 43 ++++++++++++++++++++++++++++++++++++ 2 files changed, 48 insertions(+) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 66f3933c14f6..ee7aef5f6233 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -334,6 +334,11 @@ static inline unsigned long sbi_mk_version(unsigned long major, } int sbi_err_map_linux_errno(int err); + +extern bool sbi_debug_console_available; +int sbi_debug_console_write(unsigned int num_bytes, phys_addr_t base_addr); +int sbi_debug_console_read(unsigned int num_bytes, phys_addr_t base_addr); + #else /* CONFIG_RISCV_SBI */ static inline int sbi_remote_fence_i(const struct cpumask *cpu_mask) { return -1; } static inline void sbi_init(void) {} diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c index 5a62ed1da453..73a9c22c3945 100644 --- a/arch/riscv/kernel/sbi.c +++ b/arch/riscv/kernel/sbi.c @@ -571,6 +571,44 @@ long sbi_get_mimpid(void) } EXPORT_SYMBOL_GPL(sbi_get_mimpid); +bool sbi_debug_console_available; + +int sbi_debug_console_write(unsigned int num_bytes, phys_addr_t base_addr) +{ + struct sbiret ret; + + if (!sbi_debug_console_available) + return -EOPNOTSUPP; + + if (IS_ENABLED(CONFIG_32BIT)) + ret = sbi_ecall(SBI_EXT_DBCN, SBI_EXT_DBCN_CONSOLE_WRITE, + num_bytes, lower_32_bits(base_addr), + upper_32_bits(base_addr), 0, 0, 0); + else + ret = sbi_ecall(SBI_EXT_DBCN, SBI_EXT_DBCN_CONSOLE_WRITE, + num_bytes, base_addr, 0, 0, 0, 0); + + return ret.error ? sbi_err_map_linux_errno(ret.error) : ret.value; +} + +int sbi_debug_console_read(unsigned int num_bytes, phys_addr_t base_addr) +{ + struct sbiret ret; + + if (!sbi_debug_console_available) + return -EOPNOTSUPP; + + if (IS_ENABLED(CONFIG_32BIT)) + ret = sbi_ecall(SBI_EXT_DBCN, SBI_EXT_DBCN_CONSOLE_READ, + num_bytes, lower_32_bits(base_addr), + upper_32_bits(base_addr), 0, 0, 0); + else + ret = sbi_ecall(SBI_EXT_DBCN, SBI_EXT_DBCN_CONSOLE_READ, + num_bytes, base_addr, 0, 0, 0, 0); + + return ret.error ? sbi_err_map_linux_errno(ret.error) : ret.value; +} + void __init sbi_init(void) { int ret; @@ -612,6 +650,11 @@ void __init sbi_init(void) sbi_srst_reboot_nb.priority = 192; register_restart_handler(&sbi_srst_reboot_nb); } + if ((sbi_spec_version >= sbi_mk_version(2, 0)) && + (sbi_probe_extension(SBI_EXT_DBCN) > 0)) { + pr_info("SBI DBCN extension detected\n"); + sbi_debug_console_available = true; + } } else { __sbi_set_timer = __sbi_set_timer_v01; __sbi_send_ipi = __sbi_send_ipi_v01; From patchwork Sat Nov 18 03:38:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 745135 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5DE88C47071 for ; Sat, 18 Nov 2023 03:39:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235563AbjKRDjx (ORCPT ); Fri, 17 Nov 2023 22:39:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37222 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346462AbjKRDjt (ORCPT ); Fri, 17 Nov 2023 22:39:49 -0500 Received: from mail-pj1-x102f.google.com (mail-pj1-x102f.google.com [IPv6:2607:f8b0:4864:20::102f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 03877173A for ; Fri, 17 Nov 2023 19:39:42 -0800 (PST) Received: by mail-pj1-x102f.google.com with SMTP id 98e67ed59e1d1-27ddc1b1652so2200889a91.2 for ; Fri, 17 Nov 2023 19:39:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1700278782; x=1700883582; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Ii/r8hzimL/XtavRWrcGkJgKEnLeFuQkfTAUm70Wb2A=; b=L7tk3XsPAJfBJui+7mljsx5jHduoziR5VxXsq4WSWgLyVhrKSG2R6kpLmbGgZLDnNB wqftKeb/NTcH74tLHPrV09IVx1PWAzvf8VDD4/9eQxKPe5DTpT4gqczLHCpkIUIFsxhw dQIKqTmDJK5dWM+uzcmcdnD7gB2FBY3Qu5mYbVoniYAqV0/DYD6syD+9naE1EE7gzz+I ZnYSZy7HvptS1saW9ulyRYdjhZiw58NDKM/oDZxJ3U5/JQqgFWGJOwOuelcuS18t5qoT E92fLTMkKAwAc7mCF8/bsREFCPb0kYIWAzR3b6pkAChA4yr5Msvd9uzTuKf7R9qFPLAt DNcg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700278782; x=1700883582; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Ii/r8hzimL/XtavRWrcGkJgKEnLeFuQkfTAUm70Wb2A=; b=q0Mfo32sT52g7j1APb2a0AtSCp1XtM9+8z5Pnxl5tqiYLSmymHlznhxvFpoM/26OPI LHwT0goF3uL/IaP1LUTCeVum4Vhpxob7TUTJIgx5kuggONsw0xsZ17WJkaNc0lMAaPEy UVybpZvH/Nnuli0Mn/xJo0OFIS+xTBWL1enui/LZiea66cGVX5kq+CpSwZpdARyXRUSs SpndYwAfz2+U/vzurLCSaBWutZtuXA7o9AVTMU+YKhSFs9bmCYGs/1T8nnMET5W/4jY0 9OrY6DqnZcOMFdLvmVQ2yqYrVjdJmIGAWppwntOtb6N3vMMPZf7749jFS8hpvEBQ+qBR aMSw== X-Gm-Message-State: AOJu0Yzgl4wSyLBH9NmaW0UpwNjgEhFACdqJthJbd4pgY4/RhE5mK/Yc lZE8xcTKNZh1urcvr+SGmMGmXQ== X-Google-Smtp-Source: AGHT+IEnlmvKg48AWLtRJlHz9Rg/Q27+8No7s5ojWvtL/WdnvFdbsfi5N3eU9MggG7ZhT0nUoF/4cA== X-Received: by 2002:a17:90b:38cb:b0:27d:1376:3ae1 with SMTP id nn11-20020a17090b38cb00b0027d13763ae1mr1378816pjb.0.1700278781572; Fri, 17 Nov 2023 19:39:41 -0800 (PST) Received: from anup-ubuntu-vm.localdomain ([171.76.80.108]) by smtp.gmail.com with ESMTPSA id cz8-20020a17090ad44800b00280fcbbe774sm2053823pjb.10.2023.11.17.19.39.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Nov 2023 19:39:41 -0800 (PST) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Greg Kroah-Hartman , Jiri Slaby Cc: Conor Dooley , Andrew Jones , linux-riscv@lists.infradead.org, linux-serial@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v4 3/5] tty/serial: Add RISC-V SBI debug console based earlycon Date: Sat, 18 Nov 2023 09:08:57 +0530 Message-Id: <20231118033859.726692-4-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231118033859.726692-1-apatel@ventanamicro.com> References: <20231118033859.726692-1-apatel@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org We extend the existing RISC-V SBI earlycon support to use the new RISC-V SBI debug console extension. Signed-off-by: Anup Patel Reviewed-by: Andrew Jones --- drivers/tty/serial/Kconfig | 2 +- drivers/tty/serial/earlycon-riscv-sbi.c | 24 ++++++++++++++++++++---- 2 files changed, 21 insertions(+), 5 deletions(-) diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig index 732c893c8d16..1f2594b8ab9d 100644 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig @@ -87,7 +87,7 @@ config SERIAL_EARLYCON_SEMIHOST config SERIAL_EARLYCON_RISCV_SBI bool "Early console using RISC-V SBI" - depends on RISCV_SBI_V01 + depends on RISCV_SBI select SERIAL_CORE select SERIAL_CORE_CONSOLE select SERIAL_EARLYCON diff --git a/drivers/tty/serial/earlycon-riscv-sbi.c b/drivers/tty/serial/earlycon-riscv-sbi.c index 27afb0b74ea7..5351e1e31f45 100644 --- a/drivers/tty/serial/earlycon-riscv-sbi.c +++ b/drivers/tty/serial/earlycon-riscv-sbi.c @@ -15,17 +15,33 @@ static void sbi_putc(struct uart_port *port, unsigned char c) sbi_console_putchar(c); } -static void sbi_console_write(struct console *con, - const char *s, unsigned n) +static void sbi_0_1_console_write(struct console *con, + const char *s, unsigned int n) { struct earlycon_device *dev = con->data; uart_console_write(&dev->port, s, n, sbi_putc); } +static void sbi_dbcn_console_write(struct console *con, + const char *s, unsigned int n) +{ + sbi_debug_console_write(n, __pa(s)); +} + static int __init early_sbi_setup(struct earlycon_device *device, const char *opt) { - device->con->write = sbi_console_write; - return 0; + int ret = 0; + + if (sbi_debug_console_available) { + device->con->write = sbi_dbcn_console_write; + } else { + if (IS_ENABLED(CONFIG_RISCV_SBI_V01)) + device->con->write = sbi_0_1_console_write; + else + ret = -ENODEV; + } + + return ret; } EARLYCON_DECLARE(sbi, early_sbi_setup); From patchwork Sat Nov 18 03:38:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 745342 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6CA7CC2BB3F for ; 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Fri, 17 Nov 2023 19:39:45 -0800 (PST) Received: from anup-ubuntu-vm.localdomain ([171.76.80.108]) by smtp.gmail.com with ESMTPSA id cz8-20020a17090ad44800b00280fcbbe774sm2053823pjb.10.2023.11.17.19.39.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Nov 2023 19:39:44 -0800 (PST) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Greg Kroah-Hartman , Jiri Slaby Cc: Conor Dooley , Andrew Jones , linux-riscv@lists.infradead.org, linux-serial@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org, Atish Patra , Anup Patel Subject: [PATCH v4 4/5] tty: Add SBI debug console support to HVC SBI driver Date: Sat, 18 Nov 2023 09:08:58 +0530 Message-Id: <20231118033859.726692-5-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231118033859.726692-1-apatel@ventanamicro.com> References: <20231118033859.726692-1-apatel@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org From: Atish Patra RISC-V SBI specification supports advanced debug console support via SBI DBCN extension. Extend the HVC SBI driver to support it. Signed-off-by: Atish Patra Signed-off-by: Anup Patel --- drivers/tty/hvc/Kconfig | 2 +- drivers/tty/hvc/hvc_riscv_sbi.c | 59 +++++++++++++++++++++++++++++---- 2 files changed, 53 insertions(+), 8 deletions(-) diff --git a/drivers/tty/hvc/Kconfig b/drivers/tty/hvc/Kconfig index 4f9264d005c0..6e05c5c7bca1 100644 --- a/drivers/tty/hvc/Kconfig +++ b/drivers/tty/hvc/Kconfig @@ -108,7 +108,7 @@ config HVC_DCC_SERIALIZE_SMP config HVC_RISCV_SBI bool "RISC-V SBI console support" - depends on RISCV_SBI_V01 + depends on RISCV_SBI select HVC_DRIVER help This enables support for console output via RISC-V SBI calls, which diff --git a/drivers/tty/hvc/hvc_riscv_sbi.c b/drivers/tty/hvc/hvc_riscv_sbi.c index 31f53fa77e4a..697c981221b5 100644 --- a/drivers/tty/hvc/hvc_riscv_sbi.c +++ b/drivers/tty/hvc/hvc_riscv_sbi.c @@ -39,21 +39,66 @@ static int hvc_sbi_tty_get(uint32_t vtermno, char *buf, int count) return i; } -static const struct hv_ops hvc_sbi_ops = { +static const struct hv_ops hvc_sbi_v01_ops = { .get_chars = hvc_sbi_tty_get, .put_chars = hvc_sbi_tty_put, }; -static int __init hvc_sbi_init(void) +static int hvc_sbi_dbcn_tty_put(uint32_t vtermno, const char *buf, int count) { - return PTR_ERR_OR_ZERO(hvc_alloc(0, 0, &hvc_sbi_ops, 16)); + phys_addr_t pa; + + if (is_vmalloc_addr(buf)) { + pa = page_to_phys(vmalloc_to_page(buf)) + offset_in_page(buf); + if (PAGE_SIZE < (offset_in_page(buf) + count)) + count = PAGE_SIZE - offset_in_page(buf); + } else { + pa = __pa(buf); + } + + return sbi_debug_console_write(count, pa); } -device_initcall(hvc_sbi_init); -static int __init hvc_sbi_console_init(void) +static int hvc_sbi_dbcn_tty_get(uint32_t vtermno, char *buf, int count) { - hvc_instantiate(0, 0, &hvc_sbi_ops); + phys_addr_t pa; + + if (is_vmalloc_addr(buf)) { + pa = page_to_phys(vmalloc_to_page(buf)) + offset_in_page(buf); + if (PAGE_SIZE < (offset_in_page(buf) + count)) + count = PAGE_SIZE - offset_in_page(buf); + } else { + pa = __pa(buf); + } + + return sbi_debug_console_read(count, pa); +} + +static const struct hv_ops hvc_sbi_dbcn_ops = { + .put_chars = hvc_sbi_dbcn_tty_put, + .get_chars = hvc_sbi_dbcn_tty_get, +}; + +static int __init hvc_sbi_init(void) +{ + int err; + + if (sbi_debug_console_available) { + err = PTR_ERR_OR_ZERO(hvc_alloc(0, 0, &hvc_sbi_dbcn_ops, 256)); + if (err) + return err; + hvc_instantiate(0, 0, &hvc_sbi_dbcn_ops); + } else { + if (IS_ENABLED(CONFIG_RISCV_SBI_V01)) { + err = PTR_ERR_OR_ZERO(hvc_alloc(0, 0, &hvc_sbi_v01_ops, 256)); + if (err) + return err; + hvc_instantiate(0, 0, &hvc_sbi_v01_ops); + } else { + return -ENODEV; + } + } return 0; } -console_initcall(hvc_sbi_console_init); +device_initcall(hvc_sbi_init); From patchwork Sat Nov 18 03:38:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 745134 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A33FCC47071 for ; Sat, 18 Nov 2023 03:40:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235808AbjKRDkJ (ORCPT ); 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Fri, 17 Nov 2023 19:39:48 -0800 (PST) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Greg Kroah-Hartman , Jiri Slaby Cc: Conor Dooley , Andrew Jones , linux-riscv@lists.infradead.org, linux-serial@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v4 5/5] RISC-V: Enable SBI based earlycon support Date: Sat, 18 Nov 2023 09:08:59 +0530 Message-Id: <20231118033859.726692-6-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231118033859.726692-1-apatel@ventanamicro.com> References: <20231118033859.726692-1-apatel@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org Let us enable SBI based earlycon support in defconfigs for both RV32 and RV64 so that "earlycon=sbi" can be used again. Signed-off-by: Anup Patel Reviewed-by: Andrew Jones --- arch/riscv/configs/defconfig | 1 + arch/riscv/configs/rv32_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index 905881282a7c..eaf34e871e30 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -149,6 +149,7 @@ CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_8250_DW=y CONFIG_SERIAL_OF_PLATFORM=y CONFIG_SERIAL_SH_SCI=y +CONFIG_SERIAL_EARLYCON_RISCV_SBI=y CONFIG_VIRTIO_CONSOLE=y CONFIG_HW_RANDOM=y CONFIG_HW_RANDOM_VIRTIO=y diff --git a/arch/riscv/configs/rv32_defconfig b/arch/riscv/configs/rv32_defconfig index 89b601e253a6..5721af39afd1 100644 --- a/arch/riscv/configs/rv32_defconfig +++ b/arch/riscv/configs/rv32_defconfig @@ -66,6 +66,7 @@ CONFIG_INPUT_MOUSEDEV=y CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SERIAL_EARLYCON_RISCV_SBI=y CONFIG_VIRTIO_CONSOLE=y CONFIG_HW_RANDOM=y CONFIG_HW_RANDOM_VIRTIO=y