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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id n25-20020a05600c181900b00405442edc69sm20450835wmp.14.2023.11.21.02.24.43 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 02:24:43 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 1/8] target/arm: enable FEAT_RNG on Neoverse-N2 Date: Tue, 21 Nov 2023 10:24:34 +0000 Message-Id: <20231121102441.3872902-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231121102441.3872902-1-peter.maydell@linaro.org> References: <20231121102441.3872902-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::134; envelope-from=peter.maydell@linaro.org; helo=mail-lf1-x134.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Marcin Juszkiewicz I noticed that Neoverse-V1 has FEAT_RNG enabled so let enable it also on Neoverse-N2. Signed-off-by: Marcin Juszkiewicz Reviewed-by: Richard Henderson Message-id: 20231114103443.1652308-1-marcin.juszkiewicz@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/tcg/cpu64.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 08db1dbcc74..fcda99e1583 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1018,7 +1018,7 @@ static void aarch64_neoverse_n2_initfn(Object *obj) cpu->isar.id_aa64dfr1 = 0; cpu->id_aa64afr0 = 0; cpu->id_aa64afr1 = 0; - cpu->isar.id_aa64isar0 = 0x0221111110212120ull; /* with Crypto */ + cpu->isar.id_aa64isar0 = 0x1221111110212120ull; /* with Crypto and FEAT_RNG */ cpu->isar.id_aa64isar1 = 0x0011111101211052ull; cpu->isar.id_aa64mmfr0 = 0x0000022200101125ull; cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull; From patchwork Tue Nov 21 10:24:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 745693 Delivered-To: patch@linaro.org Received: by 2002:a5d:5052:0:b0:32d:baff:b0ca with SMTP id h18csp1793348wrt; Tue, 21 Nov 2023 02:26:43 -0800 (PST) X-Google-Smtp-Source: AGHT+IF80ZapA7dWGtmxnXZvRdAop3p9x1JFNurfoc2ebFwLgcmSsvHrOzwyrq3XiJZoqItXMMEw X-Received: by 2002:a25:2083:0:b0:da0:95c0:d157 with SMTP id g125-20020a252083000000b00da095c0d157mr6722805ybg.51.1700562403589; Tue, 21 Nov 2023 02:26:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700562403; cv=none; d=google.com; s=arc-20160816; b=TDClAQFSzvUR03hDVkOy+5KlpnajJDXojXb6Sded6C8rfJxAYRdEqsE8jr5PYYNgjY p5qKjgn22S6+KkVRxX7y3+PKeGoeccN6iGZGGpp96SPMMU4cE7QageOluQgjL5IfD4Kh hCzcImp0AXJKtfbT675/GsoiToL6WDKQkqKZsyh5In3CIAnpg/TSeBiMCCDXFXObMb6y Hqz6j2jHNJeiMvff365r2O5Q5DhGvX0dQMBgtmX4sG1A6bGeDoIHg7uf0qPSXcbwTORv q5NZu4yrpZP90NVK2K2JeSXpBMZOvCjWoXA/kUSGCjoWnIwb+WfyWA7hNyw6aqkIkfWg qygA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=aWov8zdztLe0Jlc/lkRlL/DlbtZzkn3RPI3Q2gppqQQ=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=fDggR0DUc0c5dcFUlKStPCR0vLjTLpj9qPjjU776G5pAZ0JgOjJMrELXfOXH0BJRVw iObqeyoTkNjFVuQvSJJ5X6eLgzd69pqKTGcAKPLN8dR52k4bISyY+k9wEnmJgsFCkJ9u bnOV0mR9wCBkRY0qxfi/auNGeiTe+tWVBnZD50S4KU3ZA8EQmnqGL6ZJ88SwfV0IcOqG A74qVLYdS5OJnPweByWGJU1l32V8VNbryTn80o/iKGvbwlEmTdnE+t3jnc+pyhIRutBa 4TGgVIOJedOwe0E0qTOHWIT1dR0Z2hK+zF5xEQIU+jcuOuQ7mK3A1G+GB3yd+91r0D8I NUxQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vZysZ6Hr; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id n25-20020a05600c181900b00405442edc69sm20450835wmp.14.2023.11.21.02.24.44 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 02:24:44 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 2/8] hw/intc/arm_gicv3: ICC_PMR_EL1 high bits should be RAZ Date: Tue, 21 Nov 2023 10:24:35 +0000 Message-Id: <20231121102441.3872902-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231121102441.3872902-1-peter.maydell@linaro.org> References: <20231121102441.3872902-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::136; envelope-from=peter.maydell@linaro.org; helo=mail-lf1-x136.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Ben Dooks The ICC_PMR_ELx and ICV_PMR_ELx bit masks returned from ic{c,v}_fullprio_mask should technically also remove any bit above 7 as these are marked reserved (read 0) and should therefore should not be written as anything other than 0. This was noted during a run of a proprietary test system and discused on the mailing list [1] and initially thought not to be an issue due to RES0 being technically allowed to be written to and read back as long as the implementation does not use the RES0 bits. It is very possible that the values are used in comparison without masking, as pointed out by Peter in [2], if (cs->hppi.prio >= cs->icc_pmr_el1) may well do the wrong thing. Masking these values in ic{c,v}_fullprio_mask() should fix this and prevent any future problems with playing with the values. [1]: https://lists.nongnu.org/archive/html/qemu-arm/2023-11/msg00607.html [2]: https://lists.nongnu.org/archive/html/qemu-arm/2023-11/msg00737.html Signed-off-by: Ben Dooks Message-id: 20231116172818.792364-1-ben.dooks@codethink.co.uk Suggested-by: Peter Maydell Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/intc/arm_gicv3_cpuif.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index d07b13eb270..ab1a00508e6 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -146,7 +146,7 @@ static uint32_t icv_fullprio_mask(GICv3CPUState *cs) * with the group priority, whose mask depends on the value of VBPR * for the interrupt group.) */ - return ~0U << (8 - cs->vpribits); + return (~0U << (8 - cs->vpribits)) & 0xff; } static int ich_highest_active_virt_prio(GICv3CPUState *cs) @@ -803,7 +803,7 @@ static uint32_t icc_fullprio_mask(GICv3CPUState *cs) * with the group priority, whose mask depends on the value of BPR * for the interrupt group.) */ - return ~0U << (8 - cs->pribits); + return (~0U << (8 - cs->pribits)) & 0xff; } static inline int icc_min_bpr(GICv3CPUState *cs) From patchwork Tue Nov 21 10:24:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 745692 Delivered-To: patch@linaro.org Received: by 2002:a5d:5052:0:b0:32d:baff:b0ca with SMTP id h18csp1793323wrt; Tue, 21 Nov 2023 02:26:38 -0800 (PST) X-Google-Smtp-Source: AGHT+IEnsJr2tz9H9oX421tdEafuOg+fCOpkgJVN0TOPkrP3FuwCZ+is1DHJUJ840feKvUYJq5WI X-Received: by 2002:a05:620a:894:b0:774:1e10:6822 with SMTP id b20-20020a05620a089400b007741e106822mr10482551qka.77.1700562398249; Tue, 21 Nov 2023 02:26:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700562398; cv=none; d=google.com; s=arc-20160816; b=IWclkMW0N/oo6MQqhY1cX7i839lE/se2rwJm+cGD9McPY8zig5/H3VgCDW/IUJaxBO suGUCPRQ8zPvR3qH6WTNjKXx0NzaO3tQDzK5oniYPV9C6bC2ca6IJ6bIJPw6USi3v/6A mu02rlv3SpGepiftkd4NbEUt3wiJwJ9KziZktbCfZk3K6TPPSwbmerpIqZF+Kt79oUQW UK6G/tmiIWYkbENg+sPSSGO/ctyNuhyOQMbQL0ldk9aN59BuIXzxMEJLZhiGgkFPnRy5 ej0dcG6OpujMZRPDy7PDtmpszt+oPEYLsC3gK5fY/P424TCQJjOlxej+YykWQxia9bAC ZsTw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=A5nZHFs8XfXA4eqiIcDiwItWSy8HHd+ABkoJYVnAfcE=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=hMLCJWaqa6A/B6UcSmk7JHR/+QP5fYJqIcGd6nN87dlIM1a8z4S1+Y7bNtS7PjA11m KNXfFLSUdyVjW8GcccNXHf93yWGO7fbdFJbdoyQ2qSnYBFf1IYyOhah4LbXfAWjen5yX RALIcD3fih1Bqthc0my0ZNiEZtc1XTeaSARQ0UzHjUralld9WMdqYeaxmWzcC/7o8b0n bCtTeUlYSq9/5Fw/3VHJanAF3X9JqmLYpyOxUb2ghl+JNEwseGzFlTDxb8kxwuB4pFbS JGkmxmc5croHhjgHXIApgdHpyQfYc6Oh/AaLNhIIFF1Jmc/ffF+wFoVr9eAF7yO5Hlcx Uqcw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZiEA5xMW; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id n25-20020a05600c181900b00405442edc69sm20450835wmp.14.2023.11.21.02.24.44 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 02:24:44 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 3/8] target/arm: Fix SME FMOPA (16-bit), BFMOPA Date: Tue, 21 Nov 2023 10:24:36 +0000 Message-Id: <20231121102441.3872902-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231121102441.3872902-1-peter.maydell@linaro.org> References: <20231121102441.3872902-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::231; envelope-from=peter.maydell@linaro.org; helo=mail-lj1-x231.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson Perform the loop increment unconditionally, not nested within the predication. Cc: qemu-stable@nongnu.org Fixes: 3916841ac75 ("target/arm: Implement FMOPA, FMOPS (widening)") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1985 Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-id: 20231117193135.1180657-1-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/sme_helper.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/target/arm/tcg/sme_helper.c b/target/arm/tcg/sme_helper.c index 296826ffe6a..1ee2690ceb5 100644 --- a/target/arm/tcg/sme_helper.c +++ b/target/arm/tcg/sme_helper.c @@ -1037,10 +1037,9 @@ void HELPER(sme_fmopa_h)(void *vza, void *vzn, void *vzm, void *vpn, m = f16mop_adj_pair(m, pcol, 0); *a = f16_dotadd(*a, n, m, &fpst_std, &fpst_odd); - - col += 4; - pcol >>= 4; } + col += 4; + pcol >>= 4; } while (col & 15); } row += 4; @@ -1073,10 +1072,9 @@ void HELPER(sme_bfmopa)(void *vza, void *vzn, void *vzm, void *vpn, m = f16mop_adj_pair(m, pcol, 0); *a = bfdotadd(*a, n, m); - - col += 4; - pcol >>= 4; } + col += 4; + pcol >>= 4; } while (col & 15); } row += 4; From patchwork Tue Nov 21 10:24:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 745690 Delivered-To: patch@linaro.org Received: by 2002:a5d:5052:0:b0:32d:baff:b0ca with SMTP id h18csp1793214wrt; Tue, 21 Nov 2023 02:26:18 -0800 (PST) X-Google-Smtp-Source: AGHT+IGnwiYxpR12yS62IIZkzo+5BBZBjy5Z6JsuFxOvOY7n8ebNHkXF9Ua1C7mxaEubJMXxVsir X-Received: by 2002:a05:622a:130d:b0:418:1059:dfb9 with SMTP id v13-20020a05622a130d00b004181059dfb9mr13199862qtk.1.1700562378002; Tue, 21 Nov 2023 02:26:18 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700562377; cv=none; d=google.com; s=arc-20160816; b=HX/Cv2Yf80p/zo9ReA31l19ZEN0qxeTKGWt7mw4KLIqHraAF70TMRqDpydTDhQRc3I wHw3k3hUVCGs9NtVhWN3YZQ035WrVhNfpAUFQ99jJe2kr2OLkfZmJt2oZx9mxkFdPq+h ViWm1v6f9cbosO3bZcpfQXArtfg2j3hSVBANEDwmedY29PyOJbaiYbYC4LtsJ1+EwLk/ Q2AMsGk+LTJmLsc05D8lCckWeloAVoYq6jwXKPTvE0vA2a0w+jN5TzFZcc0traEP3U9k 9eH9iBeQywOHJMSQsfx/tsO9pxVB+XcV3cQlwoXCY7VNDjiuraAZCN/3F+sRBkhuwpHT X4RQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=DFKuHjN+ndUlQFTqRBZjDt9iBODNYrCuBl0JQxBqPME=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=tqD9jyZ5W4rW5eQGfhLVUKkIZPiO02thIBNd6u0h6BL0wR3zKMpTFopGr6BmEUCu/9 Fikr6j3qUlHTU0KJLcXkrz+lXz1EOsaRW2BU1x8VuJl+g+pb/sMTOm4ccFjQhwJGRO1+ shzktjP4sLnK9dl38vL46vtxMkdn+G6onwt8R3nDBirMCWVxgp434GPyzyMk+BtU9znP QUxEGFow8tXhcd+JC1bvurpU/tIN6hDEOZMRBIG9YkpYrpIavgsJ26yIFj+E0gD7miHe XhVSmEx8rucq+d52BNCDH1tlldqiJRbMMsyItNjGlvQZPyUyvmDs8Dkmh/tVNXtz3fXi 0mzA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TPXj3r9u; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id n25-20020a05600c181900b00405442edc69sm20450835wmp.14.2023.11.21.02.24.45 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 02:24:45 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 4/8] hw/core/machine: Constify MachineClass::valid_cpu_types[] Date: Tue, 21 Nov 2023 10:24:37 +0000 Message-Id: <20231121102441.3872902-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231121102441.3872902-1-peter.maydell@linaro.org> References: <20231121102441.3872902-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Gavin Shan Constify MachineClass::valid_cpu_types[i], as suggested by Richard Henderson. Suggested-by: Richard Henderson Signed-off-by: Gavin Shan Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Message-id: 20231117071704.35040-2-philmd@linaro.org [PMD: Constify HPPA machines, restrict valid_cpu_types to machine_class_init() handlers] Signed-off-by: Philippe Mathieu-Daudé Signed-off-by: Peter Maydell --- include/hw/boards.h | 2 +- hw/hppa/machine.c | 22 ++++++++++------------ hw/m68k/q800.c | 11 +++++------ 3 files changed, 16 insertions(+), 19 deletions(-) diff --git a/include/hw/boards.h b/include/hw/boards.h index a7359992980..da85f86efb9 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -273,7 +273,7 @@ struct MachineClass { bool has_hotpluggable_cpus; bool ignore_memory_transaction_failures; int numa_mem_align_shift; - const char **valid_cpu_types; + const char * const *valid_cpu_types; strList *allowed_dynamic_sysbus_devices; bool auto_enable_numa_with_memhp; bool auto_enable_numa_with_memdev; diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c index 9d08f39490e..c8da7c18d53 100644 --- a/hw/hppa/machine.c +++ b/hw/hppa/machine.c @@ -672,19 +672,18 @@ static void hppa_nmi(NMIState *n, int cpu_index, Error **errp) } } -static const char *HP_B160L_machine_valid_cpu_types[] = { - TYPE_HPPA_CPU, - NULL -}; - static void HP_B160L_machine_init_class_init(ObjectClass *oc, void *data) { + static const char * const valid_cpu_types[] = { + TYPE_HPPA_CPU, + NULL + }; MachineClass *mc = MACHINE_CLASS(oc); NMIClass *nc = NMI_CLASS(oc); mc->desc = "HP B160L workstation"; mc->default_cpu_type = TYPE_HPPA_CPU; - mc->valid_cpu_types = HP_B160L_machine_valid_cpu_types; + mc->valid_cpu_types = valid_cpu_types; mc->init = machine_HP_B160L_init; mc->reset = hppa_machine_reset; mc->block_default_type = IF_SCSI; @@ -709,19 +708,18 @@ static const TypeInfo HP_B160L_machine_init_typeinfo = { }, }; -static const char *HP_C3700_machine_valid_cpu_types[] = { - TYPE_HPPA64_CPU, - NULL -}; - static void HP_C3700_machine_init_class_init(ObjectClass *oc, void *data) { + static const char * const valid_cpu_types[] = { + TYPE_HPPA64_CPU, + NULL + }; MachineClass *mc = MACHINE_CLASS(oc); NMIClass *nc = NMI_CLASS(oc); mc->desc = "HP C3700 workstation"; mc->default_cpu_type = TYPE_HPPA64_CPU; - mc->valid_cpu_types = HP_C3700_machine_valid_cpu_types; + mc->valid_cpu_types = valid_cpu_types; mc->init = machine_HP_C3700_init; mc->reset = hppa_machine_reset; mc->block_default_type = IF_SCSI; diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c index 1d7cd5ff1c3..83d1571d02f 100644 --- a/hw/m68k/q800.c +++ b/hw/m68k/q800.c @@ -726,19 +726,18 @@ static GlobalProperty hw_compat_q800[] = { }; static const size_t hw_compat_q800_len = G_N_ELEMENTS(hw_compat_q800); -static const char *q800_machine_valid_cpu_types[] = { - M68K_CPU_TYPE_NAME("m68040"), - NULL -}; - static void q800_machine_class_init(ObjectClass *oc, void *data) { + static const char * const valid_cpu_types[] = { + M68K_CPU_TYPE_NAME("m68040"), + NULL + }; MachineClass *mc = MACHINE_CLASS(oc); mc->desc = "Macintosh Quadra 800"; mc->init = q800_machine_init; mc->default_cpu_type = M68K_CPU_TYPE_NAME("m68040"); - mc->valid_cpu_types = q800_machine_valid_cpu_types; + mc->valid_cpu_types = valid_cpu_types; mc->max_cpus = 1; mc->block_default_type = IF_SCSI; mc->default_ram_id = "m68k_mac.ram"; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id n25-20020a05600c181900b00405442edc69sm20450835wmp.14.2023.11.21.02.24.45 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 02:24:45 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 5/8] hw/arm/stm32f405: Report error when incorrect CPU is used Date: Tue, 21 Nov 2023 10:24:38 +0000 Message-Id: <20231121102441.3872902-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231121102441.3872902-1-peter.maydell@linaro.org> References: <20231121102441.3872902-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Both 'netduinoplus2' and 'olimex-stm32-h405' machines ignore the CPU type requested by the command line. This might confuse users, since the following will create a machine with a Cortex-M4 CPU: $ qemu-system-aarch64 -M netduinoplus2 -cpu cortex-r5f Set the MachineClass::valid_cpu_types field (introduced in commit c9cf636d48 "machine: Add a valid_cpu_types property"). Remove the now unused MachineClass::default_cpu_type field. We now get: $ qemu-system-aarch64 -M netduinoplus2 -cpu cortex-r5f qemu-system-aarch64: Invalid CPU type: cortex-r5f-arm-cpu The valid types are: cortex-m4-arm-cpu Since the SoC family can only use Cortex-M4 CPUs, hard-code the CPU type name at the SoC level, removing the QOM property entirely. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Gavin Shan Message-id: 20231117071704.35040-3-philmd@linaro.org Signed-off-by: Peter Maydell --- include/hw/arm/stm32f405_soc.h | 4 ---- hw/arm/netduinoplus2.c | 7 ++++++- hw/arm/olimex-stm32-h405.c | 8 ++++++-- hw/arm/stm32f405_soc.c | 8 +------- 4 files changed, 13 insertions(+), 14 deletions(-) diff --git a/include/hw/arm/stm32f405_soc.h b/include/hw/arm/stm32f405_soc.h index c968ce3ab23..d15c03c4b5d 100644 --- a/include/hw/arm/stm32f405_soc.h +++ b/include/hw/arm/stm32f405_soc.h @@ -51,11 +51,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(STM32F405State, STM32F405_SOC) #define CCM_SIZE (64 * 1024) struct STM32F405State { - /*< private >*/ SysBusDevice parent_obj; - /*< public >*/ - - char *cpu_type; ARMv7MState armv7m; diff --git a/hw/arm/netduinoplus2.c b/hw/arm/netduinoplus2.c index 515c0816054..2e589849478 100644 --- a/hw/arm/netduinoplus2.c +++ b/hw/arm/netduinoplus2.c @@ -44,7 +44,6 @@ static void netduinoplus2_init(MachineState *machine) clock_set_hz(sysclk, SYSCLK_FRQ); dev = qdev_new(TYPE_STM32F405_SOC); - qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4")); qdev_connect_clock_in(dev, "sysclk", sysclk); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); @@ -55,8 +54,14 @@ static void netduinoplus2_init(MachineState *machine) static void netduinoplus2_machine_init(MachineClass *mc) { + static const char * const valid_cpu_types[] = { + ARM_CPU_TYPE_NAME("cortex-m4"), + NULL + }; + mc->desc = "Netduino Plus 2 Machine (Cortex-M4)"; mc->init = netduinoplus2_init; + mc->valid_cpu_types = valid_cpu_types; } DEFINE_MACHINE("netduinoplus2", netduinoplus2_machine_init) diff --git a/hw/arm/olimex-stm32-h405.c b/hw/arm/olimex-stm32-h405.c index 3aa61c91b75..d793de7c97f 100644 --- a/hw/arm/olimex-stm32-h405.c +++ b/hw/arm/olimex-stm32-h405.c @@ -47,7 +47,6 @@ static void olimex_stm32_h405_init(MachineState *machine) clock_set_hz(sysclk, SYSCLK_FRQ); dev = qdev_new(TYPE_STM32F405_SOC); - qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4")); qdev_connect_clock_in(dev, "sysclk", sysclk); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); @@ -58,9 +57,14 @@ static void olimex_stm32_h405_init(MachineState *machine) static void olimex_stm32_h405_machine_init(MachineClass *mc) { + static const char * const valid_cpu_types[] = { + ARM_CPU_TYPE_NAME("cortex-m4"), + NULL + }; + mc->desc = "Olimex STM32-H405 (Cortex-M4)"; mc->init = olimex_stm32_h405_init; - mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m4"); + mc->valid_cpu_types = valid_cpu_types; /* SRAM pre-allocated as part of the SoC instantiation */ mc->default_ram_size = 0; diff --git a/hw/arm/stm32f405_soc.c b/hw/arm/stm32f405_soc.c index cef23d7ee41..a65bbe298d2 100644 --- a/hw/arm/stm32f405_soc.c +++ b/hw/arm/stm32f405_soc.c @@ -149,7 +149,7 @@ static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp) armv7m = DEVICE(&s->armv7m); qdev_prop_set_uint32(armv7m, "num-irq", 96); - qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type); + qdev_prop_set_string(armv7m, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4")); qdev_prop_set_bit(armv7m, "enable-bitband", true); qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk); qdev_connect_clock_in(armv7m, "refclk", s->refclk); @@ -287,17 +287,11 @@ static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp) create_unimplemented_device("RNG", 0x50060800, 0x400); } -static Property stm32f405_soc_properties[] = { - DEFINE_PROP_STRING("cpu-type", STM32F405State, cpu_type), - DEFINE_PROP_END_OF_LIST(), -}; - static void stm32f405_soc_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); dc->realize = stm32f405_soc_realize; - device_class_set_props(dc, stm32f405_soc_properties); /* No vmstate or reset required: device has no internal state */ } From patchwork Tue Nov 21 10:24:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 745689 Delivered-To: patch@linaro.org Received: by 2002:a5d:5052:0:b0:32d:baff:b0ca with SMTP id h18csp1793166wrt; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id n25-20020a05600c181900b00405442edc69sm20450835wmp.14.2023.11.21.02.24.45 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 02:24:45 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 6/8] hw/arm/stm32f205: Report error when incorrect CPU is used Date: Tue, 21 Nov 2023 10:24:39 +0000 Message-Id: <20231121102441.3872902-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231121102441.3872902-1-peter.maydell@linaro.org> References: <20231121102441.3872902-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé The 'netduino2' machine ignores the CPU type requested by the command line. This might confuse users, since the following will create a machine with a Cortex-M3 CPU: $ qemu-system-arm -M netduino2 -cpu cortex-a9 Set the MachineClass::valid_cpu_types field (introduced in commit c9cf636d48 "machine: Add a valid_cpu_types property"). Remove the now unused MachineClass::default_cpu_type field. We now get: $ qemu-system-arm -M netduino2 -cpu cortex-a9 qemu-system-arm: Invalid CPU type: cortex-a9-arm-cpu The valid types are: cortex-m3-arm-cpu Since the SoC family can only use Cortex-M3 CPUs, hard-code the CPU type name at the SoC level, removing the QOM property entirely. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Gavin Shan Message-id: 20231117071704.35040-4-philmd@linaro.org Signed-off-by: Peter Maydell --- include/hw/arm/stm32f205_soc.h | 4 ---- hw/arm/netduino2.c | 7 ++++++- hw/arm/stm32f205_soc.c | 9 ++------- 3 files changed, 8 insertions(+), 12 deletions(-) diff --git a/include/hw/arm/stm32f205_soc.h b/include/hw/arm/stm32f205_soc.h index 5a4f7762642..4f4c8bbebc1 100644 --- a/include/hw/arm/stm32f205_soc.h +++ b/include/hw/arm/stm32f205_soc.h @@ -49,11 +49,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(STM32F205State, STM32F205_SOC) #define SRAM_SIZE (128 * 1024) struct STM32F205State { - /*< private >*/ SysBusDevice parent_obj; - /*< public >*/ - - char *cpu_type; ARMv7MState armv7m; diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c index 83753d53a3f..501f63a77f9 100644 --- a/hw/arm/netduino2.c +++ b/hw/arm/netduino2.c @@ -44,7 +44,6 @@ static void netduino2_init(MachineState *machine) clock_set_hz(sysclk, SYSCLK_FRQ); dev = qdev_new(TYPE_STM32F205_SOC); - qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3")); qdev_connect_clock_in(dev, "sysclk", sysclk); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); @@ -54,8 +53,14 @@ static void netduino2_init(MachineState *machine) static void netduino2_machine_init(MachineClass *mc) { + static const char * const valid_cpu_types[] = { + ARM_CPU_TYPE_NAME("cortex-m3"), + NULL + }; + mc->desc = "Netduino 2 Machine (Cortex-M3)"; mc->init = netduino2_init; + mc->valid_cpu_types = valid_cpu_types; mc->ignore_memory_transaction_failures = true; } diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c index c6b75a381d9..1a548646f6e 100644 --- a/hw/arm/stm32f205_soc.c +++ b/hw/arm/stm32f205_soc.c @@ -127,7 +127,7 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp) armv7m = DEVICE(&s->armv7m); qdev_prop_set_uint32(armv7m, "num-irq", 96); - qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type); + qdev_prop_set_string(armv7m, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3")); qdev_prop_set_bit(armv7m, "enable-bitband", true); qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk); qdev_connect_clock_in(armv7m, "refclk", s->refclk); @@ -201,17 +201,12 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp) } } -static Property stm32f205_soc_properties[] = { - DEFINE_PROP_STRING("cpu-type", STM32F205State, cpu_type), - DEFINE_PROP_END_OF_LIST(), -}; - static void stm32f205_soc_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); dc->realize = stm32f205_soc_realize; - device_class_set_props(dc, stm32f205_soc_properties); + /* No vmstate or reset required: device has no internal state */ } static const TypeInfo stm32f205_soc_info = { From patchwork Tue Nov 21 10:24:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 745688 Delivered-To: patch@linaro.org Received: by 2002:a5d:5052:0:b0:32d:baff:b0ca with SMTP id h18csp1793164wrt; Tue, 21 Nov 2023 02:26:11 -0800 (PST) X-Google-Smtp-Source: AGHT+IFuYEll9rQz29KQUBKWmW92EL+sLBRxfAEoxLR+3ewTl+4U6t9ihtxpG9MiS4uapWgzgLNp X-Received: by 2002:a05:620a:17a4:b0:775:92bb:eb25 with SMTP id ay36-20020a05620a17a400b0077592bbeb25mr10452155qkb.55.1700562371351; Tue, 21 Nov 2023 02:26:11 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700562371; cv=none; d=google.com; s=arc-20160816; b=sqyS35RbLoh8+fNxBVPF2HrZ2b3h+Yc+69ce0WhnNSRMkPyTzH/klJijtaZKM6AOer izhwsWvSRP7H6D7EZ8ZLAEBNIOBABNmSutx4VGkxBrggB/BDZaxZhBqL5IF2f0lFFkOU G1MEo1oKOw5a99OSsT6z5eE9Sex2UErYMOxG9BQufqpJbScndpssP6Q2yjpEwf2fxu8N TOYevVP23oNcDlm4+PKVmWJZNQv1S52AegoTs26tqYvNDyf+qGWI/vwXvr/JZMaqTKPB Wg2u5AEmES5s5tH06nk5UvAWO9sD8/1cZyGTmEGEO707TP/Q+UgB1oS7V/eowWde66wu O6Yw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=fwjCpEg7CxgIC61BgitQvtOo2gBc/4p1x2tjHLKtQjw=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=czzdmdoXmg/oHOdvmpjkjFMb8hhN6kPZY+97jor7V4HBMAXfJA0Vikw3Jsnwdd1Rkh fE3SLOQG5sj2VB/aFyA5HHbRfEbgztl1RtOPx8iLaCNoDplDEojxmC5DxKkWFUSNoFSP M0yrZZIh52nyjgzcZURU4mDHsNya51Q0qUdZtz5R7aGeIp9Csgm8ySwYMP3z57frnm6c 8JpmoAem7H+Q5GYMCqjsmg1xjJnaQfGgftRBq6wGPAspPo3yM/XdAOBppX5gvYmQnsUp VlBjmQ4b0xdvrYnmXcDDoY9xFHGg96cm0NlACLdsJAIK0DGvwPL9mRbAcNvWTxNrlzEJ dgrw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CmYlSFp+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id n25-20020a05600c181900b00405442edc69sm20450835wmp.14.2023.11.21.02.24.46 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 02:24:46 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 7/8] hw/arm/stm32f100: Report error when incorrect CPU is used Date: Tue, 21 Nov 2023 10:24:40 +0000 Message-Id: <20231121102441.3872902-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231121102441.3872902-1-peter.maydell@linaro.org> References: <20231121102441.3872902-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé The 'stm32vldiscovery' machine ignores the CPU type requested by the command line. This might confuse users, since the following will create a machine with a Cortex-M3 CPU: $ qemu-system-aarch64 -M stm32vldiscovery -cpu neoverse-n1 Set the MachineClass::valid_cpu_types field (introduced in commit c9cf636d48 "machine: Add a valid_cpu_types property"). Remove the now unused MachineClass::default_cpu_type field. We now get: $ qemu-system-aarch64 -M stm32vldiscovery -cpu neoverse-n1 qemu-system-aarch64: Invalid CPU type: neoverse-n1-arm-cpu The valid types are: cortex-m3-arm-cpu Since the SoC family can only use Cortex-M3 CPUs, hard-code the CPU type name at the SoC level, removing the QOM property entirely. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Gavin Shan Message-id: 20231117071704.35040-5-philmd@linaro.org Signed-off-by: Peter Maydell --- include/hw/arm/stm32f100_soc.h | 4 ---- hw/arm/stm32f100_soc.c | 9 ++------- hw/arm/stm32vldiscovery.c | 7 ++++++- 3 files changed, 8 insertions(+), 12 deletions(-) diff --git a/include/hw/arm/stm32f100_soc.h b/include/hw/arm/stm32f100_soc.h index 40cd415b284..a74d7b369c1 100644 --- a/include/hw/arm/stm32f100_soc.h +++ b/include/hw/arm/stm32f100_soc.h @@ -43,12 +43,8 @@ OBJECT_DECLARE_SIMPLE_TYPE(STM32F100State, STM32F100_SOC) #define SRAM_SIZE (8 * 1024) struct STM32F100State { - /*< private >*/ SysBusDevice parent_obj; - /*< public >*/ - char *cpu_type; - ARMv7MState armv7m; STM32F2XXUsartState usart[STM_NUM_USARTS]; diff --git a/hw/arm/stm32f100_soc.c b/hw/arm/stm32f100_soc.c index f7b344ba9fb..b90d440d7aa 100644 --- a/hw/arm/stm32f100_soc.c +++ b/hw/arm/stm32f100_soc.c @@ -115,7 +115,7 @@ static void stm32f100_soc_realize(DeviceState *dev_soc, Error **errp) /* Init ARMv7m */ armv7m = DEVICE(&s->armv7m); qdev_prop_set_uint32(armv7m, "num-irq", 61); - qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type); + qdev_prop_set_string(armv7m, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3")); qdev_prop_set_bit(armv7m, "enable-bitband", true); qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk); qdev_connect_clock_in(armv7m, "refclk", s->refclk); @@ -180,17 +180,12 @@ static void stm32f100_soc_realize(DeviceState *dev_soc, Error **errp) create_unimplemented_device("CRC", 0x40023000, 0x400); } -static Property stm32f100_soc_properties[] = { - DEFINE_PROP_STRING("cpu-type", STM32F100State, cpu_type), - DEFINE_PROP_END_OF_LIST(), -}; - static void stm32f100_soc_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); dc->realize = stm32f100_soc_realize; - device_class_set_props(dc, stm32f100_soc_properties); + /* No vmstate or reset required: device has no internal state */ } static const TypeInfo stm32f100_soc_info = { diff --git a/hw/arm/stm32vldiscovery.c b/hw/arm/stm32vldiscovery.c index 67675e952fc..190db6118b9 100644 --- a/hw/arm/stm32vldiscovery.c +++ b/hw/arm/stm32vldiscovery.c @@ -47,7 +47,6 @@ static void stm32vldiscovery_init(MachineState *machine) clock_set_hz(sysclk, SYSCLK_FRQ); dev = qdev_new(TYPE_STM32F100_SOC); - qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3")); qdev_connect_clock_in(dev, "sysclk", sysclk); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); @@ -58,8 +57,14 @@ static void stm32vldiscovery_init(MachineState *machine) static void stm32vldiscovery_machine_init(MachineClass *mc) { + static const char * const valid_cpu_types[] = { + ARM_CPU_TYPE_NAME("cortex-m3"), + NULL + }; + mc->desc = "ST STM32VLDISCOVERY (Cortex-M3)"; mc->init = stm32vldiscovery_init; + mc->valid_cpu_types = valid_cpu_types; } DEFINE_MACHINE("stm32vldiscovery", stm32vldiscovery_machine_init) From patchwork Tue Nov 21 10:24:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 745691 Delivered-To: patch@linaro.org Received: by 2002:a5d:5052:0:b0:32d:baff:b0ca with SMTP id h18csp1793265wrt; Tue, 21 Nov 2023 02:26:25 -0800 (PST) X-Google-Smtp-Source: AGHT+IGZEXCK4gCcPTvUz9RxqKgZhS1wHM9OKMUYFlx61ozVRBmgqBfTBfXj3rWyteNhW6YCZxXP X-Received: by 2002:a05:6102:20d1:b0:462:a548:9bff with SMTP id i17-20020a05610220d100b00462a5489bffmr4192325vsr.35.1700562384843; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id n25-20020a05600c181900b00405442edc69sm20450835wmp.14.2023.11.21.02.24.46 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 02:24:46 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 8/8] hw/arm/fsl-imx: Do not ignore Error argument Date: Tue, 21 Nov 2023 10:24:41 +0000 Message-Id: <20231121102441.3872902-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231121102441.3872902-1-peter.maydell@linaro.org> References: <20231121102441.3872902-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::22a; envelope-from=peter.maydell@linaro.org; helo=mail-lj1-x22a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Both i.MX25 and i.MX6 SoC models ignore the Error argument when setting the PHY number. Pick &error_abort which is the error used by the i.MX7 SoC (see commit 1f7197deb0 "ability to change the FEC PHY on i.MX7 processor"). Fixes: 74c1330582 ("ability to change the FEC PHY on i.MX25 processor") Fixes: a9c167a3c4 ("ability to change the FEC PHY on i.MX6 processor") Signed-off-by: Philippe Mathieu-Daudé Message-id: 20231120115116.76858-1-philmd@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/fsl-imx25.c | 3 ++- hw/arm/fsl-imx6.c | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/hw/arm/fsl-imx25.c b/hw/arm/fsl-imx25.c index 24c43745903..9aabbf7f587 100644 --- a/hw/arm/fsl-imx25.c +++ b/hw/arm/fsl-imx25.c @@ -169,7 +169,8 @@ static void fsl_imx25_realize(DeviceState *dev, Error **errp) epit_table[i].irq)); } - object_property_set_uint(OBJECT(&s->fec), "phy-num", s->phy_num, &err); + object_property_set_uint(OBJECT(&s->fec), "phy-num", s->phy_num, + &error_abort); qdev_set_nic_properties(DEVICE(&s->fec), &nd_table[0]); if (!sysbus_realize(SYS_BUS_DEVICE(&s->fec), errp)) { diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c index 4fa7f0b95ed..7dc42cbfe64 100644 --- a/hw/arm/fsl-imx6.c +++ b/hw/arm/fsl-imx6.c @@ -379,7 +379,8 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp) spi_table[i].irq)); } - object_property_set_uint(OBJECT(&s->eth), "phy-num", s->phy_num, &err); + object_property_set_uint(OBJECT(&s->eth), "phy-num", s->phy_num, + &error_abort); qdev_set_nic_properties(DEVICE(&s->eth), &nd_table[0]); if (!sysbus_realize(SYS_BUS_DEVICE(&s->eth), errp)) { return;