From patchwork Wed Nov 22 19:13:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Kurapati PSSNV X-Patchwork-Id: 746085 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="CX+Itb0f" Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4D11EA9; Wed, 22 Nov 2023 11:14:04 -0800 (PST) Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3AMHtHj6013064; Wed, 22 Nov 2023 19:13:59 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=yXKhBC6qyjVJMI9jGI78fIEfxj9oHaei59gNVkADGJY=; b=CX+Itb0f5AlVsGlSse3xKi9Mh4s8+ni67Rpft0PkDhrHy1Gy9GpIl9A0ZbfER+G+6IjA 4yo7wchUdaVPN2OlYrgFvuqxhsINJ4D1RqbYMVUso1mNQYFuyOiCRd/dxPSDbc5dmKpw Qom9tTiJWYWyqkMMwl22X5t725qoneKTdzanYIv8doCBHG0R4/Q+JefbBjD+RtPU/ToF ALhb+9MtZeBcK+NWG0NG/OsLy+wlsbCG8urwZLx59o4ZUx/YKhA2DO3RfiYNYkaICegU IF6ce5hIiJaov5uyqOXt+UHAewz9XcpVhpnJ/25JZg0eDX+AM+wupnx6iBCt1hVlrHmQ Hw== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3uhkfnrnv9-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 22 Nov 2023 19:13:58 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3AMJDvpL031615 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 22 Nov 2023 19:13:57 GMT Received: from hu-kriskura-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 22 Nov 2023 11:13:53 -0800 From: Krishna Kurapati To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Greg Kroah-Hartman , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , CC: , , , , , , Krishna Kurapati Subject: [PATCH 1/6] dt-bindings: usb: dwc3: Clean up hs_phy_irq in bindings Date: Thu, 23 Nov 2023 00:43:35 +0530 Message-ID: <20231122191335.3058-1-quic_kriskura@quicinc.com> X-Mailer: git-send-email 2.42.0 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: eV3Adt5Fftgy3sGq-qajQRMzVYkWxWxV X-Proofpoint-ORIG-GUID: eV3Adt5Fftgy3sGq-qajQRMzVYkWxWxV X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-22_13,2023-11-22_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 impostorscore=0 mlxscore=0 clxscore=1015 spamscore=0 lowpriorityscore=0 adultscore=0 bulkscore=0 suspectscore=0 malwarescore=0 mlxlogscore=999 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311220139 The high speed related interrupts present on QC targets are as follows: dp/dm Irq's These IRQ's directly reflect changes on the DP/DM pads of the SoC. These are used as wakeup interrupts only on SoCs with non-QUSBb2 targets with exception of SDM670/SDM845/SM6350. qusb2_phy irq SoCs with QUSB2 PHY do not have separate DP/DM IRQs and expose only a single IRQ whose behavior can be modified by the QUSB2PHY_INTR_CTRL register. The required DPSE/DMSE configuration is done in QUSB2PHY_INTR_CTRL register of phy address space. hs_phy_irq This is completely different from the above two and is present on all targets with exception of a few IPQ ones. The interrupt is not enabled by default and its functionality is mutually exclusive of qusb2_phy on QUSB targets and DP/DM on femto phy targets. The DTs of several QUSB2 PHY based SoCs incorrectly define "hs_phy_irq" when they should have been "qusb2_phy_irq". On Femto phy targets, the "hs_phy_irq" mentioned is either the actual "hs_phy_irq" or "pwr_event", neither of which would never be triggered directly are non-functional currently. The implementation tries to clean up this issue by addressing the discrepencies involved and fixing the hs_phy_irq's in respective DT's. Signed-off-by: Krishna Kurapati --- .../devicetree/bindings/usb/qcom,dwc3.yaml | 125 ++++++++++-------- 1 file changed, 69 insertions(+), 56 deletions(-) diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml index e889158ca205..4a46346e2ead 100644 --- a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml +++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml @@ -17,20 +17,25 @@ properties: - qcom,ipq5018-dwc3 - qcom,ipq5332-dwc3 - qcom,ipq6018-dwc3 + - qcom,ipq6018-dwc3-sec - qcom,ipq8064-dwc3 - qcom,ipq8074-dwc3 - qcom,ipq9574-dwc3 - qcom,msm8953-dwc3 - qcom,msm8994-dwc3 - qcom,msm8996-dwc3 + - qcom,msm8996-dwc3-sec - qcom,msm8998-dwc3 - qcom,qcm2290-dwc3 - qcom,qcs404-dwc3 - qcom,sa8775p-dwc3 + - qcom,sa8775p-dwc3-ter - qcom,sc7180-dwc3 - qcom,sc7280-dwc3 + - qcom,sc7280-dwc3-sec - qcom,sc8280xp-dwc3 - qcom,sdm660-dwc3 + - qcom,sdm660-dwc3-sec - qcom,sdm670-dwc3 - qcom,sdm845-dwc3 - qcom,sdx55-dwc3 @@ -98,11 +103,11 @@ properties: interrupts: minItems: 1 - maxItems: 4 + maxItems: 5 interrupt-names: minItems: 1 - maxItems: 4 + maxItems: 5 qcom,select-utmi-as-pipe-clk: description: @@ -175,10 +180,13 @@ allOf: - qcom,ipq9574-dwc3 - qcom,msm8953-dwc3 - qcom,msm8996-dwc3 + - qcom,msm8996-dwc3-sec - qcom,msm8998-dwc3 - qcom,sa8775p-dwc3 + - qcom,sa8775p-dwc3-ter - qcom,sc7180-dwc3 - qcom,sc7280-dwc3 + - qcom,sc7280-dwc3-sec - qcom,sdm670-dwc3 - qcom,sdm845-dwc3 - qcom,sdx55-dwc3 @@ -203,6 +211,7 @@ allOf: contains: enum: - qcom,ipq6018-dwc3 + - qcom,ipq6018-dwc3-sec then: properties: clocks: @@ -285,6 +294,7 @@ allOf: contains: enum: - qcom,sdm660-dwc3 + - qcom,sdm660-dwc3-sec then: properties: clocks: @@ -357,20 +367,15 @@ allOf: compatible: contains: enum: - - qcom,ipq4019-dwc3 - - qcom,ipq6018-dwc3 - - qcom,ipq8064-dwc3 - - qcom,ipq8074-dwc3 - - qcom,msm8994-dwc3 - - qcom,qcs404-dwc3 + - qcom,sc8280xp-dwc3 + - qcom,sa8775p-dwc3 - qcom,sc7180-dwc3 + - qcom,sc7280-dwc3 - qcom,sdm670-dwc3 - qcom,sdm845-dwc3 - qcom,sdx55-dwc3 - qcom,sdx65-dwc3 - qcom,sdx75-dwc3 - - qcom,sm4250-dwc3 - - qcom,sm6125-dwc3 - qcom,sm6350-dwc3 - qcom,sm8150-dwc3 - qcom,sm8250-dwc3 @@ -381,16 +386,37 @@ allOf: properties: interrupts: items: + - description: Wakeup event on DM line. + - description: Wakeup event on DP line. - description: The interrupt that is asserted - when a wakeup event is received on USB2 bus. + based on linestates. Is enabled if qscratch + registers are configured appropirately. This + interrupt functionality is mutually exclusive + to that of {dp/d}_hs_phy_irq) + - description: Wakeup based on power events. - description: The interrupt that is asserted when a wakeup event is received on USB3 bus. - - description: Wakeup event on DM line. - - description: Wakeup event on DP line. interrupt-names: items: + - const: dm_hs_phy_irq + - const: dp_hs_phy_irq - const: hs_phy_irq + - const: pwr_event - const: ss_phy_irq + + - if: + properties: + compatible: + contains: + enum: + - qcom,sc7280-dwc3-sec + - qcom,sa8775p-ter + then: + properties: + interrupt-names: + items: + - const: pwr_event + - const: hs_phy_irq - const: dm_hs_phy_irq - const: dp_hs_phy_irq @@ -399,36 +425,29 @@ allOf: compatible: contains: enum: - - qcom,msm8953-dwc3 - - qcom,msm8996-dwc3 - - qcom,msm8998-dwc3 - - qcom,sm6115-dwc3 + - qcom,ipq6018-dwc3-sec then: properties: - interrupts: - maxItems: 2 interrupt-names: items: - - const: hs_phy_irq - - const: ss_phy_irq + - const: pwr_event + - const: qusb2_phy - if: properties: compatible: contains: enum: - - qcom,ipq5018-dwc3 - - qcom,ipq5332-dwc3 - - qcom,sdm660-dwc3 + - qcom,ipq6018-dwc3 + - qcom,ipq8074-dwc3 + - qcom,msm8953-dwc3 + - qcom,msm8998-dwc3 then: properties: - interrupts: - minItems: 1 - maxItems: 2 interrupt-names: - minItems: 1 items: - - const: hs_phy_irq + - const: pwr_event + - const: qusb2_phy - const: ss_phy_irq - if: @@ -436,55 +455,48 @@ allOf: compatible: contains: enum: - - qcom,sc7280-dwc3 + - qcom,msm8996-dwc3 + - qcom,sdm660-dwc3 + - qcom,sm4250-dwc3 + - qcom,sm6115-dwc3 + - qcom,sm6125-dwc3 then: properties: - interrupts: - minItems: 3 - maxItems: 4 interrupt-names: - minItems: 3 items: - const: hs_phy_irq - - const: dp_hs_phy_irq - - const: dm_hs_phy_irq + - const: pwr_event + - const: qusb2_phy - const: ss_phy_irq - - if: properties: compatible: contains: enum: - - qcom,sc8280xp-dwc3 + - qcom,sdm660-dwc3-sec + - qcom,msm8996-dwc3-sec + - qcom,qcs404-dwc3 then: properties: - interrupts: - maxItems: 4 interrupt-names: items: + - const: hs_phy_irq - const: pwr_event - - const: dp_hs_phy_irq - - const: dm_hs_phy_irq - - const: ss_phy_irq + - const: qusb2_phy - if: properties: compatible: contains: enum: - - qcom,sa8775p-dwc3 + - qcom,ipq5332-dwc3 then: properties: - interrupts: - minItems: 3 - maxItems: 4 interrupt-names: - minItems: 3 items: - - const: pwr_event - const: dp_hs_phy_irq - const: dm_hs_phy_irq - - const: ss_phy_irq + - const: pwr_event additionalProperties: false @@ -519,12 +531,13 @@ examples: <&gcc GCC_USB30_PRIM_MASTER_CLK>; assigned-clock-rates = <19200000>, <150000000>; - interrupts = , - , - , - ; - interrupt-names = "hs_phy_irq", "ss_phy_irq", - "dm_hs_phy_irq", "dp_hs_phy_irq"; + interrupts = , + , + , + , + ; + interrupt-names = "dm_hs_phy_irq", "dp_hs_phy_irq", + "hs_phy_irq", "pwr_event", "ss_phy_irq"; power-domains = <&gcc USB30_PRIM_GDSC>; From patchwork Wed Nov 22 19:14:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Kurapati PSSNV X-Patchwork-Id: 746084 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="CORhtxzX" Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8A64918E; Wed, 22 Nov 2023 11:14:39 -0800 (PST) Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3AMHj3k1015562; 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Wed, 22 Nov 2023 19:14:35 GMT Received: from hu-kriskura-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 22 Nov 2023 11:14:30 -0800 From: Krishna Kurapati To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , , , , Krishna Kurapati Subject: [PATCH 3/6] arm64: dts: qcom: Fix hs_phy_irq for QUSB2 targets Date: Thu, 23 Nov 2023 00:44:21 +0530 Message-ID: <20231122191421.3132-1-quic_kriskura@quicinc.com> X-Mailer: git-send-email 2.42.0 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: jqYkEVxxPwYgvWn_wlkpp2FduFSzn2bE X-Proofpoint-ORIG-GUID: jqYkEVxxPwYgvWn_wlkpp2FduFSzn2bE X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-22_13,2023-11-22_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 lowpriorityscore=0 adultscore=0 malwarescore=0 suspectscore=0 bulkscore=0 mlxscore=0 spamscore=0 phishscore=0 impostorscore=0 mlxlogscore=839 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311220139 On several QUSB2 Targets, the hs_phy_irq mentioned is actually qusb2_phy interrupt specific to QUSB2 Phy's. Rename hs_phy_irq to qusb_phy for such targets. In actuality, the hs_phy_irq is also present in these targets, but kept in for debug purposes in hw test environments. This is not triggered by default and its functionality is mutually exclusive to that of qusb2_phy interrupt. Add missing hs_phy_irq's, pwr_event irq's for qusb2 phy targets. Signed-off-by: Krishna Kurapati --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 15 ++++++++++++++- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 14 ++++++++++++++ arch/arm64/boot/dts/qcom/msm8953.dtsi | 7 +++++-- arch/arm64/boot/dts/qcom/msm8996.dtsi | 19 ++++++++++++++----- arch/arm64/boot/dts/qcom/msm8998.dtsi | 7 +++++-- arch/arm64/boot/dts/qcom/sdm630.dtsi | 19 ++++++++++++++----- arch/arm64/boot/dts/qcom/sm6115.dtsi | 9 +++++++-- arch/arm64/boot/dts/qcom/sm6125.dtsi | 9 +++++++++ 8 files changed, 82 insertions(+), 17 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index 9aec89d5e095..4edad51e0481 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -395,7 +395,7 @@ tcsr: syscon@1937000 { }; usb2: usb@70f8800 { - compatible = "qcom,ipq6018-dwc3", "qcom,dwc3"; + compatible = "qcom,ipq6018-dwc3-sec", "qcom,dwc3"; reg = <0x0 0x070f8800 0x0 0x400>; #address-cells = <2>; #size-cells = <2>; @@ -411,6 +411,12 @@ usb2: usb@70f8800 { <&gcc GCC_USB1_MOCK_UTMI_CLK>; assigned-clock-rates = <133330000>, <24000000>; + + interrupts-extended = , + ; + interrupt-names = "pwr_event", + "qusb2_phy"; + resets = <&gcc GCC_USB1_BCR>; status = "disabled"; @@ -559,6 +565,13 @@ usb3: usb@8af8800 { <133330000>, <20000000>; + interrupts-extended = , + , + ; + interrupt-names = "pwr_event", + "qusb2_phy", + "ss_phy_irq"; + resets = <&gcc GCC_USB0_BCR>; status = "disabled"; diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 5d05819f356d..2977ef424986 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -619,6 +619,13 @@ usb_0: usb@8af8800 { <133330000>, <19200000>; + interrupts-extended = , + , + ; + interrupt-names = "pwr_event", + "qusb2_phy", + "ss_phy_irq"; + power-domains = <&gcc USB0_GDSC>; resets = <&gcc GCC_USB0_BCR>; @@ -661,6 +668,13 @@ usb_1: usb@8cf8800 { <133330000>, <19200000>; + interrupts-extended = , + , + ; + interrupt-names = "pwr_event", + "qusb2_phy", + "ss_phy_irq"; + power-domains = <&gcc USB1_GDSC>; resets = <&gcc GCC_USB1_BCR>; diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi index e7de7632669a..29a6f9ad3df3 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -1118,9 +1118,12 @@ usb3: usb@70f8800 { #size-cells = <1>; ranges; - interrupts = , + interrupts = , + , ; - interrupt-names = "hs_phy_irq", "ss_phy_irq"; + interrupt-names = "pwr_event", + "qusb2_phy", + "ss_phy_irq"; clocks = <&gcc GCC_USB_PHY_CFG_AHB_CLK>, <&gcc GCC_USB30_MASTER_CLK>, diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 6ba9da9e6a8b..a5400d7dfb9c 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -3026,9 +3026,14 @@ usb3: usb@6af8800 { #size-cells = <1>; ranges; - interrupts = , + interrupts = , + , + , ; - interrupt-names = "hs_phy_irq", "ss_phy_irq"; + interrupt-names = "hs_phy_irq", + "pwr_event", + "qusb2_phy", + "ss_phy_irq"; clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>, <&gcc GCC_USB30_MASTER_CLK>, @@ -3382,14 +3387,18 @@ blsp2_spi6: spi@75ba000 { }; usb2: usb@76f8800 { - compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; + compatible = "qcom,msm8996-dwc3-sec", "qcom,dwc3"; reg = <0x076f8800 0x400>; #address-cells = <1>; #size-cells = <1>; ranges; - interrupts = ; - interrupt-names = "hs_phy_irq"; + interrupts = , + , + ; + interrupt-names = "hs_phy_irq", + "pwr_event", + "qusb2_phy"; clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>, <&gcc GCC_USB20_MASTER_CLK>, diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index b485bf925ce6..9b7d22c4f197 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -2135,9 +2135,12 @@ usb3: usb@a8f8800 { <&gcc GCC_USB30_MASTER_CLK>; assigned-clock-rates = <19200000>, <120000000>; - interrupts = , + interrupts = , + , ; - interrupt-names = "hs_phy_irq", "ss_phy_irq"; + interrupt-names = "pwr_event", + "qusb2_phy", + "ss_phy_irq"; power-domains = <&gcc USB_30_GDSC>; diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index 775700f78e0f..5be337c07393 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -1303,9 +1303,14 @@ usb3: usb@a8f8800 { assigned-clock-rates = <19200000>, <120000000>, <19200000>; - interrupts = , + interrupts = , + , + , ; - interrupt-names = "hs_phy_irq", "ss_phy_irq"; + interrupt-names = "hs_phy_irq", + "pwr_event", + "qusb2_phy", + "ss_phy_irq"; power-domains = <&gcc USB_30_GDSC>; qcom,select-utmi-as-pipe-clk; @@ -1467,7 +1472,7 @@ opp-384000000 { }; usb2: usb@c2f8800 { - compatible = "qcom,sdm660-dwc3", "qcom,dwc3"; + compatible = "qcom,sdm660-dwc3-sec", "qcom,dwc3"; reg = <0x0c2f8800 0x400>; status = "disabled"; #address-cells = <1>; @@ -1485,8 +1490,12 @@ usb2: usb@c2f8800 { <&gcc GCC_USB20_MASTER_CLK>; assigned-clock-rates = <19200000>, <60000000>; - interrupts = ; - interrupt-names = "hs_phy_irq"; + interrupts = , + , + ; + interrupt-names = "hs_phy_irq", + "pwr_event", + "qusb2_phy"; qcom,select-utmi-as-pipe-clk; diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index 839c60351240..748dfb4dc6c7 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -1301,9 +1301,14 @@ usb: usb@4ef8800 { <&gcc GCC_USB30_PRIM_MASTER_CLK>; assigned-clock-rates = <19200000>, <66666667>; - interrupts = , + interrupts = , + , + , ; - interrupt-names = "hs_phy_irq", "ss_phy_irq"; + interrupt-names = "hs_phy_irq", + "pwr_event", + "qusb2_phy", + "ss_phy_irq"; resets = <&gcc GCC_USB30_PRIM_BCR>; power-domains = <&gcc GCC_USB30_PRIM_GDSC>; diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi index eb07eca3a48d..d5b6ee4e104c 100644 --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi @@ -1185,6 +1185,15 @@ usb3: usb@4ef8800 { <&gcc GCC_USB30_PRIM_MASTER_CLK>; assigned-clock-rates = <19200000>, <66666667>; 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Wed, 22 Nov 2023 11:15:01 -0800 From: Krishna Kurapati To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , , , , Krishna Kurapati Subject: [PATCH 5/6] arm64: dts: qcom: Fix hs_phy_irq for SDM670/SDM845/SM6350 Date: Thu, 23 Nov 2023 00:44:52 +0530 Message-ID: <20231122191452.3183-1-quic_kriskura@quicinc.com> X-Mailer: git-send-email 2.42.0 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 01symdIODD-064Tlo4RYvqdIl2p6ltn7 X-Proofpoint-GUID: 01symdIODD-064Tlo4RYvqdIl2p6ltn7 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-22_13,2023-11-22_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=628 lowpriorityscore=0 spamscore=0 impostorscore=0 suspectscore=0 priorityscore=1501 mlxscore=0 malwarescore=0 clxscore=1015 phishscore=0 bulkscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311220139 For sm6350/sdm670/sdm845, although they are qusb2 phy targets, dp/dm interrupts are used for wakeup instead of qusb2_phy irq. These targets were part of a generation that were the last ones to implement QUSB2 PHY and the design incorporated dedicated DP/DM interrupts which eventually carried forward to the newer femto based targets. Add the missing pwr_event irq for these targets. Signed-off-by: Krishna Kurapati --- arch/arm64/boot/dts/qcom/sdm670.dtsi | 5 ++++- arch/arm64/boot/dts/qcom/sdm845.dtsi | 10 ++++++++-- arch/arm64/boot/dts/qcom/sm6350.dtsi | 7 +++++-- 3 files changed, 17 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi index 6d9843d05cb3..b8888f71b1d6 100644 --- a/arch/arm64/boot/dts/qcom/sdm670.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi @@ -1296,10 +1296,13 @@ usb_1: usb@a6f8800 { assigned-clock-rates = <19200000>, <150000000>; interrupts = , + , , , ; - interrupt-names = "hs_phy_irq", "ss_phy_irq", + interrupt-names = "hs_phy_irq", + "pwr_event", + "ss_phy_irq", "dm_hs_phy_irq", "dp_hs_phy_irq"; power-domains = <&gcc USB30_PRIM_GDSC>; diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index bf5e6eb9d313..c3e90e54e329 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -4054,10 +4054,13 @@ usb_1: usb@a6f8800 { assigned-clock-rates = <19200000>, <150000000>; interrupts = , + , , , ; - interrupt-names = "hs_phy_irq", "ss_phy_irq", + interrupt-names = "hs_phy_irq", + "pwr_event", + "ss_phy_irq", "dm_hs_phy_irq", "dp_hs_phy_irq"; power-domains = <&gcc USB30_PRIM_GDSC>; @@ -4105,10 +4108,13 @@ usb_2: usb@a8f8800 { assigned-clock-rates = <19200000>, <150000000>; interrupts = , + , , , ; - interrupt-names = "hs_phy_irq", "ss_phy_irq", + interrupt-names = "hs_phy_irq", + "pwr_event", + "ss_phy_irq", "dm_hs_phy_irq", "dp_hs_phy_irq"; power-domains = <&gcc USB30_SEC_GDSC>; diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 8fd6f4d03490..af788e30eb45 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -1839,12 +1839,15 @@ usb_1: usb@a6f8800 { "sleep", "mock_utmi"; - interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, <&pdc 15 IRQ_TYPE_EDGE_BOTH>, <&pdc 14 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "hs_phy_irq", "ss_phy_irq", + interrupt-names = "hs_phy_irq", + "pwr_event", + "ss_phy_irq", "dm_hs_phy_irq", "dp_hs_phy_irq"; power-domains = <&gcc USB30_PRIM_GDSC>;