From patchwork Thu Nov 30 01:10:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 748739 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="Wd3GQfKU" Received: from NAM04-DM6-obe.outbound.protection.outlook.com (mail-dm6nam04on2060.outbound.protection.outlook.com [40.107.102.60]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 526FFD54; Wed, 29 Nov 2023 17:10:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Z5DU661SRsmHA8CiOKQdRZ8DbqSu8OFEE48kOA0RmlerWUfsoDXE4Y1joDpaacFrU6oNTdY2nCTJK89W/CZ8vH9Q6Ly8AxR0pFqRf3zQNKM/1h5Nn9wGNuRQEI4QQ72l/oNnAN/BHiUsKRfQc7vk+uRCiMVyhGfY94+Xu1alXjoSpik/KoHPdPR9AGFzVTYj1WEcwEO+GcJNyQlxghvu8iyETHaQ+SszAJL2xu8B2x0Yy4JZ6Okec1cdNo/fIyA2wij6pvorVhnRU2cQI7AFZkchjOMpXkXNGS/l9mFhP+mAn5w2gMAMZEgzkKfNOPf6fR+N8B1ZL8nAncATf4ubaQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=S1/2RwZb1BvcKrWpjq41xk6R0wcBobygbj+9IidcnE8=; b=Agd/dlrnkFVoUeVayIt9ibYudFujJ5s2Kj4hTuKT1d0gPI1h32WyOi7zFfhRJIFQ27Vtu3YlX1z0RCimsbH5Sz62fzeA2b7/RmSjT2chrxICujq6mQfF4mrBZOaXlHoywtxxTCOxlpXzHy/Exj2/7k8Ppb5gpCYaLVJ5efAwQMl7RheN+cYXqRlYtY8Hc+WvgOowWb3m4bDGbWW0Mvy4QARQc+TysrE3dgmnoB2eNINK9P0/jsZDayBiFuWEjY0B3I1mYMrLDtt7omW68VedFZzoSuwFz1JUWBp5SU22O5IMd1FFkpL9EyBDpZs9aEnaX2YjGNIDAot0rq+mnBkM2w== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=S1/2RwZb1BvcKrWpjq41xk6R0wcBobygbj+9IidcnE8=; b=Wd3GQfKUtdMv1PJC8DKrRfs1e1pu+1GrORDA9mw/Xe/WjUmrRFKlPjsn1CrCx+g73L4uWk9ZJRpMClkXk0lJFRuCa5ZlbBRJZFbBO001T28yQsXTqUYF7Z9wr0v66t6vKDf1sleW5b/vmbpgXG4LdU30EpuWv5+qLI1H3OkOeakQd3sA+8NN86eVYHny5ylOVA3PUjlhGK24/viXa76WZAB9SQM/VhnuYL0yCl2hjsHGZtWZnbZd6lirHoRnDOIvgM3O0yDZS3qNFp1r4TgDjbwvCN8dHhxZC28VFu+hSjEWjQYbBhDTYf2hvL4BzfbWWdMJ+ymvvf279JY7Pkor7w== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) by DS0PR12MB7607.namprd12.prod.outlook.com (2603:10b6:8:13f::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7046.22; Thu, 30 Nov 2023 01:10:39 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93%4]) with mapi id 15.20.7046.015; Thu, 30 Nov 2023 01:10:39 +0000 From: Jason Gunthorpe To: acpica-devel@lists.linux.dev, Andy Gross , Alim Akhtar , Alyssa Rosenzweig , Bjorn Andersson , AngeloGioacchino Del Regno , asahi@lists.linux.dev, Baolin Wang , devicetree@vger.kernel.org, Frank Rowand , Hanjun Guo , "Gustavo A. R. Silva" , Heiko Stuebner , iommu@lists.linux.dev, Jean-Philippe Brucker , Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Kees Cook , Konrad Dybcio , Krzysztof Kozlowski , Len Brown , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Lorenzo Pieralisi , Marek Szyprowski , Hector Martin , Matthias Brugger , Orson Zhai , "Rafael J. Wysocki" , Rob Clark , Robert Moore , Rob Herring , Robin Murphy , Samuel Holland , Sudeep Holla , Sven Peter , Thierry Reding , Krishna Reddy , virtualization@lists.linux.dev, Chen-Yu Tsai , Will Deacon , Yong Wu , Chunyan Zhang Cc: =?utf-8?q?Andr=C3=A9_Draszik?= , patches@lists.linux.dev Subject: [PATCH 04/30] ACPI: IORT: Remove fwspec from the reserved region code Date: Wed, 29 Nov 2023 21:10:11 -0400 Message-ID: <4-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> In-Reply-To: <0-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> References: X-ClientProxiedBy: SN7PR04CA0162.namprd04.prod.outlook.com (2603:10b6:806:125::17) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|DS0PR12MB7607:EE_ X-MS-Office365-Filtering-Correlation-Id: 799948c1-d494-4ba0-9962-08dbf1412a25 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: HOwkopNGa0CBJ1OiokLpJXaWRObisYdz9OliU1tDVjJR2EnhrrKcMvn/tZ83zBYOOidiSi8ak9+LyDk0jrjNScorLATqTch+cK3eZEvCvHa9OJoe5YHgi5ryCfuHinCcJG8s5XKJSBolN6DMZl5JG3dM9HvzzfGFcFAZs6iV5V+QD3MdcEzrkWle7chIpMx3D3uJG33V1z2xUdcxzRxOA6bBKQRvTzJUJRCZ10g1HuL5tIFYzqGdsCv+MezcXMViedA2D2f/dkVQqD7s+QElsnFAS3QsMbsnhLcbguhk7k9fziOPCgn3B/kqidMU2YZorqB95rHis9lRV1uCshslD8buIhDwtYviVktRpgsJZgXGW89iPbJi7GEFipUARuQVyBUqisXCxncXwRVW8RhjpJkret/3sHfo76HuN+mj9HfKQa+rccIWWT9NqG3fhFuklkM9i6H+ysP2p047dM/5L5W+fGt+KDLyRY/eLHbTPYiBv/jZ6Esvw4h+gwP8dK7Qq1uEu1WtSXjrEorgJpM+ZiKsrE+FD1KMABgO+J7O5sg5CvDJAA7uCirdJRXqOL6qOiXaF8q0zMBZMUx6YMbFoI5tdk3RhlBthpaxCd53dhMdIssQl62wLdeMF8zQqr/zMgPYaZUM2YzPfbRig3Hcw2QxVxeWSr0HzzwrHGkMjk8= X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:LV2PR12MB5869.namprd12.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230031)(396003)(39860400002)(346002)(136003)(366004)(376002)(230922051799003)(186009)(451199024)(64100799003)(1800799012)(38100700002)(202311291699003)(83380400001)(1191002)(5660300002)(110136005)(2906002)(86362001)(4326008)(8676002)(8936002)(66556008)(7366002)(7406005)(7416002)(66476007)(66946007)(6486002)(478600001)(6666004)(316002)(36756003)(6506007)(41300700001)(6512007)(921008)(26005)(2616005)(4216001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 2mhjeIC9kP2zwjJ3vrYUZ3jAaoHBX2IY3xBPl32LW6cQIx4sFAdbPZhmnG4FuurHu6p3/dvANUAkZDtE0qDPN/ou7YhPs2tsbok7mpuaXMcMfO0M7bPh2A1fz3T9E6fJegXZa+VGcrfhLiKA+jZ1fvOie0oeI24UrywXgLEvy9hKFky4LgxovLqk+BfisoJ6k/bwUbt8HNn8j7mcwjVMqBLC1Mw2z8zYA5HeoThE2HMrRqb/kYRYE/nGY5+VghO/EJ/FyJ1PUmgPonmaL+Hng6hRhEZEshsd4k+BCVryJtnlrqQdQbNzqZ9+k/6kHfBir1tuwTV/Y1xQs6tqFRKw7LZCv9U1i3jqtRW+Fj0ACuaX5q9QkXG47MKP1qC2Hd0IBYb8lXYczGiWDp3Jq8LQHe7DhOvMJtZX3ImlfvrqcjIMhjx1LrFK/DIafD+7Wd/YRY/uaYyVFQseOvBsoPapUNoa1Qj5O3KELLC6x4avNE2/HIR2EXaav1KvNkU7c7gCrEmnoVeEdbxzKHbLv2VjJCbP22IT97ChwhkZUSYdvOw34KlafoIMGRDv85ONLD9vAuF7pfIRBwvTDqjeMmwES+rEAmUMyzlwieNm4DCpX1Ea8yKKkbJlz0CriJQwsfFTncnBtlHLna74Vk4+u5xtpvX64DJLMgg1XAVJ0JORy92xnyC7+UkgX19i6PYaWlkKhcxq4QGf4hYC7nzZ1oS5Pp5GEwMmkp2GEjFNs3cgFawMlWAWCZ2iwkHfGy44qxaptAZWc07/kMbmFqEbkAHPYFkpyCJKmPv7tYsAiPJJ3tErJIbT00MvmLZ48jtfiYiAtnwqDBEe4FqQQSryvmb/5E8mHCbXWNWQNPJp87DNTCX2ve0mvEp/VytaRQSrgaMhcPV5D6Hqc9HCNLyJpmeUyT7r8K3k6F/Mh7qpYaCn4mgiEQ3wjzWctJHnLEdT8iQCDYmV3QIDp492oWMRyl7u082Jr4tU6fBOgtBHUb5YVoAMOUEpieV+cf3sfB4c/yyw3i51kX/t8PkwNrgBGoaLtgXID4g/XFV2q2WpS3rUAe12l2QBr7rz0uSC02jcAA+C/NwqWcsyIAT4p39aYlDAgnkJA/CJqy39gJoye6JJdN8oVmTjamQpXfouVPGCX5WnC9DbXNl7QyhY2OEZCPW2q/ybiZmpni6jiwMqKaCA9vqgFVSoK/hD0MWCZCgUsUN5SdiTLxjc6j31/FUortrzLHg+K/8kiAnxrLpb0c3vdxVnJ4QDTj3fJJnO4ItGF7nZOKRV0jPbsWbWGfB4BKXmbdE5K6KJ+y2eKtHJcIz3mq12uyq5AstKy6Ci2Xw7V37Bdq2e4kufxiE7s7cFf7YC8E0/8S5hll+U/9KAXsWsCQFhIg33RhYxdEnQz5IYeHc6PrmbffrrQfqoMz3SXtyAKT9Wy0DHKmD6a74EDs4xwTpZa95ZgScZVVRXkoJt/ocLubU9iM7yTus6mwV4jn1kKEI9pyad9Wcb4vjV02TEj6LJ5wNQ3Te0SKYbTb4hapAl3cCabqW5+WgszKOoMDPTKI9NV+v3CMATwO3SJvm8uXDPHDgRo5qRDg6XL5qKBYxI X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 799948c1-d494-4ba0-9962-08dbf1412a25 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2023 01:10:38.8211 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: xmL1HXjHi6e5JgKpBsPqhhRc8AtQttGvFiUIYyPn2GmuaV9VgchKVr2DtiYJqBGB X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7607 iort_iommu_get_resv_regions() needs access to the parsed id array that is currently stored in the iommu_fwspec. Instead of getting this from the fwspec inside the iort code have the caller pass it in. Signed-off-by: Jason Gunthorpe --- drivers/acpi/arm64/iort.c | 88 ++++++++++++++++++++++++--------------- drivers/iommu/dma-iommu.c | 7 +++- include/linux/acpi_iort.h | 8 +++- 3 files changed, 65 insertions(+), 38 deletions(-) diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c index 5c9b4c23f96a87..93e30f2f5004f0 100644 --- a/drivers/acpi/arm64/iort.c +++ b/drivers/acpi/arm64/iort.c @@ -946,11 +946,19 @@ static u32 *iort_rmr_alloc_sids(u32 *sids, u32 count, u32 id_start, return new_sids; } -static bool iort_rmr_has_dev(struct device *dev, u32 id_start, +struct iort_resv_args { + struct device *dev; + struct list_head *head; + struct fwnode_handle *iommu_fwnode; + const u32 *fw_ids; + unsigned int fw_num_ids; +}; + +static bool iort_rmr_has_dev(struct iort_resv_args *args, u32 id_start, u32 id_count) { + struct device *dev = args->dev; int i; - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); /* * Make sure the kernel has preserved the boot firmware PCIe @@ -965,18 +973,18 @@ static bool iort_rmr_has_dev(struct device *dev, u32 id_start, return false; } - for (i = 0; i < fwspec->num_ids; i++) { - if (fwspec->ids[i] >= id_start && - fwspec->ids[i] <= id_start + id_count) + for (i = 0; i < args->fw_num_ids; i++) { + if (args->fw_ids[i] >= id_start && + args->fw_ids[i] <= id_start + id_count) return true; } return false; } -static void iort_node_get_rmr_info(struct acpi_iort_node *node, - struct acpi_iort_node *iommu, - struct device *dev, struct list_head *head) +static void iort_node_get_rmr_info(struct iort_resv_args *args, + struct acpi_iort_node *node, + struct acpi_iort_node *iommu) { struct acpi_iort_node *smmu = NULL; struct acpi_iort_rmr *rmr; @@ -1013,8 +1021,8 @@ static void iort_node_get_rmr_info(struct acpi_iort_node *node, continue; /* If dev is valid, check RMR node corresponds to the dev SID */ - if (dev && !iort_rmr_has_dev(dev, map->output_base, - map->id_count)) + if (args->dev && + !iort_rmr_has_dev(args, map->output_base, map->id_count)) continue; /* Retrieve SIDs associated with the Node. */ @@ -1029,12 +1037,12 @@ static void iort_node_get_rmr_info(struct acpi_iort_node *node, if (!sids) return; - iort_get_rmrs(node, smmu, sids, num_sids, head); + iort_get_rmrs(node, smmu, sids, num_sids, args->head); kfree(sids); } -static void iort_find_rmrs(struct acpi_iort_node *iommu, struct device *dev, - struct list_head *head) +static void iort_find_rmrs(struct iort_resv_args *args, + struct acpi_iort_node *iommu) { struct acpi_table_iort *iort; struct acpi_iort_node *iort_node, *iort_end; @@ -1057,7 +1065,7 @@ static void iort_find_rmrs(struct acpi_iort_node *iommu, struct device *dev, return; if (iort_node->type == ACPI_IORT_NODE_RMR) - iort_node_get_rmr_info(iort_node, iommu, dev, head); + iort_node_get_rmr_info(args, iort_node, iommu); iort_node = ACPI_ADD_PTR(struct acpi_iort_node, iort_node, iort_node->length); @@ -1069,25 +1077,23 @@ static void iort_find_rmrs(struct acpi_iort_node *iommu, struct device *dev, * If dev is NULL, the function populates all the RMRs associated with the * given IOMMU. */ -static void iort_iommu_rmr_get_resv_regions(struct fwnode_handle *iommu_fwnode, - struct device *dev, - struct list_head *head) +static void iort_iommu_rmr_get_resv_regions(struct iort_resv_args *args) { struct acpi_iort_node *iommu; - iommu = iort_get_iort_node(iommu_fwnode); + iommu = iort_get_iort_node(args->iommu_fwnode); if (!iommu) return; - iort_find_rmrs(iommu, dev, head); + iort_find_rmrs(args, iommu); } -static struct acpi_iort_node *iort_get_msi_resv_iommu(struct device *dev) +static struct acpi_iort_node * +iort_get_msi_resv_iommu(struct iort_resv_args *args) { struct acpi_iort_node *iommu; - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); - iommu = iort_get_iort_node(fwspec->iommu_fwnode); + iommu = iort_get_iort_node(args->iommu_fwnode); if (iommu && (iommu->type == ACPI_IORT_NODE_SMMU_V3)) { struct acpi_iort_smmu_v3 *smmu; @@ -1105,15 +1111,13 @@ static struct acpi_iort_node *iort_get_msi_resv_iommu(struct device *dev) * The ITS interrupt translation spaces (ITS_base + SZ_64K, SZ_64K) * associated with the device are the HW MSI reserved regions. */ -static void iort_iommu_msi_get_resv_regions(struct device *dev, - struct list_head *head) +static void iort_iommu_msi_get_resv_regions(struct iort_resv_args *args) { - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); struct acpi_iort_its_group *its; struct acpi_iort_node *iommu_node, *its_node = NULL; int i; - iommu_node = iort_get_msi_resv_iommu(dev); + iommu_node = iort_get_msi_resv_iommu(args); if (!iommu_node) return; @@ -1126,9 +1130,9 @@ static void iort_iommu_msi_get_resv_regions(struct device *dev, * a given PCI or named component may map IDs to. */ - for (i = 0; i < fwspec->num_ids; i++) { + for (i = 0; i < args->fw_num_ids; i++) { its_node = iort_node_map_id(iommu_node, - fwspec->ids[i], + args->fw_ids[i], NULL, IORT_MSI_TYPE); if (its_node) break; @@ -1151,7 +1155,7 @@ static void iort_iommu_msi_get_resv_regions(struct device *dev, prot, IOMMU_RESV_MSI, GFP_KERNEL); if (region) - list_add_tail(®ion->list, head); + list_add_tail(®ion->list, args->head); } } } @@ -1160,13 +1164,24 @@ static void iort_iommu_msi_get_resv_regions(struct device *dev, * iort_iommu_get_resv_regions - Generic helper to retrieve reserved regions. * @dev: Device from iommu_get_resv_regions() * @head: Reserved region list from iommu_get_resv_regions() + * @iommu_fwnode: fwnode that describes the iommu connection for the device + * @fw_ids: Parsed IDs + * @fw_num_ids: Length of fw_ids */ -void iort_iommu_get_resv_regions(struct device *dev, struct list_head *head) +void iort_iommu_get_resv_regions(struct device *dev, struct list_head *head, + struct fwnode_handle *iommu_fwnode, + const u32 *fw_ids, unsigned int fw_num_ids) { - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); + struct iort_resv_args args = { + .dev = dev, + .head = head, + .iommu_fwnode = iommu_fwnode, + .fw_ids = fw_ids, + .fw_num_ids = fw_num_ids, + }; - iort_iommu_msi_get_resv_regions(dev, head); - iort_iommu_rmr_get_resv_regions(fwspec->iommu_fwnode, dev, head); + iort_iommu_msi_get_resv_regions(&args); + iort_iommu_rmr_get_resv_regions(&args); } /** @@ -1178,7 +1193,12 @@ void iort_iommu_get_resv_regions(struct device *dev, struct list_head *head) void iort_get_rmr_sids(struct fwnode_handle *iommu_fwnode, struct list_head *head) { - iort_iommu_rmr_get_resv_regions(iommu_fwnode, NULL, head); + struct iort_resv_args args = { + .head = head, + .iommu_fwnode = iommu_fwnode, + }; + + iort_iommu_rmr_get_resv_regions(&args); } EXPORT_SYMBOL_GPL(iort_get_rmr_sids); diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c index 85163a83df2f68..d644b0502ef48e 100644 --- a/drivers/iommu/dma-iommu.c +++ b/drivers/iommu/dma-iommu.c @@ -468,9 +468,12 @@ void iommu_put_dma_cookie(struct iommu_domain *domain) */ void iommu_dma_get_resv_regions(struct device *dev, struct list_head *list) { + struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); - if (!is_of_node(dev_iommu_fwspec_get(dev)->iommu_fwnode)) - iort_iommu_get_resv_regions(dev, list); + if (!is_of_node(fwspec->iommu_fwnode)) { + iort_iommu_get_resv_regions(dev, list, fwspec->iommu_fwnode, + fwspec->ids, fwspec->num_ids); + } if (dev->of_node) of_iommu_get_resv_regions(dev, list); diff --git a/include/linux/acpi_iort.h b/include/linux/acpi_iort.h index 5423abff9b6b09..13f0cefb930693 100644 --- a/include/linux/acpi_iort.h +++ b/include/linux/acpi_iort.h @@ -53,7 +53,9 @@ void iort_put_rmr_sids(struct fwnode_handle *iommu_fwnode, /* IOMMU interface */ int iort_dma_get_ranges(struct device *dev, u64 *size); int iort_iommu_configure_id(struct device *dev, const u32 *id_in); -void iort_iommu_get_resv_regions(struct device *dev, struct list_head *head); +void iort_iommu_get_resv_regions(struct device *dev, struct list_head *head, + struct fwnode_handle *iommu_fwnode, + const u32 *fw_ids, unsigned int fw_num_ids); phys_addr_t acpi_iort_dma_get_max_cpu_address(void); #else static inline u32 iort_msi_map_id(struct device *dev, u32 id) @@ -72,7 +74,9 @@ static inline int iort_dma_get_ranges(struct device *dev, u64 *size) static inline int iort_iommu_configure_id(struct device *dev, const u32 *id_in) { return -ENODEV; } static inline -void iort_iommu_get_resv_regions(struct device *dev, struct list_head *head) +void iort_iommu_get_resv_regions(struct device *dev, struct list_head *head, + struct fwnode_handle *iommu_fwnode, + const u32 *fw_ids, unsigned int fw_num_ids) { } static inline phys_addr_t acpi_iort_dma_get_max_cpu_address(void) From patchwork Thu Nov 30 01:10:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 748738 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="IQjX7i/l" Received: from NAM04-DM6-obe.outbound.protection.outlook.com (mail-dm6nam04on2060.outbound.protection.outlook.com [40.107.102.60]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DA4F010A; Wed, 29 Nov 2023 17:10:46 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=HNwgJ9M0f7NHybi2UuKUbLbc/hViKCX0JdfFD4LKzmJEg6s+LP8Y9AZUuKbRNOl7yDPWwcHU1nLAi0/9wk0tqyTyShrSZGfs8teEaS7F1gURJZdlLOLIxtTtOh82QtnTbjnjD8KSdefGkuKXVvmUFcitXnfPXDyH5s1mRVgVOpADG1fzrKOXwFmUjV1EaA3NjT1ALgL2VE17RJaf4XiAMIEW9RH6DOynB3ERhCNusPdvYlWj18Eaoajekj97s/SDd2J9Hsta+77QUj163kPqcUhz8Q653OXSApzTaLoNj2XfOMaxNQVIiGGf3vcTqpEeH5jidNlKKhggxHqfm7VYiQ== ARC-Message-Signature: i=1; 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R. Silva" , Heiko Stuebner , iommu@lists.linux.dev, Jean-Philippe Brucker , Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Kees Cook , Konrad Dybcio , Krzysztof Kozlowski , Len Brown , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Lorenzo Pieralisi , Marek Szyprowski , Hector Martin , Matthias Brugger , Orson Zhai , "Rafael J. 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With the new design this will be a place for the FW logic to cache data to avoid reparsing and a to convey the currently active call path for probe while we work on restructuring parts of it. Place this in a new header "iommu-driver.h" which is intended to help isolate APIs that are only for use by the drivers away from the consumers of the IOMMU API. Signed-off-by: Jason Gunthorpe --- drivers/acpi/scan.c | 7 +++++- drivers/iommu/iommu.c | 42 ++++++++++++++++++++++++++---------- drivers/iommu/of_iommu.c | 6 +++++- include/linux/iommu-driver.h | 25 +++++++++++++++++++++ include/linux/iommu.h | 3 +++ 5 files changed, 70 insertions(+), 13 deletions(-) create mode 100644 include/linux/iommu-driver.h diff --git a/drivers/acpi/scan.c b/drivers/acpi/scan.c index 340ba720c72129..9c13df632aa5e0 100644 --- a/drivers/acpi/scan.c +++ b/drivers/acpi/scan.c @@ -1543,6 +1543,8 @@ int acpi_dma_get_range(struct device *dev, const struct bus_dma_region **map) } #ifdef CONFIG_IOMMU_API +#include + int acpi_iommu_fwspec_init(struct device *dev, u32 id, struct fwnode_handle *fwnode, const struct iommu_ops *ops) @@ -1566,6 +1568,9 @@ static int acpi_iommu_configure_id(struct device *dev, const u32 *id_in) { int err; const struct iommu_ops *ops; + struct iommu_probe_info pinf = { + .dev = dev, + }; /* Serialise to make dev->iommu stable under our potential fwspec */ mutex_lock(&iommu_probe_device_lock); @@ -1589,7 +1594,7 @@ static int acpi_iommu_configure_id(struct device *dev, const u32 *id_in) * iommu_probe_device() call for dev, replay it to get things in order. */ if (!err && dev->bus) - err = iommu_probe_device(dev); + err = iommu_probe_device_pinf(&pinf); /* Ignore all other errors apart from EPROBE_DEFER */ if (err == -EPROBE_DEFER) { diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index 9557c2ec08d915..76b245973cfafc 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -399,8 +400,10 @@ EXPORT_SYMBOL_GPL(dev_iommu_priv_set); * Init the dev->iommu and dev->iommu_group in the struct device and get the * driver probed */ -static int iommu_init_device(struct device *dev, const struct iommu_ops *ops) +static int iommu_init_device(struct iommu_probe_info *pinf, + const struct iommu_ops *ops) { + struct device *dev = pinf->dev; struct iommu_device *iommu_dev; struct iommu_group *group; int ret; @@ -413,7 +416,10 @@ static int iommu_init_device(struct device *dev, const struct iommu_ops *ops) goto err_free; } - iommu_dev = ops->probe_device(dev); + if (ops->probe_device_pinf) + iommu_dev = ops->probe_device_pinf(pinf); + else + iommu_dev = ops->probe_device(dev); if (IS_ERR(iommu_dev)) { ret = PTR_ERR(iommu_dev); goto err_module_put; @@ -496,8 +502,9 @@ static void iommu_deinit_device(struct device *dev) DEFINE_MUTEX(iommu_probe_device_lock); -static int __iommu_probe_device(struct device *dev, struct list_head *group_list) +static int __iommu_probe_device(struct iommu_probe_info *pinf) { + struct device *dev = pinf->dev; const struct iommu_ops *ops; struct iommu_fwspec *fwspec; struct iommu_group *group; @@ -533,7 +540,7 @@ static int __iommu_probe_device(struct device *dev, struct list_head *group_list if (dev->iommu_group) return 0; - ret = iommu_init_device(dev, ops); + ret = iommu_init_device(pinf, ops); if (ret) return ret; @@ -557,7 +564,7 @@ static int __iommu_probe_device(struct device *dev, struct list_head *group_list ret = __iommu_device_set_domain(group, dev, group->domain, 0); if (ret) goto err_remove_gdev; - } else if (!group->default_domain && !group_list) { + } else if (!group->default_domain && !pinf->defer_setup) { ret = iommu_setup_default_domain(group, 0); if (ret) goto err_remove_gdev; @@ -568,7 +575,7 @@ static int __iommu_probe_device(struct device *dev, struct list_head *group_list * that need further setup. */ if (list_empty(&group->entry)) - list_add_tail(&group->entry, group_list); + list_add_tail(&group->entry, pinf->deferred_group_list); } mutex_unlock(&group->mutex); @@ -588,13 +595,14 @@ static int __iommu_probe_device(struct device *dev, struct list_head *group_list return ret; } -int iommu_probe_device(struct device *dev) +int iommu_probe_device_pinf(struct iommu_probe_info *pinf) { + struct device *dev = pinf->dev; const struct iommu_ops *ops; int ret; mutex_lock(&iommu_probe_device_lock); - ret = __iommu_probe_device(dev, NULL); + ret = __iommu_probe_device(pinf); mutex_unlock(&iommu_probe_device_lock); if (ret) return ret; @@ -606,6 +614,13 @@ int iommu_probe_device(struct device *dev) return 0; } +int iommu_probe_device(struct device *dev) +{ + struct iommu_probe_info pinf = {.dev = dev}; + + return iommu_probe_device_pinf(&pinf); +} + static void __iommu_group_free_device(struct iommu_group *group, struct group_device *grp_dev) { @@ -1830,11 +1845,12 @@ struct iommu_domain *iommu_group_default_domain(struct iommu_group *group) static int probe_iommu_group(struct device *dev, void *data) { - struct list_head *group_list = data; + struct iommu_probe_info *pinf = data; int ret; + pinf->dev = dev; mutex_lock(&iommu_probe_device_lock); - ret = __iommu_probe_device(dev, group_list); + ret = __iommu_probe_device(pinf); mutex_unlock(&iommu_probe_device_lock); if (ret == -ENODEV) ret = 0; @@ -1977,9 +1993,13 @@ int bus_iommu_probe(const struct bus_type *bus) { struct iommu_group *group, *next; LIST_HEAD(group_list); + struct iommu_probe_info pinf = { + .deferred_group_list = &group_list, + .defer_setup = true, + }; int ret; - ret = bus_for_each_dev(bus, NULL, &group_list, probe_iommu_group); + ret = bus_for_each_dev(bus, NULL, &pinf, probe_iommu_group); if (ret) return ret; diff --git a/drivers/iommu/of_iommu.c b/drivers/iommu/of_iommu.c index 3d4580f1fbb378..fb743ddd239e0b 100644 --- a/drivers/iommu/of_iommu.c +++ b/drivers/iommu/of_iommu.c @@ -7,6 +7,7 @@ #include #include +#include #include #include #include @@ -139,6 +140,9 @@ static int of_iommu_for_each_id(struct device *dev, int of_iommu_configure(struct device *dev, struct device_node *master_np, const u32 *id) { + struct iommu_probe_info pinf = { + .dev = dev, + }; struct iommu_fwspec *fwspec; int err; @@ -167,7 +171,7 @@ int of_iommu_configure(struct device *dev, struct device_node *master_np, if (err) goto err_log; - err = iommu_probe_device(dev); + err = iommu_probe_device_pinf(&pinf); if (err) goto err_log; return 0; diff --git a/include/linux/iommu-driver.h b/include/linux/iommu-driver.h new file mode 100644 index 00000000000000..b85c9f15cf478b --- /dev/null +++ b/include/linux/iommu-driver.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES + * + * This file should ONLY be included by iommu drivers. These API + * calls are NOT to be used generally. + */ +#ifndef __LINUX_IOMMU_DRIVER_H +#define __LINUX_IOMMU_DRIVER_H + +#ifndef CONFIG_IOMMU_API +#error "CONFIG_IOMMU_API is not set, should this header be included?" +#endif + +#include + +struct iommu_probe_info { + struct device *dev; + struct list_head *deferred_group_list; + bool defer_setup : 1; +}; + +int iommu_probe_device_pinf(struct iommu_probe_info *pinf); + +#endif diff --git a/include/linux/iommu.h b/include/linux/iommu.h index c24933a1d0d643..cf578b8e0b59a4 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -43,6 +43,7 @@ struct notifier_block; struct iommu_sva; struct iommu_fault_event; struct iommu_dma_cookie; +struct iommu_probe_info; /* iommu fault flags */ #define IOMMU_FAULT_READ 0x0 @@ -347,6 +348,7 @@ static inline int __iommu_copy_struct_from_user( * @domain_alloc_paging: Allocate an iommu_domain that can be used for * UNMANAGED, DMA, and DMA_FQ domain types. * @probe_device: Add device to iommu driver handling + * @probe_device_pinf: New API for probe_device * @release_device: Remove device from iommu driver handling * @probe_finalize: Do final setup work after the device is added to an IOMMU * group and attached to the groups domain @@ -388,6 +390,7 @@ struct iommu_ops { struct iommu_domain *(*domain_alloc_paging)(struct device *dev); struct iommu_device *(*probe_device)(struct device *dev); + struct iommu_device *(*probe_device_pinf)(struct iommu_probe_info *pinf); void (*release_device)(struct device *dev); void (*probe_finalize)(struct device *dev); struct iommu_group *(*device_group)(struct device *dev); From patchwork Thu Nov 30 01:10:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 748726 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="XUtkMqgI" Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2053.outbound.protection.outlook.com [40.107.243.53]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B04F910DD; Wed, 29 Nov 2023 17:11:04 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=M8h+zVuDBdsEtD8H6TCgJA2MwLSAd/FjtymvxTMAqBuGb59SJb8zhULoxjPFymw/rSehI+9F97nRW90sYQl9orND7GYsSev+18N6mSFpbL4hyo9AoCDYHfrvZQrXO0h1U88QGcVw/2G8218vdEaTCv5i1px80jSALeQtnbeUk2Q3H88vwG5G0LO0FAu6o7s0nt3V0yxAC5SdGwS364wkd0HrAdKjqtJZqBZRHNLZw7uesqzKAKYw2aRTbAj2Ieo55XwT6C+JHogQqb7G/ATWBk7OF8qWkRzVwz1LQTcluBHV7JzsBiDO95gS2+jO9cvlXH3jEwuBs1hXzjo7uJ0WIA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=fwf/8BLazV78Ujjm7q8f4RCgFTKfbzZbel/RjT7b+os=; b=DTpFkSYFrAF65h7jTbnVQ4ztMHgT/lA6WKdxLpLCU27OwAo5qKbaeqk6SZzi4vFvpCXYgBR9Q8ZHQCWzl13XCc+3DZeKee6Y//PLgpGgfstRV6S1IXk4598LaAjIvltNSH5KnBRIGN4HEysDYU/xbvd4bTOrnBQ9Dst1/8FVMG+gAscXvoaDFipPgC+KKC+AcPBoLaqgTr9cnOw6SnBPFMpnGk0p8qOW3q8vQtXXI5fpYQl9Hizp5KPfeWl3EjeBxW5skw5ScMprHZzXFIv11Ut/DbGTyaW5jk8iLwEmFsKWCUxyL2Rji+I4s9N6a/lZEIR0l7VDpM2bW7o/Ub3Bzg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=fwf/8BLazV78Ujjm7q8f4RCgFTKfbzZbel/RjT7b+os=; b=XUtkMqgIGrf6ZOF3tXgS5FIQKR92exTcBtJzon6HxXDyLHQEWjyPB8XRh9c0wR1fr0ut4L2lW5IUwH4HEicNey7hsZel1YQxgWV7XgL4JwMloeI+L8SrGlJ4JBuGhMGIjmJLTfXiHsOJnCTfYPEf+h/1v1Hp71XFzqYl4T6IJe0A9KRDucrrFS9DHo61m8US4ZgPjVhGzLLJMPjCs4zgBhbR8rqJ4D4m5Q1+vKywoUMzrf0HVIDQPuyzfQtbpOUs2aTii23iUU1AIsNpoBBkQWj6Xd0wFY47k6rc6DP6fwf4fjweH4/8RKcSWHZzZgCb786HCs2HFl/3BQNUkvyGqw== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) by PH0PR12MB5484.namprd12.prod.outlook.com (2603:10b6:510:eb::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7046.24; Thu, 30 Nov 2023 01:10:54 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93%4]) with mapi id 15.20.7046.015; Thu, 30 Nov 2023 01:10:54 +0000 From: Jason Gunthorpe To: acpica-devel@lists.linux.dev, Andy Gross , Alim Akhtar , Alyssa Rosenzweig , Bjorn Andersson , AngeloGioacchino Del Regno , asahi@lists.linux.dev, Baolin Wang , devicetree@vger.kernel.org, Frank Rowand , Hanjun Guo , "Gustavo A. R. Silva" , Heiko Stuebner , iommu@lists.linux.dev, Jean-Philippe Brucker , Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Kees Cook , Konrad Dybcio , Krzysztof Kozlowski , Len Brown , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Lorenzo Pieralisi , Marek Szyprowski , Hector Martin , Matthias Brugger , Orson Zhai , "Rafael J. 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All drivers need a way to get the iommu_device instance the FW says the device should be using. Wrap the function with a macro that does the container_of(). The driver indicates what instances it accepts by passing in its ops. num_cells is provided to validate that the args are correctly sized. This function is all that is required by drivers that only support a single IOMMU instance and no IDs data. Driver's should follow a typical pattern in their probe_device: iommu = iommu_of_get_single_iommu(pinf, &rk_iommu_ops, -1, struct rk_iommu, iommu); if (IS_ERR(iommu)) return ERR_CAST(iommu); data = kzalloc(sizeof(*data), GFP_KERNEL); if (!data) return ERR_PTR(-ENOMEM); [..] dev_iommu_priv_set(dev, data); return &iommu->iommu; Signed-off-by: Jason Gunthorpe --- drivers/acpi/scan.c | 1 + drivers/iommu/iommu.c | 52 ++++++++++++++++++++++ drivers/iommu/of_iommu.c | 59 +++++++++++++++++++++++++ include/linux/iommu-driver.h | 85 ++++++++++++++++++++++++++++++++++++ 4 files changed, 197 insertions(+) diff --git a/drivers/acpi/scan.c b/drivers/acpi/scan.c index 9c13df632aa5e0..de36299c3b75bf 100644 --- a/drivers/acpi/scan.c +++ b/drivers/acpi/scan.c @@ -1570,6 +1570,7 @@ static int acpi_iommu_configure_id(struct device *dev, const u32 *id_in) const struct iommu_ops *ops; struct iommu_probe_info pinf = { .dev = dev, + .is_dma_configure = true, }; /* Serialise to make dev->iommu stable under our potential fwspec */ diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index 45e6543748fd46..ca411ad14c1182 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -3015,6 +3015,58 @@ struct iommu_device *iommu_device_from_fwnode(struct fwnode_handle *fwnode) return NULL; } +/* + * Helper for FW interfaces to parse the fwnode into an iommu_driver. This + * caches past search results to avoid re-searching the linked list and computes + * if the FW is describing a single or multi-instance ID list. + */ +struct iommu_device * +iommu_device_from_fwnode_pinf(struct iommu_probe_info *pinf, + const struct iommu_ops *ops, + struct fwnode_handle *fwnode) +{ + struct iommu_device *iommu = pinf->cached_iommu; + + if (!pinf->num_ids) + pinf->cached_single_iommu = true; + + if (!iommu || iommu->fwnode != fwnode) { + iommu = iommu_device_from_fwnode(fwnode); + if (!iommu) + return ERR_PTR( + driver_deferred_probe_check_state(pinf->dev)); + pinf->cached_iommu = iommu; + if (pinf->num_ids) + pinf->cached_single_iommu = false; + } + + /* NULL ops is used for the -EPROBE_DEFER check, match everything */ + if (ops && iommu->ops != ops) { + if (!pinf->num_ids) + return ERR_PTR(-ENODEV); + dev_err(pinf->dev, + FW_BUG + "One device in the FW has iommu's with different Linux drivers, expecting %ps FW wants %ps.", + ops, iommu->ops); + return ERR_PTR(-EINVAL); + } + return iommu; +} + +struct iommu_device *iommu_fw_finish_get_single(struct iommu_probe_info *pinf) +{ + if (WARN_ON(!pinf->num_ids || !pinf->cached_iommu)) + return ERR_PTR(-EINVAL); + if (!pinf->cached_single_iommu) { + dev_err(pinf->dev, + FW_BUG + "The iommu driver %ps expects only one iommu instance, the FW has more.\n", + pinf->cached_iommu->ops); + return ERR_PTR(-EINVAL); + } + return pinf->cached_iommu; +} + int iommu_fwspec_init(struct device *dev, struct fwnode_handle *iommu_fwnode, const struct iommu_ops *ops) { diff --git a/drivers/iommu/of_iommu.c b/drivers/iommu/of_iommu.c index 20266a8edd5c71..37af32a6bc84e5 100644 --- a/drivers/iommu/of_iommu.c +++ b/drivers/iommu/of_iommu.c @@ -138,6 +138,9 @@ int of_iommu_configure(struct device *dev, struct device_node *master_np, { struct iommu_probe_info pinf = { .dev = dev, + .of_master_np = master_np, + .of_map_id = id, + .is_dma_configure = true, }; struct iommu_fwspec *fwspec; int err; @@ -277,3 +280,59 @@ void of_iommu_get_resv_regions(struct device *dev, struct list_head *list) #endif } EXPORT_SYMBOL(of_iommu_get_resv_regions); + +struct parse_info { + struct iommu_probe_info *pinf; + const struct iommu_ops *ops; + int num_cells; +}; + +static struct iommu_device *parse_iommu(struct parse_info *info, + struct of_phandle_args *iommu_spec) +{ + if (!of_device_is_available(iommu_spec->np)) + return ERR_PTR(-ENODEV); + + if (info->num_cells != -1 && iommu_spec->args_count != info->num_cells) { + dev_err(info->pinf->dev, + FW_BUG + "Driver %ps expects number of cells %u but DT has %u\n", + info->ops, info->num_cells, iommu_spec->args_count); + return ERR_PTR(-EINVAL); + } + return iommu_device_from_fwnode_pinf(info->pinf, info->ops, + &iommu_spec->np->fwnode); +} + +static int parse_single_iommu(struct of_phandle_args *iommu_spec, void *_info) +{ + struct parse_info *info = _info; + struct iommu_device *iommu; + + iommu = parse_iommu(info, iommu_spec); + if (IS_ERR(iommu)) + return PTR_ERR(iommu); + info->pinf->num_ids++; + return 0; +} + +struct iommu_device *__iommu_of_get_single_iommu(struct iommu_probe_info *pinf, + const struct iommu_ops *ops, + int num_cells) +{ + struct parse_info info = { .pinf = pinf, + .ops = ops, + .num_cells = num_cells }; + int err; + + if (!pinf->is_dma_configure || !pinf->of_master_np) + return ERR_PTR(-ENODEV); + + iommu_fw_clear_cache(pinf); + err = of_iommu_for_each_id(pinf->dev, pinf->of_master_np, + pinf->of_map_id, parse_single_iommu, &info); + if (err) + return ERR_PTR(err); + return iommu_fw_finish_get_single(pinf); +} +EXPORT_SYMBOL_GPL(__iommu_of_get_single_iommu); diff --git a/include/linux/iommu-driver.h b/include/linux/iommu-driver.h index c572620d3069b4..597998a62b0dd6 100644 --- a/include/linux/iommu-driver.h +++ b/include/linux/iommu-driver.h @@ -13,25 +13,110 @@ #endif #include +#include +#include +struct of_phandle_args; struct fwnode_handle; +struct iommu_device; +struct iommu_ops; + +/* + * FIXME this is sort of like container_of_safe() that was removed, do we want + * to put it in the common header? + */ +#define container_of_err(ptr, type, member) \ + ({ \ + void *__mptr = (void *)(ptr); \ + \ + (offsetof(type, member) != 0 && IS_ERR(__mptr)) ? \ + (type *)ERR_CAST(__mptr) : \ + container_of(ptr, type, member); \ + }) struct iommu_probe_info { struct device *dev; struct list_head *deferred_group_list; + struct iommu_device *cached_iommu; + struct device_node *of_master_np; + const u32 *of_map_id; + unsigned int num_ids; bool defer_setup : 1; + bool is_dma_configure : 1; + bool cached_single_iommu : 1; }; +static inline void iommu_fw_clear_cache(struct iommu_probe_info *pinf) +{ + pinf->num_ids = 0; + pinf->cached_single_iommu = true; +} + int iommu_probe_device_pinf(struct iommu_probe_info *pinf); struct iommu_device *iommu_device_from_fwnode(struct fwnode_handle *fwnode); +struct iommu_device * +iommu_device_from_fwnode_pinf(struct iommu_probe_info *pinf, + const struct iommu_ops *ops, + struct fwnode_handle *fwnode); +struct iommu_device *iommu_fw_finish_get_single(struct iommu_probe_info *pinf); #if IS_ENABLED(CONFIG_OF_IOMMU) void of_iommu_get_resv_regions(struct device *dev, struct list_head *list); + +struct iommu_device *__iommu_of_get_single_iommu(struct iommu_probe_info *pinf, + const struct iommu_ops *ops, + int num_cells); #else static inline void of_iommu_get_resv_regions(struct device *dev, struct list_head *list) { } +static inline +struct iommu_device *__iommu_of_get_single_iommu(struct iommu_probe_info *pinf, + const struct iommu_ops *ops, + int num_cells) +{ + return ERR_PTR(-ENODEV); +} #endif +/** + * iommu_of_get_single_iommu - Return the driver's iommu instance + * @pinf: The iommu_probe_info + * @ops: The ops the iommu instance must have + * @num_cells: #iommu-cells value to enforce, -1 is no check + * @drv_struct: The driver struct containing the struct iommu_device + * @member: The name of the iommu_device member + * + * Parse the OF table describing the iommus and return a pointer to the driver's + * iommu_device struct that the OF table points to. Check that the OF table is + * well formed with a single iommu for all the entries and that the table refers + * to this iommu driver. Integrates a container_of() to simplify all users. + */ +#define iommu_of_get_single_iommu(pinf, ops, num_cells, drv_struct, member) \ + container_of_err(__iommu_of_get_single_iommu(pinf, ops, num_cells), \ + drv_struct, member) + +/** + * iommu_of_num_ids - Return the number of iommu associations the FW has + * @pinf: The iommu_probe_info + * + * For drivers using iommu_of_get_single_iommu() this will return the number + * of ids associated with the iommu instance. For other cases this will return + * the sum of all ids across all instances. Returns >= 1. + */ +static inline unsigned int iommu_of_num_ids(struct iommu_probe_info *pinf) +{ + return pinf->num_ids; +} + +/* + * Used temporarily to indicate drivers that have moved to the new probe method. + */ +static inline int iommu_dummy_of_xlate(struct device *dev, + struct of_phandle_args *args) +{ + return 0; +} + #endif From patchwork Thu Nov 30 01:10:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 748734 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="bt72uduo" Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2053.outbound.protection.outlook.com [40.107.243.53]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CD75E10D7; Wed, 29 Nov 2023 17:10:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=EHviIIoeYGnFvTiRuP4hmMzCpBC1erusmHD//dURo3osiQ0nIWcAKYj9QktHk8QAD2528PE6Iaxr0rh9kusTlu3cBF8VFa59X3Wj42yihuiNCwpWbW6W130YmiWjCyJeiEqFYehK4RJ7VPUoYTybGq54JsezFl2Uy3GwyvtkZNSyDdbiSKVDmzka53QMJ/HpXaephtgKiHH984q/H4snhUys/o20JceuJuzLb6ulbknWu48dUiTjtbWWTtclouSu9sIPcmTtfVrVaRJAh9S3xE2L55WiruJhYGLJ+kXULIQAecnXF1hUTVNa/jnPxJrYmZh+SG10g8DQBH5V5Ly68g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=pH0gW84gOXxliY71EzUBCEAqil4815K+q+c+KD8Jig0=; b=grpc2QHgqMoqmavTtArDjqOThLx6m0b+fwvSpt11L5rBUQ8m1b8/GVNTbYKtmE6mPpFengzd+x5wQdW9h6kVe11lj602EQ4Ob8e8FqHJTRiv+XBttyFoCRC0hvs2D4eH944nijo6/aY6SAUHdPXGDsd7fRpoBZ82QKHsS4dDNdtvMMkAsOKe17dj+j1cCXYmpZh/njJxZqoWaPq6OycqUQMq4BVt99lCuwu0wgmCgEvwul8HxYE2GFiGYXJWrgJ8W9ct+C/U3XLWARtDPQdnj/OU9On9inFcXVWWT+QTKR+FK2sRHC1WdzX7+Jgm1F8L25R+XspdXz+hJQiP2ZzsZw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=pH0gW84gOXxliY71EzUBCEAqil4815K+q+c+KD8Jig0=; b=bt72uduozeMkhtIrVviUsicUctr6C6o5YJ0GvT3SQhYkQAZN+9Sz3IVs7fJ0MsiXt8wQ0+PGWpczdvbt92fHpO8F1JMaivnwyVFT5dGfxCHUNPPvL3tcQQjP4MIhuJvKKNLdPcxUtaHKUGbL4KJxSk1PKnBfD18lweBTSV2MSIzwmdLycn0lo9RagI5nHtZQB24eZzsnfYINr8I2YVMqhSnT8Ua36PUdIU7XZCtAnfcoikbWOSWPKEBNY2WC/dMR7nEqoXKOC1et/tsDB4zwGwSZ1kOdDIYf6LsGYruWtiwurhiyLOnKOBI+f4+XsgTlmErQrA/bnOnzpLkMYWLfaQ== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) by PH0PR12MB5484.namprd12.prod.outlook.com (2603:10b6:510:eb::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7046.24; Thu, 30 Nov 2023 01:10:47 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93%4]) with mapi id 15.20.7046.015; Thu, 30 Nov 2023 01:10:47 +0000 From: Jason Gunthorpe To: acpica-devel@lists.linux.dev, Andy Gross , Alim Akhtar , Alyssa Rosenzweig , Bjorn Andersson , AngeloGioacchino Del Regno , asahi@lists.linux.dev, Baolin Wang , devicetree@vger.kernel.org, Frank Rowand , Hanjun Guo , "Gustavo A. R. Silva" , Heiko Stuebner , iommu@lists.linux.dev, Jean-Philippe Brucker , Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Kees Cook , Konrad Dybcio , Krzysztof Kozlowski , Len Brown , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Lorenzo Pieralisi , Marek Szyprowski , Hector Martin , Matthias Brugger , Orson Zhai , "Rafael J. Wysocki" , Rob Clark , Robert Moore , Rob Herring , Robin Murphy , Samuel Holland , Sudeep Holla , Sven Peter , Thierry Reding , Krishna Reddy , virtualization@lists.linux.dev, Chen-Yu Tsai , Will Deacon , Yong Wu , Chunyan Zhang Cc: =?utf-8?q?Andr=C3=A9_Draszik?= , patches@lists.linux.dev Subject: [PATCH 09/30] iommu/rockchip: Move to iommu_of_get_single_iommu() Date: Wed, 29 Nov 2023 21:10:16 -0400 Message-ID: <9-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> In-Reply-To: <0-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> References: X-ClientProxiedBy: SN6PR16CA0043.namprd16.prod.outlook.com (2603:10b6:805:ca::20) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|PH0PR12MB5484:EE_ X-MS-Office365-Filtering-Correlation-Id: fc7ed155-37f1-4855-5c7a-08dbf1412b4e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: umO1ddYmJzHiPe/jglh3QVymxKzgOl3MVjcBhSWQDjWMRKWR8HZVwrI79C7ISCJr9SqH/28vyXDldPiqHoxK4wjKpDqIRfITgrO1HNCUqi+cqE3NfriRJMPlCMD737cdyI2IywQiD2HW2l3RV06Axv5ENsUPcDtd7WeW+PRLqh0p4Nyj9tMR5O+U/kK3lfsVhijwxxPkdyxR6FByxCIN6XssDr1ncHGfbXl+fvaiyBwVQGWCYvzBcJ4EH3og85kOP6+YebkGlapaQNdMEWDR5fUine7h0o57M8K+ZTYLHBJN3tSlX0S5qlvIfQXBmptAjdqq76AXo+if7d1cXg/Vi1F2AmIRlwvgNEO/Vbxi/byaz9tfWho0USuyrmtjec0a8Cu6tbCRAOm/cBZRAgUaIrzgkA/iCyy9NtHqunAVHrE0XsEXfhUj8OzKPrY6z85T6BYeJJFyAeXTuzAUR2fMPieYLQDs2kqEjay3aW0cV3rgNDDdapLoHCY6UnDIJV9EUyOHbKNPHChT2S/rUdFuR7b0aTjrXaghzPn4wGtyUS8i6fKHUiy6ZDX4BoT8zGcKvjierkteLZ9f8wpmxqG49KIf1byjgxkK8cQD7QtFttKijq/LkAW6mjLVdhWMGOCW/6Jh6gpuEmpOpDGc8pOav6AnI+iJvTCV6sNT467zjMs= X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:LV2PR12MB5869.namprd12.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230031)(366004)(346002)(136003)(396003)(39860400002)(376002)(230922051799003)(451199024)(1800799012)(186009)(64100799003)(1191002)(8936002)(110136005)(8676002)(316002)(66556008)(4326008)(86362001)(66476007)(6486002)(478600001)(66946007)(41300700001)(36756003)(921008)(7416002)(7366002)(2906002)(7406005)(5660300002)(38100700002)(2616005)(6512007)(6506007)(6666004)(83380400001)(26005)(202311291699003)(4216001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: RvweIR4IeBPVT59G+mnbsZU6UEVqLrPN3J6FlzJYjO7J+iz1H9Ah/TTZnpLVbzzXdnsYfu73hOvVyIhyFFy2Y9iAVTmQOGBNtfiNqHatKLecwWkvRnGucJYl6ayVdDsEhu6c09vb6JX0jl/6ylYdM5BnKZHVZMExj+31UkSpqyN2FuU5uT2Xr90Ueo0jXA2Z03kTEU8ch32Daa+DHzVEBQgRavFpjPYfxw5GRN2DMKctlHfmDFTmqw1mRmxXrKmQxuow1xsXgnt6IVv2HLHLfEV6J5u1iWc3eX0RFwewgApDZKmbxceJxhnuc0WMwnkzRKtis8NmuvwPf0/iTYocY1FXnBQMmQZVDu1YYw0bgiWqcbhhxouju/phOCCPrif2M0x8xucKxsDN1fjHrSKbJIrsyfaPlYahaJAdhgdvt0N+bbbSCcud2mG3QNAxEyZZiJ4aL184Yk4Zd88dgS6DA6T9o2uGWdhQLG/bOKomviLNB5exuz9DaGsBlXCQs7430xqlvDvrGsZ1/mQ1zoqyunFnNfny8Kou2tXkB3/vYaQ4/qTYAVWVuWsF+QGKpktcPneGCR5n7RGeeB4xV1Yh1m4b9hz5c23dJhHEA5a7RqEWhMMm2GNBSKL+tczXWR7OJYloObO47zOY3IBp+qWaoIXXLAmE7e7yqh1h+lVJUgGWuF35ywfY+uhqb/44D8xTB/TnYBIE4yoeiq1AjP9XQzew3lYb47TrHhWG7a57SHpabRxwdHJzlLFsCp6qWdS7TTjMYgp3Mb5TiYlRclucUXccEh/OhDKbShwAgWkBcCO6R4OCxIwWsSdVhYtaUiBkwAoGZY1sb0fD0Bq9TpDj7oyB4j6Nkm1uCcdbtCaz9GNCAOGCKHmogx610igV0IfQfp8uknMZkaDo6EcP4BHPC0/jdpMfRNgvvgMwSyqAwJQj/v7JQXXQ1l19Fp8hOKI/hYJMhq0+B3t4WbpGYuKWyrOEtTzE7hNq1vUJeLfVejwY710Xd4mb2UZrmrZyL+e35o8YcnGMnCwakua1HE94aRpW0sTilCvXyoTZGMkFmJXMUvTF7YJ2nYBRnzgeGrgcmaKpbL3tqtPt1HtwwNPnOyR7e1sFaip6WXk84n9Ci5NiYzdpKxo5ycWSzfSmeVlfe7p+yaYLSWVmH5/0GKCH+Td3zX2OXiEc4yK0DBYRQNfPww5KCYBUfMPTn+jTaGAjyXunmxpKxKVL8qkexOOVeEIOrp9RhbO0qRfnjH2yuZaEL2Ex85uF1huZMYmdsAym1TA5/HArddMm8fheg5PcwfD23SIPODEvBaumCKG2tTTFWcCdcCZ6B/BVKf0yXNzelhSF1EUIPbM3a1VaRWG1jK9wY12IIqkypXGcsARUQ8cBzBvRpn3OnspuU7z4+nV0P7vklV94icGGoExM5hxz/RShanrOe5mUGc8dt1fPi/77DPNR8ksydGyBX/CSpVWg+KLHtR/u++VBpfPB95h/3vBI9iMbswdR4273IB0fw9RKasdHtw+MqMsJjdI0idrWTtSQIdXIqD5yz+7fuL9KptqecViBCNaE4iZQwJTPGd8D5aTKbWX3FPdzKxCVvKbl X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: fc7ed155-37f1-4855-5c7a-08dbf1412b4e X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2023 01:10:40.7378 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: PVtzl/qCMXCu7rm7n3eTwSdj/9QrQ5oeVSrwEHZuO+Yjour4vrdh6fDtSjtcF5io X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB5484 rockchip supports a single iommu instance and does not support multiple IDs. Move the per-device allocation from rk_iommu_of_xlate() and completely delete rk_iommu_of_xlate(). The iommu instance is obtained via iommu_of_get_single_iommu(). Don't use devm to manage the lifetime of the per-device data, this just results in memory leaking if there are probe error/retry paths. Use the normal lifecycle with alloc in probe_device and free in release_device. The comment about "virtual devices" seems out of date. With today's code the core will not call attach_device/detach_device unless dev->iommu is set and has an ops. This can only happen if probe_device was done. Remove the checks. Signed-off-by: Jason Gunthorpe --- drivers/iommu/rockchip-iommu.c | 74 +++++++++++----------------------- 1 file changed, 24 insertions(+), 50 deletions(-) diff --git a/drivers/iommu/rockchip-iommu.c b/drivers/iommu/rockchip-iommu.c index 2685861c0a1262..4cff06a2a24f74 100644 --- a/drivers/iommu/rockchip-iommu.c +++ b/drivers/iommu/rockchip-iommu.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -123,6 +124,7 @@ struct rk_iommudata { static struct device *dma_dev; static const struct rk_iommu_ops *rk_ops; static struct iommu_domain rk_identity_domain; +static const struct iommu_ops rk_iommu_ops; static inline void rk_table_flush(struct rk_iommu_domain *dom, dma_addr_t dma, unsigned int count) @@ -896,13 +898,6 @@ static size_t rk_iommu_unmap(struct iommu_domain *domain, unsigned long _iova, return unmap_size; } -static struct rk_iommu *rk_iommu_from_dev(struct device *dev) -{ - struct rk_iommudata *data = dev_iommu_priv_get(dev); - - return data ? data->iommu : NULL; -} - /* Must be called with iommu powered on and attached */ static void rk_iommu_disable(struct rk_iommu *iommu) { @@ -958,16 +953,12 @@ static int rk_iommu_enable(struct rk_iommu *iommu) static int rk_iommu_identity_attach(struct iommu_domain *identity_domain, struct device *dev) { - struct rk_iommu *iommu; + struct rk_iommudata *data = dev_iommu_priv_get(dev); + struct rk_iommu *iommu = data->iommu; struct rk_iommu_domain *rk_domain; unsigned long flags; int ret; - /* Allow 'virtual devices' (eg drm) to detach from domain */ - iommu = rk_iommu_from_dev(dev); - if (!iommu) - return -ENODEV; - rk_domain = to_rk_domain(iommu->domain); dev_dbg(dev, "Detaching from iommu domain\n"); @@ -1003,19 +994,12 @@ static struct iommu_domain rk_identity_domain = { static int rk_iommu_attach_device(struct iommu_domain *domain, struct device *dev) { - struct rk_iommu *iommu; + struct rk_iommudata *data = dev_iommu_priv_get(dev); + struct rk_iommu *iommu = data->iommu; struct rk_iommu_domain *rk_domain = to_rk_domain(domain); unsigned long flags; int ret; - /* - * Allow 'virtual devices' (e.g., drm) to attach to domain. - * Such a device does not belong to an iommu group. - */ - iommu = rk_iommu_from_dev(dev); - if (!iommu) - return 0; - dev_dbg(dev, "Attaching to iommu domain\n"); /* iommu already attached */ @@ -1115,20 +1099,30 @@ static void rk_iommu_domain_free(struct iommu_domain *domain) kfree(rk_domain); } -static struct iommu_device *rk_iommu_probe_device(struct device *dev) +static struct iommu_device *rk_iommu_probe_device(struct iommu_probe_info *pinf) { + struct device *dev = pinf->dev; struct rk_iommudata *data; struct rk_iommu *iommu; - data = dev_iommu_priv_get(dev); - if (!data) - return ERR_PTR(-ENODEV); + iommu = iommu_of_get_single_iommu(pinf, &rk_iommu_ops, -1, + struct rk_iommu, iommu); + if (IS_ERR(iommu)) + return ERR_CAST(iommu); + if (iommu_of_num_ids(pinf) != 1) + return ERR_PTR(-EINVAL); - iommu = rk_iommu_from_dev(dev); + data = kzalloc(sizeof(*data), GFP_KERNEL); + if (!data) + return ERR_PTR(-ENOMEM); + data->iommu = iommu; + data->iommu->domain = &rk_identity_domain; data->link = device_link_add(dev, iommu->dev, DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME); + dev_iommu_priv_set(dev, data); + return &iommu->iommu; } @@ -1137,37 +1131,17 @@ static void rk_iommu_release_device(struct device *dev) struct rk_iommudata *data = dev_iommu_priv_get(dev); device_link_del(data->link); -} - -static int rk_iommu_of_xlate(struct device *dev, - struct of_phandle_args *args) -{ - struct platform_device *iommu_dev; - struct rk_iommudata *data; - - data = devm_kzalloc(dma_dev, sizeof(*data), GFP_KERNEL); - if (!data) - return -ENOMEM; - - iommu_dev = of_find_device_by_node(args->np); - - data->iommu = platform_get_drvdata(iommu_dev); - data->iommu->domain = &rk_identity_domain; - dev_iommu_priv_set(dev, data); - - platform_device_put(iommu_dev); - - return 0; + kfree(data); } static const struct iommu_ops rk_iommu_ops = { .identity_domain = &rk_identity_domain, .domain_alloc_paging = rk_iommu_domain_alloc_paging, - .probe_device = rk_iommu_probe_device, + .probe_device_pinf = rk_iommu_probe_device, .release_device = rk_iommu_release_device, .device_group = generic_single_device_group, .pgsize_bitmap = RK_IOMMU_PGSIZE_BITMAP, - .of_xlate = rk_iommu_of_xlate, + .of_xlate = iommu_dummy_of_xlate, .default_domain_ops = &(const struct iommu_domain_ops) { .attach_dev = rk_iommu_attach_device, .map_pages = rk_iommu_map, From patchwork Thu Nov 30 01:10:17 2023 Content-Type: text/plain; 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Received: from LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) by DS0PR12MB7607.namprd12.prod.outlook.com (2603:10b6:8:13f::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7046.22; Thu, 30 Nov 2023 01:10:43 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93%4]) with mapi id 15.20.7046.015; Thu, 30 Nov 2023 01:10:43 +0000 From: Jason Gunthorpe To: acpica-devel@lists.linux.dev, Andy Gross , Alim Akhtar , Alyssa Rosenzweig , Bjorn Andersson , AngeloGioacchino Del Regno , asahi@lists.linux.dev, Baolin Wang , devicetree@vger.kernel.org, Frank Rowand , Hanjun Guo , "Gustavo A. R. Silva" , Heiko Stuebner , iommu@lists.linux.dev, Jean-Philippe Brucker , Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Kees Cook , Konrad Dybcio , Krzysztof Kozlowski , Len Brown , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Lorenzo Pieralisi , Marek Szyprowski , Hector Martin , Matthias Brugger , Orson Zhai , "Rafael J. Wysocki" , Rob Clark , Robert Moore , Rob Herring , Robin Murphy , Samuel Holland , Sudeep Holla , Sven Peter , Thierry Reding , Krishna Reddy , virtualization@lists.linux.dev, Chen-Yu Tsai , Will Deacon , Yong Wu , Chunyan Zhang Cc: =?utf-8?q?Andr=C3=A9_Draszik?= , patches@lists.linux.dev Subject: [PATCH 10/30] iommu/sprd: Move to iommu_of_get_single_iommu() Date: Wed, 29 Nov 2023 21:10:17 -0400 Message-ID: <10-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> In-Reply-To: <0-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> References: X-ClientProxiedBy: SN1PR12CA0079.namprd12.prod.outlook.com (2603:10b6:802:21::14) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|DS0PR12MB7607:EE_ X-MS-Office365-Filtering-Correlation-Id: 14aed4a1-bf58-47eb-12ad-08dbf1412b13 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: W5Nxve/hqSj2fuhMm2GUE8Ugqq65w6lrhvAxJlDuYQAoascTZndUawxgYmMzPHUTROjaxA17hQEA1WAPy+gO1UeMF1jbAXKWgYt2iqL9YM6PyhRidYbqWuw0SXYp5rrrekwfvsduFWkgME8qJ8L2B6hZViLqSHqyBJzIkqRIHXGcGG8UqHIiXZeJdhq0S/ZiTbfdXC6UeZ4HcMXitUVnf2+RpEkQO9ZtW4Omer9YmPz26v4eZHDaVhkk1ZCq/YOt0JGDxQSpNNZKDnnm1QmPaPhjajk4x9R500US9vnR6Bk7e+z3DRo+sZyjfISmuxrLSUIxcGkpgPu0gY5OSRcDTV0/lU2MCJuQASBxx5ZxIGiAvXAJDgL9jmoAAFgwyBfVoTxS65dkMzhuelOVPoMe1nzSq8HWy1bVuDPYyhnTsEhKtvA+ICAI4GiwZ6yhBsAszJzHJyUoAInLT03gQRbzo8Uh8oz5bkxxEwc0lix2/WNL00WryIpk2SfjSCwPMmLMeQ2VsHcZ+4FyjJ0lZ7K8lEsqdhfU5pvYEMTRRen8dPhOFV2IxXRVI7tuHM/5AZxrhMlCV2np7AD/VRIzrd5NFMgaRrJHpmcR4iXOVU5hyb/zzRfbKPnOv1xAoLtjr02ZYpYx2ZrTLhd4jwPWuULtyQ== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:LV2PR12MB5869.namprd12.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230031)(396003)(39860400002)(346002)(136003)(366004)(376002)(230922051799003)(186009)(451199024)(64100799003)(1800799012)(38100700002)(202311291699003)(83380400001)(1191002)(5660300002)(110136005)(2906002)(86362001)(4326008)(8676002)(8936002)(66556008)(7366002)(7406005)(7416002)(66476007)(66946007)(6486002)(478600001)(6666004)(316002)(36756003)(6506007)(41300700001)(6512007)(921008)(26005)(2616005); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 5j5KbY0xHJ94YSN0oEFEhn+lLo7j7xo7/c6H3tHrg1HpeRqz4yUGA4TZ8Y233YrbRcuowllYoHvNBVkulCaqkMi58Gsoiz+HgOEOAuyaCAgtiXJvp64j4+fc6VrfezNBuKgPTnglm++deyPCIVlBg4w3ejnuUEZWJ8zY8orQLQ8L7yPenUVDk3BaRmdv5aaxBJiD4RgQ9nGxUZGR3ESi9+U09Q8A/ucxmwSESdpmK1yAwm9aPS0EOoSJJm3ijCJ1wwVzyxw5iDGLft6D7LWsxFnyNM51Brqdxn+ROdNuWB2+tl5bGn2uNxkfEOW/n87Q6sxbDlTHaa7/Qj8teTNK3Z3vURZ6ep7Plf3BK5/Wc3ZOQLAb/IepDYWRhHOZ5Iz+KIIxdq+OlX7jpv/twzd2zlxSVOMsE5fcMs8tRCQKo2dGCVs/GqhlXJT0ltmSmLvsy7k6g+Wr44gEjDQzLs1hHhXMJURG723ilhrEWNFn00SjpXxsYkLN4AJkMlPhgKV7uIKPNtWWPvaWt3OXZIRtMqpjc3arlZbAJhUFADkBO5yg8l9gPrvNQreQ0GxT5Qd5H80nur9MwYqHkcW9LCA5cUep5W2KuXytJ2aDkxR6544c+3B1MqzMvZuSDvJr1WvFH3ky3ljJ7BXczj9OTUw9A4e1X/3FGxQwqLmdwxXnOcnUFUUp1zFVKMNXCdzOAFwmPeaMRCg+eCUvaFH8krz7geNKxcCXV2k+iME5rTDdYPP1GebTGbsI30y7FFNhQ+NmcddyY5V4wdhA/ioHoMONjrhz8Ba9tGC/EkW0qGnqWUTQvdal0frVd7b1zOoN+g92c64KIYLW252azzq6SkwzNdI2z9+NxzZOM+/IX13KzFg4TIKJWMqcYlNOtBiicijYOmda4+SfdWF9ehMUb9LmkX3ZwB+5qye030ZLU84zwhy+nSkEU+9dEpJcOnX622KlG23KAY/EkZCDzMyL+0Dvb9u5ZfZxtdYq2zJnSbX0cJP6TjgL/7czlfa/8T5BuQu7NI9YrCroiEygbECFa0W6FKK2siugg/K9sHHqpts2XVDQJr2LBnOvVTQWsFWiH8/PL/whAGzvux+9zzOBIbBkkzCERlqQ4ocUEU7JVf6mUb466rarda8fc2vtEnLs/hh8ZJFR3HPpB5+QiK24qqN2A5HIvDHRbh+awlASW5abf+NZwIEeHjk7LwsPIxJCbd2lkP/rKvO1dlEXGUansYFblkgUWBARmlTcr/WqY+Kp15dBmFx/5i+82GuVsAdkOLygWMqjxXta0Xr4H1weIQQ0rVlrpFFf9DrCAZNKu1uzZaImIaS0gOWGXrVCPpx8iCDYfXq601fIPKfNV+/3RKLM/94io/A2Tca2msLl7Om2/XDoqRSUuFl7ncHEvDvFNu6OoPNCiKX3rWpwx7P/1OzYOnrVhy0TC2zZcmbSm5zbsZw6y22HqjEkkS+gWu3UBq3H6+el0LGPBOWDnD0FwW6C4r4WAgkHsGw/4MNSEmBoHq/R4NVfcotafuKDhLVjYHJmZgFad/SbnxPrqVJqtzlf99+mhkLt22RJ6t8irn8YBrPQCLETf6EIBZpYrDbBNj// X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 14aed4a1-bf58-47eb-12ad-08dbf1412b13 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2023 01:10:40.1895 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: RImw/klw6uR5u3kIEI5FDYwuyW8PkAy+C/GVi680wwYw6hU0nSKvh/ViUO5uWBs7 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7607 sprd suports a single iommu instance and only a single id. Parse it directly using iommu_of_get_single_iommu() and remove sprd_iommu_of_xlate(). It stores the iommu, not a per-driver struct in the dev_iommu_priv(), keep it that way for now. Signed-off-by: Jason Gunthorpe --- drivers/iommu/sprd-iommu.c | 32 ++++++++++++++------------------ 1 file changed, 14 insertions(+), 18 deletions(-) diff --git a/drivers/iommu/sprd-iommu.c b/drivers/iommu/sprd-iommu.c index 537359f109979b..f1b87f8661e199 100644 --- a/drivers/iommu/sprd-iommu.c +++ b/drivers/iommu/sprd-iommu.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -383,32 +384,27 @@ static phys_addr_t sprd_iommu_iova_to_phys(struct iommu_domain *domain, return pa; } -static struct iommu_device *sprd_iommu_probe_device(struct device *dev) +static struct iommu_device *sprd_iommu_probe_device(struct iommu_probe_info *pinf) { - struct sprd_iommu_device *sdev = dev_iommu_priv_get(dev); + struct sprd_iommu_device *sdev; + + sdev = iommu_of_get_single_iommu(pinf, &sprd_iommu_ops, -1, + struct sprd_iommu_device, iommu); + if (IS_ERR(sdev)) + return ERR_CAST(sdev); + if (iommu_of_num_ids(pinf) != 1) + return ERR_PTR(-EINVAL); + + dev_iommu_priv_set(pinf->dev, sdev); return &sdev->iommu; } -static int sprd_iommu_of_xlate(struct device *dev, struct of_phandle_args *args) -{ - struct platform_device *pdev; - - if (!dev_iommu_priv_get(dev)) { - pdev = of_find_device_by_node(args->np); - dev_iommu_priv_set(dev, platform_get_drvdata(pdev)); - platform_device_put(pdev); - } - - return 0; -} - - static const struct iommu_ops sprd_iommu_ops = { .domain_alloc_paging = sprd_iommu_domain_alloc_paging, - .probe_device = sprd_iommu_probe_device, + .probe_device_pinf = sprd_iommu_probe_device, .device_group = generic_single_device_group, - .of_xlate = sprd_iommu_of_xlate, + .of_xlate = iommu_dummy_of_xlate, .pgsize_bitmap = SPRD_IOMMU_PAGE_SIZE, .owner = THIS_MODULE, .default_domain_ops = &(const struct iommu_domain_ops) { From patchwork Thu Nov 30 01:10:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 748728 Authentication-Results: smtp.subspace.kernel.org; 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Received: from LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) by PH0PR12MB5484.namprd12.prod.outlook.com (2603:10b6:510:eb::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7046.24; Thu, 30 Nov 2023 01:10:53 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93%4]) with mapi id 15.20.7046.015; Thu, 30 Nov 2023 01:10:53 +0000 From: Jason Gunthorpe To: acpica-devel@lists.linux.dev, Andy Gross , Alim Akhtar , Alyssa Rosenzweig , Bjorn Andersson , AngeloGioacchino Del Regno , asahi@lists.linux.dev, Baolin Wang , devicetree@vger.kernel.org, Frank Rowand , Hanjun Guo , "Gustavo A. R. Silva" , Heiko Stuebner , iommu@lists.linux.dev, Jean-Philippe Brucker , Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Kees Cook , Konrad Dybcio , Krzysztof Kozlowski , Len Brown , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Lorenzo Pieralisi , Marek Szyprowski , Hector Martin , Matthias Brugger , Orson Zhai , "Rafael J. Wysocki" , Rob Clark , Robert Moore , Rob Herring , Robin Murphy , Samuel Holland , Sudeep Holla , Sven Peter , Thierry Reding , Krishna Reddy , virtualization@lists.linux.dev, Chen-Yu Tsai , Will Deacon , Yong Wu , Chunyan Zhang Cc: =?utf-8?q?Andr=C3=A9_Draszik?= , patches@lists.linux.dev Subject: [PATCH 11/30] iommu/sun50i: Move to iommu_of_get_single_iommu() Date: Wed, 29 Nov 2023 21:10:18 -0400 Message-ID: <11-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> In-Reply-To: <0-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> References: X-ClientProxiedBy: SN6PR08CA0012.namprd08.prod.outlook.com (2603:10b6:805:66::25) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|PH0PR12MB5484:EE_ X-MS-Office365-Filtering-Correlation-Id: 202f467c-ccd0-4067-7ecf-08dbf1412c4e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: wDaTT+ItBQkwfzcOkVg2Mm6eY2SM6MzCUmBpSQHf6eTxjKudDQ3FJrLtC7843i5IRrcwn8Wp3kyfu6/Yh11FUDQgsLe09RbqFC9c2+iHarhPjCgkaI2RwUCtNnHyx1f2GX4soqsXrPW3tZjeHuhABq1xMhcgDnPvrLZmLnuXL2YUzE6qEmHYTRhSCwDecEzEQqk3k0mZwtI9954N7vcDEfs3+s9793mSLR4FCD88WcYY3N9tSP7mTocrA7xWY9eF6jrtozd+HQst/hJospZz6+END6XGVPatK4VBOXB+imY7adaFenJ0MD1QGaumMJitErYRDwzrgCZmy418ZXqH30+cb/9zNzH/WcPrjxVK6W3kB0g6I70noY3NnRRyoT+NB7EWk3sYMVTq8fa6KlOPD9Pdxw/aOkJBCKwhLrM7al2n1j/5h3LbnyhJv+auY8lm0VOMlHMs97bHEXNDGBCVdGQcdHjui/H76ko5oarfbYDoF1fWy3AMooL7COYFS0X0YRtuzPAU+5RhjGp++wmJmXcNTrW38ZWCR1NwdSydhfmm8OyAUTknpAzEaWoLPV75JG8gvtcRUxLH8XQmiu9vkE7ux9a9ykBt+G4RepwDKzVS2XNyaYMOAz4Zl7eop97FzmS+T70+iRR9y9s9Oo4HCw== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:LV2PR12MB5869.namprd12.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230031)(366004)(346002)(136003)(396003)(39860400002)(376002)(230922051799003)(451199024)(1800799012)(186009)(64100799003)(1191002)(8936002)(110136005)(8676002)(316002)(66556008)(4326008)(86362001)(66476007)(6486002)(478600001)(66946007)(41300700001)(36756003)(921008)(7416002)(7366002)(2906002)(7406005)(5660300002)(38100700002)(2616005)(6512007)(6506007)(6666004)(83380400001)(26005)(202311291699003); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: wWcuxQ+bqZ5gr7soEwznyBgBycyNZqXKcFDlwc7STj6auYzuzroGafPTSpivIwLxcXuyAoaQVLZ6IfPMCSvSqVvc+2/M0h6wJLXdgA9MQBYFSH+z/3Evzra7w2Aqf3rzO82n4GtdJo5pb0Eq1lCLtr/+m0yPelra2eVek7ZBOxGFOrDvAsLk89czFKtigbQw3ogWsAgRjTlhJsLudryGaq97tLfKg+GvnVP3aqsxJvMJGR1Ti7Ky2fr+8RoRNWeDguYNt7XHSrsnCzy4oGVUHJFPsaa4rmt51GZ6/BLrhv5o+0/B37CBhFKeLNT6Y72w8hkl7sMZ1Qf+lpZOW0dSNxXnS/Fd7nLg0wfFe6BgFjUfo8grRg2Vik/WiqLn6mQnvMvWvkFac0l9Vww722EeE/Nm1W4+q/OEurTFfwrw2qldfQL5up6pTVSGf1tH+6Ppx1DFeXBd93LkHUb6bCddqBslvFnev1DhIc+t6rSPBiiM0wo8cXd+4mVrV582BsXOfvXucezKbMBNAc6qMH+SmEioDZSPJbCRJTkiA1lb3hfhH6Lq/Zivt2j8DugFo7YyFOXu8/JZDd2sgUonx0LqVPmIhxq6sC43aMFfoDNB4sB0VYfHE6ZcuEWDEszyrahpHYVlcSAPvL5VNHi1In/X9EiFfaDGEGgVSo7++9gG0iuPro3R566N3C8ftrSJtrOmpbzTmRxeNfzAB5rnhxyfwxaYxvAkFL1ST4d1+4FjfYWJEDiDNGRQ/AkgiRb5e93aPtRQ6eWAtFsl9mTmtbcvc0WR2WJ95frA0979Zjmch18U7McnZ+4CthhaHY8uHBWuwq2/q2T/CtdfxFtbjx/7zD6eAMoUQ0E+1klw9aFI4pTv8bsev37W24cWlQAD5ntr9IxlfEGWWe3Es1c1zpCWeMjmAKi/3Yz2dEk9DGKyjfuzzYdO/bIY8RcmvzfylpnHKVsIqdSm863AKsFlR7UC93lbZsHYDepY3BZFmFVhYwdxDGp28dfW9luiELXOa+j0ZyaMK3J/9/14i3VaH6sULWA1dZoqy0YJBAMgOpcKD9GZ63TzlLG1Z9s36cUvswWBuYOrUEtfaN69cnXinClrdVVr1nK13HJSIgpP1OkiIpGPr7PZo+FaxwU0wDIVJtl9slL8E1pDe3fnelSGlGSfuA8fvLNbnl5trv+hgofCTicScRguIIQvEV0XS/gCsnKj944zUANMLSugalmGuGAuLHTE5kCWQPI4BHaiShXbAemH+QBVCNNWaFI+5YotCOVM3721IVlPIQWd25ANil9kSiX7IyXalWLP6O88+YoTgbG6+mrUS0oQFffU+R9YXI62lfgmd9Uk1HzljQm4tn6nCCc/FmROrOo/Ueqz6Im6pDAO7mPOQKT4ToaPakFOfgJEUVTe0n1CBZSHwzug5Qjmkc5dTRG+W5TrWQA/oa7bn6YYSV/Wr9iJSWVmGVVPAng+YHBcOpQJ4MYNTHNeBh6vumTi0y6mdUtAD9KPgo3I0eBCtQpAwBP8EdehOjkdPFIOMX39FvxKwZjRaIKs9+alpM5iW5h9pqHqgw2wb2g7IPGhxJ5hW1GLk/3ZOdArN+Vp X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 202f467c-ccd0-4067-7ecf-08dbf1412c4e X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2023 01:10:42.2642 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: iBIHLWUjNcLd7jknHW9Ss0txa1WTmqIItJzPMglQflJMXkc9yvM+62hk/Nml2vr3 X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB5484 sun50i uses a simple binding where a the OF iommus's can describe a single iommu instrance with a single ID, reflecting the master, on it. The driver ignores the ID from the OF, it looks like the instance can only do a single translation as the entire thing is managed with generic_single_device_group(). Since there is a single translation the ID presumably doesn't matter. Allocate a sun50i_iommu_device struct during probe to be like all the other drivers. Signed-off-by: Jason Gunthorpe --- drivers/iommu/sun50i-iommu.c | 60 +++++++++++++++++++++--------------- 1 file changed, 36 insertions(+), 24 deletions(-) diff --git a/drivers/iommu/sun50i-iommu.c b/drivers/iommu/sun50i-iommu.c index 41484a5a399bb1..84038705cf657d 100644 --- a/drivers/iommu/sun50i-iommu.c +++ b/drivers/iommu/sun50i-iommu.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -95,6 +96,8 @@ #define SPAGE_SIZE 4096 +static const struct iommu_ops sun50i_iommu_ops; + struct sun50i_iommu { struct iommu_device iommu; @@ -110,6 +113,10 @@ struct sun50i_iommu { struct kmem_cache *pt_pool; }; +struct sun50i_iommu_device { + struct sun50i_iommu *iommu; +}; + struct sun50i_iommu_domain { struct iommu_domain domain; @@ -128,11 +135,6 @@ static struct sun50i_iommu_domain *to_sun50i_domain(struct iommu_domain *domain) return container_of(domain, struct sun50i_iommu_domain, domain); } -static struct sun50i_iommu *sun50i_iommu_from_dev(struct device *dev) -{ - return dev_iommu_priv_get(dev); -} - static u32 iommu_read(struct sun50i_iommu *iommu, u32 offset) { return readl(iommu->base + offset); @@ -760,7 +762,8 @@ static void sun50i_iommu_detach_domain(struct sun50i_iommu *iommu, static int sun50i_iommu_identity_attach(struct iommu_domain *identity_domain, struct device *dev) { - struct sun50i_iommu *iommu = dev_iommu_priv_get(dev); + struct sun50i_iommu_device *sdev = dev_iommu_priv_get(dev); + struct sun50i_iommu *iommu = sdev->iommu; struct sun50i_iommu_domain *sun50i_domain; dev_dbg(dev, "Detaching from IOMMU domain\n"); @@ -786,12 +789,9 @@ static struct iommu_domain sun50i_iommu_identity_domain = { static int sun50i_iommu_attach_device(struct iommu_domain *domain, struct device *dev) { + struct sun50i_iommu_device *sdev = dev_iommu_priv_get(dev); struct sun50i_iommu_domain *sun50i_domain = to_sun50i_domain(domain); - struct sun50i_iommu *iommu; - - iommu = sun50i_iommu_from_dev(dev); - if (!iommu) - return -ENODEV; + struct sun50i_iommu *iommu = sdev->iommu; dev_dbg(dev, "Attaching to IOMMU domain\n"); @@ -807,26 +807,37 @@ static int sun50i_iommu_attach_device(struct iommu_domain *domain, return 0; } -static struct iommu_device *sun50i_iommu_probe_device(struct device *dev) +static struct iommu_device * +sun50i_iommu_probe_device(struct iommu_probe_info *pinf) { + struct sun50i_iommu_device *sdev; struct sun50i_iommu *iommu; - iommu = sun50i_iommu_from_dev(dev); - if (!iommu) - return ERR_PTR(-ENODEV); + iommu = iommu_of_get_single_iommu(pinf, &sun50i_iommu_ops, 1, + struct sun50i_iommu, iommu); + if (IS_ERR(iommu)) + return ERR_CAST(iommu); + /* + * The ids are ignored because the all the devices are placed in a + * single group and the core code will enforce the same translation for + * all ids. + */ + + sdev = kzalloc(sizeof(*sdev), GFP_KERNEL); + if (!sdev) + return ERR_PTR(-ENOMEM); + sdev->iommu = iommu; + + dev_iommu_priv_set(pinf->dev, sdev); return &iommu->iommu; } -static int sun50i_iommu_of_xlate(struct device *dev, - struct of_phandle_args *args) +static void sun50i_iommu_release_device(struct device *dev) { - struct platform_device *iommu_pdev = of_find_device_by_node(args->np); - unsigned id = args->args[0]; + struct sun50i_iommu_device *sdev = dev_iommu_priv_get(dev); - dev_iommu_priv_set(dev, platform_get_drvdata(iommu_pdev)); - - return iommu_fwspec_add_ids(dev, &id, 1); + kfree(sdev); } static const struct iommu_ops sun50i_iommu_ops = { @@ -834,8 +845,9 @@ static const struct iommu_ops sun50i_iommu_ops = { .pgsize_bitmap = SZ_4K, .device_group = generic_single_device_group, .domain_alloc_paging = sun50i_iommu_domain_alloc_paging, - .of_xlate = sun50i_iommu_of_xlate, - .probe_device = sun50i_iommu_probe_device, + .of_xlate = iommu_dummy_of_xlate, + .probe_device_pinf = sun50i_iommu_probe_device, + .release_device = sun50i_iommu_release_device, .default_domain_ops = &(const struct iommu_domain_ops) { .attach_dev = sun50i_iommu_attach_device, .flush_iotlb_all = sun50i_iommu_flush_iotlb_all, From patchwork Thu Nov 30 01:10:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 748732 Authentication-Results: smtp.subspace.kernel.org; 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Received: from LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) by PH0PR12MB5484.namprd12.prod.outlook.com (2603:10b6:510:eb::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7046.24; Thu, 30 Nov 2023 01:10:47 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93%4]) with mapi id 15.20.7046.015; Thu, 30 Nov 2023 01:10:47 +0000 From: Jason Gunthorpe To: acpica-devel@lists.linux.dev, Andy Gross , Alim Akhtar , Alyssa Rosenzweig , Bjorn Andersson , AngeloGioacchino Del Regno , asahi@lists.linux.dev, Baolin Wang , devicetree@vger.kernel.org, Frank Rowand , Hanjun Guo , "Gustavo A. R. Silva" , Heiko Stuebner , iommu@lists.linux.dev, Jean-Philippe Brucker , Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Kees Cook , Konrad Dybcio , Krzysztof Kozlowski , Len Brown , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Lorenzo Pieralisi , Marek Szyprowski , Hector Martin , Matthias Brugger , Orson Zhai , "Rafael J. Wysocki" , Rob Clark , Robert Moore , Rob Herring , Robin Murphy , Samuel Holland , Sudeep Holla , Sven Peter , Thierry Reding , Krishna Reddy , virtualization@lists.linux.dev, Chen-Yu Tsai , Will Deacon , Yong Wu , Chunyan Zhang Cc: =?utf-8?q?Andr=C3=A9_Draszik?= , patches@lists.linux.dev Subject: [PATCH 12/30] iommu/of: Add iommu_of_xlate() Date: Wed, 29 Nov 2023 21:10:19 -0400 Message-ID: <12-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> In-Reply-To: <0-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> References: X-ClientProxiedBy: SN7P222CA0006.NAMP222.PROD.OUTLOOK.COM (2603:10b6:806:124::19) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|PH0PR12MB5484:EE_ X-MS-Office365-Filtering-Correlation-Id: 2f806ee4-4326-45e2-79e6-08dbf1412b63 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: TIZFqfzvtr2YcYNETFF/PTb94RNIUhTKxEEbcXysqAEzMAQoDXWV8aJFOi75zFaI0Il5TP4NPzByEX5F4XAhxGeE4tISihfjAz+eiHGxeNjT5XRrLukZy5iM2DLqlBNBSsBLqaXUUoO+tKjMsDsTVHkav75R34Yu1u5OQnfWYlp65PLg4mvIH4VJTfqV2FSsvPoEj1TASVrSAOkWsi1BMTHSMvlpSMReWwo5cDJoyzm6GcwrCmzB+zdkAxAP9htTkvIfi2vwU6Zw3jTV1A8/81ee52LNiTs6vtGNG0uuAJW7DGu+c+rmLV8pfxCiYjOL4p7wWpCN4wqDPYny4RUkKhxPRGhx1kGJnnQsViyHw6NxLspRbntoCnW7xEImAmedCqwHbZMngmgII4hR7G319RNBMiGxoCIv0BVsr19KkObtLnQOStGLEsSYVLRNU8qATn3Zn6wBiYaAnr1DIk47DQIdGs3l1h36pYGLA6RHiwM+6mm+G+ZB3SN7nOAy6P6KOHYrQlt3ptvtb5bN4dg+NZ2EOOf802I9EEbRwRjgYIeE8QTE/QcykFH/p+EkZez9d1lrBHCKQKAE9dtlxUPjBQ4trFIjKwjAT5H3dNvQJazHUc8/+NQhK2vYHdRsJXH20357ODwmeYDRCPFUicWPNw== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:LV2PR12MB5869.namprd12.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230031)(366004)(346002)(136003)(396003)(39860400002)(376002)(230922051799003)(451199024)(1800799012)(186009)(64100799003)(1191002)(8936002)(110136005)(8676002)(316002)(66556008)(4326008)(86362001)(66476007)(6486002)(478600001)(66946007)(41300700001)(36756003)(921008)(7416002)(7366002)(2906002)(7406005)(5660300002)(38100700002)(2616005)(6512007)(6506007)(6666004)(83380400001)(26005)(202311291699003); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: HkGVBSCT9IGS1U/algNjEDu00nCBkERPgTh2ZudgjMK8/qB6HPEgafNREsBlG/4vTMnQ2uEbm33HKDHnsBzo2gHoqRyCyTKwrTiy7KuuEvxyJ9fnW5NrYqgGMVMTzIgR/TbZ5Es1Yp6KrUHGYmDTdfcfOzmMLiatRNaprFWGMXwruJWUhsDc97Fkdk/NgN+nl2HdEXVqrWJ7um1bn0sTa4MtAsTlcXTJI6XX3ZtJtW44YsPtA8paIVNJOp62CnVpeCufgbEx0Z9qfvLOMHWVnCcza5gMdxA0Yz9/adQkhU36+6wZR13bY+97HyPMaKhQLytgld10nHj3k+ToGH+n3c5CJ+VNlK3Qs+YcNJzFwGPa1wJrA9FFg/o3M2pTJSXpE+GiLVJNLSbd89RZBYFOsRESPH62svGVBTeLaupliGjznLkHf7hCR2FYm0W6RgoIi522IzjJuayYKq/leLq28CN8+L1lTyujvAiMDbuVg+7UxXH63FmuX2jFoN+U92G+W3Mgs2TrpMROhIllFkRqKeJjCH21+KAbZREINMDlNME3LO0W8ITTDcqT30lHRvb+bJFEts0y7y2knmVBJEZf5WAxoganc61AncBesmxvrOm/ByG2ZCzZYzE8tmZCS3A2qsvf4CcaYoEKGF3HWZghnjeJJwJT2VbfUAA+Z/gRu4wsekJZ8Pd2eUEQDiXHJhXnANp6hK4Tl4uJXui9fH/sNS7lUVNs55ukLC2lioLTNlRH0RFKT9wH8i4iMhqzpnMnaZ6KhSXh5LmPW+yOeTiSvUWZ8wH6ISJOvv5k3rforInSAFHs/k7YjTaCGn5Iu0dwvk1dfFw7cREWbdkx3iict5BWt0zfdnn7KQv4msGTSPKLouj4YtkS1TA5CoT4vUwOf1gWvPZlwVkIXjMDxYakxxsjrNf5RPkZkDRXeQOtZmqruseceH+xS02Pc3xFboBjciTW4G78EYMdHz2YgveI5cN5qlMuvNHg6u5H9CP8AWVr5YhHiaLYCG5qR6mV0Pns850dXm/wl5MDaV6qQgatKQTo7bD5lwyY7V4znNnAMEvCyuILT9BGlZcgOF42a4nKeftmaiElEK+wTWoLzNbSWj89X6yA35n6UoKqNNtUf4qCGvUFzgaJU2owZNycMrYws4k8aQ/zV38tu/+3ue9ZTI9GexHRYdJln3hxM0/J/PWFjji6BuTfDaM72ZTovBPeNJa7RgXZgru217vUnpUSQarBCG2TKMdesqeQlgOB2bPFVu9iHOnUeLtEIugulnONacvWYvPmtf5xlzUqf8yCeeEIGrax8xM28YXBgn3hMhVIl5P10WFM3bBIMMb0oKcG4KxdSuTLrlnGeD/T/IDYfvGxuNk8rxuXuiylpRcvv0t/NQ//gbJurtiIBVoSzEYKDaigCwVWNgy5zA8286mdTkYk5BqGaZ2USznxpIhd/eVfUF3CAxzkYWbzScdVtZvSr9XfPLPEE05aN03mDvoz+tH4A6CLxKRgiFLWzTsJi2eegK2zXIx0x2tKWQT33djZzavCGPecHCoN0ZznnjQ1Yj2uutamU7fneNgVD2rWJbpV5NxW+XyYVflFPKa529Hn X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 2f806ee4-4326-45e2-79e6-08dbf1412b63 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2023 01:10:40.7736 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: wqSzRYknoJdjHiGX0z3ucmQf7nPG+CbmvO67yHZIMSADsmvKJUkHoPYZETTpR9Ko X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB5484 This function can be called by drivers in their probe function if they want to parse their own ID table, almost always because the driver supports a multi-instance configuration and needs to extract the list of iommu_driver's and data from the ID into some internal format. The core code will find the iommu_driver for each ID table entry and validate that it matches the driver's ops. A driver provided function is called to handle the (iommu_driver, ID) tuple. Before calling this function the driver should allocate its per-driver private data and pass it through the opaque cookie priv argument. Driver's should follow a typical pattern in their probe_device: static int apple_dart_of_xlate(struct iommu_device *iommu, struct of_phandle_args *args, void *priv); [..] cfg = kzalloc(sizeof(*cfg), GFP_KERNEL); if (!cfg) return ERR_PTR(-ENOMEM); ret = iommu_of_xlate(pinf, &apple_dart_iommu_ops, 1, &apple_dart_of_xlate, cfg); if (ret) goto err_free; dev_iommu_priv_set(dev, cfg); return &??->iommu; // The first iommu_device parsed Signed-off-by: Jason Gunthorpe --- drivers/iommu/of_iommu.c | 58 ++++++++++++++++++++++++++++++++++++ include/linux/iommu-driver.h | 13 ++++++++ 2 files changed, 71 insertions(+) diff --git a/drivers/iommu/of_iommu.c b/drivers/iommu/of_iommu.c index 37af32a6bc84e5..9c1d398aa2cd9c 100644 --- a/drivers/iommu/of_iommu.c +++ b/drivers/iommu/of_iommu.c @@ -285,6 +285,8 @@ struct parse_info { struct iommu_probe_info *pinf; const struct iommu_ops *ops; int num_cells; + iommu_of_xlate_fn xlate_fn; + void *priv; }; static struct iommu_device *parse_iommu(struct parse_info *info, @@ -336,3 +338,59 @@ struct iommu_device *__iommu_of_get_single_iommu(struct iommu_probe_info *pinf, return iommu_fw_finish_get_single(pinf); } EXPORT_SYMBOL_GPL(__iommu_of_get_single_iommu); + +static int parse_of_xlate(struct of_phandle_args *iommu_spec, void *_info) +{ + struct parse_info *info = _info; + struct iommu_device *iommu; + + iommu = parse_iommu(info, iommu_spec); + if (IS_ERR(iommu)) + return PTR_ERR(iommu); + info->pinf->num_ids++; + return info->xlate_fn(iommu, iommu_spec, info->priv); +} + +/** + * iommu_of_xlate - Parse all OF ids for an IOMMU + * @pinf: The iommu_probe_info + * @ops: The ops the iommu instance must have + * @num_cells: #iommu-cells value to enforce, -1 is no check + * @fn: Call for each Instance and ID + * @priv: Opaque cookie for fn + * + * Drivers that support multiple iommu instances must call this function to + * parse each instance from the OF table. fn will be called with the driver's + * iommu_driver instance and the raw of_phandle_args that contains the ID. + * + * Drivers that need to parse a complex ID format should also use this function. + */ +int iommu_of_xlate(struct iommu_probe_info *pinf, const struct iommu_ops *ops, + int num_cells, iommu_of_xlate_fn fn, void *priv) +{ + struct parse_info info = { .pinf = pinf, + .ops = ops, + .num_cells = num_cells, + .xlate_fn = fn, + .priv = priv }; + + pinf->num_ids = 0; + return of_iommu_for_each_id(pinf->dev, pinf->of_master_np, + pinf->of_map_id, parse_of_xlate, &info); +} +EXPORT_SYMBOL_GPL(iommu_of_xlate); + +/* + * Temporary approach to allow drivers to opt into the bus probe. It configures + * the iommu_probe_info to probe the dev->of_node. This is a bit hacky because + * it mutates the iommu_probe_info and thus assumes there is only one op in the + * system. Remove when we call probe from the bus always anyhow. + */ +void iommu_of_allow_bus_probe(struct iommu_probe_info *pinf) +{ + if (pinf->is_dma_configure) + return; + pinf->of_master_np = pinf->dev->of_node; + pinf->is_dma_configure = true; +} +EXPORT_SYMBOL_GPL(iommu_of_allow_bus_probe); diff --git a/include/linux/iommu-driver.h b/include/linux/iommu-driver.h index 597998a62b0dd6..622d6ad9056ce0 100644 --- a/include/linux/iommu-driver.h +++ b/include/linux/iommu-driver.h @@ -60,9 +60,16 @@ iommu_device_from_fwnode_pinf(struct iommu_probe_info *pinf, struct fwnode_handle *fwnode); struct iommu_device *iommu_fw_finish_get_single(struct iommu_probe_info *pinf); +typedef int (*iommu_of_xlate_fn)(struct iommu_device *iommu, + struct of_phandle_args *args, void *priv); +void iommu_of_allow_bus_probe(struct iommu_probe_info *pinf); + #if IS_ENABLED(CONFIG_OF_IOMMU) void of_iommu_get_resv_regions(struct device *dev, struct list_head *list); +int iommu_of_xlate(struct iommu_probe_info *pinf, const struct iommu_ops *ops, + int num_cells, iommu_of_xlate_fn fn, void *priv); + struct iommu_device *__iommu_of_get_single_iommu(struct iommu_probe_info *pinf, const struct iommu_ops *ops, int num_cells); @@ -71,6 +78,12 @@ static inline void of_iommu_get_resv_regions(struct device *dev, struct list_head *list) { } +static inline int iommu_of_xlate(struct iommu_probe_info *pinf, + const struct iommu_ops *ops, int num_cells, + iommu_of_xlate_fn fn, void *priv) +{ + return -ENODEV; +} static inline struct iommu_device *__iommu_of_get_single_iommu(struct iommu_probe_info *pinf, const struct iommu_ops *ops, From patchwork Thu Nov 30 01:10:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 748729 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="BjmT8lbX" Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2082.outbound.protection.outlook.com [40.107.243.82]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F3AC810EA; Wed, 29 Nov 2023 17:11:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=ka5+Tn0dtGD82doSLCdRzFAdZU+soCknlkmhpYprPjL/OEtXbLG43HRLzmLKkr86KdFd4lZ16IQm3mc908D2W7OUdSfCIWrg2xjtXemm56kaGKyct8QoRV6MNBE+Lkn//JGELyOgxoMcLTyZHXd8Jj6AV2Jm01O2opSey2ZeZ0+1McByqH8JPhpe3Auv1ufuu7X20oBZKsrz+sANhDt553M+BkaMB9wguQBxHF07TI1GxJfIZ2seqCWPfa+OXOQqD5gM9nOYuPodYuDiBNV2WZWMC+2ztS42sEKCWqCuEKGEcn7SLYuhabPGHG0Unl0c2Tx0hx8Q+SSIimQdjnsevg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=DWZ926ZLNg56KWjCc5bGDycCVGjrN5wZd1+rheKLVFg=; b=OC/gfjy7SmizxL5B+/qJlDZkBscnLWQJM8R1l85aeCrEQsEzkOSg3/CrHa4UbLSsvnDQlrAEKLaEWDkWZEToSD7VbLxsskvdvVWZ+IRZc8e6ZRg7e57mmXNShuGbo5ofD7JvEkkYU2sPru4Bgdh+c1298GWmJ+tk3KpSxyJy2e8jMGB7H6QQlnQaN5Zo5rGIFQVZETzEKBwy6avzhzPec9culajVcwnnvmUtLLfheF3Ebqu+PNm/IChmwu5E8bPWdsj6oECRe1YS1ChmYMHL6nHDlUfEz9Xe22sZdYXxN1JhZbSidmEAqtXx2vrqop6E99pOjUSClW3UGjnHrZraew== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=DWZ926ZLNg56KWjCc5bGDycCVGjrN5wZd1+rheKLVFg=; b=BjmT8lbXwnW6JZmFNYNAVEUqwi/eLtYmxKMIapa0cwURuUJa6Z70jxreC7lR9XxwdoljYcubePkyb3R0rhMfX/b9vGzcCNN7Vcav6tuQYd8x/UBEvuE2DohQCvsSI/iydQXQb9TLClZqlaLJJGsjRQuRv60Lm/in1VUWlv59XdyrePUxNn7ymqhnLjUzr2tiiAgZU7e745OS2irqIeyxTLfhPAhjjhyWmXs3oP+xQPOyGVWq37tglWPlKZp8Hwm5gLpCe3p6LR7oBx7lhkR5JTo5MOKATnsHwl1nRGlJxCb76EiQKJUCJnxiQUafxx8EvXtI9V0MjyKmgvzspPyV8Q== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) by PH0PR12MB5484.namprd12.prod.outlook.com (2603:10b6:510:eb::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7046.24; Thu, 30 Nov 2023 01:10:52 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93%4]) with mapi id 15.20.7046.015; Thu, 30 Nov 2023 01:10:52 +0000 From: Jason Gunthorpe To: acpica-devel@lists.linux.dev, Andy Gross , Alim Akhtar , Alyssa Rosenzweig , Bjorn Andersson , AngeloGioacchino Del Regno , asahi@lists.linux.dev, Baolin Wang , devicetree@vger.kernel.org, Frank Rowand , Hanjun Guo , "Gustavo A. R. Silva" , Heiko Stuebner , iommu@lists.linux.dev, Jean-Philippe Brucker , Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Kees Cook , Konrad Dybcio , Krzysztof Kozlowski , Len Brown , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Lorenzo Pieralisi , Marek Szyprowski , Hector Martin , Matthias Brugger , Orson Zhai , "Rafael J. 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It loads the FW data into a pre-allocated 2d array inside it's per-device data. Switch over by allocating the per-device data at the top of probe then calling iommu_of_xlate() to fill in the 2d array. The iommu instance is located by the core code and container_of() gets to the dart version. Solve a few issues: - A bus probe was failing by accident because the of_xlate not being called left a NULL cfg in the priv, and other code tended to free the dev->iommu. iommu_of_xlate() will fail bus probe directly - Missing validation that the node in the iommus instance is actually pointing at this driver - Don't leak the cfg. It is allocated during probe, freed on probe failure, and freed in release_device() on probe success. Previously it would allocate it in of_xlate and leak it in some possible error flows. Signed-off-by: Jason Gunthorpe --- drivers/iommu/apple-dart.c | 58 +++++++++++++++++++++----------------- 1 file changed, 32 insertions(+), 26 deletions(-) diff --git a/drivers/iommu/apple-dart.c b/drivers/iommu/apple-dart.c index bb0e5a4577fc03..b796c68ae45ad8 100644 --- a/drivers/iommu/apple-dart.c +++ b/drivers/iommu/apple-dart.c @@ -268,10 +268,10 @@ struct apple_dart_domain { }; /* - * This structure is attached to devices with dev_iommu_priv_set() on of_xlate - * and contains a list of streams bound to this device. - * So far the worst case seen is a single device with two streams - * from different darts, such that this simple static array is enough. + * This structure is attached to devices with dev_iommu_priv_set() on + * probe_device and contains a list of streams bound to this device. So far the + * worst case seen is a single device with two streams from different darts, + * such that this simple static array is enough. * * @streams: streams for this device */ @@ -295,6 +295,9 @@ struct apple_dart_master_cfg { static struct platform_driver apple_dart_driver; static const struct iommu_ops apple_dart_iommu_ops; +static int apple_dart_of_xlate(struct iommu_device *iommu, + struct of_phandle_args *args, void *priv); + static struct apple_dart_domain *to_dart_domain(struct iommu_domain *dom) { return container_of(dom, struct apple_dart_domain, domain); @@ -721,21 +724,34 @@ static struct iommu_domain apple_dart_blocked_domain = { .ops = &apple_dart_blocked_ops, }; -static struct iommu_device *apple_dart_probe_device(struct device *dev) +static struct iommu_device * +apple_dart_probe_device(struct iommu_probe_info *pinf) { - struct apple_dart_master_cfg *cfg = dev_iommu_priv_get(dev); + struct device *dev = pinf->dev; + struct apple_dart_master_cfg *cfg; struct apple_dart_stream_map *stream_map; + int ret; int i; + cfg = kzalloc(sizeof(*cfg), GFP_KERNEL); if (!cfg) - return ERR_PTR(-ENODEV); + return ERR_PTR(-ENOMEM); + ret = iommu_of_xlate(pinf, &apple_dart_iommu_ops, 1, + &apple_dart_of_xlate, cfg); + if (ret) + goto err_free; for_each_stream_map(i, cfg, stream_map) device_link_add( dev, stream_map->dart->dev, DL_FLAG_PM_RUNTIME | DL_FLAG_AUTOREMOVE_SUPPLIER); + dev_iommu_priv_set(dev, cfg); return &cfg->stream_maps[0].dart->iommu; + +err_free: + kfree(cfg); + return ERR_PTR(ret); } static void apple_dart_release_device(struct device *dev) @@ -778,25 +794,15 @@ static void apple_dart_domain_free(struct iommu_domain *domain) kfree(dart_domain); } -static int apple_dart_of_xlate(struct device *dev, struct of_phandle_args *args) +static int apple_dart_of_xlate(struct iommu_device *iommu, + struct of_phandle_args *args, void *priv) { - struct apple_dart_master_cfg *cfg = dev_iommu_priv_get(dev); - struct platform_device *iommu_pdev = of_find_device_by_node(args->np); - struct apple_dart *dart = platform_get_drvdata(iommu_pdev); - struct apple_dart *cfg_dart; - int i, sid; + struct apple_dart *dart = container_of(iommu, struct apple_dart, iommu); + struct apple_dart_master_cfg *cfg = priv; + struct apple_dart *cfg_dart = cfg->stream_maps[0].dart; + int sid = args->args[0]; + int i; - if (args->args_count != 1) - return -EINVAL; - sid = args->args[0]; - - if (!cfg) - cfg = kzalloc(sizeof(*cfg), GFP_KERNEL); - if (!cfg) - return -ENOMEM; - dev_iommu_priv_set(dev, cfg); - - cfg_dart = cfg->stream_maps[0].dart; if (cfg_dart) { if (cfg_dart->supports_bypass != dart->supports_bypass) return -EINVAL; @@ -978,10 +984,10 @@ static const struct iommu_ops apple_dart_iommu_ops = { .identity_domain = &apple_dart_identity_domain, .blocked_domain = &apple_dart_blocked_domain, .domain_alloc_paging = apple_dart_domain_alloc_paging, - .probe_device = apple_dart_probe_device, + .probe_device_pinf = apple_dart_probe_device, .release_device = apple_dart_release_device, .device_group = apple_dart_device_group, - .of_xlate = apple_dart_of_xlate, + .of_xlate = iommu_dummy_of_xlate, .def_domain_type = apple_dart_def_domain_type, .get_resv_regions = apple_dart_get_resv_regions, .pgsize_bitmap = -1UL, /* Restricted during dart probe */ From patchwork Thu Nov 30 01:10:23 2023 Content-Type: text/plain; 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Received: from LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) by PH0PR12MB5484.namprd12.prod.outlook.com (2603:10b6:510:eb::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7046.24; Thu, 30 Nov 2023 01:10:55 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93%4]) with mapi id 15.20.7046.015; Thu, 30 Nov 2023 01:10:55 +0000 From: Jason Gunthorpe To: acpica-devel@lists.linux.dev, Andy Gross , Alim Akhtar , Alyssa Rosenzweig , Bjorn Andersson , AngeloGioacchino Del Regno , asahi@lists.linux.dev, Baolin Wang , devicetree@vger.kernel.org, Frank Rowand , Hanjun Guo , "Gustavo A. R. Silva" , Heiko Stuebner , iommu@lists.linux.dev, Jean-Philippe Brucker , Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Kees Cook , Konrad Dybcio , Krzysztof Kozlowski , Len Brown , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Lorenzo Pieralisi , Marek Szyprowski , Hector Martin , Matthias Brugger , Orson Zhai , "Rafael J. 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The function allows such units, only for tegra, to get the IDs they are supposed to program. The tegra HW that needs this function only supports tegra-smmu and arm-smmu, so implement the function there. This makes way to moving the id list into the private memory of the driver. Signed-off-by: Jason Gunthorpe --- drivers/iommu/arm/arm-smmu/arm-smmu.c | 11 +++++++++++ drivers/iommu/of_iommu.c | 18 ++++++++++++++++++ drivers/iommu/tegra-smmu.c | 11 +++++++++++ include/linux/iommu.h | 21 +++++++-------------- 4 files changed, 47 insertions(+), 14 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c index adc7937fd8a3a3..02b8dc4f366aa9 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c @@ -1551,6 +1551,16 @@ static int arm_smmu_def_domain_type(struct device *dev) return 0; } +static bool arm_smmu_get_stream_id(struct device *dev, u32 *stream_id) +{ + struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); + + if (fwspec->num_ids != 1) + return false; + *stream_id = fwspec->ids[0] & 0xffff; + return true; +} + static struct iommu_ops arm_smmu_ops = { .capable = arm_smmu_capable, .domain_alloc = arm_smmu_domain_alloc, @@ -1561,6 +1571,7 @@ static struct iommu_ops arm_smmu_ops = { .of_xlate = arm_smmu_of_xlate, .get_resv_regions = arm_smmu_get_resv_regions, .def_domain_type = arm_smmu_def_domain_type, + .tegra_dev_iommu_get_stream_id = arm_smmu_get_stream_id, .pgsize_bitmap = -1UL, /* Restricted during device attach */ .owner = THIS_MODULE, .default_domain_ops = &(const struct iommu_domain_ops) { diff --git a/drivers/iommu/of_iommu.c b/drivers/iommu/of_iommu.c index 9c1d398aa2cd9c..8d5495f03dbbcb 100644 --- a/drivers/iommu/of_iommu.c +++ b/drivers/iommu/of_iommu.c @@ -8,6 +8,7 @@ #include #include #include +#include "iommu-priv.h" #include #include #include @@ -281,6 +282,23 @@ void of_iommu_get_resv_regions(struct device *dev, struct list_head *list) } EXPORT_SYMBOL(of_iommu_get_resv_regions); +#if IS_ENABLED(CONFIG_TEGRA_IOMMU_SMMU) || IS_ENABLED(CONFIG_ARM_SMMU) +/* + * Newer generations of Tegra SoCs require devices' stream IDs to be directly + * programmed into some registers. These are always paired with a Tegra SMMU or + * ARM SMMU which provides an implementation of this op. + */ +bool tegra_dev_iommu_get_stream_id(struct device *dev, u32 *stream_id) +{ + const struct iommu_ops *ops = dev_iommu_ops(dev); + + if (!ops || !ops->tegra_dev_iommu_get_stream_id) + return false; + return ops->tegra_dev_iommu_get_stream_id(dev, stream_id); +} +EXPORT_SYMBOL_GPL(tegra_dev_iommu_get_stream_id); +#endif + struct parse_info { struct iommu_probe_info *pinf; const struct iommu_ops *ops; diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c index 310871728ab4b6..cf563db3e3b48d 100644 --- a/drivers/iommu/tegra-smmu.c +++ b/drivers/iommu/tegra-smmu.c @@ -989,6 +989,16 @@ static int tegra_smmu_def_domain_type(struct device *dev) return IOMMU_DOMAIN_IDENTITY; } +static bool tegra_smmu_get_stream_id(struct device *dev, u32 *stream_id) +{ + struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); + + if (fwspec->num_ids != 1) + return false; + *stream_id = fwspec->ids[0] & 0xffff; + return true; +} + static const struct iommu_ops tegra_smmu_ops = { .identity_domain = &tegra_smmu_identity_domain, .def_domain_type = &tegra_smmu_def_domain_type, @@ -996,6 +1006,7 @@ static const struct iommu_ops tegra_smmu_ops = { .probe_device = tegra_smmu_probe_device, .device_group = tegra_smmu_device_group, .of_xlate = tegra_smmu_of_xlate, + .tegra_dev_iommu_get_stream_id = tegra_smmu_get_stream_id, .pgsize_bitmap = SZ_4K, .default_domain_ops = &(const struct iommu_domain_ops) { .attach_dev = tegra_smmu_attach_dev, diff --git a/include/linux/iommu.h b/include/linux/iommu.h index f0aaf55db3c09b..0ba12e0e450705 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -412,6 +412,9 @@ struct iommu_ops { int (*def_domain_type)(struct device *dev); void (*remove_dev_pasid)(struct device *dev, ioasid_t pasid); + bool (*tegra_dev_iommu_get_stream_id)(struct device *dev, + u32 *stream_id); + const struct iommu_domain_ops *default_domain_ops; unsigned long pgsize_bitmap; struct module *owner; @@ -1309,26 +1312,16 @@ static inline void iommu_dma_compose_msi_msg(struct msi_desc *desc, struct msi_m #endif /* CONFIG_IOMMU_DMA */ -/* - * Newer generations of Tegra SoCs require devices' stream IDs to be directly programmed into - * some registers. These are always paired with a Tegra SMMU or ARM SMMU, for which the contents - * of the struct iommu_fwspec are known. Use this helper to formalize access to these internals. - */ #define TEGRA_STREAM_ID_BYPASS 0x7f +#if IS_ENABLED(CONFIG_TEGRA_IOMMU_SMMU) || IS_ENABLED(CONFIG_ARM_SMMU) +bool tegra_dev_iommu_get_stream_id(struct device *dev, u32 *stream_id); +#else static inline bool tegra_dev_iommu_get_stream_id(struct device *dev, u32 *stream_id) { -#ifdef CONFIG_IOMMU_API - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); - - if (fwspec && fwspec->num_ids == 1) { - *stream_id = fwspec->ids[0] & 0xffff; - return true; - } -#endif - return false; } +#endif #ifdef CONFIG_IOMMU_SVA static inline void mm_pasid_init(struct mm_struct *mm) From patchwork Thu Nov 30 01:10:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 748730 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="INXWqdqc" Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2053.outbound.protection.outlook.com [40.107.243.53]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4FA3DD54; Wed, 29 Nov 2023 17:10:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=MdI03JHoSpNb6wfkhxmvINBZ5QE3A1X7JT0qNXTCqxTSnw9/G5qjD1TxxRyE8cnk0mU4W05J9+24jseiY0nLbPcz226Z/UXgtcHZUUll7xgF9HMqiBw4Ns8weogdaYbAMFZj3bRt4nIjxx7+c5A14sRbSytt9kP/7LoL/2HZRDMv/j5aOtxz19rPmXjRlZ1MdJqvqna8vUS+FMRpBkwzjrJjPKe5XdvIx6YmHaIuYoUSL8WlhhGY4bHqn9zxuygVF/l+JOXg8QMem/w3QkdSFj0GGnDAKa0bKDDPkhyYL/cSj8XgGzVKrQ9TqXX5dFEeA/Xd1Z8cHQyJuz3Cjrlx1A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=mNc0i8b19f67qGg7jaCMO7gIkmzVDan6cC8FlSSYH2o=; b=PVFYPcyxvDMzXhe1i/g0aqirYRrbXjl7/xMmKcK3yWNwrjaHQMe/Q9MvRBUnMrR9lKrMwHW/z4pgj2ikNbQGZUGtQKz2SdJM8aX3ZZz8yXJgWf0RHx7LnDbviOQwHIslqon/FK5+CC9qhj5DtjNVrZVpsJQ2kBSmvfkY2Z8KTXsdbUcrQZQlrwevWAC/GT2PMMUmFUr5VsIsAFyrhQVJM4wnyQqrd1Le5RD/wXslCDWrrPVwoiP0BPFMRIzqtfnQYVwoKI1WoKG1TxvQtB3/JI53UGmYDhKi9ETC/DqnrPx8kmE0xFB57LvGprjMnImIJRjiRt6+IFX6OaJtEKleaQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=mNc0i8b19f67qGg7jaCMO7gIkmzVDan6cC8FlSSYH2o=; b=INXWqdqclBICUJjjXFuMPgFLO24Al4fug/47pDUXnE+dt1EFdrhWsovH259yZyK99z8XSxR4I1TkDubuSn4KmxnLbYUuSqkFYH0U6lNYIGg1A4wJErBXg8VA0c3CFT4XSnTEepmicUaBzj37Xa1J+JY1UfIH4R3tFnSskHMB/uHbAIQIkfSKEZ4W1Fka1eEqpHqjfb+3D1FPWxUb5jnMrjrEHYByhvZDEAhvLmGD+wIXq0Ofr0EXtTb80ygvF75xkmQ8oAZa/O01ND5rfMm/3Pb2LnZ2tn57AAJUt33N6cPKlEq936U3CUKjiPmBatbxI9D1yj7RWPYqM1tC2rR8jA== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) by PH0PR12MB5484.namprd12.prod.outlook.com (2603:10b6:510:eb::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7046.24; Thu, 30 Nov 2023 01:10:48 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93%4]) with mapi id 15.20.7046.015; Thu, 30 Nov 2023 01:10:48 +0000 From: Jason Gunthorpe To: acpica-devel@lists.linux.dev, Andy Gross , Alim Akhtar , Alyssa Rosenzweig , Bjorn Andersson , AngeloGioacchino Del Regno , asahi@lists.linux.dev, Baolin Wang , devicetree@vger.kernel.org, Frank Rowand , Hanjun Guo , "Gustavo A. R. Silva" , Heiko Stuebner , iommu@lists.linux.dev, Jean-Philippe Brucker , Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Kees Cook , Konrad Dybcio , Krzysztof Kozlowski , Len Brown , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Lorenzo Pieralisi , Marek Szyprowski , Hector Martin , Matthias Brugger , Orson Zhai , "Rafael J. Wysocki" , Rob Clark , Robert Moore , Rob Herring , Robin Murphy , Samuel Holland , Sudeep Holla , Sven Peter , Thierry Reding , Krishna Reddy , virtualization@lists.linux.dev, Chen-Yu Tsai , Will Deacon , Yong Wu , Chunyan Zhang Cc: =?utf-8?q?Andr=C3=A9_Draszik?= , patches@lists.linux.dev Subject: [PATCH 19/30] iommu/mtk: Move to iommu_fw_alloc_per_device_ids() Date: Wed, 29 Nov 2023 21:10:26 -0400 Message-ID: <19-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> In-Reply-To: <0-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> References: X-ClientProxiedBy: SN7P222CA0004.NAMP222.PROD.OUTLOOK.COM (2603:10b6:806:124::18) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|PH0PR12MB5484:EE_ X-MS-Office365-Filtering-Correlation-Id: 9d3c6e54-176d-498f-da95-08dbf1412b79 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: EXY2ttH4pyhsm2YJc/WuQ+XxNnXTnWaCedP+qxpCDaXJuBY7Tnu6X3q/091tlNCC51kpIbTaV+RhcD0QTjd9Wn31YcPOcpLPqPFZ2idU9CL24yyyLpMxYkxNIjqawWiQJfWFzsKlC+0cStc9n7I7OFBViRdl7j3L1TFzbKltsBS0yN3nwdpzkDFkOR05+zo2V+9kWqmk/tCTPetycKAUMb+k6uoVs9HIMiMJnWGBkSDm3Q3+0fmyD4y8Q5osfIPiOzvEcY54fo5SEd2EYrKtrH6/UQTsTvtQjKzYbxcRf25toMrpwSgvung13rUy657rXuy0YLCCYOqwM5naOAf2Jgj1ldhmcWLjtLHIlh0yTZHOn6XofOzXdv+yN3yrzfuh3i0mpY6r4tLI4zw4r3Ca3RGIPRgR/k7/r4H7OZg65TMBsx1j08VyZ/t1ELExLLCG4FjJylPecIfH1Fw/QgRxmNm/GfUEHUNx6kdmAprvP2NNKtH4UFpchmT01d40+nEaxXlXfgjRvHiAIYliKu5HY4ilGKQjFyaRMlTbAowRCHO6L/TGuwqvf9MVkygm9SGIpxqzS6RoXFCRcSdAkIxOBYZNfwf6swBYZnf/H4Znb/SQhHLfreFkaiYHM7vKzKx0Kt6GxYsj2RdD1xCZpQoMrg== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:LV2PR12MB5869.namprd12.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230031)(366004)(346002)(136003)(396003)(39860400002)(376002)(230922051799003)(451199024)(1800799012)(186009)(64100799003)(1191002)(8936002)(110136005)(8676002)(316002)(66556008)(4326008)(86362001)(66476007)(6486002)(478600001)(66946007)(41300700001)(36756003)(921008)(30864003)(7416002)(7366002)(2906002)(7406005)(5660300002)(38100700002)(2616005)(6512007)(6506007)(6666004)(83380400001)(26005)(202311291699003); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: m/tpZQKcluujheAqzGnsfhypUuiVioZwVqtFoS6Q8reZVg9Zvx1h+ck+rqme/IFQXOPfDArHdTxbN5Qka4omTa/liI0RQTbxtrQiH9h7KjMpn7Q46tLjqL35V3QoIp2OVmHeX0zUV0lexS7xuwH3jodV6j2wBf7Y48ARZEwHR1ndObPARt5DvoqLcEV7proUdCQtWgXqoOuAN96KOifHDPX0jbMx3I+ee5idllzMTlQaHzECbJbWzQBzcEQoDKGeSiTYBhbwXHkQNm0jJu36TucLgk88rpLncdj9/IzvnAaFT+NMTTAdg/2RJfNLJjO0giloleI05kNDngZ6sCxTVY5csnFPwX0l5c0Jr3KDPUy7YUx85Jzq9G9FjhZ8L2b0u09ZXt8BXwGEl556I8ca5BVcfdfE7gGWxe3JlgVorbhV2kG0hxDsYVzs7eUIhQPaXfMmq+dQzi3yI6Pz+1cDEoAVONG9/MkbJEkGIyUJCjBKcwDl3WC6/CmONsaCpzcLgyam+GYbKDJ/Xwz4Wdxl039/i+X+BgP5u6YndVo58649BClQx9i8jDfTlpqTLEF5pwJA1mA5g7XUgziOga06oymnUbybEPCiOxyMIQG256kegwt/x2YyfEQSFBqDxsSZZ+O9mBrH5VBrZRfPks57jb4n57JK39llHLHGjpAbrI9L/HthwY7Gwi+S7P5Qfzgg5kZnNxYZ3PD/fPUpCvv/shtva1wsV0e3W1W56v/9hMbwyL8x42Zru8/y2qlavaP9Aqgs9eETqasDhcRVFFShTGN9rRcTlYD6UnzLaTOcOeASXFQ01RsjJn3h+CbKXlH+RqXA2JtrdIBPGVi5AqpyT12aC5q+9ce1P0WnNkreDaawWIs8cuKjv5oXMpq0D9j8eYlodJwq0SetltIwuMbX3cPJo+1zZRm972yo7JHsj0B0CjvSl/uE1F8yNXC/vMSnmC6Ko9d3eZ4nwuYX/1sH0r4pYs2mghmt3QPuCS5RT6SK16tBaifBr4MC7sQqtF9KvcUb0EAzw5n8JsSg4Dfs6zX4I2VUD5fDfgXVK4tXAAobuS/ZH8JjDzwrss/KYsy24HniPbN/sqR0VOK/jmN0P1mDhCWO3zIW5LVilY1ZelPqQ1KIU54peTMiDpzZ5JkyBKwRTU0KM3eh9KRdWrLXhDi6qNDxn40E60HtuMDaNP4dQbwt27NbK87+MrR8cCM+WG8xgjhNjZ2ZhJnZBaOz4QcIVSKcIhxaoKMtQQNiL4eELSvLc/8YnE6y7dSlR4Uzdpz2PTIX64jy/X/8VxI7M+O92spUPjKEmuZQ2Il14f/jeP6239QQ8iehu+v/KIqtdWsVezVpdY6FpREB4866WE2I7QkWAuVWR9S3JTUOeU9FLEAcTyPdfkctEpfcnelFPTpwr6wgOHgrMqzj22KRo3JYJbzuAZBcNufjsPruG6rg4K8rp5GM0Vhvv44yOhYagbJlhlVJ1CwSFipPCtf5KOupaqaw558DhHJIdqLQNEN9DGppCNN30Oi6DwHjpSPoEJl17j6/twzaVcaH9jPaGYfP7goRcjFeKuBAqkSUooyq1SO+J5Rv7WWdj2YW4DOQ X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 9d3c6e54-176d-498f-da95-08dbf1412b79 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2023 01:10:40.9319 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 5iQCpGHG8rrK0heO2B4CQgapUNp1ZK85FyWiYHYC54oG2yQrFPC3AxQeYD/nYFkY X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB5484 mtk was doing a lot of stuff under of_xlate, and it looked kind of like it might support multi-instances. But the dt files don't do that, and the driver has no way to keep track of which instance the ids are for. Enforce single instance with iommu_of_get_single_iommu(). Introduce a per-device data to store the iommu and ids list. Allocate and initialize it with iommu_fw_alloc_per_device_ids(). Remove mtk_iommu_of_xlate(). Convert the rest of the funcs from calling dev_iommu_fwspec_get() to using the per-device data and remove all use of fwspec. Covnert the places using dev_iommu_priv_get() to use the per-device data not the iommu. Signed-off-by: Jason Gunthorpe --- drivers/iommu/mtk_iommu.c | 116 ++++++++++++++++++++------------------ 1 file changed, 62 insertions(+), 54 deletions(-) diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index 7abe9e85a57063..477171e83eaa6e 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -277,6 +278,12 @@ struct mtk_iommu_data { struct mtk_smi_larb_iommu larb_imu[MTK_LARB_NR_MAX]; }; +struct mtk_iommu_device { + struct mtk_iommu_data *iommu; + unsigned int num_ids; + u32 ids[] __counted_by(num_ids); +}; + struct mtk_iommu_domain { struct io_pgtable_cfg cfg; struct io_pgtable_ops *iop; @@ -526,14 +533,14 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_id) static unsigned int mtk_iommu_get_bank_id(struct device *dev, const struct mtk_iommu_plat_data *plat_data) { - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); + struct mtk_iommu_device *mtkdev = dev_iommu_priv_get(dev); unsigned int i, portmsk = 0, bankid = 0; if (plat_data->banks_num == 1) return bankid; - for (i = 0; i < fwspec->num_ids; i++) - portmsk |= BIT(MTK_M4U_TO_PORT(fwspec->ids[i])); + for (i = 0; i < mtkdev->num_ids; i++) + portmsk |= BIT(MTK_M4U_TO_PORT(mtkdev->ids[i])); for (i = 0; i < plat_data->banks_num && i < MTK_IOMMU_BANK_MAX; i++) { if (!plat_data->banks_enable[i]) @@ -550,7 +557,7 @@ static unsigned int mtk_iommu_get_bank_id(struct device *dev, static int mtk_iommu_get_iova_region_id(struct device *dev, const struct mtk_iommu_plat_data *plat_data) { - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); + struct mtk_iommu_device *mtkdev = dev_iommu_priv_get(dev); unsigned int portidmsk = 0, larbid; const u32 *rgn_larb_msk; int i; @@ -558,9 +565,9 @@ static int mtk_iommu_get_iova_region_id(struct device *dev, if (plat_data->iova_region_nr == 1) return 0; - larbid = MTK_M4U_TO_LARB(fwspec->ids[0]); - for (i = 0; i < fwspec->num_ids; i++) - portidmsk |= BIT(MTK_M4U_TO_PORT(fwspec->ids[i])); + larbid = MTK_M4U_TO_LARB(mtkdev->ids[0]); + for (i = 0; i < mtkdev->num_ids; i++) + portidmsk |= BIT(MTK_M4U_TO_PORT(mtkdev->ids[i])); for (i = 0; i < plat_data->iova_region_nr; i++) { rgn_larb_msk = plat_data->iova_region_larb_msk[i]; @@ -579,22 +586,22 @@ static int mtk_iommu_get_iova_region_id(struct device *dev, static int mtk_iommu_config(struct mtk_iommu_data *data, struct device *dev, bool enable, unsigned int regionid) { + struct mtk_iommu_device *mtkdev = dev_iommu_priv_get(dev); struct mtk_smi_larb_iommu *larb_mmu; unsigned int larbid, portid; - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); const struct mtk_iommu_iova_region *region; unsigned long portid_msk = 0; struct arm_smccc_res res; int i, ret = 0; - for (i = 0; i < fwspec->num_ids; ++i) { - portid = MTK_M4U_TO_PORT(fwspec->ids[i]); + for (i = 0; i < mtkdev->num_ids; ++i) { + portid = MTK_M4U_TO_PORT(mtkdev->ids[i]); portid_msk |= BIT(portid); } if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) { /* All ports should be in the same larb. just use 0 here */ - larbid = MTK_M4U_TO_LARB(fwspec->ids[0]); + larbid = MTK_M4U_TO_LARB(mtkdev->ids[0]); larb_mmu = &data->larb_imu[larbid]; region = data->plat_data->iova_region + regionid; @@ -618,7 +625,7 @@ static int mtk_iommu_config(struct mtk_iommu_data *data, struct device *dev, } else { /* PCI dev has only one output id, enable the next writing bit for PCIe */ if (dev_is_pci(dev)) { - if (fwspec->num_ids != 1) { + if (mtkdev->num_ids != 1) { dev_err(dev, "PCI dev can only have one port.\n"); return -ENODEV; } @@ -708,7 +715,9 @@ static void mtk_iommu_domain_free(struct iommu_domain *domain) static int mtk_iommu_attach_device(struct iommu_domain *domain, struct device *dev) { - struct mtk_iommu_data *data = dev_iommu_priv_get(dev), *frstdata; + struct mtk_iommu_device *mtkdev = dev_iommu_priv_get(dev); + struct mtk_iommu_data *data = mtkdev->iommu; + struct mtk_iommu_data *frstdata; struct mtk_iommu_domain *dom = to_mtk_domain(domain); struct list_head *hw_list = data->hw_list; struct device *m4udev = data->dev; @@ -777,12 +786,12 @@ static int mtk_iommu_identity_attach(struct iommu_domain *identity_domain, struct device *dev) { struct iommu_domain *domain = iommu_get_domain_for_dev(dev); - struct mtk_iommu_data *data = dev_iommu_priv_get(dev); + struct mtk_iommu_device *mtkdev = dev_iommu_priv_get(dev); if (domain == identity_domain || !domain) return 0; - mtk_iommu_config(data, dev, false, 0); + mtk_iommu_config(mtkdev->iommu, dev, false, 0); return 0; } @@ -860,14 +869,28 @@ static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain, return pa; } -static struct iommu_device *mtk_iommu_probe_device(struct device *dev) +static struct iommu_device * +mtk_iommu_probe_device(struct iommu_probe_info *pinf) { - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); - struct mtk_iommu_data *data = dev_iommu_priv_get(dev); + struct mtk_iommu_device *mtkdev; + struct device *dev = pinf->dev; + struct mtk_iommu_data *data; struct device_link *link; struct device *larbdev; unsigned int larbid, larbidx, i; + data = iommu_of_get_single_iommu(pinf, &mtk_iommu_ops, 1, + struct mtk_iommu_data, iommu); + if (IS_ERR(data)) + return ERR_CAST(data); + + mtkdev = iommu_fw_alloc_per_device_ids(pinf, mtkdev); + if (IS_ERR(mtkdev)) + return ERR_CAST(mtkdev); + mtkdev->iommu = data; + + dev_iommu_priv_set(dev, mtkdev); + if (!MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) return &data->iommu; @@ -876,42 +899,46 @@ static struct iommu_device *mtk_iommu_probe_device(struct device *dev) * The device that connects with each a larb is a independent HW. * All the ports in each a device should be in the same larbs. */ - larbid = MTK_M4U_TO_LARB(fwspec->ids[0]); + larbid = MTK_M4U_TO_LARB(mtkdev->ids[0]); if (larbid >= MTK_LARB_NR_MAX) - return ERR_PTR(-EINVAL); + goto err_out; - for (i = 1; i < fwspec->num_ids; i++) { - larbidx = MTK_M4U_TO_LARB(fwspec->ids[i]); + for (i = 1; i < mtkdev->num_ids; i++) { + larbidx = MTK_M4U_TO_LARB(mtkdev->ids[i]); if (larbid != larbidx) { dev_err(dev, "Can only use one larb. Fail@larb%d-%d.\n", larbid, larbidx); - return ERR_PTR(-EINVAL); + goto err_out; } } larbdev = data->larb_imu[larbid].dev; if (!larbdev) - return ERR_PTR(-EINVAL); + goto err_out; link = device_link_add(dev, larbdev, DL_FLAG_PM_RUNTIME | DL_FLAG_STATELESS); if (!link) dev_err(dev, "Unable to link %s\n", dev_name(larbdev)); return &data->iommu; + +err_out: + kfree(mtkdev); + return ERR_PTR(-EINVAL); } static void mtk_iommu_release_device(struct device *dev) { - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); - struct mtk_iommu_data *data; + struct mtk_iommu_device *mtkdev = dev_iommu_priv_get(dev); + struct mtk_iommu_data *data = mtkdev->iommu; struct device *larbdev; unsigned int larbid; - data = dev_iommu_priv_get(dev); if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) { - larbid = MTK_M4U_TO_LARB(fwspec->ids[0]); + larbid = MTK_M4U_TO_LARB(mtkdev->ids[0]); larbdev = data->larb_imu[larbid].dev; device_link_remove(dev, larbdev); } + kfree(mtkdev); } static int mtk_iommu_get_group_id(struct device *dev, const struct mtk_iommu_plat_data *plat_data) @@ -931,7 +958,9 @@ static int mtk_iommu_get_group_id(struct device *dev, const struct mtk_iommu_pla static struct iommu_group *mtk_iommu_device_group(struct device *dev) { - struct mtk_iommu_data *c_data = dev_iommu_priv_get(dev), *data; + struct mtk_iommu_device *mtkdev = dev_iommu_priv_get(dev); + struct mtk_iommu_data *c_data = mtkdev->iommu; + struct mtk_iommu_data *data; struct list_head *hw_list = c_data->hw_list; struct iommu_group *group; int groupid; @@ -957,32 +986,11 @@ static struct iommu_group *mtk_iommu_device_group(struct device *dev) return group; } -static int mtk_iommu_of_xlate(struct device *dev, struct of_phandle_args *args) -{ - struct platform_device *m4updev; - - if (args->args_count != 1) { - dev_err(dev, "invalid #iommu-cells(%d) property for IOMMU\n", - args->args_count); - return -EINVAL; - } - - if (!dev_iommu_priv_get(dev)) { - /* Get the m4u device */ - m4updev = of_find_device_by_node(args->np); - if (WARN_ON(!m4updev)) - return -EINVAL; - - dev_iommu_priv_set(dev, platform_get_drvdata(m4updev)); - } - - return iommu_fwspec_add_ids(dev, args->args, 1); -} - static void mtk_iommu_get_resv_regions(struct device *dev, struct list_head *head) { - struct mtk_iommu_data *data = dev_iommu_priv_get(dev); + struct mtk_iommu_device *mtkdev = dev_iommu_priv_get(dev); + struct mtk_iommu_data *data = mtkdev->iommu; unsigned int regionid = mtk_iommu_get_iova_region_id(dev, data->plat_data), i; const struct mtk_iommu_iova_region *resv, *curdom; struct iommu_resv_region *region; @@ -1012,10 +1020,10 @@ static void mtk_iommu_get_resv_regions(struct device *dev, static const struct iommu_ops mtk_iommu_ops = { .identity_domain = &mtk_iommu_identity_domain, .domain_alloc_paging = mtk_iommu_domain_alloc_paging, - .probe_device = mtk_iommu_probe_device, + .probe_device_pinf = mtk_iommu_probe_device, .release_device = mtk_iommu_release_device, .device_group = mtk_iommu_device_group, - .of_xlate = mtk_iommu_of_xlate, + .of_xlate = iommu_dummy_of_xlate, .get_resv_regions = mtk_iommu_get_resv_regions, .pgsize_bitmap = SZ_4K | SZ_64K | SZ_1M | SZ_16M, .owner = THIS_MODULE, From patchwork Thu Nov 30 01:10:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 748737 Authentication-Results: smtp.subspace.kernel.org; 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R. Silva" , Heiko Stuebner , iommu@lists.linux.dev, Jean-Philippe Brucker , Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Kees Cook , Konrad Dybcio , Krzysztof Kozlowski , Len Brown , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Lorenzo Pieralisi , Marek Szyprowski , Hector Martin , Matthias Brugger , Orson Zhai , "Rafael J. Wysocki" , Rob Clark , Robert Moore , Rob Herring , Robin Murphy , Samuel Holland , Sudeep Holla , Sven Peter , Thierry Reding , Krishna Reddy , virtualization@lists.linux.dev, Chen-Yu Tsai , Will Deacon , Yong Wu , Chunyan Zhang Cc: =?utf-8?q?Andr=C3=A9_Draszik?= , patches@lists.linux.dev Subject: [PATCH 24/30] iommu/virtio: Move to iommu_fw_alloc_per_device_ids() Date: Wed, 29 Nov 2023 21:10:31 -0400 Message-ID: <24-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> In-Reply-To: <0-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> References: X-ClientProxiedBy: SN7P222CA0017.NAMP222.PROD.OUTLOOK.COM (2603:10b6:806:124::15) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|DS0PR12MB7607:EE_ X-MS-Office365-Filtering-Correlation-Id: f184cbfa-52b3-4d89-5ed6-08dbf1412a6b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: LGVZ66x0Z/c4A6yfd8vLDEdf+b6sgChnN84rSZ7LBwHl2BtRXlBVm+2WpXBl5Lkgt3fvU9Y1jumfYyLXJwVsnSFmOeTPAuBHcQDCgsdIdbAPylZktkseaBYMxfcarg8nttCn/+57uar/E2l1KQB/VJWY9cA+j8Y3mvgbsDbFIa9pp9m991KxuSayertSROc3nPNAz51GFOUAe2rHa9DOrbyDMKntkOq92h+axz5GMHkTRVWdoZdNDpMMl9i6/YGtbvRS6eCqkt022p8DRfU3hoXgunNUV7EgTapOcWYY53teGi+TQoCViuNRCLerPKEKh1ETHIHmW21/uEqIsHCdQQUJnTpHffTwP3Gk8tXacvS3FqFSFc/FMNiAC2it8rjjbfsF1krkCJUfkUJaeBmSV8vOifI0dT6gZfKt0dbN3VQnwDogqEL3voeyWIIaQ/mn8TyHU2gNhhicbFjBJmRK9Ry0te6+5aw9mFHFSJwINCHBl7E6rQbUdzR1hUWbHP4in+htuzLmpRngudq7rkQ4bvcgHBH4gTeu/HwCZUpN60oPIz+0OPu7flsHG5DMHRHgRIQXuwjMFc4H+iKvhhBn7TWz8nARPFxV3Vj5Ug/lbRDB1hF/TzlsGlMMVErzoNN54o4jAv/2JE1X2R/zz8kc1A== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:LV2PR12MB5869.namprd12.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230031)(396003)(39860400002)(346002)(136003)(366004)(376002)(230922051799003)(186009)(451199024)(64100799003)(1800799012)(38100700002)(202311291699003)(83380400001)(1191002)(5660300002)(110136005)(2906002)(86362001)(4326008)(8676002)(8936002)(66556008)(7366002)(7406005)(7416002)(66476007)(66946007)(6486002)(478600001)(6666004)(316002)(36756003)(6506007)(41300700001)(6512007)(921008)(26005)(2616005); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Nwh4P5igKZINuWBNkgxmbvQVTx47VsyJlltLwDktBJ5Sfp+zWmHQRpNfPorx4iyl/Hgvhh1/FEeVyBF5Zq6fZ+2eyUE5WCbGEENQVCQPOwqldo36I2pczKDdV+eJ8nL0hCElkytr7kOfsogkKAV5pW5CD91YfwGzNL9eaX9C7/qO/l3e1zZUC4n4PaBymBeYddMrCztcXPyYl7P0iWtG5BA6K56QnJaLNcag9o+CbNGC+xFzJOREmljn/ZBaTzekHRAtiL/dYVB8ahqkg5ATjqWO+GoeObHVJ226nME2nEPIkZlS3Bd84gVE4AO/WNv11kXn5i45BoeLjdAi5U/cokM+QZYgLNepxmBaR1f7pMT3mwyfzNKF4jobw40tRv0LrcuUS3zIwhCnEMBKuo3G8fLapkZdyAZEVjfl6DVgov90plihm222NmdccwdRZFkrL7TI9dZwc6moWNNFPYwY+WLwDZQxitzRWQ/QjNcLiHRQPkncotfYaAbRHoNxu/GDxwvi0bRtKMMHMm8coHdM0MwGDWth9m12fNr2jfD+T9dLbuBzDQxgtxSHY0sSrJHPwYH76Jf5+Rcctt/o7vcc0Nbn8dYGs0FU1E/Q7EFdJDiLC3/hVAMfFW7xSkBWxGUpzSce4wKc/VpKg5NdJ9wyyPBItYvh+PG6dHk31G7BUwZ07mmPSX1kB5zisliy+8Qoj9vZh1PKlyjxVgQwW3ygv+MQ2KWlMn2MtxPDCvcxrKw1ngCSVMsgMV9GJUVWRSdUfxiCfF3r9MXqs1UA9ttjsz8173lGm0pI6Z+saOjrid9zq+fFjk1rkxn0Hh+bSnZbIBZ761+3jo5tvjXV3FvnfNx6MZIMnxl7/vGrNyxPDUck+d6l5FkyMs+XOoNLuwE54XUvoOvRlKlx84Tgxis7ttjSB+gqjrGGRqcdAEE9PqyyCgGkuzmB771Xyc/pcnsxYw3QCS9nQxEp1vztCE/+fcTz/nyaPpvfVdJMyVyDf7KbwZ2c92TAOXEhZykKl6qdXeppjvdL46Ctb2Qpcq5AmP6/x+gQqWM8CXH2sG4LZhcSBjJtrJHpYBs2MJbb8FUuF10DjM1hW3cVwm21wdp+VV1ZEjkKBOqRebIRzp6TpxZNr5zhgl5+Z89NRMG+U5LIDJx3nrveJCfPi/x7GoRMQHsCBx8ZEqBXpBlk8hLdGc8xDQizKMlQhoKN3t9Vdr+yRgyLqBnxZJhGWl+yhIfdn9qR+l0hnuMt+kfAXcxaS9HrOfL8TlYf93+7AFXXOt3sZTozi+zH+wkCGvp+hV2mgcV07gtlkVL8wtnDqgvcfTF5PB8xLsxnO2O/8O7WP6fB+3sjijOwEPiRTknInkW8KApty5bMTfglfpsLXa7eINg9E17IYIJxSn9kQOVk8nRnKTHIKKaaldEG+gFcKPJAJH40I5NEsbdu02UOtY86j9Vv6ttgh/yDZM0X6jl+UnvjA/X921+yeXFPEKlQzJLICs509GYnwWQG/7V4oY/8gV/svW0abeQxthJGvNGt+YWN0/PHHnXxDimEbTQfaLcso3Ons4SGokaZcshVdezW+tK1s33bzXmp51Mo0XVv7s+N X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: f184cbfa-52b3-4d89-5ed6-08dbf1412a6b X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2023 01:10:39.2211 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 6f71zxWNLJgkgz6I6UQT2udJEyUgiiFHt2tncVABgwqBz9pvFR9sJ/GUov3TVaZL X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7607 virtio supports a single iommu instance with multiple ids. It has a combined ACPI (via the VIOT table) and OF probe path, add iommu_viot_get_single_iommu() to respresent this. It already has a per-instance structure, extend it with the ids[] array and use iommu_fw_alloc_per_device_ids() to populate it. Convert the rest of the funcs from calling dev_iommu_fwspec_get() to using he per-device data and remove all use of fwspec. Signed-off-by: Jason Gunthorpe --- drivers/iommu/virtio-iommu.c | 67 +++++++++++++----------------------- 1 file changed, 23 insertions(+), 44 deletions(-) diff --git a/drivers/iommu/virtio-iommu.c b/drivers/iommu/virtio-iommu.c index b1a7b14a6c7a2f..767919bf848999 100644 --- a/drivers/iommu/virtio-iommu.c +++ b/drivers/iommu/virtio-iommu.c @@ -77,6 +77,8 @@ struct viommu_endpoint { struct viommu_dev *viommu; struct viommu_domain *vdomain; struct list_head resv_regions; + unsigned int num_ids; + u32 ids[] __counted_by(num_ids); }; struct viommu_request { @@ -510,19 +512,16 @@ static int viommu_add_resv_mem(struct viommu_endpoint *vdev, return 0; } -static int viommu_probe_endpoint(struct viommu_dev *viommu, struct device *dev) +static int viommu_probe_endpoint(struct viommu_endpoint *vdev) { int ret; u16 type, len; size_t cur = 0; size_t probe_len; + struct device *dev = vdev->dev; struct virtio_iommu_req_probe *probe; struct virtio_iommu_probe_property *prop; - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); - struct viommu_endpoint *vdev = dev_iommu_priv_get(dev); - - if (!fwspec->num_ids) - return -EINVAL; + struct viommu_dev *viommu = vdev->viommu; probe_len = sizeof(*probe) + viommu->probe_size + sizeof(struct virtio_iommu_req_tail); @@ -535,7 +534,7 @@ static int viommu_probe_endpoint(struct viommu_dev *viommu, struct device *dev) * For now, assume that properties of an endpoint that outputs multiple * IDs are consistent. Only probe the first one. */ - probe->endpoint = cpu_to_le32(fwspec->ids[0]); + probe->endpoint = cpu_to_le32(vdev->ids[0]); ret = viommu_send_req_sync(viommu, probe, probe_len); if (ret) @@ -721,7 +720,6 @@ static int viommu_attach_dev(struct iommu_domain *domain, struct device *dev) int i; int ret = 0; struct virtio_iommu_req_attach req; - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); struct viommu_endpoint *vdev = dev_iommu_priv_get(dev); struct viommu_domain *vdomain = to_viommu_domain(domain); @@ -763,8 +761,8 @@ static int viommu_attach_dev(struct iommu_domain *domain, struct device *dev) if (vdomain->bypass) req.flags |= cpu_to_le32(VIRTIO_IOMMU_ATTACH_F_BYPASS); - for (i = 0; i < fwspec->num_ids; i++) { - req.endpoint = cpu_to_le32(fwspec->ids[i]); + for (i = 0; i < vdev->num_ids; i++) { + req.endpoint = cpu_to_le32(vdev->ids[i]); ret = viommu_send_req_sync(vdomain->viommu, &req, sizeof(req)); if (ret) @@ -792,7 +790,6 @@ static void viommu_detach_dev(struct viommu_endpoint *vdev) int i; struct virtio_iommu_req_detach req; struct viommu_domain *vdomain = vdev->vdomain; - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(vdev->dev); if (!vdomain) return; @@ -802,8 +799,8 @@ static void viommu_detach_dev(struct viommu_endpoint *vdev) .domain = cpu_to_le32(vdomain->id), }; - for (i = 0; i < fwspec->num_ids; i++) { - req.endpoint = cpu_to_le32(fwspec->ids[i]); + for (i = 0; i < vdev->num_ids; i++) { + req.endpoint = cpu_to_le32(vdev->ids[i]); WARN_ON(viommu_send_req_sync(vdev->viommu, &req, sizeof(req))); } vdomain->nr_endpoints--; @@ -974,34 +971,21 @@ static void viommu_get_resv_regions(struct device *dev, struct list_head *head) static struct iommu_ops viommu_ops; static struct virtio_driver virtio_iommu_drv; -static int viommu_match_node(struct device *dev, const void *data) -{ - return device_match_fwnode(dev->parent, data); -} - -static struct viommu_dev *viommu_get_by_fwnode(struct fwnode_handle *fwnode) -{ - struct device *dev = driver_find_device(&virtio_iommu_drv.driver, NULL, - fwnode, viommu_match_node); - put_device(dev); - - return dev ? dev_to_virtio(dev)->priv : NULL; -} - -static struct iommu_device *viommu_probe_device(struct device *dev) +static struct iommu_device *viommu_probe_device(struct iommu_probe_info *pinf) { int ret; + struct viommu_dev *viommu; struct viommu_endpoint *vdev; - struct viommu_dev *viommu = NULL; - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); + struct device *dev = pinf->dev; - viommu = viommu_get_by_fwnode(fwspec->iommu_fwnode); - if (!viommu) - return ERR_PTR(-ENODEV); + viommu = iommu_viot_get_single_iommu(pinf, &viommu_ops, + struct viommu_dev, iommu); + if (IS_ERR(viommu)) + return ERR_CAST(viommu); - vdev = kzalloc(sizeof(*vdev), GFP_KERNEL); - if (!vdev) - return ERR_PTR(-ENOMEM); + vdev = iommu_fw_alloc_per_device_ids(pinf, vdev); + if (IS_ERR(vdev)) + return ERR_CAST(vdev); vdev->dev = dev; vdev->viommu = viommu; @@ -1010,7 +994,7 @@ static struct iommu_device *viommu_probe_device(struct device *dev) if (viommu->probe_size) { /* Get additional information for this endpoint */ - ret = viommu_probe_endpoint(viommu, dev); + ret = viommu_probe_endpoint(vdev); if (ret) goto err_free_dev; } @@ -1050,11 +1034,6 @@ static struct iommu_group *viommu_device_group(struct device *dev) return generic_device_group(dev); } -static int viommu_of_xlate(struct device *dev, struct of_phandle_args *args) -{ - return iommu_fwspec_add_ids(dev, args->args, 1); -} - static bool viommu_capable(struct device *dev, enum iommu_cap cap) { switch (cap) { @@ -1070,12 +1049,12 @@ static bool viommu_capable(struct device *dev, enum iommu_cap cap) static struct iommu_ops viommu_ops = { .capable = viommu_capable, .domain_alloc = viommu_domain_alloc, - .probe_device = viommu_probe_device, + .probe_device_pinf = viommu_probe_device, .probe_finalize = viommu_probe_finalize, .release_device = viommu_release_device, .device_group = viommu_device_group, .get_resv_regions = viommu_get_resv_regions, - .of_xlate = viommu_of_xlate, + .of_xlate = iommu_dummy_of_xlate, .owner = THIS_MODULE, .default_domain_ops = &(const struct iommu_domain_ops) { .attach_dev = viommu_attach_dev, From patchwork Thu Nov 30 01:10:32 2023 Content-Type: text/plain; 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Received: from LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) by PH0PR12MB5484.namprd12.prod.outlook.com (2603:10b6:510:eb::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7046.24; Thu, 30 Nov 2023 01:10:46 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93%4]) with mapi id 15.20.7046.015; Thu, 30 Nov 2023 01:10:46 +0000 From: Jason Gunthorpe To: acpica-devel@lists.linux.dev, Andy Gross , Alim Akhtar , Alyssa Rosenzweig , Bjorn Andersson , AngeloGioacchino Del Regno , asahi@lists.linux.dev, Baolin Wang , devicetree@vger.kernel.org, Frank Rowand , Hanjun Guo , "Gustavo A. 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Wysocki" , Rob Clark , Robert Moore , Rob Herring , Robin Murphy , Samuel Holland , Sudeep Holla , Sven Peter , Thierry Reding , Krishna Reddy , virtualization@lists.linux.dev, Chen-Yu Tsai , Will Deacon , Yong Wu , Chunyan Zhang Cc: =?utf-8?q?Andr=C3=A9_Draszik?= , patches@lists.linux.dev Subject: [PATCH 25/30] iommu/iort: Add iommu_iort_get_single_iommu() Date: Wed, 29 Nov 2023 21:10:32 -0400 Message-ID: <25-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> In-Reply-To: <0-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> References: X-ClientProxiedBy: SN7P222CA0024.NAMP222.PROD.OUTLOOK.COM (2603:10b6:806:124::20) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|PH0PR12MB5484:EE_ X-MS-Office365-Filtering-Correlation-Id: 0ba4ed4b-c8b8-4b73-6c85-08dbf1412b2e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 2JeKNRlI6vQmBvNqI3r/MC2iGwy98kh+yqTFTheuJ/cA4n/03zJRILbuuiDEw9A5ByJYqzcmEIH/0B/41ldDouMvELZwBYlQ85VJTT4IlfMEaGEwxqFxzxqrCAuoMd/BgPdmJrSvNbpFbFkZU5+Xp6jjBUleRg8Iqph2DZ7yC2rC/W7O7BTZU+b6IKHnlUKK9M6MMYrh1CC1w7LUKfSxgEZHTPvVaoKB2YZFpkau2GYCjuVjvxNXRFSXZyQ7X/oJF4Y1rWl18BN+wqXJp6rzW3va+8ECDJ/FS9A9wuQNEExja55s/avbZa8/dUATA0fvijYIGaSdVgrZdHt1oLHMYuhc3QD5QDTt63Oij/0bucxrj0KOU+OfwXESN4I/hCYJqlJ3ilti63alsGhgvqg1wmxnfvgd6+22UnJ9oCYA4RPakyqVUexAJZ0alFG747F4dhZ0XHHmzWSqKCmjrkscoXMfaEwiqxfT7AtXpTfA1pPJFLYmJiPJKWOrED775HnupYgOc+bWB9oX4Wh9J/17amBZ64CwNqnYlrY5k/uvtHUlu9fvGZQKiLmgS0XveIlPMgKeGsvCmfToC9PVGTrfYzIIVdfqUivMN62DODe/sStO3etVABOJ4pV61JFMMx7YjS+o7XmBvXStWJvgE9j7Dg== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:LV2PR12MB5869.namprd12.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230031)(366004)(346002)(136003)(396003)(39860400002)(376002)(230922051799003)(451199024)(1800799012)(186009)(64100799003)(1191002)(8936002)(110136005)(8676002)(316002)(66556008)(4326008)(86362001)(66476007)(6486002)(478600001)(66946007)(41300700001)(36756003)(921008)(7416002)(7366002)(2906002)(7406005)(5660300002)(38100700002)(2616005)(6512007)(6506007)(6666004)(83380400001)(26005)(202311291699003); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: +DDY0B7tA7PB0dRRBXyE54dSkQ0AmSQcYgFiz2FZb1NHkGPaUzdec4FSkiYNwpxwSjfTnKSf6tREttknkmX6iTtSon1wC75j+GyMDCxBE92Pjzj9xGjyJbekwTsaQhB2vN44Wnp5Hml+5yvlMbmhndXKCFAsPeMS4gCG++ECIZdZ1KyIKBV8CvR7aNdrIk8pQsHKJwWzmbNVZDKuMQvm6oT5hftMZub4VppMA+73lFTR/ev0imkt+O8BWmYVykaoQIiDVQD5o19OM7txglBbhMgDMdjrINkglUabxpPMFomgRHTIW2JT+yGrYezzVnNAMJ5brZMlu1Ad8edmP+R2rfcRtqZyKU35oHvR794VFr5PYBBeUU15oXxeqeigZkCvGqDwU7V93VPUV9OJUhgN3aa/6TQzA0WJazb24VeIWkolrWOBAu0RgwKgC7vRLyBDx8dEou0ZEB8ISmI2q66KgyIusfa2hykuCoxKtoEtjP7CqRKvJO3G/wPIVxuFMF2NTA0d5e6KOMMOmVYhUAWRZ3DcGzZco8t3oUo65dFXQMRgbuubCR6rrKRAdoNLYvi0XRtujrVWX1q/UlM9/oNMUoOdryarR6WlwdSHEZOIax/8vRsOmGDByLct0Fddpi3pfwwerKL35H//n3l9ly1H8iKPtsMFyXe1aOkLw73si85AdRROubo9K+bo971gBumTqdwfJmNJFi8nB5KWI7iQNp7MjwIH3N41AkRQ9dAQ46KX2EMqsvwR+7hw7NRYTeUF8QNaPEEKDakIQLY0whT1SoWXa7XxI7vT8cKfZEhJMo/khN9PSAFbUy6lEoHGTHbQYE+5ciA7TaZDI7QDJJOh+ww4useldU/mDftwfuYNbOeUmVCBLOwYzFTAVwOlhN7wAK8jNRannpcCUmOsbSnclGaXDpupinuTxk4whBLW+Zp3lwdnBpfLUenJbpTMc940d5tkXiMT6XCGNQyjFfwxAmZVouFDOSoQ9k+FODvLoE3FFuGvxaI1iNUrjkQPjogvb7UqaTJvdVn0PmYpRT7Rri08TrRFUFq2VVDK1wgYXVs++p2RrPdgGzK1g3CLyvQGcLxI2FRRGkL+I6i45QArP4zWa0i+DB6hUCSk0Dkk/LCZ+0BUQviPOUa0kmVnlTFC1g/wJSZ8yUFyALKA+c3NnPPoF8yrKckIx3HsOUf+tlD+jlW4GXQxvUl7hPqS3CI0DILqkb/94D8YlWkVeycE3WDjZ9l/PBKDKGbq9AjKNhNAmZT7QtJ4YmDTwHuv9uker7jj5ZfBIeSA/Gj247SI1sm2rs2omunZju3kZrkoYht8XKV6QNDq3nGd+b8tJrSH7Lx9rVlB8/YSLGb0ms49bdPuy9zmUx2jlnUF8iI4MUTs4iukSKky87SbPfvV/lEb7ZJkPHVbgRjQA3zsKBZImjD8ifwvKX8YpqFKHVbA+y9myucbWetzo97TyPyKSN7qanqNUcnfPYEQ+UsXAixgCLB26DqLO4y49mEuckrAC3WLtteWoACWpg32sBcmdx043pSjtqI1mFkeeXZYgV0o3Ew1GbGOds+cgqLh8gd6RNsT+mGl6cLxn5E6zxM3GnBz X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 0ba4ed4b-c8b8-4b73-6c85-08dbf1412b2e X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2023 01:10:40.5310 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: T1ptQ4YEgwN12VSPI5d2e8VoSf0UaubtgfJzy2NZU2EGMrMwSithTO2wuZ6PAL3w X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB5484 This API is basically the same as iommu_of_get_single_iommu(), except that it will try to parse the ACPI IORT table if it is available. The ACPI IORT table can return a flags value to indicate IOMMU_FWSPEC_PCI_RC_ATS, return this through an output flags pointer. Signed-off-by: Jason Gunthorpe --- drivers/acpi/arm64/iort.c | 3 +- drivers/acpi/scan.c | 1 + drivers/iommu/Makefile | 1 + drivers/iommu/iommu.c | 3 ++ drivers/iommu/iort_iommu.c | 98 ++++++++++++++++++++++++++++++++++++ include/linux/acpi_iort.h | 1 + include/linux/iommu-driver.h | 41 +++++++++++++++ 7 files changed, 146 insertions(+), 2 deletions(-) create mode 100644 drivers/iommu/iort_iommu.c diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c index 798c0b344f4be8..6b2d50cc9ac180 100644 --- a/drivers/acpi/arm64/iort.c +++ b/drivers/acpi/arm64/iort.c @@ -79,8 +79,7 @@ static inline int iort_set_fwnode(struct acpi_iort_node *iort_node, * * Returns: fwnode_handle pointer on success, NULL on failure */ -static inline struct fwnode_handle *iort_get_fwnode( - struct acpi_iort_node *node) +struct fwnode_handle *iort_get_fwnode(struct acpi_iort_node *node) { struct iort_fwnode *curr; struct fwnode_handle *fwnode = NULL; diff --git a/drivers/acpi/scan.c b/drivers/acpi/scan.c index 9ec01196573b6e..eb7406cdc9a464 100644 --- a/drivers/acpi/scan.c +++ b/drivers/acpi/scan.c @@ -1571,6 +1571,7 @@ static int acpi_iommu_configure_id(struct device *dev, const u32 *id_in) struct iommu_probe_info pinf = { .dev = dev, .is_dma_configure = true, + .acpi_map_id = id_in, .is_acpi = true, }; diff --git a/drivers/iommu/Makefile b/drivers/iommu/Makefile index 9c35b106cecb2e..ebf6c151a97746 100644 --- a/drivers/iommu/Makefile +++ b/drivers/iommu/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_IOMMU_IO_PGTABLE_LPAE) += io-pgtable-arm.o obj-$(CONFIG_IOMMU_IO_PGTABLE_DART) += io-pgtable-dart.o obj-$(CONFIG_IOMMU_IOVA) += iova.o obj-$(CONFIG_OF_IOMMU) += of_iommu.o +obj-$(CONFIG_ACPI_IORT) += iort_iommu.o obj-$(CONFIG_ACPI_VIOT) += viot_iommu.o obj-$(CONFIG_MSM_IOMMU) += msm_iommu.o obj-$(CONFIG_IPMMU_VMSA) += ipmmu-vmsa.o diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index caf14a53ed1952..7468a64778931b 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -3030,6 +3030,9 @@ iommu_device_from_fwnode_pinf(struct iommu_probe_info *pinf, if (!pinf->num_ids) pinf->cached_single_iommu = true; + if (pinf->is_acpi) + pinf->acpi_fwnode = fwnode; + if (!iommu || iommu->fwnode != fwnode) { iommu = iommu_device_from_fwnode(fwnode); if (!iommu) diff --git a/drivers/iommu/iort_iommu.c b/drivers/iommu/iort_iommu.c new file mode 100644 index 00000000000000..9a997b0fd5d5f1 --- /dev/null +++ b/drivers/iommu/iort_iommu.c @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES + */ +#include +#include + +#include +#include + +struct parse_info { + struct iommu_probe_info *pinf; + const struct iommu_ops *ops; + u32 *ids; +}; + +static bool iort_iommu_driver_enabled(struct iommu_probe_info *pinf, u8 type) +{ + switch (type) { + case ACPI_IORT_NODE_SMMU_V3: + return IS_ENABLED(CONFIG_ARM_SMMU_V3); + case ACPI_IORT_NODE_SMMU: + return IS_ENABLED(CONFIG_ARM_SMMU); + default: + dev_warn(pinf->dev, + FW_WARN + "IORT node type %u does not describe an SMMU\n", + type); + return false; + } +} + +static int parse_single_iommu(struct acpi_iort_node *iort_iommu, u32 streamid, + void *_info) +{ + struct parse_info *info = _info; + struct iommu_probe_info *pinf = info->pinf; + struct fwnode_handle *fwnode; + struct iommu_device *iommu; + + fwnode = iort_get_fwnode(iort_iommu); + if (!fwnode) + return -ENODEV; + + iommu = iommu_device_from_fwnode_pinf(pinf, info->ops, fwnode); + if (IS_ERR(iommu)) { + if (iommu == ERR_PTR(-EPROBE_DEFER) && + !iort_iommu_driver_enabled(pinf, iort_iommu->type)) + return -ENODEV; + return PTR_ERR(iommu); + } + iommu_fw_cache_id(pinf, streamid); + return 0; +} + +static int parse_read_ids(struct acpi_iort_node *iommu, u32 streamid, + void *_info) +{ + struct parse_info *info = _info; + + *info->ids = streamid; + (*info->ids)++; + return 0; +} + +static int iort_get_u32_ids(struct iommu_probe_info *pinf, u32 *ids) +{ + struct parse_info info = { .pinf = pinf, .ids = ids }; + struct iort_params params; + + return iort_iommu_for_each_id(pinf->dev, pinf->acpi_map_id, ¶ms, + parse_read_ids, &info); +} + +struct iommu_device * +__iommu_iort_get_single_iommu(struct iommu_probe_info *pinf, + const struct iommu_ops *ops, + struct iort_params *params) +{ + struct parse_info info = { .pinf = pinf, .ops = ops }; + struct iort_params unused_params; + int err; + + if (!pinf->is_dma_configure || !pinf->is_acpi) + return ERR_PTR(-ENODEV); + + if (!params) + params = &unused_params; + + iommu_fw_clear_cache(pinf); + err = iort_iommu_for_each_id(pinf->dev, pinf->acpi_map_id, params, + parse_single_iommu, &info); + if (err) + return ERR_PTR(err); + pinf->get_u32_ids = iort_get_u32_ids; + return iommu_fw_finish_get_single(pinf); +} +EXPORT_SYMBOL(__iommu_iort_get_single_iommu); diff --git a/include/linux/acpi_iort.h b/include/linux/acpi_iort.h index 13f0cefb930693..bacba2a76c3acb 100644 --- a/include/linux/acpi_iort.h +++ b/include/linux/acpi_iort.h @@ -40,6 +40,7 @@ typedef int (*iort_for_each_fn)(struct acpi_iort_node *iommu, u32 streamid, int iort_iommu_for_each_id(struct device *dev, const u32 *id_in, struct iort_params *params, iort_for_each_fn fn, void *info); +struct fwnode_handle *iort_get_fwnode(struct acpi_iort_node *node); #ifdef CONFIG_ACPI_IORT u32 iort_msi_map_id(struct device *dev, u32 id); diff --git a/include/linux/iommu-driver.h b/include/linux/iommu-driver.h index ce0ba1f35bb5dc..c4e133cdef2c78 100644 --- a/include/linux/iommu-driver.h +++ b/include/linux/iommu-driver.h @@ -19,6 +19,7 @@ struct of_phandle_args; struct fwnode_handle; struct iommu_device; +struct iort_params; struct iommu_ops; /* @@ -39,7 +40,9 @@ struct iommu_probe_info { struct list_head *deferred_group_list; struct iommu_device *cached_iommu; struct device_node *of_master_np; + struct fwnode_handle *acpi_fwnode; const u32 *of_map_id; + const u32 *acpi_map_id; int (*get_u32_ids)(struct iommu_probe_info *pinf, u32 *ids); unsigned int num_ids; u32 cached_ids[8]; @@ -63,6 +66,21 @@ iommu_device_from_fwnode_pinf(struct iommu_probe_info *pinf, struct fwnode_handle *fwnode); struct iommu_device *iommu_fw_finish_get_single(struct iommu_probe_info *pinf); +/** + * iommu_fw_acpi_fwnode - Get an ACPI fwnode_handle + * @pinf: The iommu_probe_info + * + * Return the ACPI version of the fwnode describing the iommu data that is + * associated with the device being probed. + */ +static inline struct fwnode_handle * +iommu_fw_acpi_fwnode(struct iommu_probe_info *pinf) +{ + if (!pinf->is_acpi) + return NULL; + return pinf->acpi_fwnode; +} + typedef int (*iommu_of_xlate_fn)(struct iommu_device *iommu, struct of_phandle_args *args, void *priv); void iommu_of_allow_bus_probe(struct iommu_probe_info *pinf); @@ -213,4 +231,27 @@ __iommu_viot_get_single_iommu(struct iommu_probe_info *pinf, __iommu_of_get_single_iommu(pinf, ops, -1)), \ drv_struct, member) +#if IS_ENABLED(CONFIG_ACPI_IORT) +struct iommu_device * +__iommu_iort_get_single_iommu(struct iommu_probe_info *pinf, + const struct iommu_ops *ops, + struct iort_params *params); +#else +static inline struct iommu_device * +__iommu_iort_get_single_iommu(struct iommu_probe_info *pinf, + const struct iommu_ops *ops, + struct iort_params *params) +{ + return ERR_PTR(-ENODEV); +} +#endif +#define iommu_iort_get_single_iommu(pinf, ops, params, drv_struct, member) \ + ({ \ + memset(params, 0, sizeof(*(params))); \ + container_of_err(__iommu_first(__iommu_iort_get_single_iommu( \ + pinf, ops, params), \ + __iommu_of_get_single_iommu( \ + pinf, ops, -1)), \ + drv_struct, member) \ + }) #endif From patchwork Thu Nov 30 01:10:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 748735 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="CN8+7BV7" Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2053.outbound.protection.outlook.com [40.107.243.53]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D415B10CB; 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Thu, 30 Nov 2023 01:10:46 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93%4]) with mapi id 15.20.7046.015; Thu, 30 Nov 2023 01:10:46 +0000 From: Jason Gunthorpe To: acpica-devel@lists.linux.dev, Andy Gross , Alim Akhtar , Alyssa Rosenzweig , Bjorn Andersson , AngeloGioacchino Del Regno , asahi@lists.linux.dev, Baolin Wang , devicetree@vger.kernel.org, Frank Rowand , Hanjun Guo , "Gustavo A. R. Silva" , Heiko Stuebner , iommu@lists.linux.dev, Jean-Philippe Brucker , Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Kees Cook , Konrad Dybcio , Krzysztof Kozlowski , Len Brown , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Lorenzo Pieralisi , Marek Szyprowski , Hector Martin , Matthias Brugger , Orson Zhai , "Rafael J. Wysocki" , Rob Clark , Robert Moore , Rob Herring , Robin Murphy , Samuel Holland , Sudeep Holla , Sven Peter , Thierry Reding , Krishna Reddy , virtualization@lists.linux.dev, Chen-Yu Tsai , Will Deacon , Yong Wu , Chunyan Zhang Cc: =?utf-8?q?Andr=C3=A9_Draszik?= , patches@lists.linux.dev Subject: [PATCH 26/30] iommu/arm-smmu-v3: Move to iommu_fw_alloc_per_device_ids() Date: Wed, 29 Nov 2023 21:10:33 -0400 Message-ID: <26-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> In-Reply-To: <0-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> References: X-ClientProxiedBy: SN6PR08CA0001.namprd08.prod.outlook.com (2603:10b6:805:66::14) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|PH0PR12MB5484:EE_ X-MS-Office365-Filtering-Correlation-Id: 72d5ace2-3b95-4d23-87a1-08dbf1412b2c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 92Xkiy7Ge3EyyeZMq1jHCmrHDof2nfgXnt5krfuyp9sXi5zeS2ZGZyMrV6BODuhKVOxL/AUCDG8k3aP3Q9diTte8jlkNdoNTiQaEQAg1uA5/BzT0l4TrCaV2MkMLSU5bCsDB3Oz8BtjmiY6ToeQJtpjT+YOTO8FW5SnVCUg615BnKNDZBoHvhUF70D5L93CnxfzK1mnAChT1KjyqQHJU6NcloZjQNdI7Zz4W0B6BOIVpK1VVt1sbObC38NKWcahueEozbssTYBNci7B9u0RjxjitSPIxiCypxWTKgNHQJSZ8g70qh2AJn0dWjHpbYzOQJWqk/SRx3BnT3IIixzAHsTKifAShMiXY3nxFT6OicBPkwv38/2jIw+bGZk8Gh8VoPAqa6THx13y9KP3GxVM1Y9Dzqze7kBxN80YpqcT8BOyx+Zq8qhtokRrwuA3Aicz37U2/uMHmqCG06Bj6MqP6JneUuURaUCXBcgVIQgT382RsNifCMTixt+yuCDzwva11J4DFikqxx+pKbo+NeC63iCeUxnJqJuIIP1NwvYUrE62z7QC6kmrU9w5uW1T9PtpUlB+ziRAnilzZrRb9nGhDzmmT3Ck7P9yNIGYCZ4mzrKsLw+3/BnpZzV8gNfejkPvWw1c2yn5WpHJRazxA+uqL6g== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:LV2PR12MB5869.namprd12.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230031)(366004)(346002)(136003)(396003)(39860400002)(376002)(230922051799003)(451199024)(1800799012)(186009)(64100799003)(1191002)(8936002)(110136005)(8676002)(316002)(66556008)(4326008)(86362001)(66476007)(6486002)(478600001)(66946007)(41300700001)(36756003)(921008)(7416002)(7366002)(2906002)(7406005)(5660300002)(38100700002)(2616005)(6512007)(6506007)(6666004)(83380400001)(26005)(202311291699003); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: sJvPkKnT8OSWWSISjBxvPyOFfkzFZcWpoixVo4xEwL74hOkh8fL0JxMduSr+AvWSIcipMikb42ZUgKnGDZvvDZBR+Ugsinx8GGDY1LACAoRCpOBYFipKMSXv8r+ZfjVFEk9IvOIZkInwyBBzRQdPs2onnnLRZQT/6aKmLbdXmqgcGXfjlLsTeC2DDVCebf0nRYY0/5fOZME9YxM7I9YZ0xF7+GQ1rPAD4qJuNCfB5wOm3UY74IUQM0Ss1ftMB/8gtpp0dShVgtv3X7p1zQ82a7/2EC8Rz+QQKQfZXAPvUdHz9FAUKJcmIqwyl4b8jNMVLrWFlGxVw+ZDe1pc22HAQ34Uk+mgYPwMeOUEDXEeJqBitoe4N6XDnw1vLSSwbCD+x1XHy4ufGmay8me0gD9x0tdtTicRP6AbVpW7Bd/dFCp2eAS2bjcRiw0OM3I7iY6AK0BbPZ9EuepRBZ9thCy7nHwLm3fCgmQpv1xdAgSU9BbsYQJcUr/sp6QD9j6i1y3LRPZl/PomMsl0NI1XjW7b2qg3voR5Ki22pcY1owZHkJrNfc9u+np6svDjw3Q91BDyh1Sc2RLIcVlL0tKDv+n/TKgy9NN6sGHU5G6SphvazGn0udlfpgyK5ZIMjVe6O3J0mXsBGX3SZeIMDQYoVkDYNN9c2NW67dq0nbq9eKguBuLaB0F7rK2OZ36WCqTNBxbvCqTRSZpDlQ56XBPAB4zsAthR20n9c2ReguPEYgRNJduX94s5PQMF1aECpAPafZhDZYDjh0rnU6l8h6J7Lqa1H6hCVYSZDVYCDxWEz8LRBFq1nBHPDbtZhWcgpBthIAd/6isoxsBxOknvJjkgDZ3MTbf2ZJn8v/Ipos9ft6k3Z6V29yM8BL0tshhVfkuR0lKC4bOAcNXIKMa1j3rJCyogOZFSNrf3QSZ+/3iZoP6e6VMQpH9BYU7cGnfmP6qW6loNphSG78algA7ncihi95VlKwU7WAAgYQoqkwIS/3d2S3V72fDYtYlX6nMaSHvKZYEZewHnHv4Qw4PKom31Hoz8qQ7zkUoKCd2vZ4F4aZMsfu3p7iFgvRKzRJHF+J7NT1bIqH/222/Nb8UPJ5WnVsrvPszLPtjlSE3e4MHjgSy9uMRsNCIYnhitK70li3C5oqKkgDqlkT6J/MfTRbGfP5hEcCCQR8l13bY+BeQAEEjZ/dM46feMtnYIB3gCheDHlG8/yfYFgGpGxMFqdyCGs+hM2xNjqg9xRkllCTfj80tiSxMCpwIWYsBGQ/6PpXWUS2IK+BALXA6UQNjwSW/WA/lygxzosVeSssxImkZkxWhVdwrd12tS7R6pZHPVu03PT8q9EiVs/eknw/dhTVGTTjT9A04bgz2y24RL2wUXn1KLhmR1IuKdpwA12E7Ap0hcGp+PXF8i1YMEn7HKD3Oj2nvEWWyIT+E1Khqv3DcmFox6rEwkPNbD0vEJZOD0ErHHKRK+eaXaRmOBEEZ6tYddrs4MRiH/LKQseXA6ogAstefjZux1ay4QWGam54uLgwmZvY/HB33OtAYFNtsZQ2cyJYtIs52nAGmxvsK3I4R+3jWYCkZW8Hi5JEYo2ROcy0q89VgK X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 72d5ace2-3b95-4d23-87a1-08dbf1412b2c X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2023 01:10:40.4864 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 4t7oHSiKphoopW92I1Rm+6YwRFEu5JL6Inb7Ybt6vg/SK6SPNORu2XecHKqXHdbE X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB5484 SMMUv3 supports a single iommu instance with multiple ids. It has a combined ACPI (via the IORT table) and OF probe path, add iommu_iort_get_single_iommu() to respresent this. It already has a per-instance structure, extend it with the ids[] array and use iommu_fwb_alloc_per_device_ids() to populate it. Convert the rest of the funcs from calling dev_iommu_fwspec_get() to using the per-device data and remove all use of fwspec. Directly call iort_iommu_get_resv_regions() and pass in the internal id array instead of getting it from the fwspec. Signed-off-by: Jason Gunthorpe --- drivers/acpi/arm64/iort.c | 2 - drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 74 +++++++++------------ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 4 ++ include/linux/iommu-driver.h | 2 +- 4 files changed, 35 insertions(+), 47 deletions(-) diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c index 6b2d50cc9ac180..acd2e48590f37a 100644 --- a/drivers/acpi/arm64/iort.c +++ b/drivers/acpi/arm64/iort.c @@ -1297,8 +1297,6 @@ static void iort_named_component_init(struct device *dev, props[0] = PROPERTY_ENTRY_U32("pasid-num-bits", FIELD_GET(ACPI_IORT_NC_PASID_BITS, nc->node_flags)); - if (nc->node_flags & ACPI_IORT_NC_STALL_SUPPORTED) - props[1] = PROPERTY_ENTRY_BOOL("dma-can-stall"); if (device_create_managed_software_node(dev, props, NULL)) dev_warn(dev, "Could not add device properties\n"); diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 1855d3892b15f8..1a43c677e2feaf 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -26,9 +26,9 @@ #include #include #include +#include #include "arm-smmu-v3.h" -#include "../../dma-iommu.h" #include "../../iommu-sva.h" static bool disable_bypass = true; @@ -2255,12 +2255,11 @@ static bool arm_smmu_ats_supported(struct arm_smmu_master *master) { struct device *dev = master->dev; struct arm_smmu_device *smmu = master->smmu; - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); if (!(smmu->features & ARM_SMMU_FEAT_ATS)) return false; - if (!(fwspec->flags & IOMMU_FWSPEC_PCI_RC_ATS)) + if (!master->pci_rc_ats) return false; return dev_is_pci(dev) && pci_ats_supported(to_pci_dev(dev)); @@ -2382,14 +2381,10 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) { int ret = 0; unsigned long flags; - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); struct arm_smmu_device *smmu; struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); struct arm_smmu_master *master; - if (!fwspec) - return -ENOENT; - master = dev_iommu_priv_get(dev); smmu = master->smmu; @@ -2529,15 +2524,6 @@ arm_smmu_iova_to_phys(struct iommu_domain *domain, dma_addr_t iova) static struct platform_driver arm_smmu_driver; -static -struct arm_smmu_device *arm_smmu_get_by_fwnode(struct fwnode_handle *fwnode) -{ - struct device *dev = driver_find_device_by_fwnode(&arm_smmu_driver.driver, - fwnode); - put_device(dev); - return dev ? dev_get_drvdata(dev) : NULL; -} - static bool arm_smmu_sid_in_range(struct arm_smmu_device *smmu, u32 sid) { unsigned long limit = smmu->strtab_cfg.num_l1_ents; @@ -2568,17 +2554,16 @@ static int arm_smmu_insert_master(struct arm_smmu_device *smmu, int ret = 0; struct arm_smmu_stream *new_stream, *cur_stream; struct rb_node **new_node, *parent_node = NULL; - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(master->dev); - master->streams = kcalloc(fwspec->num_ids, sizeof(*master->streams), + master->streams = kcalloc(master->num_ids, sizeof(*master->streams), GFP_KERNEL); if (!master->streams) return -ENOMEM; - master->num_streams = fwspec->num_ids; + master->num_streams = master->num_ids; mutex_lock(&smmu->streams_mutex); - for (i = 0; i < fwspec->num_ids; i++) { - u32 sid = fwspec->ids[i]; + for (i = 0; i < master->num_ids; i++) { + u32 sid = master->ids[i]; new_stream = &master->streams[i]; new_stream->id = sid; @@ -2627,13 +2612,12 @@ static void arm_smmu_remove_master(struct arm_smmu_master *master) { int i; struct arm_smmu_device *smmu = master->smmu; - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(master->dev); if (!smmu || !master->streams) return; mutex_lock(&smmu->streams_mutex); - for (i = 0; i < fwspec->num_ids; i++) + for (i = 0; i < master->num_ids; i++) rb_erase(&master->streams[i].node, &smmu->streams); mutex_unlock(&smmu->streams_mutex); @@ -2642,26 +2626,27 @@ static void arm_smmu_remove_master(struct arm_smmu_master *master) static struct iommu_ops arm_smmu_ops; -static struct iommu_device *arm_smmu_probe_device(struct device *dev) +static struct iommu_device *arm_smmu_probe_device(struct iommu_probe_info *pinf) { int ret; + struct device *dev = pinf->dev; struct arm_smmu_device *smmu; struct arm_smmu_master *master; - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); + struct iort_params params; - if (WARN_ON_ONCE(dev_iommu_priv_get(dev))) - return ERR_PTR(-EBUSY); + smmu = iommu_iort_get_single_iommu(pinf, &arm_smmu_ops, ¶ms, + struct arm_smmu_device, iommu); + if (IS_ERR(smmu)) + return ERR_CAST(smmu); - smmu = arm_smmu_get_by_fwnode(fwspec->iommu_fwnode); - if (!smmu) - return ERR_PTR(-ENODEV); - - master = kzalloc(sizeof(*master), GFP_KERNEL); - if (!master) - return ERR_PTR(-ENOMEM); + master = iommu_fw_alloc_per_device_ids(pinf, master); + if (IS_ERR(master)) + return ERR_CAST(master); master->dev = dev; master->smmu = smmu; + master->pci_rc_ats = params.pci_rc_ats; + master->acpi_fwnode = iommu_fw_acpi_fwnode(pinf); INIT_LIST_HEAD(&master->bonds); dev_iommu_priv_set(dev, master); @@ -2670,7 +2655,8 @@ static struct iommu_device *arm_smmu_probe_device(struct device *dev) goto err_free_master; device_property_read_u32(dev, "pasid-num-bits", &master->ssid_bits); - master->ssid_bits = min(smmu->ssid_bits, master->ssid_bits); + master->ssid_bits = min(smmu->ssid_bits, + max(params.pasid_num_bits, master->ssid_bits)); /* * Note that PASID must be enabled before, and disabled after ATS: @@ -2687,7 +2673,8 @@ static struct iommu_device *arm_smmu_probe_device(struct device *dev) CTXDESC_LINEAR_CDMAX); if ((smmu->features & ARM_SMMU_FEAT_STALLS && - device_property_read_bool(dev, "dma-can-stall")) || + (device_property_read_bool(dev, "dma-can-stall") || + params.dma_can_stall)) || smmu->features & ARM_SMMU_FEAT_STALL_FORCE) master->stall_enabled = true; @@ -2744,14 +2731,10 @@ static int arm_smmu_enable_nesting(struct iommu_domain *domain) return ret; } -static int arm_smmu_of_xlate(struct device *dev, struct of_phandle_args *args) -{ - return iommu_fwspec_add_ids(dev, args->args, 1); -} - static void arm_smmu_get_resv_regions(struct device *dev, struct list_head *head) { + struct arm_smmu_master *master = dev_iommu_priv_get(dev); struct iommu_resv_region *region; int prot = IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO; @@ -2762,7 +2745,10 @@ static void arm_smmu_get_resv_regions(struct device *dev, list_add_tail(®ion->list, head); - iommu_dma_get_resv_regions(dev, head); + if (master->acpi_fwnode) + iort_iommu_get_resv_regions(dev, head, master->acpi_fwnode, + master->ids, master->num_ids); + of_iommu_get_resv_regions(dev, head); } static int arm_smmu_dev_enable_feature(struct device *dev, @@ -2851,10 +2837,10 @@ static void arm_smmu_remove_dev_pasid(struct device *dev, ioasid_t pasid) static struct iommu_ops arm_smmu_ops = { .capable = arm_smmu_capable, .domain_alloc = arm_smmu_domain_alloc, - .probe_device = arm_smmu_probe_device, + .probe_device_pinf = arm_smmu_probe_device, .release_device = arm_smmu_release_device, .device_group = arm_smmu_device_group, - .of_xlate = arm_smmu_of_xlate, + .of_xlate = iommu_dummy_of_xlate, .get_resv_regions = arm_smmu_get_resv_regions, .remove_dev_pasid = arm_smmu_remove_dev_pasid, .dev_enable_feat = arm_smmu_dev_enable_feature, diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index 961205ba86d25d..ac293265b21a13 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -692,6 +692,7 @@ struct arm_smmu_stream { struct arm_smmu_master { struct arm_smmu_device *smmu; struct device *dev; + struct fwnode_handle *acpi_fwnode; struct arm_smmu_domain *domain; struct list_head domain_head; struct arm_smmu_stream *streams; @@ -702,8 +703,11 @@ struct arm_smmu_master { bool stall_enabled; bool sva_enabled; bool iopf_enabled; + bool pci_rc_ats; struct list_head bonds; unsigned int ssid_bits; + unsigned int num_ids; + u32 ids[] __counted_by(num_ids); }; /* SMMU private data for an IOMMU domain */ diff --git a/include/linux/iommu-driver.h b/include/linux/iommu-driver.h index c4e133cdef2c78..8f7089d3bb7135 100644 --- a/include/linux/iommu-driver.h +++ b/include/linux/iommu-driver.h @@ -252,6 +252,6 @@ __iommu_iort_get_single_iommu(struct iommu_probe_info *pinf, pinf, ops, params), \ __iommu_of_get_single_iommu( \ pinf, ops, -1)), \ - drv_struct, member) \ + drv_struct, member); \ }) #endif From patchwork Thu Nov 30 01:10:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 748725 Authentication-Results: smtp.subspace.kernel.org; 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Received: from LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) by DM6PR12MB4484.namprd12.prod.outlook.com (2603:10b6:5:28f::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7046.23; Thu, 30 Nov 2023 01:11:26 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93%4]) with mapi id 15.20.7046.015; Thu, 30 Nov 2023 01:11:26 +0000 From: Jason Gunthorpe To: acpica-devel@lists.linux.dev, Andy Gross , Alim Akhtar , Alyssa Rosenzweig , Bjorn Andersson , AngeloGioacchino Del Regno , asahi@lists.linux.dev, Baolin Wang , devicetree@vger.kernel.org, Frank Rowand , Hanjun Guo , "Gustavo A. R. Silva" , Heiko Stuebner , iommu@lists.linux.dev, Jean-Philippe Brucker , Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Kees Cook , Konrad Dybcio , Krzysztof Kozlowski , Len Brown , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Lorenzo Pieralisi , Marek Szyprowski , Hector Martin , Matthias Brugger , Orson Zhai , "Rafael J. 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We don't need the concept of "global" drivers with a NULL fwspec, just invoke all the ops. Real systems only have one ops, so this effectively invokes the single op in the system to probe each device. If there are multiple ops we invoke each one once, and drivers that don't understand the struct device should return -ENODEV. Signed-off-by: Jason Gunthorpe --- drivers/iommu/iommu.c | 59 +++++++++++++++++++++++++++++++++++-------- 1 file changed, 48 insertions(+), 11 deletions(-) diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index 7468a64778931b..54e3f14429b3b4 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -241,6 +241,26 @@ static int remove_iommu_group(struct device *dev, void *data) return 0; } +static void iommu_device_add(struct iommu_device *iommu) +{ + struct iommu_device *cur; + + /* + * Keep the iommu_device_list grouped by ops so that + * iommu_find_init_device() works efficiently. + */ + mutex_lock(&iommu_probe_device_lock); + list_for_each_entry(cur, &iommu_device_list, list) { + if (cur->ops == iommu->ops) { + list_add(&iommu->list, &cur->list); + goto out; + } + } + list_add(&iommu->list, &iommu_device_list); +out: + mutex_unlock(&iommu_probe_device_lock); +} + /** * iommu_device_register() - Register an IOMMU hardware instance * @iommu: IOMMU handle for the instance @@ -262,9 +282,7 @@ int iommu_device_register(struct iommu_device *iommu, if (hwdev) iommu->fwnode = dev_fwnode(hwdev); - mutex_lock(&iommu_probe_device_lock); - list_add_tail(&iommu->list, &iommu_device_list); - mutex_unlock(&iommu_probe_device_lock); + iommu_device_add(iommu); for (int i = 0; i < ARRAY_SIZE(iommu_buses) && !err; i++) err = bus_iommu_probe(iommu_buses[i]); @@ -502,6 +520,29 @@ static void iommu_deinit_device(struct device *dev) DEFINE_MUTEX(iommu_probe_device_lock); +static int iommu_find_init_device(struct iommu_probe_info *pinf) +{ + const struct iommu_ops *ops = NULL; + struct iommu_device *iommu; + int ret; + + lockdep_assert_held(&iommu_probe_device_lock); + + /* + * Each unique ops gets a chance to claim the device, -ENODEV means the + * driver does not support the device. + */ + list_for_each_entry(iommu, &iommu_device_list, list) { + if (iommu->ops != ops) { + ops = iommu->ops; + ret = iommu_init_device(pinf, iommu->ops); + if (ret != -ENODEV) + return ret; + } + } + return -ENODEV; +} + static int __iommu_probe_device(struct iommu_probe_info *pinf) { struct device *dev = pinf->dev; @@ -524,13 +565,6 @@ static int __iommu_probe_device(struct iommu_probe_info *pinf) ops = fwspec->ops; if (!ops) return -ENODEV; - } else { - struct iommu_device *iommu; - - iommu = iommu_device_from_fwnode(NULL); - if (!iommu) - return -ENODEV; - ops = iommu->ops; } /* @@ -546,7 +580,10 @@ static int __iommu_probe_device(struct iommu_probe_info *pinf) if (dev->iommu_group) return 0; - ret = iommu_init_device(pinf, ops); + if (ops) + ret = iommu_init_device(pinf, ops); + else + ret = iommu_find_init_device(pinf); if (ret) return ret;