From patchwork Sat Dec 2 22:42:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 749820 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="eAqRW7rG" Received: from mail-lf1-x134.google.com (mail-lf1-x134.google.com [IPv6:2a00:1450:4864:20::134]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EAE2211F for ; Sat, 2 Dec 2023 14:42:50 -0800 (PST) Received: by mail-lf1-x134.google.com with SMTP id 2adb3069b0e04-50bc21821a1so4662476e87.0 for ; Sat, 02 Dec 2023 14:42:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1701556969; x=1702161769; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3aih6OHSDkGdiO3pHVc1FL+ZZ8/szuX4lHE6IeURhsw=; b=eAqRW7rGrb5kR6M+wGh5K7etg/MmLi6hjI+GE3JUGUnLpimons7m3nLGFtzzQgS+sW d8bqSNTYN+wL4Gdc7MQV6iIVbp9qLy8QNLzOrOSyekd80k7onhxN1/xN3JD1oTtz80qW pnC1OZjC8kQ9v0e0yuHC+BOv3J4K2LbjU9Z9ntPlW6hAGBLzylM+6Di+2JZFzyIr8QLo RlTmnCS6H7K+0Hf5cc7Qtnc6W1R7ILcaKjiW8xh+Ld2N0+ITXjruMDpKRve/zbG4YWhi nbautUUP37OAZtE9ld01GvvcmgMclBpFwD0LfQqoNFc5ZEP+dT8Gr4FLVHQoEXA6jvx9 WuNw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701556969; x=1702161769; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3aih6OHSDkGdiO3pHVc1FL+ZZ8/szuX4lHE6IeURhsw=; b=s7jKrVkQYQje612ueFiu8kVtUu+FhfLaQ08LpBQrKDMhGb+Laqza8qnOC9SqnELkpm ZdGaK93qrYdNTOJEKAc8o1SYWXQNMZfcsNd6SFrojBMdSTFntWI4M/ayI+MrAFMqYWRF j6Bzmmp4rQpalhT8KpSK7YAQiMhoUa7d8s81fQkQeuLLG5MP2GF6sNPOPIDrzUovzg4n tB2C0f/7MBXineJZ7WUhW30HFoe4l8il0z87bk+E7LzeulSHXMvlOni1XiJ+I5crmDLo gbpHBTr+jRYPEJuFEQmTCQ+2JDUN1fBraAn671jWI2IhITsolCnBsXbboeMVow3UFI75 ocmA== X-Gm-Message-State: AOJu0YwQNOBWpaH8R3pqlehmxEhyzKnwk2AZa98oilaPHhASU2y4pIk7 j/YAH/gLu8OQNDY5jH520LeD2A== X-Google-Smtp-Source: AGHT+IHZeVKOmByoJTMNtpTseW+90giyj7nm8L2MlkKFWc7pmChImdK+NbNbAAwO85Bzsqca44SybQ== X-Received: by 2002:a05:6512:104f:b0:50b:e1ea:f7c5 with SMTP id c15-20020a056512104f00b0050be1eaf7c5mr937950lfb.138.1701556969321; Sat, 02 Dec 2023 14:42:49 -0800 (PST) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id o20-20020a056512051400b0050bed700f5esm187015lfb.91.2023.12.02.14.42.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 02 Dec 2023 14:42:48 -0800 (PST) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar , Marijn Suijten Cc: Stephen Boyd , David Airlie , Daniel Vetter , Bjorn Andersson , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Konrad Dybcio Subject: [PATCH v4 1/4] drm/msm/mdss: switch mdss to use devm_of_icc_get() Date: Sun, 3 Dec 2023 01:42:44 +0300 Message-Id: <20231202224247.1282567-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231202224247.1282567-1-dmitry.baryshkov@linaro.org> References: <20231202224247.1282567-1-dmitry.baryshkov@linaro.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Stop using hand-written reset function for ICC release, use devm_of_icc_get() instead. Signed-off-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar --- drivers/gpu/drm/msm/msm_mdss.c | 16 ++-------------- 1 file changed, 2 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c index 29bb38f0bb2c..53bc496ace99 100644 --- a/drivers/gpu/drm/msm/msm_mdss.c +++ b/drivers/gpu/drm/msm/msm_mdss.c @@ -50,14 +50,14 @@ static int msm_mdss_parse_data_bus_icc_path(struct device *dev, struct icc_path *path0; struct icc_path *path1; - path0 = of_icc_get(dev, "mdp0-mem"); + path0 = devm_of_icc_get(dev, "mdp0-mem"); if (IS_ERR_OR_NULL(path0)) return PTR_ERR_OR_ZERO(path0); msm_mdss->path[0] = path0; msm_mdss->num_paths = 1; - path1 = of_icc_get(dev, "mdp1-mem"); + path1 = devm_of_icc_get(dev, "mdp1-mem"); if (!IS_ERR_OR_NULL(path1)) { msm_mdss->path[1] = path1; msm_mdss->num_paths++; @@ -66,15 +66,6 @@ static int msm_mdss_parse_data_bus_icc_path(struct device *dev, return 0; } -static void msm_mdss_put_icc_path(void *data) -{ - struct msm_mdss *msm_mdss = data; - int i; - - for (i = 0; i < msm_mdss->num_paths; i++) - icc_put(msm_mdss->path[i]); -} - static void msm_mdss_icc_request_bw(struct msm_mdss *msm_mdss, unsigned long bw) { int i; @@ -391,9 +382,6 @@ static struct msm_mdss *msm_mdss_init(struct platform_device *pdev, bool is_mdp5 dev_dbg(&pdev->dev, "mapped mdss address space @%pK\n", msm_mdss->mmio); ret = msm_mdss_parse_data_bus_icc_path(&pdev->dev, msm_mdss); - if (ret) - return ERR_PTR(ret); - ret = devm_add_action_or_reset(&pdev->dev, msm_mdss_put_icc_path, msm_mdss); if (ret) return ERR_PTR(ret); From patchwork Sat Dec 2 22:42:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 749503 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="OZSWwzPO" Received: from mail-lf1-x12a.google.com (mail-lf1-x12a.google.com [IPv6:2a00:1450:4864:20::12a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B5C66119 for ; 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The former ones share how their values are calculated, but the latter one has static predefines spanning all SoCs. In preparation for supporting the CPU<->SLAVE_DISPLAY_CFG path, rename the path-related struct members to include "mdp_". Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/msm_mdss.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c index 53bc496ace99..e1b208fd072e 100644 --- a/drivers/gpu/drm/msm/msm_mdss.c +++ b/drivers/gpu/drm/msm/msm_mdss.c @@ -40,8 +40,8 @@ struct msm_mdss { struct irq_domain *domain; } irq_controller; const struct msm_mdss_data *mdss_data; - struct icc_path *path[2]; - u32 num_paths; + struct icc_path *mdp_path[2]; + u32 num_mdp_paths; }; static int msm_mdss_parse_data_bus_icc_path(struct device *dev, @@ -54,13 +54,13 @@ static int msm_mdss_parse_data_bus_icc_path(struct device *dev, if (IS_ERR_OR_NULL(path0)) return PTR_ERR_OR_ZERO(path0); - msm_mdss->path[0] = path0; - msm_mdss->num_paths = 1; + msm_mdss->mdp_path[0] = path0; + msm_mdss->num_mdp_paths = 1; path1 = devm_of_icc_get(dev, "mdp1-mem"); if (!IS_ERR_OR_NULL(path1)) { - msm_mdss->path[1] = path1; - msm_mdss->num_paths++; + msm_mdss->mdp_path[1] = path1; + msm_mdss->num_mdp_paths++; } return 0; @@ -70,8 +70,8 @@ static void msm_mdss_icc_request_bw(struct msm_mdss *msm_mdss, unsigned long bw) { int i; - for (i = 0; i < msm_mdss->num_paths; i++) - icc_set_bw(msm_mdss->path[i], 0, Bps_to_icc(bw)); + for (i = 0; i < msm_mdss->num_mdp_paths; i++) + icc_set_bw(msm_mdss->mdp_path[i], 0, Bps_to_icc(bw)); } static void msm_mdss_irq(struct irq_desc *desc) From patchwork Sat Dec 2 22:42:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 749819 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="LUpABkRq" Received: from mail-lf1-x132.google.com (mail-lf1-x132.google.com [IPv6:2a00:1450:4864:20::132]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 87464124 for ; Sat, 2 Dec 2023 14:42:52 -0800 (PST) Received: by mail-lf1-x132.google.com with SMTP id 2adb3069b0e04-50bb8ff22e6so4575797e87.0 for ; Sat, 02 Dec 2023 14:42:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1701556971; x=1702161771; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7zovWCGMEaCBXEAS5mSNY7Kpzzx6U3mmVxujhNd8FwI=; b=LUpABkRq5D9HlmxDtNrLwXMcxK4Zrec3tj/BNmnRN6+dHv8avAAxMBVRnxDpeTV4oD Raj3cHDxEWv+QzbPDYghK1Ou0Vjc8XIigwS+4MumcHxFzuNZMdrT764JBCBSqYNNbQdX pHh/taeXs9AdTbCwZ570zMi4MhYYztZB0gYwh1ox8rSpGK5xajOLg/6crJl4fYx/xFDA WT8jBqeLeVOCZ493R6yOiDH3m9trTT366IiMLslaUXsrW1VDmi6sUksCbZZRGUcq7peJ PK13KHW+lz1sNElCvlFVJ4vYFEfTYaPRMmBHxYL4J9A3tlsByLOnIC1LwrZWtc6nVR+E VLJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701556971; x=1702161771; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7zovWCGMEaCBXEAS5mSNY7Kpzzx6U3mmVxujhNd8FwI=; b=fAT6GvHBkgM4crJf1FI2zsEDDztRpqtariwDZuKLpBEtmRUzUkYbEWxl4Rq/qjP2p2 UzAC1G5mWibFz4BgXCGy/bP57x+mMvWVuujQrnXoQ6pnil/5s8vL3fbaNabi56YMBb1C oOPqdCh73jFyphKD6peSs9XaRuVgE9x7taW/UbNL1KGsyC3nONbJxra/GzPB+rSIt7DQ LXel4K+vzGeNq3dmiaNmLQjOGWVzda+dsxl6MdAxLyXwkcPBWOJtJ5Cwf8+z6dYDB1Ov ME0+x3ju9Zwd0Rs9JN5TOb2gq8RsScfR0kBTBH2eC3Muosr40YFcuUUa8VldDSvDF4s7 xkUw== X-Gm-Message-State: AOJu0YxhYIcMdGGVmfa2vZlSYm3wGRwEOMwVIJqQ3SB+jm+1sMuSIvD7 weRfJjNdslIbBBt69ZhERH5P+Q== X-Google-Smtp-Source: AGHT+IGCx/hr9NPk4n8oWXdCugVcqzn1jGMHeBV9inPV/Mf00IxYZnUA8gjKRMpAvoYKPjvV+1LA0w== X-Received: by 2002:ac2:5989:0:b0:50b:ec8c:a293 with SMTP id w9-20020ac25989000000b0050bec8ca293mr471560lfn.15.1701556970837; Sat, 02 Dec 2023 14:42:50 -0800 (PST) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id o20-20020a056512051400b0050bed700f5esm187015lfb.91.2023.12.02.14.42.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 02 Dec 2023 14:42:50 -0800 (PST) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar , Marijn Suijten Cc: Stephen Boyd , David Airlie , Daniel Vetter , Bjorn Andersson , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Konrad Dybcio Subject: [PATCH v4 3/4] drm/msm/mdss: inline msm_mdss_icc_request_bw() Date: Sun, 3 Dec 2023 01:42:46 +0300 Message-Id: <20231202224247.1282567-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231202224247.1282567-1-dmitry.baryshkov@linaro.org> References: <20231202224247.1282567-1-dmitry.baryshkov@linaro.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 There are just two places where we set the bandwidth: in the resume and in the suspend paths. Drop the wrapping function msm_mdss_icc_request_bw() and call icc_set_bw() directly. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Reviewed-by: Abhinav Kumar --- drivers/gpu/drm/msm/msm_mdss.c | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c index e1b208fd072e..eeca281e9d6d 100644 --- a/drivers/gpu/drm/msm/msm_mdss.c +++ b/drivers/gpu/drm/msm/msm_mdss.c @@ -66,14 +66,6 @@ static int msm_mdss_parse_data_bus_icc_path(struct device *dev, return 0; } -static void msm_mdss_icc_request_bw(struct msm_mdss *msm_mdss, unsigned long bw) -{ - int i; - - for (i = 0; i < msm_mdss->num_mdp_paths; i++) - icc_set_bw(msm_mdss->mdp_path[i], 0, Bps_to_icc(bw)); -} - static void msm_mdss_irq(struct irq_desc *desc) { struct msm_mdss *msm_mdss = irq_desc_get_handler_data(desc); @@ -227,14 +219,15 @@ const struct msm_mdss_data *msm_mdss_get_mdss_data(struct device *dev) static int msm_mdss_enable(struct msm_mdss *msm_mdss) { - int ret; + int ret, i; /* * Several components have AXI clocks that can only be turned on if * the interconnect is enabled (non-zero bandwidth). Let's make sure * that the interconnects are at least at a minimum amount. */ - msm_mdss_icc_request_bw(msm_mdss, MIN_IB_BW); + for (i = 0; i < msm_mdss->num_mdp_paths; i++) + icc_set_bw(msm_mdss->mdp_path[i], 0, Bps_to_icc(MIN_IB_BW)); ret = clk_bulk_prepare_enable(msm_mdss->num_clocks, msm_mdss->clocks); if (ret) { @@ -286,8 +279,12 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss) static int msm_mdss_disable(struct msm_mdss *msm_mdss) { + int i; + clk_bulk_disable_unprepare(msm_mdss->num_clocks, msm_mdss->clocks); - msm_mdss_icc_request_bw(msm_mdss, 0); + + for (i = 0; i < msm_mdss->num_mdp_paths; i++) + icc_set_bw(msm_mdss->mdp_path[i], 0, 0); return 0; } From patchwork Sat Dec 2 22:42:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 749502 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="Gy0SqrDJ" Received: from mail-lf1-x12a.google.com (mail-lf1-x12a.google.com [IPv6:2a00:1450:4864:20::12a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 21A39125 for ; Sat, 2 Dec 2023 14:42:53 -0800 (PST) Received: by mail-lf1-x12a.google.com with SMTP id 2adb3069b0e04-50be4f03b06so994309e87.0 for ; Sat, 02 Dec 2023 14:42:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1701556971; x=1702161771; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=F60WGVzSyw8ZAyBBSZRfJ8j084J+A5mcN0DSUk2L02s=; b=Gy0SqrDJ6mIKG0+mFKbE5/HigZ0h9PZ4jyLAyu+HNetHWBG2/o24IC5yVmgOzB/xX3 yQ773r4r6y+EkFcNvpcok+pKb2ibQy6NTrN0x/Kv1VdFYzS7acc8e9t1SCSeghu+sId2 YlsTmRSgEyYe9NCJ7XtuvczRAPhIMgek5U6Lyh8jQlOe+/K5oz6BwWjs3qdJF+EdfLwV G5VnxAyx0NERrhxQeLNk1TmSmw+63XDrKfjd9S+iUV96sPK83y4U5Gx4Lfbnm9LKjJY+ OTw9mL7ShaAmtbmvq9NgWN5g89QuK2tHqeRaS0vD/u0MqMutXsDAsDN8XjmCElFNbc81 17mQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701556971; x=1702161771; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=F60WGVzSyw8ZAyBBSZRfJ8j084J+A5mcN0DSUk2L02s=; b=PkFcRU0LvxolIzo6rfjPG9V8cfpaPZZmzPFkFvi2bCw8ivDcKA/6Fq9uCHQMIKfSEl WvvQB5rE3/ldfPlj1eWPT/n5ZTSMsgAluYwOnYLyw8MVqHxDfcWCetHcAGMjlb4+bbdQ TcA4GRIj2LwjOHdBeNS9VRK9ZDFKg4U0ZHkDzKgWTfiFpHfu3bqUem8frvJ/FWyvV4/H bT5JbeAwoqo4owmM7h0rCfS5XJmjjUgzDNZz/hK0a9WespOiTeASS75QMgoMQJvbc5+q bfRLZRDYiQ3MAhXj0rxQZEP62NCOQQO3xJWZgDPlNu/g60BFHFzu6nrcO8ZL1MsUh5sF lBfA== X-Gm-Message-State: AOJu0Yy3fzPAh/Yd0dkQWu/XxKsjyylAjTdad3Nr4bvuEcQGAPf2mEwI 3hsQ7WDvJYuqtO0GbzfZkZnmAw== X-Google-Smtp-Source: AGHT+IH3k5kN0DMHoRKb0i348vqgiuzpUSRHtY5AZJwhNYCx+JKo+PTwlB3/BShhwQbvIzoD66pnWA== X-Received: by 2002:ac2:47f2:0:b0:50b:d764:2904 with SMTP id b18-20020ac247f2000000b0050bd7642904mr1214606lfp.156.1701556971486; Sat, 02 Dec 2023 14:42:51 -0800 (PST) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id o20-20020a056512051400b0050bed700f5esm187015lfb.91.2023.12.02.14.42.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 02 Dec 2023 14:42:51 -0800 (PST) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar , Marijn Suijten Cc: Stephen Boyd , David Airlie , Daniel Vetter , Bjorn Andersson , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Konrad Dybcio Subject: [PATCH v4 4/4] drm/msm/mdss: Handle the reg bus ICC path Date: Sun, 3 Dec 2023 01:42:47 +0300 Message-Id: <20231202224247.1282567-5-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231202224247.1282567-1-dmitry.baryshkov@linaro.org> References: <20231202224247.1282567-1-dmitry.baryshkov@linaro.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Apart from the already handled data bus (MAS_MDP_Pn<->DDR), there's another path that needs to be handled to ensure MDSS functions properly, namely the "reg bus", a.k.a the CPU-MDSS interconnect. Gating that path may have a variety of effects, from none to otherwise inexplicable DSI timeouts. Provide a way for MDSS driver to vote on this bus. A note regarding vote values. Newer platforms have corresponding bandwidth values in the vendor DT files. For the older platforms there was a static vote in the mdss_mdp and rotator drivers. I choose to be conservative here and choose this value as a default. Co-developed-by: Konrad Dybcio Signed-off-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/msm_mdss.c | 49 +++++++++++++++++++++++++++++++--- drivers/gpu/drm/msm/msm_mdss.h | 1 + 2 files changed, 46 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c index eeca281e9d6d..18b07619d6fc 100644 --- a/drivers/gpu/drm/msm/msm_mdss.c +++ b/drivers/gpu/drm/msm/msm_mdss.c @@ -28,6 +28,8 @@ #define MIN_IB_BW 400000000UL /* Min ib vote 400MB */ +#define DEFAULT_REG_BW 153600 /* Used in mdss fbdev driver */ + struct msm_mdss { struct device *dev; @@ -42,6 +44,7 @@ struct msm_mdss { const struct msm_mdss_data *mdss_data; struct icc_path *mdp_path[2]; u32 num_mdp_paths; + struct icc_path *reg_bus_path; }; static int msm_mdss_parse_data_bus_icc_path(struct device *dev, @@ -49,6 +52,7 @@ static int msm_mdss_parse_data_bus_icc_path(struct device *dev, { struct icc_path *path0; struct icc_path *path1; + struct icc_path *reg_bus_path; path0 = devm_of_icc_get(dev, "mdp0-mem"); if (IS_ERR_OR_NULL(path0)) @@ -63,6 +67,10 @@ static int msm_mdss_parse_data_bus_icc_path(struct device *dev, msm_mdss->num_mdp_paths++; } + reg_bus_path = of_icc_get(dev, "cpu-cfg"); + if (!IS_ERR_OR_NULL(reg_bus_path)) + msm_mdss->reg_bus_path = reg_bus_path; + return 0; } @@ -229,6 +237,13 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss) for (i = 0; i < msm_mdss->num_mdp_paths; i++) icc_set_bw(msm_mdss->mdp_path[i], 0, Bps_to_icc(MIN_IB_BW)); + if (msm_mdss->mdss_data && msm_mdss->mdss_data->reg_bus_bw) + icc_set_bw(msm_mdss->reg_bus_path, 0, + msm_mdss->mdss_data->reg_bus_bw); + else + icc_set_bw(msm_mdss->reg_bus_path, 0, + DEFAULT_REG_BW); + ret = clk_bulk_prepare_enable(msm_mdss->num_clocks, msm_mdss->clocks); if (ret) { dev_err(msm_mdss->dev, "clock enable failed, ret:%d\n", ret); @@ -286,6 +301,9 @@ static int msm_mdss_disable(struct msm_mdss *msm_mdss) for (i = 0; i < msm_mdss->num_mdp_paths; i++) icc_set_bw(msm_mdss->mdp_path[i], 0, 0); + if (msm_mdss->reg_bus_path) + icc_set_bw(msm_mdss->reg_bus_path, 0, 0); + return 0; } @@ -372,6 +390,8 @@ static struct msm_mdss *msm_mdss_init(struct platform_device *pdev, bool is_mdp5 if (!msm_mdss) return ERR_PTR(-ENOMEM); + msm_mdss->mdss_data = of_device_get_match_data(&pdev->dev); + msm_mdss->mmio = devm_platform_ioremap_resource_byname(pdev, is_mdp5 ? "mdss_phys" : "mdss"); if (IS_ERR(msm_mdss->mmio)) return ERR_CAST(msm_mdss->mmio); @@ -462,8 +482,6 @@ static int mdss_probe(struct platform_device *pdev) if (IS_ERR(mdss)) return PTR_ERR(mdss); - mdss->mdss_data = of_device_get_match_data(&pdev->dev); - platform_set_drvdata(pdev, mdss); /* @@ -495,11 +513,13 @@ static const struct msm_mdss_data msm8998_data = { .ubwc_enc_version = UBWC_1_0, .ubwc_dec_version = UBWC_1_0, .highest_bank_bit = 2, + .reg_bus_bw = 76800, }; static const struct msm_mdss_data qcm2290_data = { /* no UBWC */ .highest_bank_bit = 0x2, + .reg_bus_bw = 76800, }; static const struct msm_mdss_data sc7180_data = { @@ -507,6 +527,7 @@ static const struct msm_mdss_data sc7180_data = { .ubwc_dec_version = UBWC_2_0, .ubwc_static = 0x1e, .highest_bank_bit = 0x3, + .reg_bus_bw = 76800, }; static const struct msm_mdss_data sc7280_data = { @@ -516,6 +537,7 @@ static const struct msm_mdss_data sc7280_data = { .ubwc_static = 1, .highest_bank_bit = 1, .macrotile_mode = 1, + .reg_bus_bw = 74000, }; static const struct msm_mdss_data sc8180x_data = { @@ -523,6 +545,7 @@ static const struct msm_mdss_data sc8180x_data = { .ubwc_dec_version = UBWC_3_0, .highest_bank_bit = 3, .macrotile_mode = 1, + .reg_bus_bw = 76800, }; static const struct msm_mdss_data sc8280xp_data = { @@ -532,12 +555,14 @@ static const struct msm_mdss_data sc8280xp_data = { .ubwc_static = 1, .highest_bank_bit = 3, .macrotile_mode = 1, + .reg_bus_bw = 76800, }; static const struct msm_mdss_data sdm845_data = { .ubwc_enc_version = UBWC_2_0, .ubwc_dec_version = UBWC_2_0, .highest_bank_bit = 2, + .reg_bus_bw = 76800, }; static const struct msm_mdss_data sm6350_data = { @@ -546,12 +571,14 @@ static const struct msm_mdss_data sm6350_data = { .ubwc_swizzle = 6, .ubwc_static = 0x1e, .highest_bank_bit = 1, + .reg_bus_bw = 76800, }; static const struct msm_mdss_data sm8150_data = { .ubwc_enc_version = UBWC_3_0, .ubwc_dec_version = UBWC_3_0, .highest_bank_bit = 2, + .reg_bus_bw = 76800, }; static const struct msm_mdss_data sm6115_data = { @@ -560,6 +587,7 @@ static const struct msm_mdss_data sm6115_data = { .ubwc_swizzle = 7, .ubwc_static = 0x11f, .highest_bank_bit = 0x1, + .reg_bus_bw = 76800, }; static const struct msm_mdss_data sm6125_data = { @@ -577,6 +605,18 @@ static const struct msm_mdss_data sm8250_data = { /* TODO: highest_bank_bit = 2 for LP_DDR4 */ .highest_bank_bit = 3, .macrotile_mode = 1, + .reg_bus_bw = 76800, +}; + +static const struct msm_mdss_data sm8350_data = { + .ubwc_enc_version = UBWC_4_0, + .ubwc_dec_version = UBWC_4_0, + .ubwc_swizzle = 6, + .ubwc_static = 1, + /* TODO: highest_bank_bit = 2 for LP_DDR4 */ + .highest_bank_bit = 3, + .macrotile_mode = 1, + .reg_bus_bw = 74000, }; static const struct msm_mdss_data sm8550_data = { @@ -587,6 +627,7 @@ static const struct msm_mdss_data sm8550_data = { /* TODO: highest_bank_bit = 2 for LP_DDR4 */ .highest_bank_bit = 3, .macrotile_mode = 1, + .reg_bus_bw = 57000, }; static const struct of_device_id mdss_dt_match[] = { { .compatible = "qcom,mdss" }, @@ -603,8 +644,8 @@ static const struct of_device_id mdss_dt_match[] = { { .compatible = "qcom,sm6375-mdss", .data = &sm6350_data }, { .compatible = "qcom,sm8150-mdss", .data = &sm8150_data }, { .compatible = "qcom,sm8250-mdss", .data = &sm8250_data }, - { .compatible = "qcom,sm8350-mdss", .data = &sm8250_data }, - { .compatible = "qcom,sm8450-mdss", .data = &sm8250_data }, + { .compatible = "qcom,sm8350-mdss", .data = &sm8350_data }, + { .compatible = "qcom,sm8450-mdss", .data = &sm8350_data }, { .compatible = "qcom,sm8550-mdss", .data = &sm8550_data }, {} }; diff --git a/drivers/gpu/drm/msm/msm_mdss.h b/drivers/gpu/drm/msm/msm_mdss.h index 02bbab42adbc..3afef4b1786d 100644 --- a/drivers/gpu/drm/msm/msm_mdss.h +++ b/drivers/gpu/drm/msm/msm_mdss.h @@ -14,6 +14,7 @@ struct msm_mdss_data { u32 ubwc_static; u32 highest_bank_bit; u32 macrotile_mode; + u32 reg_bus_bw; }; #define UBWC_1_0 0x10000000