From patchwork Sun Dec 3 15:40:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chukun Pan X-Patchwork-Id: 749803 Received: from mail-m17224.xmail.ntesmail.com (mail-m17224.xmail.ntesmail.com [45.195.17.224]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 79C0EFC; Sun, 3 Dec 2023 07:40:23 -0800 (PST) Received: from Vostro-3710.lan (unknown [119.122.215.53]) by mail-m121145.qiye.163.com (Hmail) with ESMTPA id DF26B80003D; Sun, 3 Dec 2023 23:40:06 +0800 (CST) From: Chukun Pan To: Bjorn Andersson Cc: Andy Gross , Konrad Dybcio , Krzysztof Kozlowski , Conor Dooley , Rob Herring , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Chukun Pan Subject: [PATCH v2 1/1] arm64: dts: qcom: ipq6018: Add QUP5 SPI node Date: Sun, 3 Dec 2023 23:40:03 +0800 Message-Id: <20231203154003.532765-1-amadeus@jmu.edu.cn> X-Mailer: git-send-email 2.25.1 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFITzdXWS1ZQUlXWQ8JGhUIEh9ZQVkZS0kZVkkfSUodHkJMGk9ISFUTARMWGhIXJBQOD1 lXWRgSC1lBWUpKQlVKSUlVSUpOVU5IWVdZFhoPEhUdFFlBWU9LSFVKSktISkNVSktLVUtZBg++ X-HM-Tid: 0a8c30563ca5b03akuuudf26b80003d X-HM-MType: 10 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6Mio6Mxw4Ezw0KAkqVjw4NwtK CVEKCQFVSlVKTEtKTUpDS0tMQ0hLVTMWGhIXVRoWGh8eDgg7ERYOVR4fDlUYFUVZV1kSC1lBWUpK QlVKSUlVSUpOVU5IWVdZCAFZQUlPSEI3Bg++ Add node to support the QUP5 SPI controller inside of IPQ6018. Some routers use this bus to connect SPI TPM chips. Signed-off-by: Chukun Pan --- Changes in v2: * No changes, resend due to error link to other threads. arch/arm64/boot/dts/qcom/ipq6018.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index ec0a0ce1849e..2399d16f147e 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -527,6 +527,20 @@ blsp1_spi2: spi@78b6000 { status = "disabled"; }; + blsp1_spi5: spi@78b9000 { + compatible = "qcom,spi-qup-v2.2.1"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x078b9000 0x0 0x600>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 20>, <&blsp_dma 21>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + blsp1_i2c2: i2c@78b6000 { compatible = "qcom,i2c-qup-v2.2.1"; #address-cells = <1>;