From patchwork Mon Dec 4 12:55:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 750132 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="b4yzsUly" Received: from mail-ej1-x636.google.com (mail-ej1-x636.google.com [IPv6:2a00:1450:4864:20::636]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C586DD2 for ; Mon, 4 Dec 2023 04:55:41 -0800 (PST) Received: by mail-ej1-x636.google.com with SMTP id a640c23a62f3a-a184d717de1so599746766b.1 for ; Mon, 04 Dec 2023 04:55:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1701694540; x=1702299340; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=m/scYT3hZ9U86e3nTrsd4m2SOrNBxrMSkO8yKXa3OKg=; b=b4yzsUlyaHQC63JUigF7CxDKS4Y/SWxJRTk/rdNHc81O6TzVdmeFky8Zt/g3QNiWg1 zp2Ob4mxHXwZ+YRsjOM89Qr25UkSv9yBzNTQKO2d/vZMFePydHdevwSui9Jovh6S95Sk YQJwAs/SB1S8nmxDucGeDcg8WZOPKMm2y9HsGJYwRAn6wyrG/uLHQErFWI/lU2Qa2G6f fPkpt9ApV7NiMo0upVyZbFly6L3gLamauDmR4DZQHfLtjpCWxMOE8H0kX1Cni/xBbbm/ y2XdYpgLB2eTCpTNAfCubsSJmBrqaBNgXyRBL/QwKv46jIw3kDvRGyEhbKDeASAEZVqj YqGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701694540; x=1702299340; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=m/scYT3hZ9U86e3nTrsd4m2SOrNBxrMSkO8yKXa3OKg=; b=gBMYD05wXrhbVxDrDKSKQtg+Z1n6kP26zEtOpO3jPjHWWSy4era+EGbIy6bbLPBhUn d59kYvPWtQsh+YcgWqAxuWJyJog/05wv8xIsUlWuhETI72SPzlCf6wVD/d+26lP40xwa x+Sj+TKhjrknv5ELqBTH9FAu9Wy8epwOchRbaoxHJPmazbhFCehEIlsbTWbzfz0kF1kq rdhpFH8Ekd7gILqh3dkN732C67mOpGqWFGkstI8nycOxJtQgXKSa7le5QTirMyLigye+ a7HCtPnX1vnSxh+15zldZu311CgWyUtx2pp0Tw9SNhKW5MYVS0yGsaZPQ/a6wyOH1Dfc 9HWw== X-Gm-Message-State: AOJu0Yzd6cJgq7M8s3TPuxpPf48MSM6QbpvKyw5QRM0ra4Tt8Ylo9d6i 9zdNcfl+xsaRimmvba7IkmdKsQ== X-Google-Smtp-Source: AGHT+IFsxmTIj0K6MaN0knP1bd/tcVoDHhmxpM2jrCRTcy2nJxt4ToGJYNyTgV+I0VbQ+CUdJ6L4vA== X-Received: by 2002:a17:906:34d8:b0:a18:9bf7:beb2 with SMTP id h24-20020a17090634d800b00a189bf7beb2mr2339025ejb.39.1701694540253; Mon, 04 Dec 2023 04:55:40 -0800 (PST) Received: from [10.167.154.1] (178235179097.dynamic-4-waw-k-1-3-0.vectranet.pl. [178.235.179.97]) by smtp.gmail.com with ESMTPSA id ay22-20020a170906d29600b009efe6fdf615sm5241373ejb.150.2023.12.04.04.55.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Dec 2023 04:55:39 -0800 (PST) From: Konrad Dybcio Date: Mon, 04 Dec 2023 13:55:21 +0100 Subject: [PATCH v2 2/6] arm64: dts: qcom: sm8450: Add GPU nodes Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20231127-topic-a7xx_dt-v2-2-2a437588e563@linaro.org> References: <20231127-topic-a7xx_dt-v2-0-2a437588e563@linaro.org> In-Reply-To: <20231127-topic-a7xx_dt-v2-0-2a437588e563@linaro.org> To: Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson Cc: Marijn Suijten , Neil Armstrong , Dmitry Baryshkov , linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1701694533; l=7180; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=CUEgyrTkc+PFJXmRHVyPymkBE71IGdpDnV6mBH5mDlk=; b=n/rpi+cAz5c+c7My2pM/6gxPtCAGoHdn8etrFChtq1Bj5x6pQ+VpirxUWAfL7AKSqCrbCDW1B MDeIcK0Nc4cDs8VvMw9em4hxU1F8Aw3mOmGPTLhFz1rkYdDfl1KMdxa X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Add the required nodes to support the A730 GPU. Reviewed-by: Neil Armstrong Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 202 +++++++++++++++++++++++++++++++++++ 1 file changed, 202 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index bde9c1093384..e9664672c160 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -18,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -2019,6 +2021,206 @@ tcsr: syscon@1fc0000 { reg = <0x0 0x1fc0000 0x0 0x30000>; }; + gpu: gpu@3d00000 { + compatible = "qcom,adreno-730.1", "qcom,adreno"; + reg = <0x0 0x03d00000 0x0 0x40000>, + <0x0 0x03d9e000 0x0 0x1000>, + <0x0 0x03d61000 0x0 0x800>; + reg-names = "kgsl_3d0_reg_memory", + "cx_mem", + "cx_dbgc"; + + interrupts = ; + + iommus = <&adreno_smmu 0 0x400>, + <&adreno_smmu 1 0x400>; + + operating-points-v2 = <&gpu_opp_table>; + + qcom,gmu = <&gmu>; + + status = "disabled"; + + zap-shader { + memory-region = <&gpu_micro_code_mem>; + }; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-818000000 { + opp-hz = /bits/ 64 <818000000>; + opp-level = ; + }; + + opp-791000000 { + opp-hz = /bits/ 64 <791000000>; + opp-level = ; + }; + + opp-734000000 { + opp-hz = /bits/ 64 <734000000>; + opp-level = ; + }; + + opp-640000000 { + opp-hz = /bits/ 64 <640000000>; + opp-level = ; + }; + + opp-599000000 { + opp-hz = /bits/ 64 <599000000>; + opp-level = ; + }; + + opp-545000000 { + opp-hz = /bits/ 64 <545000000>; + opp-level = ; + }; + + opp-492000000 { + opp-hz = /bits/ 64 <492000000>; + opp-level = ; + }; + + opp-421000000 { + opp-hz = /bits/ 64 <421000000>; + opp-level = ; + }; + + opp-350000000 { + opp-hz = /bits/ 64 <350000000>; + opp-level = ; + }; + + opp-317000000 { + opp-hz = /bits/ 64 <317000000>; + opp-level = ; + }; + + opp-285000000 { + opp-hz = /bits/ 64 <285000000>; + opp-level = ; + }; + + opp-220000000 { + opp-hz = /bits/ 64 <220000000>; + opp-level = ; + }; + }; + }; + + gmu: gmu@3d6a000 { + compatible = "qcom,adreno-gmu-730.1", "qcom,adreno-gmu"; + reg = <0x0 0x03d6a000 0x0 0x35000>, + <0x0 0x03d50000 0x0 0x10000>, + <0x0 0x0b290000 0x0 0x10000>; + reg-names = "gmu", "rscc", "gmu_pdc"; + + interrupts = , + ; + interrupt-names = "hfi", "gmu"; + + clocks = <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_DEMET_CLK>; + clock-names = "ahb", + "gmu", + "cxo", + "axi", + "memnoc", + "hub", + "demet"; + + power-domains = <&gpucc GPU_CX_GDSC>, + <&gpucc GPU_GX_GDSC>; + power-domain-names = "cx", + "gx"; + + iommus = <&adreno_smmu 5 0x400>; + + qcom,qmp = <&aoss_qmp>; + + operating-points-v2 = <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-level = ; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-level = ; + }; + }; + }; + + gpucc: clock-controller@3d90000 { + compatible = "qcom,sm8450-gpucc"; + reg = <0x0 0x03d90000 0x0 0xa000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + adreno_smmu: iommu@3da0000 { + compatible = "qcom,sm8450-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x03da0000 0x0 0x40000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>; + clock-names = "gmu", + "hub", + "hlos", + "bus", + "iface", + "ahb"; + power-domains = <&gpucc GPU_CX_GDSC>; + dma-coherent; + }; + usb_1_hsphy: phy@88e3000 { compatible = "qcom,sm8450-usb-hs-phy", "qcom,usb-snps-hs-7nm-phy"; From patchwork Mon Dec 4 12:55:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 750131 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="m9q9dSUn" Received: from mail-lf1-x130.google.com (mail-lf1-x130.google.com [IPv6:2a00:1450:4864:20::130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 994F4106 for ; Mon, 4 Dec 2023 04:55:44 -0800 (PST) Received: by mail-lf1-x130.google.com with SMTP id 2adb3069b0e04-50bfd8d5c77so500867e87.1 for ; Mon, 04 Dec 2023 04:55:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1701694543; x=1702299343; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=HmgwqYrBNnDHL/Mz+RV2OWlSk4GK1FPHNtwtHnFOAsI=; b=m9q9dSUnd11YyPCKhB8nwUZYfNK2N10IypvYPeSE6/AjEFI9Pa9EjMUC5ECo+C7xDe rEniRuT6r7zVSHE8befDAe5Hq3JtnfH7JC9WKjRz/EJMd84N6eWMFNpDMy1ipVK0kU9C 6j4CnK9DvhSdeexh3h+7sUdg4cRizvQ9aMOX4DC+kY7NcEgwoowtZpGxlT5/Pv1fKUSb Ekz94AGREr/OhdnyYaH3GlOkPJJs6yQFtSb8cmfhxTeEOCHyAWrs3qGklHZjE+iorY7W G//PC2IUJEhV1hHv/nm5H7hgYqVzOk1kxltTBEhlS9H1y4b47QmEB10dhYjuq0oxKqqQ FGUw== X-Google-DKIM-Signature: v=1; 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[178.235.179.97]) by smtp.gmail.com with ESMTPSA id ay22-20020a170906d29600b009efe6fdf615sm5241373ejb.150.2023.12.04.04.55.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Dec 2023 04:55:42 -0800 (PST) From: Konrad Dybcio Date: Mon, 04 Dec 2023 13:55:22 +0100 Subject: [PATCH v2 3/6] arm64: dts: qcom: sm8550: Add GPU nodes Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20231127-topic-a7xx_dt-v2-3-2a437588e563@linaro.org> References: <20231127-topic-a7xx_dt-v2-0-2a437588e563@linaro.org> In-Reply-To: <20231127-topic-a7xx_dt-v2-0-2a437588e563@linaro.org> To: Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson Cc: Marijn Suijten , Neil Armstrong , Dmitry Baryshkov , linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1701694533; l=5785; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=Yb/XfhNkL2cLIAdC0dUOyswve2maY47HKpIqukNc+Dw=; b=+ZJ6RcBAQK3p+vlX7qkHyaNJMOXR8PuT98SWByMX2AACmjrt6djSkhi7s17leLWxtGuCl8B08 GnLAZ6WRhcSDP2pQODQG518pS5mvV/1fivdrLm8ASD2BwZhW66PFKro X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Add the required nodes to support the A740 GPU. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 166 +++++++++++++++++++++++++++++++++++ 1 file changed, 166 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 7bafb3d88d69..8f59085c804d 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -1984,6 +1984,128 @@ tcsr: clock-controller@1fc0000 { #reset-cells = <1>; }; + gpu: gpu@3d00000 { + compatible = "qcom,adreno-43050a01", "qcom,adreno"; + reg = <0x0 0x03d00000 0x0 0x40000>, + <0x0 0x03d9e000 0x0 0x1000>, + <0x0 0x03d61000 0x0 0x800>; + reg-names = "kgsl_3d0_reg_memory", + "cx_mem", + "cx_dbgc"; + + interrupts = ; + + iommus = <&adreno_smmu 0 0x0>, + <&adreno_smmu 1 0x0>; + + operating-points-v2 = <&gpu_opp_table>; + + qcom,gmu = <&gmu>; + + status = "disabled"; + + zap-shader { + memory-region = <&gpu_micro_code_mem>; + }; + + /* Speedbin needs more work on A740+, keep only lower freqs */ + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-680000000 { + opp-hz = /bits/ 64 <680000000>; + opp-level = ; + }; + + opp-615000000 { + opp-hz = /bits/ 64 <615000000>; + opp-level = ; + }; + + opp-550000000 { + opp-hz = /bits/ 64 <550000000>; + opp-level = ; + }; + + opp-475000000 { + opp-hz = /bits/ 64 <475000000>; + opp-level = ; + }; + + opp-401000000 { + opp-hz = /bits/ 64 <401000000>; + opp-level = ; + }; + + opp-348000000 { + opp-hz = /bits/ 64 <348000000>; + opp-level = ; + }; + + opp-295000000 { + opp-hz = /bits/ 64 <295000000>; + opp-level = ; + }; + + opp-220000000 { + opp-hz = /bits/ 64 <220000000>; + opp-level = ; + }; + }; + }; + + gmu: gmu@3d6a000 { + compatible = "qcom,adreno-gmu-740.1", "qcom,adreno-gmu"; + reg = <0x0 0x03d6a000 0x0 0x35000>, + <0x0 0x03d50000 0x0 0x10000>, + <0x0 0x0b280000 0x0 0x10000>; + reg-names = "gmu", "rscc", "gmu_pdc"; + + interrupts = , + ; + interrupt-names = "hfi", "gmu"; + + clocks = <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_DEMET_CLK>; + clock-names = "ahb", + "gmu", + "cxo", + "axi", + "memnoc", + "hub", + "demet"; + + power-domains = <&gpucc GPU_CC_CX_GDSC>, + <&gpucc GPU_CC_GX_GDSC>; + power-domain-names = "cx", + "gx"; + + iommus = <&adreno_smmu 5 0x0>; + + qcom,qmp = <&aoss_qmp>; + + operating-points-v2 = <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-level = ; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-level = ; + }; + }; + }; + gpucc: clock-controller@3d90000 { compatible = "qcom,sm8550-gpucc"; reg = <0 0x03d90000 0 0xa000>; @@ -1995,6 +2117,50 @@ gpucc: clock-controller@3d90000 { #power-domain-cells = <1>; }; + adreno_smmu: iommu@3da0000 { + compatible = "qcom,sm8550-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x03da0000 0x0 0x40000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>; + clock-names = "hlos", + "bus", + "iface", + "ahb"; + power-domains = <&gpucc GPU_CC_CX_GDSC>; + dma-coherent; + }; + remoteproc_mpss: remoteproc@4080000 { compatible = "qcom,sm8550-mpss-pas"; reg = <0x0 0x04080000 0x0 0x4040>; From patchwork Mon Dec 4 12:55:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 750130 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="I88nEEOK" Received: from mail-ed1-x535.google.com (mail-ed1-x535.google.com [IPv6:2a00:1450:4864:20::535]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 105E7AA for ; Mon, 4 Dec 2023 04:55:48 -0800 (PST) Received: by mail-ed1-x535.google.com with SMTP id 4fb4d7f45d1cf-54cfd70b2dcso34400a12.3 for ; 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[178.235.179.97]) by smtp.gmail.com with ESMTPSA id ay22-20020a170906d29600b009efe6fdf615sm5241373ejb.150.2023.12.04.04.55.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Dec 2023 04:55:46 -0800 (PST) From: Konrad Dybcio Date: Mon, 04 Dec 2023 13:55:24 +0100 Subject: [PATCH v2 5/6] arm64: dts: qcom: sm8550-mtp: Enable the A740 GPU Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20231127-topic-a7xx_dt-v2-5-2a437588e563@linaro.org> References: <20231127-topic-a7xx_dt-v2-0-2a437588e563@linaro.org> In-Reply-To: <20231127-topic-a7xx_dt-v2-0-2a437588e563@linaro.org> To: Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson Cc: Marijn Suijten , Neil Armstrong , Dmitry Baryshkov , linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1701694533; l=725; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=9FJMq5XZXBPBjP7KOy0b1q2lfGMXMmYwfkQChVXyG58=; b=dZQFJAa43yRKRFVuhYC59lVTywRwiU+Z0ruBiOuzMDG984BZCFwibm30OYopXSQz1iEUiR2Kv fnvSNpONBQeAECiGUNL/pvHsWJ8Izr1Y1LW3p+shWU/3y27ivta91tX X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Enable the GPU and provide a path for the ZAP blob. Reviewed-by: Neil Armstrong Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts index 9a70875028b7..52244e9bfdee 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts @@ -512,6 +512,14 @@ vreg_l3g_1p2: ldo3 { }; }; +&gpu { + status = "okay"; + + zap-shader { + firmware-name = "qcom/sm8550/a740_zap.mbn"; + }; +}; + &i2c_master_hub_0 { status = "okay"; };