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Y. Srinivasan" , Laxman Dewangan , Len Brown , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-hyperv@vger.kernel.org, linux-mips@vger.kernel.org, linux-riscv@lists.infradead.org, linux-snps-arc@lists.infradead.org, linux-tegra@vger.kernel.org, Russell King , Lyude Paul , Marek Szyprowski , nouveau@lists.freedesktop.org, Palmer Dabbelt , Paul Walmsley , "Rafael J. Wysocki" , Rob Herring , Robin Murphy , Suravee Suthikulpanit , Sven Peter , Thomas Bogendoerfer , Vineet Gupta , Vinod Koul , Wei Liu , Will Deacon Cc: Lu Baolu , Christoph Hellwig , Jerry Snitselaar , Hector Martin , Moritz Fischer , Moritz Fischer , patches@lists.linux.dev, "Rafael J. Wysocki" , Rob Herring , Thierry Reding , Thierry Reding Subject: [PATCH v2 1/7] iommu: Remove struct iommu_ops *iommu from arch_setup_dma_ops() Date: Thu, 7 Dec 2023 14:03:08 -0400 Message-ID: <1-v2-16e4def25ebb+820-iommu_fwspec_p1_jgg@nvidia.com> In-Reply-To: <0-v2-16e4def25ebb+820-iommu_fwspec_p1_jgg@nvidia.com> References: X-ClientProxiedBy: MN2PR16CA0043.namprd16.prod.outlook.com (2603:10b6:208:234::12) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|CH3PR12MB7667:EE_ X-MS-Office365-Filtering-Correlation-Id: 7532026a-c5a4-4feb-7ebc-08dbf74ec946 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: OL4oxLu2HmdIFWI3PgTpbOCCuJGfoKH5jF4H2wvkdlB5IvcgCN0eCe/uaY5wt9ZHFxXNk3zvcfiTQj7l2oOhcK2TP2EeMN+/pLNxRLoASj0SvHGELOBq/Nr9tskzoGuKuCyQvm+kNdRUChnSlbVcGNEPjM5WLqeuuywoF1NSqLwx6i4s/DvojSM6R7OQ3hQns5AlvzuIMtcFSEf0C0OkDR/3R1lxnNM0EN8D3f6kvUXKzEPxt1woKqDRt2dEVOyvYk5NMUbBc2wn9w0xxpvD4AeLVShnxSJ4iw3C2ySkrTWtXwNyAsku7dNvprdRn4WLOR4krROV+NzwPssWYuGfk45CHlSye7bf+rV4039ey7ZvQJo95HmwsXakMYAWgwOOmTjqy47GFDW1BUwc/gdhvc5+qEKACAqcY55e2atDGf3pEryJABO70hPzOIXS+DTO11gENLq3Yyxedeihpvzw0ecvmUBctc+9rGm4S92iLRsTyK9/8LwYANY/M46UWJ1nJcHWkuvHK36+4tfW/8ghJ230hBMAIkewn4QPTQScp4YGIotyc/kXDMHly9blydP3sANPKFB6Krh1IryBrKpS4bjfClumpjogBWmzn9KbvUZ5h5gzHNa9APL/FDCrw2XB X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:LV2PR12MB5869.namprd12.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230031)(39860400002)(366004)(376002)(346002)(136003)(396003)(230922051799003)(186009)(1800799012)(451199024)(64100799003)(7366002)(7416002)(2906002)(7406005)(5660300002)(41300700001)(86362001)(8676002)(4326008)(8936002)(36756003)(316002)(66946007)(66556008)(66476007)(54906003)(110136005)(921008)(38100700002)(6486002)(478600001)(66899024)(107886003)(83380400001)(6666004)(6506007)(26005)(6512007)(2616005)(4216001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: TXDSH4i/OYjpMMf8kW5NZVtGJ4U5KbOsa5yPoehYWv4pCLUB21hiBBvVsfi8AUs2t79/f6WxWrctdDDfVDD+eLJMEO2/L4ciy79njgEUaAZ8aJAnI1qnX7wo6dGQ1nRWwVbbYaH574eCQQqubesdToLqlDB1dMvGWS9pLa94Xl2RE2HqqK+akmKd/h5O+WYLoocGGw1X1k2TNEzaNDQw/S4vUD2AQbwd06sVr9uuXh6F9q1/vUhTktv4O9o+RQYi6nnWpyei9PZtDWWhZV51r/+Luh+nDEaZCB7r44bT+48md1sdEfZkuXa6vRTAikZUdn6jovOIympL5VeiTfaOtggCm7oYx1oZ/NYk8E3VlpSs/O0892fD3wqB8Jkxk3bu6J+g00qG2I92Rn+XUmjOPUP7cO49UEFIX2xrv+vtenkIpRBxwCxEAupS+bmSQoAF+G5b3q2uFdRaeIR01YSX3zHdp6gH3ugyy94EHEwdulcMJoxWBREHSzRVitxWRzavHT9wmDTBVwP5SeSwzuZzwZIZPQR8PNQuy6YMTiaYXrfcJfd9mNpTvS9rMKTaPRBa4k4uFS4dTW0lyJik6WaDLvLvBB4xOBkfjqXfm2JOzdYI6DlUIxFe/bFOfMVHv5QogXysbF3f5K2DLLLV0EPB8IWjMQp3TIyZdhDk8DTdKrzSxaw9k5UBsHHOnliL6j/vR183RZUuaipcsNGXI5MzbeD3eayFqMoMiSmj23orV/93hHX55rtovD3T4UT3O6+cn9iBRaajQjfUdrd65oCwHtbEXQLFJDOEDq5WYb20Wwx1UC4gNp7qHZwicpQ5f/KGwQpEJ/O8OQ9J7xarwNuNYmEc5/JxqhLnFXeIs6eDu1aXbhktWfWtCKN6vUlYaCxJlff8SZ5VbDeLRrB/mo4GtYxmQH+oknvkCjam4OpaT3Sr00pY0x6iQAP4a9oD1+fI2kjfowlztq1pcIseLhpj7uG0dXj45szQzSjSwzYJ1Jii6RbbKl4pSU5rASNNbXVbywWI/rY7HPsWFHuf0Rg2U2XtAf7p2kQ/c3uxnkGlrn6SG6tU2WExV6ydUXBmKwL8uy1qEOfbStlAM/2OBK5LQriHy2Le/RyZxlc76di2tn+IOt0GUZ4sMQRg99Wa3zGYDAJFt8d3z2HD+KP7TOJMciRe9MMxWeDyjY14c+ngl+bEqU7GDruteYoJel4LmNJfzG7mmUc7MLLNIwr2JjbB+ZQTH6EmJ25xSoZVJcvJ8rPcGQP+MN+s7F7Vmn7h28ZWo/K/Acv04pKjHF/gvDFpqvxe90vtv5yy9cZJfVLUt18HH7ou7sjtlDBABBiU/XCvvF15m0hfTihR470QqqgWjfeRptVzHZipoW/ev9OSDg4nnsolxZ0gpJKqb6rfIX2B5fkEsoK3zuDXWxxt2HsT2Guof8LXFfRluwbultUnDG828ediF1IJRhZBeoxJLCim+isdtPpY+LKil9piV38etX8igtFBHHEeE6Qv0UAZzwVpTafMwhUaRci/iR/AiwqaniQW3YHDKTu+VBwIrtwRckw1bVob1+0wC1NOmGrjYLtybaPX8UnWp2qkn0+Z2Y8t X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 7532026a-c5a4-4feb-7ebc-08dbf74ec946 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Dec 2023 18:03:16.6061 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 7LsOURoOM2mfHOCuCiGoM+bpJRfQaVsUSG/U/puCLWsq2tHvMFfJenu2qtyJ//ky X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB7667 This is not being used to pass ops, it is just a way to tell if an iommu driver was probed. These days this can be detected directly via device_iommu_mapped(). Call device_iommu_mapped() in the two places that need to check it and remove the iommu parameter everywhere. Reviewed-by: Jerry Snitselaar Reviewed-by: Lu Baolu Reviewed-by: Moritz Fischer Acked-by: Christoph Hellwig Acked-by: Rob Herring Tested-by: Hector Martin Signed-off-by: Jason Gunthorpe --- arch/arc/mm/dma.c | 2 +- arch/arm/mm/dma-mapping-nommu.c | 2 +- arch/arm/mm/dma-mapping.c | 10 +++++----- arch/arm64/mm/dma-mapping.c | 4 ++-- arch/mips/mm/dma-noncoherent.c | 2 +- arch/riscv/mm/dma-noncoherent.c | 2 +- drivers/acpi/scan.c | 3 +-- drivers/hv/hv_common.c | 2 +- drivers/of/device.c | 2 +- include/linux/dma-map-ops.h | 4 ++-- 10 files changed, 16 insertions(+), 17 deletions(-) diff --git a/arch/arc/mm/dma.c b/arch/arc/mm/dma.c index 2a7fbbb83b7056..197707bc765889 100644 --- a/arch/arc/mm/dma.c +++ b/arch/arc/mm/dma.c @@ -91,7 +91,7 @@ void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size, * Plug in direct dma map ops. */ void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size, - const struct iommu_ops *iommu, bool coherent) + bool coherent) { /* * IOC hardware snoops all DMA traffic keeping the caches consistent diff --git a/arch/arm/mm/dma-mapping-nommu.c b/arch/arm/mm/dma-mapping-nommu.c index cfd9c933d2f09c..b94850b579952a 100644 --- a/arch/arm/mm/dma-mapping-nommu.c +++ b/arch/arm/mm/dma-mapping-nommu.c @@ -34,7 +34,7 @@ void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size, } void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size, - const struct iommu_ops *iommu, bool coherent) + bool coherent) { if (IS_ENABLED(CONFIG_CPU_V7M)) { /* diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c index 5409225b4abc06..6c359a3af8d9c7 100644 --- a/arch/arm/mm/dma-mapping.c +++ b/arch/arm/mm/dma-mapping.c @@ -1713,7 +1713,7 @@ void arm_iommu_detach_device(struct device *dev) EXPORT_SYMBOL_GPL(arm_iommu_detach_device); static void arm_setup_iommu_dma_ops(struct device *dev, u64 dma_base, u64 size, - const struct iommu_ops *iommu, bool coherent) + bool coherent) { struct dma_iommu_mapping *mapping; @@ -1748,7 +1748,7 @@ static void arm_teardown_iommu_dma_ops(struct device *dev) #else static void arm_setup_iommu_dma_ops(struct device *dev, u64 dma_base, u64 size, - const struct iommu_ops *iommu, bool coherent) + bool coherent) { } @@ -1757,7 +1757,7 @@ static void arm_teardown_iommu_dma_ops(struct device *dev) { } #endif /* CONFIG_ARM_DMA_USE_IOMMU */ void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size, - const struct iommu_ops *iommu, bool coherent) + bool coherent) { /* * Due to legacy code that sets the ->dma_coherent flag from a bus @@ -1776,8 +1776,8 @@ void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size, if (dev->dma_ops) return; - if (iommu) - arm_setup_iommu_dma_ops(dev, dma_base, size, iommu, coherent); + if (device_iommu_mapped(dev)) + arm_setup_iommu_dma_ops(dev, dma_base, size, coherent); xen_setup_dma_ops(dev); dev->archdata.dma_ops_setup = true; diff --git a/arch/arm64/mm/dma-mapping.c b/arch/arm64/mm/dma-mapping.c index 3cb101e8cb29ba..61886e43e3a10f 100644 --- a/arch/arm64/mm/dma-mapping.c +++ b/arch/arm64/mm/dma-mapping.c @@ -47,7 +47,7 @@ void arch_teardown_dma_ops(struct device *dev) #endif void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size, - const struct iommu_ops *iommu, bool coherent) + bool coherent) { int cls = cache_line_size_of_cpu(); @@ -58,7 +58,7 @@ void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size, ARCH_DMA_MINALIGN, cls); dev->dma_coherent = coherent; - if (iommu) + if (device_iommu_mapped(dev)) iommu_setup_dma_ops(dev, dma_base, dma_base + size - 1); xen_setup_dma_ops(dev); diff --git a/arch/mips/mm/dma-noncoherent.c b/arch/mips/mm/dma-noncoherent.c index 3c4fc97b9f394b..0f3cec663a12cd 100644 --- a/arch/mips/mm/dma-noncoherent.c +++ b/arch/mips/mm/dma-noncoherent.c @@ -138,7 +138,7 @@ void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size, #ifdef CONFIG_ARCH_HAS_SETUP_DMA_OPS void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size, - const struct iommu_ops *iommu, bool coherent) + bool coherent) { dev->dma_coherent = coherent; } diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoherent.c index 4e4e469b8dd66c..843107f834b231 100644 --- a/arch/riscv/mm/dma-noncoherent.c +++ b/arch/riscv/mm/dma-noncoherent.c @@ -129,7 +129,7 @@ void arch_dma_prep_coherent(struct page *page, size_t size) } void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size, - const struct iommu_ops *iommu, bool coherent) + bool coherent) { WARN_TAINT(!coherent && riscv_cbom_block_size > ARCH_DMA_MINALIGN, TAINT_CPU_OUT_OF_SPEC, diff --git a/drivers/acpi/scan.c b/drivers/acpi/scan.c index 02bb2cce423f47..444a0b3c72f2d8 100644 --- a/drivers/acpi/scan.c +++ b/drivers/acpi/scan.c @@ -1641,8 +1641,7 @@ int acpi_dma_configure_id(struct device *dev, enum dev_dma_attr attr, if (PTR_ERR(iommu) == -EPROBE_DEFER) return -EPROBE_DEFER; - arch_setup_dma_ops(dev, 0, U64_MAX, - iommu, attr == DEV_DMA_COHERENT); + arch_setup_dma_ops(dev, 0, U64_MAX, attr == DEV_DMA_COHERENT); return 0; } diff --git a/drivers/hv/hv_common.c b/drivers/hv/hv_common.c index 4372f5d146ab22..0285a74363b3d1 100644 --- a/drivers/hv/hv_common.c +++ b/drivers/hv/hv_common.c @@ -488,7 +488,7 @@ void hv_setup_dma_ops(struct device *dev, bool coherent) * Hyper-V does not offer a vIOMMU in the guest * VM, so pass 0/NULL for the IOMMU settings */ - arch_setup_dma_ops(dev, 0, 0, NULL, coherent); + arch_setup_dma_ops(dev, 0, 0, coherent); } EXPORT_SYMBOL_GPL(hv_setup_dma_ops); diff --git a/drivers/of/device.c b/drivers/of/device.c index 1ca42ad9dd159d..65c71be71a8d45 100644 --- a/drivers/of/device.c +++ b/drivers/of/device.c @@ -193,7 +193,7 @@ int of_dma_configure_id(struct device *dev, struct device_node *np, dev_dbg(dev, "device is%sbehind an iommu\n", iommu ? " " : " not "); - arch_setup_dma_ops(dev, dma_start, size, iommu, coherent); + arch_setup_dma_ops(dev, dma_start, size, coherent); if (!iommu) of_dma_set_restricted_buffer(dev, np); diff --git a/include/linux/dma-map-ops.h b/include/linux/dma-map-ops.h index a52e508d1869f6..e9cc317e9d7de6 100644 --- a/include/linux/dma-map-ops.h +++ b/include/linux/dma-map-ops.h @@ -427,10 +427,10 @@ bool arch_dma_unmap_sg_direct(struct device *dev, struct scatterlist *sg, #ifdef CONFIG_ARCH_HAS_SETUP_DMA_OPS void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size, - const struct iommu_ops *iommu, bool coherent); + bool coherent); #else static inline void arch_setup_dma_ops(struct device *dev, u64 dma_base, - u64 size, const struct iommu_ops *iommu, bool coherent) + u64 size, bool coherent) { } #endif /* CONFIG_ARCH_HAS_SETUP_DMA_OPS */ From patchwork Thu Dec 7 18:03:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 751827 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="BCwWKP37" Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2078.outbound.protection.outlook.com [40.107.220.78]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E0C801711; Thu, 7 Dec 2023 10:03:22 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=HeNqIi2EmzTO5yXwRQ0WcT89WIDsLHFTSvI53pRyEBtGbiOG/W6KAsogfhZOPhRLwWBEopkUv9CH4YxctooIwYSd3VxeCu0XcCdof0/BfYV3aqOsuj5CLaaZkjDZdy3bSJjrwLzPKCqXOFOUT1gRUlGPTe0QDwzej8y6/28PGWnoFsX4xxalS3MSxv3UHBXHVllQGq5ow5lkmzBz+VowtuUf+B6aeVewP8NhMswi0fw3kPUBKgYn0AOWojlFVoupKM6GjOh27L+fTynYIi+6NgkJzK91m1TZJ5qEwFT7RfZV5tzk24uYAwWvUWyu4SfUmQnWBHFJEL0SewXg5bqk5w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=HQVz5Sf7uBZmUEQ1+Za3derhxylOeBzYVSpFmrWOsVI=; b=Q2o2B5R0mhz0STijuqXjnQSoModBveQ2FOajBYkD9k2JU9HyxO5EcBk7NOoFqVtVT7jEI8aU8M8oHWS3V2VtFlouyY2lR5VOcEPr0CBDd+sWgsW0Yp2Umz4hEsnXxs7ubAhFAAMrQPZ6TsdK1e0TXXNyjT6V7hbBwwRY6mgNcyux8JyL1Te4ldBWEhdNdNWNbTJXnVnsXNnY31/+Q+rezDqCAINKJerFipzUmdCKuE1fVM8l3voZeiO3i2Lbbi4INVK1pCSeAwevb7auLPVDoxQ5jEGgSDeVfcE29pz1yNovgfPgP+HWcpXjd+ex1mAt4FRGVh7FFYOA3js/T0Layw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=HQVz5Sf7uBZmUEQ1+Za3derhxylOeBzYVSpFmrWOsVI=; b=BCwWKP37UqSHwcqNkU2FHwwbTq0YqOrjmMdpgDyNwNwR1AX7sCpJ4rVVKnsSLod7rQdamXrKEn2Xoz9JCV7gh1/AkvKcpCpg6izW9DAIneZz4TmQulF0F81VThSBXnYYDuUb9ifF4M8jTwxlqJQyi/npezSqu4A+TErhkb+y+mkMuzoG88QWcEcTUnWttTCWTBFgIAy8TdzFdND88/pTDak73pXE+UmfPeaagm1A4HB0i8NCo9hZ6EBMscADa487fx6zyPy37YNyGvFLo4wKKKFGbYQZqrTOROKfsq0TNOtdaz2P9XDS2VnGj0sC9JOEZjaOPcY29+zqXLELvLVgbA== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) by CH3PR12MB7667.namprd12.prod.outlook.com (2603:10b6:610:14f::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7068.25; Thu, 7 Dec 2023 18:03:16 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93%4]) with mapi id 15.20.7046.038; Thu, 7 Dec 2023 18:03:16 +0000 From: Jason Gunthorpe To: David Airlie , Alyssa Rosenzweig , Albert Ou , asahi@lists.linux.dev, Catalin Marinas , Danilo Krummrich , Daniel Vetter , Dexuan Cui , devicetree@vger.kernel.org, dmaengine@vger.kernel.org, dri-devel@lists.freedesktop.org, David Woodhouse , Frank Rowand , Haiyang Zhang , iommu@lists.linux.dev, Jon Hunter , Joerg Roedel , Karol Herbst , Krzysztof Kozlowski , "K. Y. Srinivasan" , Laxman Dewangan , Len Brown , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-hyperv@vger.kernel.org, linux-mips@vger.kernel.org, linux-riscv@lists.infradead.org, linux-snps-arc@lists.infradead.org, linux-tegra@vger.kernel.org, Russell King , Lyude Paul , Marek Szyprowski , nouveau@lists.freedesktop.org, Palmer Dabbelt , Paul Walmsley , "Rafael J. Wysocki" , Rob Herring , Robin Murphy , Suravee Suthikulpanit , Sven Peter , Thomas Bogendoerfer , Vineet Gupta , Vinod Koul , Wei Liu , Will Deacon Cc: Lu Baolu , Christoph Hellwig , Jerry Snitselaar , Hector Martin , Moritz Fischer , Moritz Fischer , patches@lists.linux.dev, "Rafael J. Wysocki" , Rob Herring , Thierry Reding , Thierry Reding Subject: [PATCH v2 2/7] iommmu/of: Do not return struct iommu_ops from of_iommu_configure() Date: Thu, 7 Dec 2023 14:03:09 -0400 Message-ID: <2-v2-16e4def25ebb+820-iommu_fwspec_p1_jgg@nvidia.com> In-Reply-To: <0-v2-16e4def25ebb+820-iommu_fwspec_p1_jgg@nvidia.com> References: X-ClientProxiedBy: MN2PR16CA0053.namprd16.prod.outlook.com (2603:10b6:208:234::22) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|CH3PR12MB7667:EE_ X-MS-Office365-Filtering-Correlation-Id: 8883fa97-f385-40db-464d-08dbf74ec90d X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: bik1C0Co744Es0lTJv+3BijxVw1aiemPIwRJ/MZomitEPkJTAPRYu83qOJoVMJEqvEiw1ahh/2euwS0IXEwT3ygx87XF9q2rP5Sf9EZN+OR7+LhPu5bMY9jk+CjXSZMz/8Uo+lhCAH8sDMhrPTfiPbgT43WoJTdjKCqDMq+v3KmPEIFl+iFJDbKkOO6XhCxW+bWf6zIqMKB87f7lMTSiZI14S0v1fgoMr2opY2By8xzk6ZN+vzaOrYiHCgEq9uTKgKaxhcbjD+xAtOpvCsnzp+IeYhkF71it5odtKwTfDk3pb6Oc/a1Fgz9pjacGgXgRH36UvTSxh7r9QDAbHd9COiTVgXnXDMZBW+KbMpUVH9gyObuK5u2WId/GMiocgYT6Cu0ztLpHONKYkRP5h9QRm67Uz+RFxQjN0YDfTh9EUzOgf6MwJAwWoFv97z+Fyntg5wkAWAFxWAclFY+5KNUsUGmPp1JgIliqgITFsPKeqAJapdQDLn3bYehNwyuYrUMtySmZ9L906CJ3ooHJbqAc3ifQ+WdTdJSNs4aaDoBWx2IVFlP4ogNqiEqk5IWtIklloc2+DpOsxSxM0ASn/MtUYbtRf2zv+6qt3KqhLfGqXa6O845L7L0jgBH67BoKX/9n X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:LV2PR12MB5869.namprd12.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230031)(39860400002)(366004)(376002)(346002)(136003)(396003)(230922051799003)(186009)(1800799012)(451199024)(64100799003)(7366002)(7416002)(2906002)(7406005)(5660300002)(41300700001)(86362001)(8676002)(4326008)(8936002)(36756003)(316002)(66946007)(66556008)(66476007)(54906003)(110136005)(921008)(38100700002)(6486002)(478600001)(107886003)(83380400001)(6666004)(6506007)(26005)(6512007)(2616005)(4216001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 4/oDryAAnEa3DRqqrnr/3ElrzAHQHzbcHQuqMdEHlsXbpQEGYvd4lwM3mfE36gELYBLSEt8g7JUMWsndj29YAZOgYRfiQDI1uMNtEdqjAmkDrKpj95ke3H+7s/VV2mjukdJOLXVM0AvSyL5B6j5zWvqWj2rQtQQ1UNg1zVLH2uIVYTXMlQVrQBnrB2GR5A6YeOM3LhTG9hfuPb38NQ5FdczS6eCEq3U+Jm5oHTqSul8lwjAHXsanTW02kvQFeG8f7W0wgEa+VZ5uL9Xa238yOFK2xteL8jEjTiYQ0ZenYMWJ+RF//vsmeXr9Av9nxHZnjDZNDJ7OOEF95wbizIs6fjYAtAmXjB5kyxWuD1PBnhP9iUrZJqQx71wzcpSpFBHPpCoQqN5YZVeN6AxWN8fCBXDDDD1SF9DKxQlktWImHntSTUmLSbhpOyujvILxIJCfrgJRgQp2NnIpGz6nlB9zOlt/LHg27iyypLo5iIqdMhFqDRPvFt9yr3eaEiJtdKAzd5SCcorZY+JHLps2E8rW7+okMOieR5ac4iNogyGZnyVXcJ63B0fxh9JQWjXTnRpbygan7lbivGZhiDJB3JptkxJxXO+B1CqUvbGWjdOwWhZWghVndMGGpXRdpt46gcUVG/j0iPKKwqGplM95rVHsfMZ8s8RynZDxh+MaErEzd5PslbifsmpUXEZ8UsJJFvZHRpfeezLPMwUdQg7ohabaDgqX+m80Fd1YgIFafyWjMRocpclikI0bUX52fzX7S+JmX7sgvrfavnPGYknov54P8AS1tLFIyKWmOD+/8xMPeM1Ipet832BsYgc5oaWqm/9R8vrGZIDjERgnmqvRSR92pcXW+83nU7YDFZB7EmCMau3d9wq9bq4G4ABklPl39rLFtd8uOdlk7ph2XDaV/R4W53QkSEXulaYgTQTMnfftkjhWu3kQPgGN6xWzSiCLB/3nYGaS2lQ7Hqkhu6TPJwSZVThfkyTxrPZP88wjfO0956YeGKOv4ug9BAeZ22Hxuj61NdlYf/FGypaVOMZTk5eLOva7DRj5S9Yy88y0KgY7ukvbey3VCaoEoTwOTFRKXoqbkiR3vqXHXlwOpQWdhvibPbyYUIBvzQ97EwYbn0I/oGY6Jb7tem2WTCcJpUf1SHsK+G7YBrk91d2RxF0ZNtFgXIpziQ9QcorfvBcI422mBifV9V0DUHuGxjeuFcbr7hxWuDVFgvfYern67gSdFQZkNeze25EPnX8UZcUJlLNgtKsMXXbK5QTP7nkCqOBQymoZ/YZbJ1EEncistcGOlgX8AoruhtdqEhz2CJKgmT2HS2c5u5h7+Q4lhQ6ZzboXiuCqyMGMosneeirUJ+G2RABnhuJQeTHgk+1XLnXLiSuSzkAPlJzH9+M4sDo5j5IeDtospxrtBqo3ZcOoCsa8/yatn8clSiwCcgZtRI2+QSkfsB+B1OFKuXa2blsj1eQJl+c1QLNtICJO0foxHrdfyxcKGIES4nL3SJYM03Uk0bnWjRBM8cythYIYIQt7PN6GqhEAc6oJ6wzpK5mkRHDBOb3hwk/Zc1J5I64Px2/1t6A25kWf4LZYC0pKc1+uZSKv0qL+ X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 8883fa97-f385-40db-464d-08dbf74ec90d X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Dec 2023 18:03:15.6999 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: ASGCIsyuj/Bow4dRSISfnn+CjYbuuPW25wC3ShehYaUWAiB3+4bfF85nzeUw23JS X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB7667 Nothing needs this pointer. Return a normal error code with the usual IOMMU semantic that ENODEV means 'there is no IOMMU driver'. Reviewed-by: Jerry Snitselaar Reviewed-by: Lu Baolu Acked-by: Rob Herring Tested-by: Hector Martin Signed-off-by: Jason Gunthorpe --- drivers/iommu/of_iommu.c | 31 +++++++++++++++++++------------ drivers/of/device.c | 22 +++++++++++++++------- include/linux/of_iommu.h | 13 ++++++------- 3 files changed, 40 insertions(+), 26 deletions(-) diff --git a/drivers/iommu/of_iommu.c b/drivers/iommu/of_iommu.c index 5ecca53847d325..c6510d7e7b241b 100644 --- a/drivers/iommu/of_iommu.c +++ b/drivers/iommu/of_iommu.c @@ -107,16 +107,22 @@ static int of_iommu_configure_device(struct device_node *master_np, of_iommu_configure_dev(master_np, dev); } -const struct iommu_ops *of_iommu_configure(struct device *dev, - struct device_node *master_np, - const u32 *id) +/* + * Returns: + * 0 on success, an iommu was configured + * -ENODEV if the device does not have any IOMMU + * -EPROBEDEFER if probing should be tried again + * -errno fatal errors + */ +int of_iommu_configure(struct device *dev, struct device_node *master_np, + const u32 *id) { const struct iommu_ops *ops = NULL; struct iommu_fwspec *fwspec; int err = NO_IOMMU; if (!master_np) - return NULL; + return -ENODEV; /* Serialise to make dev->iommu stable under our potential fwspec */ mutex_lock(&iommu_probe_device_lock); @@ -124,7 +130,7 @@ const struct iommu_ops *of_iommu_configure(struct device *dev, if (fwspec) { if (fwspec->ops) { mutex_unlock(&iommu_probe_device_lock); - return fwspec->ops; + return 0; } /* In the deferred case, start again from scratch */ iommu_fwspec_free(dev); @@ -169,14 +175,15 @@ const struct iommu_ops *of_iommu_configure(struct device *dev, err = iommu_probe_device(dev); /* Ignore all other errors apart from EPROBE_DEFER */ - if (err == -EPROBE_DEFER) { - ops = ERR_PTR(err); - } else if (err < 0) { - dev_dbg(dev, "Adding to IOMMU failed: %d\n", err); - ops = NULL; + if (err < 0) { + if (err == -EPROBE_DEFER) + return err; + dev_dbg(dev, "Adding to IOMMU failed: %pe\n", ERR_PTR(err)); + return err; } - - return ops; + if (!ops) + return -ENODEV; + return 0; } static enum iommu_resv_type __maybe_unused diff --git a/drivers/of/device.c b/drivers/of/device.c index 65c71be71a8d45..873d933e8e6d1d 100644 --- a/drivers/of/device.c +++ b/drivers/of/device.c @@ -93,12 +93,12 @@ of_dma_set_restricted_buffer(struct device *dev, struct device_node *np) int of_dma_configure_id(struct device *dev, struct device_node *np, bool force_dma, const u32 *id) { - const struct iommu_ops *iommu; const struct bus_dma_region *map = NULL; struct device_node *bus_np; u64 dma_start = 0; u64 mask, end, size = 0; bool coherent; + int iommu_ret; int ret; if (np == dev->of_node) @@ -181,21 +181,29 @@ int of_dma_configure_id(struct device *dev, struct device_node *np, dev_dbg(dev, "device is%sdma coherent\n", coherent ? " " : " not "); - iommu = of_iommu_configure(dev, np, id); - if (PTR_ERR(iommu) == -EPROBE_DEFER) { + iommu_ret = of_iommu_configure(dev, np, id); + if (iommu_ret == -EPROBE_DEFER) { /* Don't touch range map if it wasn't set from a valid dma-ranges */ if (!ret) dev->dma_range_map = NULL; kfree(map); return -EPROBE_DEFER; - } + } else if (iommu_ret == -ENODEV) { + dev_dbg(dev, "device is not behind an iommu\n"); + } else if (iommu_ret) { + dev_err(dev, "iommu configuration for device failed with %pe\n", + ERR_PTR(iommu_ret)); - dev_dbg(dev, "device is%sbehind an iommu\n", - iommu ? " " : " not "); + /* + * Historically this routine doesn't fail driver probing + * due to errors in of_iommu_configure() + */ + } else + dev_dbg(dev, "device is behind an iommu\n"); arch_setup_dma_ops(dev, dma_start, size, coherent); - if (!iommu) + if (iommu_ret) of_dma_set_restricted_buffer(dev, np); return 0; diff --git a/include/linux/of_iommu.h b/include/linux/of_iommu.h index 9a5e6b410dd2fb..e61cbbe12dac6f 100644 --- a/include/linux/of_iommu.h +++ b/include/linux/of_iommu.h @@ -8,20 +8,19 @@ struct iommu_ops; #ifdef CONFIG_OF_IOMMU -extern const struct iommu_ops *of_iommu_configure(struct device *dev, - struct device_node *master_np, - const u32 *id); +extern int of_iommu_configure(struct device *dev, struct device_node *master_np, + const u32 *id); extern void of_iommu_get_resv_regions(struct device *dev, struct list_head *list); #else -static inline const struct iommu_ops *of_iommu_configure(struct device *dev, - struct device_node *master_np, - const u32 *id) +static inline int of_iommu_configure(struct device *dev, + struct device_node *master_np, + const u32 *id) { - return NULL; + return -ENODEV; } static inline void of_iommu_get_resv_regions(struct device *dev, From patchwork Thu Dec 7 18:03:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 751828 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="uHEngP5w" Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2087.outbound.protection.outlook.com [40.107.220.87]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 526B710F7; Thu, 7 Dec 2023 10:03:21 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=IfUXgKTejQA4jstSuFLc744GgJhGrxaUe7mP3xop4ipVew4lMwFR/4ilJUAf9MFYJVdSepnJuuKCW1WJtSFS54cvjfQ1fTEslFm4ze6VeFXcyABqOKq4mwzm6YpvMzlqMKnv2sucyrzUVAqqvvegiTf92X0QJ1QXrd2i+Gz1bmBzTiAzAjhZcR7x/6LqOpzI5X7C4zKbjndkhpwMMOFILCu0nLn9LyKbLLW/vchLBCu4/mrG+6d8r0DFemLrIvgOBpPvrbT/xSbK5NUv2P0T9BHaE+D/jkwgg5gpF8b3bUOymg5i1npuxcbsDWEYDW6JU5zhsDTPd8uoHxws1JRWhg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=yWIwmEuWImSSTmwf8ViG61yiRK9AiGEml5HPWK2cQs0=; b=Chc+EJHUTTELTAbhADfMsUMD83wFo8IqDtgz+XNuX8NPXzCn40XpM25UeCwh6n9J8dtzoF2IlfQ/Bl2a/MHB1qFN4m3mMxJs90TfnZWDMBn3WW16Ff1gIh6gfB7Fnd8Ho5uolEwfuqelsVAx+f+AyW3OhjJ63SuLXnyWrfde5pPFv5Y0xPZm8Oe9k/lw33+eI5jNsfMQVw2k5DXF/2OB20Vpuyxd2TmRYo3twFOBY3+Aodi77NboIpcQm9eq+zZ8tWtx4pBpbCuViWvEtxPMevgsZFZ5k8CHZxWJcvmlBNzncTuiVxtVkAn+L5SvVcL0fq/XwjODbskHg6tEl5M8cQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=yWIwmEuWImSSTmwf8ViG61yiRK9AiGEml5HPWK2cQs0=; b=uHEngP5w8zYof4h2unuFsqucwK2tsSWdiFdDX3qls4z80PAFFikZNSYd6GR4P/sf1pkWL8Is0bHRGaNmRUQT9sRt6kel7z7N5Vtdi+J+owwBosNHR8o+sBEMUaj+FgIvwDQzErJzdkD4IWQbJ0iBUB9/lXhruNoX9drvrWSDd2ffGSrz2DcH8QItTny3zpzblCHOP8oxrJcAEUdQHtoXP/14QzzWEfdpCmTniZz/RXbVVXrp0+3kXCo+k8aIFOjsgnd9xu1kijpn+L5blTGLAcO4p0orIZkQ+waa0rlprzK/aDe54qaaYtZ81AMG/378M33JYlzPxWk4Qfr7XVsshA== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) by CH3PR12MB7667.namprd12.prod.outlook.com (2603:10b6:610:14f::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7068.25; Thu, 7 Dec 2023 18:03:16 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93%4]) with mapi id 15.20.7046.038; Thu, 7 Dec 2023 18:03:16 +0000 From: Jason Gunthorpe To: David Airlie , Alyssa Rosenzweig , Albert Ou , asahi@lists.linux.dev, Catalin Marinas , Danilo Krummrich , Daniel Vetter , Dexuan Cui , devicetree@vger.kernel.org, dmaengine@vger.kernel.org, dri-devel@lists.freedesktop.org, David Woodhouse , Frank Rowand , Haiyang Zhang , iommu@lists.linux.dev, Jon Hunter , Joerg Roedel , Karol Herbst , Krzysztof Kozlowski , "K. Y. Srinivasan" , Laxman Dewangan , Len Brown , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-hyperv@vger.kernel.org, linux-mips@vger.kernel.org, linux-riscv@lists.infradead.org, linux-snps-arc@lists.infradead.org, linux-tegra@vger.kernel.org, Russell King , Lyude Paul , Marek Szyprowski , nouveau@lists.freedesktop.org, Palmer Dabbelt , Paul Walmsley , "Rafael J. Wysocki" , Rob Herring , Robin Murphy , Suravee Suthikulpanit , Sven Peter , Thomas Bogendoerfer , Vineet Gupta , Vinod Koul , Wei Liu , Will Deacon Cc: Lu Baolu , Christoph Hellwig , Jerry Snitselaar , Hector Martin , Moritz Fischer , Moritz Fischer , patches@lists.linux.dev, "Rafael J. Wysocki" , Rob Herring , Thierry Reding , Thierry Reding Subject: [PATCH v2 3/7] iommu/of: Use -ENODEV consistently in of_iommu_configure() Date: Thu, 7 Dec 2023 14:03:10 -0400 Message-ID: <3-v2-16e4def25ebb+820-iommu_fwspec_p1_jgg@nvidia.com> In-Reply-To: <0-v2-16e4def25ebb+820-iommu_fwspec_p1_jgg@nvidia.com> References: X-ClientProxiedBy: BLAPR03CA0054.namprd03.prod.outlook.com (2603:10b6:208:32d::29) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|CH3PR12MB7667:EE_ X-MS-Office365-Filtering-Correlation-Id: 280d834f-15e4-4df5-fae8-08dbf74ec8c0 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: bsgQUSXxN7dCltll6CjCkPlMZFIgFP7i1IrAkFYOQMVFC7IAU7ROSWiqBU9TBTNZQWUmJ8GJTYiqJilPdokzYIGTy//9L/hV2oNoe8tBth2tYj662qSVgnamip6Wy+4wnmYuRC0lW+8Ut6DdhiXPXVzWky7ikqxjVjTgCCtWKVEcjmDUPQoL/EsAqsrDTD3jJJFGxIjOpWVN94f7q+VgTW44PuyklRxjLGduIyBGZe3oZ78CzU1C2A+edex6zFb+6s3zL5+nGiIOc9f/vA9sNQJANqHgcnPBcfxfVjObprbTLyDyF4uWheNNXh8HLv2zxkLzZ2LMxKme3G6b0MnXbUn2QSQFNThL5KxByBcqY6+mbESFuXp6BfgHtU+HJ3vc059zfwjoLJLG0vvR80uyT8lZxRnsL1Olelfrisa6PMspkDJ5XzmWh7sdcTLdBtx3Up0apHWIR5RFRbjp4zz+POXt2GW7kmeoitagUj4Q72YLuuwQhyYyWVi5dWE654OV+2GEmVSHf2yDEdPf3YQNtYfSGQ83Yn4zzckOnou24PCRQH/vzPznhWhbvVnapkkT8QX93UFO7NUHHye/vCncn1w/RGPH2VmzANHXozZSq8YeCg7VvSTje3lXv3c9ERfD X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:LV2PR12MB5869.namprd12.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230031)(39860400002)(366004)(376002)(346002)(136003)(396003)(230922051799003)(186009)(1800799012)(451199024)(64100799003)(7366002)(7416002)(2906002)(7406005)(5660300002)(41300700001)(86362001)(8676002)(4326008)(8936002)(36756003)(316002)(66946007)(66556008)(66476007)(54906003)(110136005)(921008)(38100700002)(6486002)(478600001)(107886003)(83380400001)(6666004)(6506007)(26005)(6512007)(2616005)(4216001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: vgb+bYitXAtHpG90YCWagwRP5QvBeBpZ01DOmL5P1g23eVNewd2V6mjfmt5g9e6l1t2iZecRN8strjkmEZQztMs7daHHsKlD3dOlJXlk+HhiDv5gghNec7LuRo3bms0Ey87u32Angc2Ephaqe+TqTY9ayu5PkL9s+/cndRXR3e7FpLuXGZIp6bl13anXW2Ffb9mZzyXMPopDZqArIzHMGjh4NX9VIKAwMJGf7+HnbPpDe0/zTwcOsLdKvhZEacQ6Tt5VDk2jZu9or0MO/PrBR3gZpR+n8j4125RgEQcZ5q4Rzh7zK1n3GmEFoEheNWNUd5n8wQkEgreQ/39ULs+aP8AIv8ZHEXRZQv/73Vst22ZoYdKYXRFqEOrUIQ7bCcB1CpqBMaGzyuy6u7YY3PSbLMHbX6cDdclkf7DrP4yl1yufwEfewllkATw2WDtQFslFbD+vDkV9r8XqivGQNqbA+dRWnP90X5oziJiWAKRfiwGIvPeLQcsB8toP/a9i7VzWklscUE5WzTLJnoLQvTg/yyg2Dh5khDISqYkb2vQ4HjXCd/a5nw0rbZp9LowN03buCFoktl5VBXghbUbbB5oZqpSHvphsbFCtw0gyM/x8aKUoEXF+CeBBbtttkt8kIaxDh1/ZX5Fg68047kWdJDE487gSz90aAUjAtnFJxSDQ8NKN757VRIkUWbPh7+UTlZyVO+uNYR9DM68Jj4tzbbo8a3f2WWIWdyZWaUnMc6gPMHTRwJUeUOlEfW2+kxelV8lE87H/Ta36gPyOm/6951DH8yv/K6cvvCa6gQ4ivkTREzG/xbr/0PdYL5WklhoHVJBEI6McGnaqrRyrOFK6rI0NdzD5bVLu+1aO2AcZxzxhGCZf2MThgvwzn6gF3I+0qtX7TtvM894T+T5UKcunPsOW0bUcYyotxIU2+zWiizqoBsKeR0NWLFo2QRV7Z0DA88I8KNQpwmNulSRMysP/oILWcamkPXOFXR7Z4AHOdHJ7r4/UsMdjDOxYMfajAEyoX+SBUNo6rYfUxtfDyp9nq6Jen8T13uPRkqMLSrFzhU0UNdtKYFGygUerK3aSj+mJ/h0Ej/SoH3tZz3PiC/w4gn0LrTc40B7u5ipEtbsPJIqPjfkJW+kXPWfiM66TUNV/LrKEfw3nQWAgFhHTfegRCcY5Zz0gdCsc8PTBHrmivc7yP9PYDqIpdsp+Bf5VDj+DU3Qv28n5wzkeY7DN9DlPPhrAzYDSYnAP2bzGBw/fdBE0E1tK6S9Aot5IUv494NNqW0HHBkX6foNDhKXFvwShb0m3K3bDZMlUmrZNkRuoUJUzb0rFqUddJgsHgbHkAFoxUvtF2fXDtkUvWCdDXOrSd5wrT9F3KcVqCni1+KSG8c+UiiKmZtLKmGpJTE267NGuJxf2cP4NCnDB7K9rPLV/x2A7LgX4vvCCbOQ2QwX/9idxt30rPZkXMX3pON7+qrCKhCAdVTGtNHG1X54IrkhkIE973VhPsN6/P5dup5WuFa6kJL+ffU+l33+CSFgYM1PtUMhiGnTRPAqoMT0Y/cwHNqpXZSt2rIqgR5dPkeZDxPXeYQ/uugmKOXCUWuTE6W0I+rpD X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 280d834f-15e4-4df5-fae8-08dbf74ec8c0 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Dec 2023 18:03:15.2272 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: umm7RhHZZ7XK2vJf6srTrWIFnDAVscDE7SbqOUMWZws5Px3ErVnmvG8pQpff4vPw X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB7667 Instead of returning 1 and trying to handle positive error codes just stick to the convention of returning -ENODEV. Remove references to ops from of_iommu_configure(), a NULL ops will already generate an error code. There is no reason to check dev->bus, if err=0 at this point then the called configure functions thought there was an iommu and we should try to probe it. Remove it. Reviewed-by: Jerry Snitselaar Reviewed-by: Moritz Fischer Tested-by: Hector Martin Signed-off-by: Jason Gunthorpe --- drivers/iommu/of_iommu.c | 49 ++++++++++++---------------------------- 1 file changed, 15 insertions(+), 34 deletions(-) diff --git a/drivers/iommu/of_iommu.c b/drivers/iommu/of_iommu.c index c6510d7e7b241b..164317bfb8a81f 100644 --- a/drivers/iommu/of_iommu.c +++ b/drivers/iommu/of_iommu.c @@ -17,8 +17,6 @@ #include #include -#define NO_IOMMU 1 - static int of_iommu_xlate(struct device *dev, struct of_phandle_args *iommu_spec) { @@ -29,7 +27,7 @@ static int of_iommu_xlate(struct device *dev, ops = iommu_ops_from_fwnode(fwnode); if ((ops && !ops->of_xlate) || !of_device_is_available(iommu_spec->np)) - return NO_IOMMU; + return -ENODEV; ret = iommu_fwspec_init(dev, &iommu_spec->np->fwnode, ops); if (ret) @@ -61,7 +59,7 @@ static int of_iommu_configure_dev_id(struct device_node *master_np, "iommu-map-mask", &iommu_spec.np, iommu_spec.args); if (err) - return err == -ENODEV ? NO_IOMMU : err; + return err; err = of_iommu_xlate(dev, &iommu_spec); of_node_put(iommu_spec.np); @@ -72,7 +70,7 @@ static int of_iommu_configure_dev(struct device_node *master_np, struct device *dev) { struct of_phandle_args iommu_spec; - int err = NO_IOMMU, idx = 0; + int err = -ENODEV, idx = 0; while (!of_parse_phandle_with_args(master_np, "iommus", "#iommu-cells", @@ -117,9 +115,8 @@ static int of_iommu_configure_device(struct device_node *master_np, int of_iommu_configure(struct device *dev, struct device_node *master_np, const u32 *id) { - const struct iommu_ops *ops = NULL; struct iommu_fwspec *fwspec; - int err = NO_IOMMU; + int err; if (!master_np) return -ENODEV; @@ -153,37 +150,21 @@ int of_iommu_configure(struct device *dev, struct device_node *master_np, } else { err = of_iommu_configure_device(master_np, dev, id); } - - /* - * Two success conditions can be represented by non-negative err here: - * >0 : there is no IOMMU, or one was unavailable for non-fatal reasons - * 0 : we found an IOMMU, and dev->fwspec is initialised appropriately - * <0 : any actual error - */ - if (!err) { - /* The fwspec pointer changed, read it again */ - fwspec = dev_iommu_fwspec_get(dev); - ops = fwspec->ops; - } mutex_unlock(&iommu_probe_device_lock); - /* - * If we have reason to believe the IOMMU driver missed the initial - * probe for dev, replay it to get things in order. - */ - if (!err && dev->bus) - err = iommu_probe_device(dev); - - /* Ignore all other errors apart from EPROBE_DEFER */ - if (err < 0) { - if (err == -EPROBE_DEFER) - return err; - dev_dbg(dev, "Adding to IOMMU failed: %pe\n", ERR_PTR(err)); + if (err == -ENODEV || err == -EPROBE_DEFER) return err; - } - if (!ops) - return -ENODEV; + if (err) + goto err_log; + + err = iommu_probe_device(dev); + if (err) + goto err_log; return 0; + +err_log: + dev_dbg(dev, "Adding to IOMMU failed: %pe\n", ERR_PTR(err)); + return err; } static enum iommu_resv_type __maybe_unused From patchwork Thu Dec 7 18:03:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 751233 Authentication-Results: smtp.subspace.kernel.org; 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Wysocki" , Rob Herring , Thierry Reding , Thierry Reding Subject: [PATCH v2 4/7] iommu: Mark dev_iommu_get() with lockdep Date: Thu, 7 Dec 2023 14:03:11 -0400 Message-ID: <4-v2-16e4def25ebb+820-iommu_fwspec_p1_jgg@nvidia.com> In-Reply-To: <0-v2-16e4def25ebb+820-iommu_fwspec_p1_jgg@nvidia.com> References: X-ClientProxiedBy: BLAPR03CA0038.namprd03.prod.outlook.com (2603:10b6:208:32d::13) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|CH3PR12MB7667:EE_ X-MS-Office365-Filtering-Correlation-Id: be10007d-4d75-49f9-acbf-08dbf74ec8b2 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: zB31Xwo8xTT0IQlVyTOSpFALZWtirXQ08TLtuYRAyAfguODKpTMPMXmEJIUrQN+GUgDPjOW9+lNQxkA6Ot4RKRHDsJC6QUSL2MWP4dJ8cDeDd0OLbD3JRqAT+6M1l9sNo1CAGQfZpF4w72RUQOfTH/tv6S9Vn/oRoGEWSmrSprshW2Marad3SeWtnSYi+h8YOikSBhtRQvRzNlLikYFIx/OCejp5KpzR6grVpfCM5vTg9vzOozeinAe0RRBqLnFWFVyYh4Plw4rc5YpkJGfP46v3zyFuEfq2HIaZw7PYI7XmJu8jlSwCMjD+ifXx6kmrHA0C/z/0SYYVav1pPKuCnwTWfBpHwMumU8xytQBFu0jwbfJzBlq551Uo9rWtADBst1Bo7M65FcXNUgDMJqGhJII0acO/bC1N9Et3z06GLmFmQYoN42m8DptBRt9wPkWLpvWAGxnGD+Y+eFcs/WCJWNf0H3BMuq0Y0P8dO84tjeI0iZE4+WTy9fiv8hOhDx8+szm6O80fwzStUPbPLOHk4BrKmR3Y+sjowrROy3eJzTgHjQGAQBGxMwQduZex1PTnUdf0YlA/W9Ts9F1SgEDbuicPXxLI6o2GIdPEZmtA+0Ge+1YDdKNweg1RRWnzKkhF X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:LV2PR12MB5869.namprd12.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230031)(39860400002)(366004)(376002)(346002)(136003)(396003)(230922051799003)(186009)(1800799012)(451199024)(64100799003)(7366002)(4744005)(7416002)(2906002)(7406005)(5660300002)(41300700001)(86362001)(8676002)(4326008)(8936002)(36756003)(316002)(66946007)(66556008)(66476007)(54906003)(110136005)(921008)(38100700002)(6486002)(478600001)(107886003)(83380400001)(6666004)(6506007)(26005)(6512007)(2616005)(4216001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: JsweJX/iMV05pHS/7MjTfWzoD9ABMJm4jHOkQ35cG1twZE9zgPr4TMrF3kP8jFH+XLWot7UHyWuDFVdIUtCjNZwoSfn/RtoNMdi+AFuumEagqtutyqE0esSYzx5atAG1QyGon9waDDbURLWjRNTojBXlCTxGzKUVoqUsfumFEBjnJyNaifH19g+r/oe5UY57YOeB4Zq/ydCLs/QCd6lVAcjPbBIN43E2w/2Wu8lAfw66mQx6OZ84DzUBwka6UV7h/90kP+w/6un4Jht8xDabTNn5927qmK2rpe/mOPHhaKm/t+6BGn5O//sIatKLD1VXNHTPxiHXQ1O2g97VTcVgWib0O2rfdKd94PL7e4vAIwH5Ww8eEHHY7/E0Cr0sGio1Omz9ldjfoJ6WSgx12ywIx9Ci8Ef7WXBtj+f4SGsWK3IzmmJlB8arAcF5YUOSvBCbn2MYm0OzyCn1c6CXz63ydxWqP+1AdgGiJTfrQZzJmuYXDDR94Kse7jA6Ab8fUKIVj7bZGL+cTSrGYjkRkdIF/WOwfG2Qp3SJ+Qzrc62R4bIEz+//OR59NGtl2zQAsW+YxNTxc94Nq652Fn6NoxvnZ8JuOJlIHARK5DkLgYm2DHWd1Mzr9fnInTeuR+zmfu83J+rOq70so+ggLHpGs93kCDwab1CEFqWhyr6/wCLHdSAuT9KmlE8P+3DhmEdG2lTSonK/fQFO0PCTh/jOUvqr8afupgiKOwPwOCjvULppha/hStSzo10Yl07K+hAV83nOLh6dYo/AOyuj/bfDP0SVJTi6Zxy+ZkIpsnEmHmcIczHBrIPqmhHvd0I5NyQDkhxR+C3V6iTkOpgyvXJuQVxSAgJAdOo2VMyK6IFgkKVVIRk2uPzEQY7f3yPanPm1JYxALIQ+Yat7qC9RssiYv9YxeuHhIQ5G9r6ILUWTzSsPpPVVL416dNobiXFgOys9tKt105x9TTcJSdm7q0jV3gAaASp34L8epWYMaeh43nV59U0oLIh1PIzGMz7iZYdY3ty1QoNGAPWhFyKGzl/ARltEWETc71Domsh4g28VJwxZu5KzF8dctkxOSbEs6Q1XCSNSNIQDgihW6W6pcTqyjOEYlrS0Kp/SI3maDrsahCUIkBj1B4ageDB/TF6TG0Y6NfNLyX/Y5Uo4SJaQi7T67v3lg7lSciO1xBN1mwL3nOot2zFp5eHxIQHFfT0CxByYSoP51EdKaFlZ68amUzp5g0LmBV2ey2J8ctQep1JPNiJhE0bVISw0YuuQ+0L1g2J3bGuBZ4Wu56W+VrZudch4A3Z9KaHVBO0vOHNppQlJHciQO4igXDLIUvtLf3nOTlgC5gVZmui5pwDKKXeW435igiRZw3RUS4lVmb8LLkDEiKEMOylHEXQhI3UM25Ad+JF9pLyDPUvuJwvxBk0UKKGztAcCILRFUz9ZvTano30Ub9SJxavO2AoM9krrGtubAr1KUQeQo58XzWnznjybI2iqSbk2ejmgWxbqaG49q+C1r75RgszV91kKbYtRrH7+L5ffAwUyrx+mKZNOqpn3tV1oe+nAFEXdhOwbRgQoyUG2YTZEZOevfUUnDjC0BmavzhR75pa7 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: be10007d-4d75-49f9-acbf-08dbf74ec8b2 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Dec 2023 18:03:15.2068 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: lieThUuRh1+FpPXFTEYv1mJDv/P5EhQSZ7+KvAdBY/o4zzTiaZQDkRcEBvV9kvWn X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB7667 Allocation of dev->iommu must be done under the iommu_probe_device_lock. Mark this with lockdep to discourage future mistakes. Reviewed-by: Jerry Snitselaar Tested-by: Hector Martin Reviewed-by: Lu Baolu Reviewed-by: Moritz Fischer Signed-off-by: Jason Gunthorpe --- drivers/iommu/iommu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index 0d25468d53a68a..4323b6276e977f 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -334,6 +334,8 @@ static struct dev_iommu *dev_iommu_get(struct device *dev) { struct dev_iommu *param = dev->iommu; + lockdep_assert_held(&iommu_probe_device_lock); + if (param) return param; From patchwork Thu Dec 7 18:03:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 751231 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="K3vZusnO" Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2078.outbound.protection.outlook.com [40.107.220.78]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3689412E; Thu, 7 Dec 2023 10:03:24 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=U91GqJ+XlRLAUqZSsoqfM6zO7h5WNmslDySXM2uxkbf6Y0Vuj3Uv4GhzN2OcPd6sSHJ4WR3jxYpl2AApHsmpQ9S3kDehB4okHXXEJcDQfSiKtC7gZJ26yZwO1VkPPLvkP7GPZyA62rgYSM4KH8Y+7W/dFnTx+7ovo/Lu0wiPkjb7kAAoBdj5KilrEMMLYYe/l/FX6aBCNsN3i1wZH1rbnUf64uWX2nHkyYml3JaHse3+z8w9yV5sCqDdkH3OlIqCcBkJG3T27XahVf0/8FeJWJjNe769QYNEEr4lTazed3AylqKPgsccKRWzfOQQvybLjazu4TCY25DYxz28Jj+Glg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=fPnu0s6EHoasXHG3G2uyD2OsRploKXFt6sJ2tSaWqZA=; b=L7xQOHisxEkKCjhjNuvnaRCAwt9PEeM8pxfeNHwhsXOZo5ZnXkh3GzqWeh/SCy9X4aus5N+J9acEcTaSKHu03nDLNvZTmG4qPBKlxODbTu9dCYCHxYAAGvx6Dyojp/KpjXpNkdRiognLMT6/V4WdEo/Xu4Vs7Nkk7MlYkH4Zd/5SfZkgBre9HRgr38n6fD2j0dDakkHbXIK3TUIrZNZihlOvEzMsLEJTdeaBH7Zd6pQNTxTmnI+b3UJkPJY6KAW5AyCme+gHaiNoJgn4QW+W4qbL6NBxgL4L/SoDZIveNYfh/iAVS4stPmmdwWzLPTJDd8GD3wyTSLlA4wTsxMtpew== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=fPnu0s6EHoasXHG3G2uyD2OsRploKXFt6sJ2tSaWqZA=; b=K3vZusnOS7OqG+ACHUlMC1JE1HAdks7KFASHFiA6uM2XN1w/3ebBn300P/i3SBDXXmYbl2FRwIFSgrQTUlHK3eLaRU58vpgxANrfNu8Au8kmvlcQRYhNKJWGu0f9xKY/8Al76SCkeUS43uhG2ThPxgNwfnvGqPVAroTWJJdj4h0Shsdy6vh0S0tm9S1uw5xFJoEjrwDXZTRUT5MuCXiizAS1Ok3RlSZqoJk/tU+jc32wRZnKGhk0fUm+cdbJYgqp/kNdeTivruaiWJOPhQkzkeN8Gub+7819hK30Gr/z/QTdyVPgBEqQDTgNPdRs/mGoQkiP34Ec5Ryzr1mIkAwZ7g== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) by CH3PR12MB7667.namprd12.prod.outlook.com (2603:10b6:610:14f::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7068.25; Thu, 7 Dec 2023 18:03:18 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93%4]) with mapi id 15.20.7046.038; Thu, 7 Dec 2023 18:03:18 +0000 From: Jason Gunthorpe To: David Airlie , Alyssa Rosenzweig , Albert Ou , asahi@lists.linux.dev, Catalin Marinas , Danilo Krummrich , Daniel Vetter , Dexuan Cui , devicetree@vger.kernel.org, dmaengine@vger.kernel.org, dri-devel@lists.freedesktop.org, David Woodhouse , Frank Rowand , Haiyang Zhang , iommu@lists.linux.dev, Jon Hunter , Joerg Roedel , Karol Herbst , Krzysztof Kozlowski , "K. Y. Srinivasan" , Laxman Dewangan , Len Brown , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-hyperv@vger.kernel.org, linux-mips@vger.kernel.org, linux-riscv@lists.infradead.org, linux-snps-arc@lists.infradead.org, linux-tegra@vger.kernel.org, Russell King , Lyude Paul , Marek Szyprowski , nouveau@lists.freedesktop.org, Palmer Dabbelt , Paul Walmsley , "Rafael J. Wysocki" , Rob Herring , Robin Murphy , Suravee Suthikulpanit , Sven Peter , Thomas Bogendoerfer , Vineet Gupta , Vinod Koul , Wei Liu , Will Deacon Cc: Lu Baolu , Christoph Hellwig , Jerry Snitselaar , Hector Martin , Moritz Fischer , Moritz Fischer , patches@lists.linux.dev, "Rafael J. Wysocki" , Rob Herring , Thierry Reding , Thierry Reding Subject: [PATCH v2 5/7] iommu: Mark dev_iommu_priv_set() with a lockdep Date: Thu, 7 Dec 2023 14:03:12 -0400 Message-ID: <5-v2-16e4def25ebb+820-iommu_fwspec_p1_jgg@nvidia.com> In-Reply-To: <0-v2-16e4def25ebb+820-iommu_fwspec_p1_jgg@nvidia.com> References: X-ClientProxiedBy: BL6PEPF00013E12.NAMP222.PROD.OUTLOOK.COM (2603:10b6:22e:400:0:1001:0:16) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|CH3PR12MB7667:EE_ X-MS-Office365-Filtering-Correlation-Id: cd431882-78d4-495b-0431-08dbf74ec9ad X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 7n1SvipzavvDG5XswVnXJY3ekiDKcx6quxHJz1IaAVfkgXglEmltvBzf1DDtQpyriRlOijerEvyJg9TyuI9rk/DfNrAkT3FZwpNeBUBisLpiL8PaaJTucmEYr9D/TzhxkoBK6pfs3dFmyegWYziv+Pm0FnApPZHp8GSVvg6P7lFFcCTA+nOjH/lS55tZnCM+y39wKJ0OD6bB75iyBoq9EtVsCfKXhLvAg8yqLksyBkQUlqKAdGIdx64+5ycQaIfVQFTd2S2A3xbDPE0Zr3SIKRGTcvUcAI/tnXFIb0VQONkF68EqI4raOQFf49xtwT3sutMgBZjdzkfaPLdwfPUeOow7vE2mACUckqFi/LiE0MWBOMYb/rkE/0dj8jaz2jqiUlsv+rKPDGUXjFak40QRmEVUeOUYDr3QAiutVpHkgxGsc6IGlIyWwG+xfK/uGNNaMEuU+q2Aq5cm2cLohf/c0GpwHeGxfuzSrko1WS1z4XQbnItOZSdVJSzg5IqVL1fj2Pktpb4IWSSP/9u44fCrcLWPNW2elnNrWYPhD0aUVpwlAykCpsszVwfKmc5Dh95ADB8XxNmeb4cqqa6o2FxksTYHDHFy/Skm1kN74tuAlCgXvEtb04Ay8okoaT4hYz4L X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:LV2PR12MB5869.namprd12.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230031)(39860400002)(366004)(376002)(346002)(136003)(396003)(230922051799003)(186009)(1800799012)(451199024)(64100799003)(7366002)(7416002)(2906002)(7406005)(5660300002)(41300700001)(86362001)(8676002)(4326008)(8936002)(36756003)(316002)(66946007)(66556008)(66476007)(54906003)(110136005)(921008)(38100700002)(6486002)(478600001)(107886003)(83380400001)(6666004)(6506007)(26005)(6512007)(2616005)(4216001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: h5fCYn1C5HAWUCy7obfNUqaoTCEkFVMeQnEDAZuubngm8Fg1s/MljXxumArz4yL9slqk7Dg93lt8zvNYQErl0CLfneGPn1UXTSMlPzV1LDpdI4AiUeiCTvBjEoEHl5OCW4tifzIWGyJKFhypqbRYnqyys51gWgQUG5ueGj20U69rnZ+A+b+mA8bz0/ElTN2bOocGKPby47stzMHrY7H3TTnU5Mr3X0Br3Vf2v+DOS75Gbxpcrx6eS6Y4+F/ZQt8s5qd06MTRuwh18nT0wVW+5kC58ieaLbf9+UWEZM9QXRtlB512PUp3lXZcMMt552PckTZb7FP4iVdE5+94Hcy/p+NHy9fQjinC1O3feDURTXQJwcOxp9tdOOQCp/rEvMjkKXmCD00bOapwpqUZ8sW8DVEvdM3edLOISaD6viYAeDVcW4ySsFoBlMQHNXO4uRloumQjdYi3rColBe+s9W0gE9IpCoXMeZV/F0EPYm15pfdnyRxdqHfIpn3O4YeD1qDsN79mtDbhlOimlpwqAA26zkI/SNejIoMgO1fuhR26xK/0opRCldBilb39HmiaqwKhzJUAl1bVRRnZLV+klLU7fSMM5bztRanlfxdlzdgWkEP1ADJ7wHFi1I33Xt5Ubaf/eZsGgDuP0uvkTlA/68/uvcb4kcFJwQ+cXLm2XCGCMNm4ETNMlqRw28qv2w0ZYKGuYHaUUzoHupIaEsuiEv6PXPAy4bVUNAQNx+e7cPcsY2dzTJ+qK9qv/LgHax8nWhcLLdvC9dyscaZHSCmrC3Rxl0N3YVVDCP92KuUJIk87d+AdGEvtf1/REER5GYJA1U7N/Eu79o1AsFELNZCG1deNS7HcK4sC1n1Bo4zuijVgLhAFPteaArN4aH7rGzksQmJd35TzQR9TDImIHVvHRAzcLDaOsaDZeDL+Vos6JRwsIH31kDijYg/6uusUik7irVWGA10TOKLszAj3riV+fbuTdcll1GwHG+LfLg0gANTDo18Rb4p7LxVk2MpddV/ZG69/yR2bezRBgqfh1Rp2apXAcbyx0zcJjQi/IRfk7XRC14FFPhRYcZh9X1CbnlioyFuxzZe8woGVLtGyC8mM7a9mD1FQYsddsLFHyWLEIsfVAct7svZeszmjB1jMQCURLSsR0a7Kx4X42xWpcR8vTGMu/SEi2pFWjOw3+ZX7vp9ZW/nStdI+o6M3LiV9fK2MTMELvYCJGdvXbQxCoXVb5Bkku87Q7dpnufC1nxxyqybzqrXP1O+UyH8VX04XvG1HPFCkldNHoz416e7HIsykl/qsmT4y35CHotG2cQyJR6xGIMQO6m1Icogezlib5AeTEXN87F4ZCozNdR7Hdpky5Dh1qF1GiEsrKnM64zbqh5klMARHgGLGP9v7C1vP2AarQ5UZCThUgInmZY8kqC4243nuhIgtDlZKh6bXuVFnjbJFTx1PjgoBwSq1AAoUriakRqCxdwWV/2CRXBbzB6G2DNuuttT/n+wDQcYnktgudSnBGF3ZyffQntAnIZ+okCIP4V20M9Lgakiqb1oMSwqZxojXySp+h8Vbn6XU0rleIjQIULW4XYaCUym7zw1jFzCbjHaB X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: cd431882-78d4-495b-0431-08dbf74ec9ad X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Dec 2023 18:03:16.7701 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: SA6avtUo/6SaD/jVHgNNjpu7H6BOIllVm8dCXMxyGnlCyF8dY7mvZk6UiUSm7Nvu X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB7667 A perfect driver would only call dev_iommu_priv_set() from its probe callback. We've made it functionally correct to call it from the of_xlate by adding a lock around that call. lockdep assert that iommu_probe_device_lock is held to discourage misuse. Exclude PPC kernels with CONFIG_FSL_PAMU turned on because FSL_PAMU uses a global static for its priv and abuses priv for its domain. Remove the pointless stores of NULL, all these are on paths where the core code will free dev->iommu after the op returns. Reviewed-by: Lu Baolu Reviewed-by: Jerry Snitselaar Tested-by: Hector Martin Signed-off-by: Jason Gunthorpe --- drivers/iommu/amd/iommu.c | 2 -- drivers/iommu/apple-dart.c | 1 - drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 1 - drivers/iommu/arm/arm-smmu/arm-smmu.c | 1 - drivers/iommu/intel/iommu.c | 2 -- drivers/iommu/iommu.c | 9 +++++++++ drivers/iommu/omap-iommu.c | 1 - include/linux/iommu.h | 5 +---- 8 files changed, 10 insertions(+), 12 deletions(-) diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 9f706436082833..be58644a6fa518 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -551,8 +551,6 @@ static void amd_iommu_uninit_device(struct device *dev) if (dev_data->domain) detach_device(dev); - dev_iommu_priv_set(dev, NULL); - /* * We keep dev_data around for unplugged devices and reuse it when the * device is re-plugged - not doing so would introduce a ton of races. diff --git a/drivers/iommu/apple-dart.c b/drivers/iommu/apple-dart.c index 7438e9c82ba982..25135440b5dd54 100644 --- a/drivers/iommu/apple-dart.c +++ b/drivers/iommu/apple-dart.c @@ -743,7 +743,6 @@ static void apple_dart_release_device(struct device *dev) { struct apple_dart_master_cfg *cfg = dev_iommu_priv_get(dev); - dev_iommu_priv_set(dev, NULL); kfree(cfg); } diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index fc4317c25b6d53..1855d3892b15f8 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2695,7 +2695,6 @@ static struct iommu_device *arm_smmu_probe_device(struct device *dev) err_free_master: kfree(master); - dev_iommu_priv_set(dev, NULL); return ERR_PTR(ret); } diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c index 4d09c004789274..adc7937fd8a3a3 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c @@ -1420,7 +1420,6 @@ static void arm_smmu_release_device(struct device *dev) arm_smmu_rpm_put(cfg->smmu); - dev_iommu_priv_set(dev, NULL); kfree(cfg); } diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index 897159dba47de4..511589341074f0 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -4461,7 +4461,6 @@ static struct iommu_device *intel_iommu_probe_device(struct device *dev) ret = intel_pasid_alloc_table(dev); if (ret) { dev_err(dev, "PASID table allocation failed\n"); - dev_iommu_priv_set(dev, NULL); kfree(info); return ERR_PTR(ret); } @@ -4479,7 +4478,6 @@ static void intel_iommu_release_device(struct device *dev) dmar_remove_one_dev_info(dev); intel_pasid_free_table(dev); intel_iommu_debugfs_remove_dev(info); - dev_iommu_priv_set(dev, NULL); kfree(info); set_dma_ops(dev, NULL); } diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index 4323b6276e977f..08f29a1dfcd5f8 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -387,6 +387,15 @@ static u32 dev_iommu_get_max_pasids(struct device *dev) return min_t(u32, max_pasids, dev->iommu->iommu_dev->max_pasids); } +void dev_iommu_priv_set(struct device *dev, void *priv) +{ + /* FSL_PAMU does something weird */ + if (!IS_ENABLED(CONFIG_FSL_PAMU)) + lockdep_assert_held(&iommu_probe_device_lock); + dev->iommu->priv = priv; +} +EXPORT_SYMBOL_GPL(dev_iommu_priv_set); + /* * Init the dev->iommu and dev->iommu_group in the struct device and get the * driver probed diff --git a/drivers/iommu/omap-iommu.c b/drivers/iommu/omap-iommu.c index c66b070841dd41..c9528065a59afa 100644 --- a/drivers/iommu/omap-iommu.c +++ b/drivers/iommu/omap-iommu.c @@ -1719,7 +1719,6 @@ static void omap_iommu_release_device(struct device *dev) if (!dev->of_node || !arch_data) return; - dev_iommu_priv_set(dev, NULL); kfree(arch_data); } diff --git a/include/linux/iommu.h b/include/linux/iommu.h index c7394b39599c84..c24933a1d0d643 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -840,10 +840,7 @@ static inline void *dev_iommu_priv_get(struct device *dev) return NULL; } -static inline void dev_iommu_priv_set(struct device *dev, void *priv) -{ - dev->iommu->priv = priv; -} +void dev_iommu_priv_set(struct device *dev, void *priv); extern struct mutex iommu_probe_device_lock; int iommu_probe_device(struct device *dev); From patchwork Thu Dec 7 18:03:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 751232 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="i+Zgt48l" Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2087.outbound.protection.outlook.com [40.107.220.87]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CBDF2170E; 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Wysocki" , Rob Herring , Thierry Reding , Thierry Reding Subject: [PATCH v2 6/7] acpi: Do not return struct iommu_ops from acpi_iommu_configure_id() Date: Thu, 7 Dec 2023 14:03:13 -0400 Message-ID: <6-v2-16e4def25ebb+820-iommu_fwspec_p1_jgg@nvidia.com> In-Reply-To: <0-v2-16e4def25ebb+820-iommu_fwspec_p1_jgg@nvidia.com> References: X-ClientProxiedBy: BL1P221CA0025.NAMP221.PROD.OUTLOOK.COM (2603:10b6:208:2c5::13) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|CH3PR12MB7667:EE_ X-MS-Office365-Filtering-Correlation-Id: 94f60b06-8b83-4788-5937-08dbf74ec920 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 6pjzyakgO6WZSkr+3aQ01y5dJ/yHRr0D72iug9y5Z3l6xhxccxNqDXerZanhpWhQEGZwHpVRp6mEMe5G7tHFpWUMr10zhou1uJ4b9c+0zf9WOxHIrX5qqnywMTHbqu2lCQgCXAqyKvJu5vXtzlFFaLxtJgR1C6GzdfyRNSKbpwdg8iKFGpxPTnz5PrQsZS+RaHuOcVSN+WtHq/wBEY5CgljFHUqgmwDU3P9inQvlyFlqfgzrTJkKSHWB/8tsTcZNw0Jy8dBD9NQNf0RnikeODKXzuKeRYXdmFSh73QOjufZTpiuYPNhl7MrRsZJ1M9iYbQnUKVDml0K+wlBMd9//ZqPKYH7zGKbFv9pFkioOOsE8k03a6s/11xyVJ0nBcCZu3sLrZZROoz4zYop1J5hPQ5XRXtaavxI40O882l36OTRQZCFJ0B8fwJppG2GXwGtqprQk8HJmDBlBiXu5z0Lr0fB2K+VfAmtJVZxxEqh4eUEu/b2IzAlz2qcGeHpOk7q9zL22weJSP0Y7ezEeQ67A0m0NknY+9IOkrOnA0QrEMlPHRvw+ClqB5DB6ybpfCjWC8VEm5MWx6PqWkKxiYvsKiaMZrX4ykIxqYBdBuuG1hzyhv9YwC7Pi4288JnIKmr4+ X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:LV2PR12MB5869.namprd12.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230031)(39860400002)(366004)(376002)(346002)(136003)(396003)(230922051799003)(186009)(1800799012)(451199024)(64100799003)(7366002)(7416002)(2906002)(7406005)(5660300002)(41300700001)(86362001)(8676002)(4326008)(8936002)(36756003)(316002)(66946007)(66556008)(66476007)(54906003)(110136005)(921008)(38100700002)(6486002)(478600001)(107886003)(83380400001)(6666004)(6506007)(26005)(6512007)(2616005)(4216001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: eLqj4kaGAHzd5LAMIZQ/hZPM88A2h5zXgC28I+ZkNCbo7s5gQh8jQRwbU2tPfe+ksUKz/TreBKAHf05cc8MmomeW11snYIdlPhYwxJg1bwrOciZeXZ5FP+mjWc8U76jXZ3+QckW6oda7CrxZ/WKIcjwrlHrpoq2+xCOsH0kKhWKv3grAjHM7Kvv/vglQHm9HUbnt0UPJk3vt0sz8SlMGyBdNOdP3IyMwGv0PlYSCOV+jOvzuOfNkdyrS9kiT07T1AJjIvMyXKwapp4vTz7A1RqkBF/pQFvFWQTMBtG0tJ+9ANJt8r2RBxV+KIzgHuKhT83k/sbKcJmq4z8W71vmQAgffOdgYrXxbk1IutQn8/ROrhtL+7mhUEvHcZmbGukfIC0ME+Mnya+ljHWGWxu0p+DABx1MIdSgXvZwIY+h4pTKjuY5tyJ5Vkp0xBhaYulqEsYoxNlrkLbXIZ5kaBND13q997mxYNFPuQKAbHztOa6XMTsUXzmOs7P21Fg+Uokgoa61lGjwDWPK9IAP5sfpW2SKz0Ll+80zl1FcQjoPDk02nTZ+DzBkvJFcwnJWhTFK5Jl61+iaYA7Ymwc/fiAdxNgeHAhIIY2fO6W5KeduOPY4Z3paKcXKVIqRSMVnlFlDtMN47TRhuRohj9E3ma5jSMvc4VVwbAAOvqvpYgk27JtvZi8XqU0sldstMJeFMrt9KvBlD0Tas5luyQZy/2OiSqNa4FqDrYsOjKNT1FY8Ou3xec5sf1A6+53Z3H19s/IS78hg49PHe+T+La2yACaKlh44G0ROlsYCCd0lcTxNHABGBMv1Euxvk+DBwpRoYwz4FpgkMujqf2A1pu0XSW5yuEgnMHkU5UrlE6cgyAyvc2yikvqqFJrsHRhFxCKHCtKsdPP9khEemR2MOydu1f+huddRYF5JZMf6ZjG2XKeXfquimERvxRYyT4/PsQkz7bmgph4A3U5jeTEJ+SJ1tWB0h95SfEp8j9s8iswe8QwlY6cVUa1q+2y9ZVxqTH55TGVMpW3/AHTYdlV4ChXn0K95xAvjC19L+EkbimJBj8QFrFXjzstFY6sKv2wEL2I2rdk7QimDbu68JJ7hkGLfwRJ4ePl+JTjt+h+meQHSaDdWPL9/0XR9lkXG6M6zuoqVh58DhY/vFHQhI8B2RMYa+ht6gLI+UeWDRw04JRpOLXorkVNI6clwWRdHGSGHzDhVgY0+JDjnfAO7+MeBki8LeznhCGmI6Dk2xxSalPwuMf21gCQ+2BSNl4NsD+z1o3Unai20O3FQhlbvNQRfqmCpk+OtXIQaGXTyHewjx+94wwq1mIMp45nKQIf6B8qK3QLDQA+GjDCj6aSAaxeZVwCcE06L28h6PLaIl5AnrNB0G38gkWGJHXcA4dLquVaJTlwHSJT/QgGmvJVLOYEgiTfWfH1rR+IoA5MHzxZurCYSyfZ+M2zFaUF665EJpUQFUS0wjwtETJdWKOJ9DdSAHrRRg/rBv4UI03H4/hyJZKq1Z+/O3QbBM9MIBX1da4BwBi+gHhapwewtizo3FvvW7FX+N2/cILDIuQ8RLJAzjQxyEfzNMfW2GnHP3mv0GLZZgHGUnHSLr X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 94f60b06-8b83-4788-5937-08dbf74ec920 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Dec 2023 18:03:15.8580 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: KreLPiS/tPu0PoY6hT4BaJs/2pHwl0AEbI48HLrDnJmtcTYizNJqe6V1LMlgUydH X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB7667 Nothing needs this pointer. Return a normal error code with the usual IOMMU semantic that ENODEV means 'there is no IOMMU driver'. Acked-by: Rafael J. Wysocki Reviewed-by: Jerry Snitselaar Reviewed-by: Lu Baolu Reviewed-by: Moritz Fischer Tested-by: Hector Martin Signed-off-by: Jason Gunthorpe --- drivers/acpi/scan.c | 29 +++++++++++++++++------------ 1 file changed, 17 insertions(+), 12 deletions(-) diff --git a/drivers/acpi/scan.c b/drivers/acpi/scan.c index 444a0b3c72f2d8..340ba720c72129 100644 --- a/drivers/acpi/scan.c +++ b/drivers/acpi/scan.c @@ -1562,8 +1562,7 @@ static inline const struct iommu_ops *acpi_iommu_fwspec_ops(struct device *dev) return fwspec ? fwspec->ops : NULL; } -static const struct iommu_ops *acpi_iommu_configure_id(struct device *dev, - const u32 *id_in) +static int acpi_iommu_configure_id(struct device *dev, const u32 *id_in) { int err; const struct iommu_ops *ops; @@ -1577,7 +1576,7 @@ static const struct iommu_ops *acpi_iommu_configure_id(struct device *dev, ops = acpi_iommu_fwspec_ops(dev); if (ops) { mutex_unlock(&iommu_probe_device_lock); - return ops; + return 0; } err = iort_iommu_configure_id(dev, id_in); @@ -1594,12 +1593,14 @@ static const struct iommu_ops *acpi_iommu_configure_id(struct device *dev, /* Ignore all other errors apart from EPROBE_DEFER */ if (err == -EPROBE_DEFER) { - return ERR_PTR(err); + return err; } else if (err) { dev_dbg(dev, "Adding to IOMMU failed: %d\n", err); - return NULL; + return -ENODEV; } - return acpi_iommu_fwspec_ops(dev); + if (!acpi_iommu_fwspec_ops(dev)) + return -ENODEV; + return 0; } #else /* !CONFIG_IOMMU_API */ @@ -1611,10 +1612,9 @@ int acpi_iommu_fwspec_init(struct device *dev, u32 id, return -ENODEV; } -static const struct iommu_ops *acpi_iommu_configure_id(struct device *dev, - const u32 *id_in) +static int acpi_iommu_configure_id(struct device *dev, const u32 *id_in) { - return NULL; + return -ENODEV; } #endif /* !CONFIG_IOMMU_API */ @@ -1628,7 +1628,7 @@ static const struct iommu_ops *acpi_iommu_configure_id(struct device *dev, int acpi_dma_configure_id(struct device *dev, enum dev_dma_attr attr, const u32 *input_id) { - const struct iommu_ops *iommu; + int ret; if (attr == DEV_DMA_NOT_SUPPORTED) { set_dma_ops(dev, &dma_dummy_ops); @@ -1637,10 +1637,15 @@ int acpi_dma_configure_id(struct device *dev, enum dev_dma_attr attr, acpi_arch_dma_setup(dev); - iommu = acpi_iommu_configure_id(dev, input_id); - if (PTR_ERR(iommu) == -EPROBE_DEFER) + ret = acpi_iommu_configure_id(dev, input_id); + if (ret == -EPROBE_DEFER) return -EPROBE_DEFER; + /* + * Historically this routine doesn't fail driver probing due to errors + * in acpi_iommu_configure_id() + */ + arch_setup_dma_ops(dev, 0, U64_MAX, attr == DEV_DMA_COHERENT); return 0; From patchwork Thu Dec 7 18:03:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 751829 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="RM1T2z1H" Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2087.outbound.protection.outlook.com [40.107.220.87]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AE8F6170E; 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Y. Srinivasan" , Laxman Dewangan , Len Brown , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-hyperv@vger.kernel.org, linux-mips@vger.kernel.org, linux-riscv@lists.infradead.org, linux-snps-arc@lists.infradead.org, linux-tegra@vger.kernel.org, Russell King , Lyude Paul , Marek Szyprowski , nouveau@lists.freedesktop.org, Palmer Dabbelt , Paul Walmsley , "Rafael J. Wysocki" , Rob Herring , Robin Murphy , Suravee Suthikulpanit , Sven Peter , Thomas Bogendoerfer , Vineet Gupta , Vinod Koul , Wei Liu , Will Deacon Cc: Lu Baolu , Christoph Hellwig , Jerry Snitselaar , Hector Martin , Moritz Fischer , Moritz Fischer , patches@lists.linux.dev, "Rafael J. Wysocki" , Rob Herring , Thierry Reding , Thierry Reding Subject: [PATCH v2 7/7] iommu/tegra: Use tegra_dev_iommu_get_stream_id() in the remaining places Date: Thu, 7 Dec 2023 14:03:14 -0400 Message-ID: <7-v2-16e4def25ebb+820-iommu_fwspec_p1_jgg@nvidia.com> In-Reply-To: <0-v2-16e4def25ebb+820-iommu_fwspec_p1_jgg@nvidia.com> References: X-ClientProxiedBy: BL6PEPF00013E0D.NAMP222.PROD.OUTLOOK.COM (2603:10b6:22e:400:0:1001:0:11) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|CH3PR12MB7667:EE_ X-MS-Office365-Filtering-Correlation-Id: d4e13b29-904d-42f6-d3e4-08dbf74ec8b9 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: +n/l6UAabUdpS5PVFZStuBJoDnIqrihHpl7qOWQuw3pmkEzShA3wA/eXc4fdVlynIh7D9Nf3S612YCYIhbrM7Hl4E/BN7BoAyn2n4VsqWc1GZW7/rzEX5BeTphiYPcoGkBQMq11bqvUYStxI1UMF+AVmK84hjOE850BnHjFp4IVpfnVHaPuT+p6AevNDvV07SMjpgC99U4Lulo2Vy1DwoFKL90lyMyQhCaiZl0IPuAGwUQLy7fF67nmfYg3tT6ydQmzc+qaCvy7UBj7ZNk/cTTSHmwAb54uQSpvvgvMrVPDJjlp1PgsCOhQYBTij4L7LBk4TMsgc0qt282aj7NG+5gqGKf003hF5vJk6xG3irbyy+kDwXcDUY8s28eKT9nfdB30hOqhq3OYEQpVEWPEhLwZrdyOo7pyP90cEV//IFKTRoXv9Qbxym7kcoB3CKaXtDKB0ntchgRUcuBO9EYjl+YZ4Q0p7hE6XvWGQ6YonBpSS0/AvpvMf3N/t7bYCVlFXdoRPwzWlA0hyEZLa3scpmKw8F8ZZEBNrOQXTuuoBVh7lPB4b+RthKJgF7KSaDF3ajhGGvvX/o06XHSkmXphfWqCiNebxomSynFjo2sUm2onTb8PI312bij44oQvF3LVx X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:LV2PR12MB5869.namprd12.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230031)(39860400002)(366004)(376002)(346002)(136003)(396003)(230922051799003)(186009)(1800799012)(451199024)(64100799003)(7366002)(7416002)(2906002)(7406005)(5660300002)(41300700001)(86362001)(8676002)(4326008)(8936002)(36756003)(316002)(66946007)(66556008)(66476007)(54906003)(110136005)(921008)(38100700002)(6486002)(478600001)(107886003)(66574015)(83380400001)(6506007)(26005)(6512007)(2616005)(4216001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: +JFcrODuzG05IJoMWbmoOiF4vCjY3SH3yczsBv+1cnvZb/PHHqr49Ya4DxGwFFAQzMVFPEBCbqJCLO2JFNYQpbPesApFsErSdY8FP+I8ZggtbmX9g5iA2T78TJxK8Naww7UoETmaOG85QiH70jfDBMbAgVh6wQBcrkj/ziWx28ybAxIc857GGpK/IMMi+42kB/0+GPojg6Q0J40FLr1/rdfmp/3VsizdJ7gZUl5Ii9sSbOoz2aJYBilbWAAhWtJGamsfsHUOQmRqkmz6Tikek1xlNutEscjt6A/LRPBFHVGSr4BzqQzf50TXJKHbNtMOiGsy2gylTQPS5ZVxWyIP4s3AJSzZ1murhL7tdf/3aAQMlACPZfkqoknaexWV8w4IgzEAFXbmZdBl3QMZ9AVqFXyoPpEglsbLAwSLImos7H4nFoLkGfGAXm5Nhom2pa97gjirhWNpHP8B2b2Yun3N8ecicrCp0D+0GrExXcj9kyUzIxH9qsYADh5PglW0gvklbFU+CEmWINm14Y0AcASbbQcemucBcgsiw/voFBeTxf2jEhXadDBT13I1WV8e8GPELL87KqgWi7e8NcaJ96oqltaZbKojsGRMz8E43qVLE7GH2kCyXcWOFY5thGXyGelilGmjF5reNtx6ZoP8sJI8ZJuyrNM2cSXKpEvQKVqeXDJIHWg+oPk9f0Xigzpi7cWtxl96CRpfCgSS7ZtiWoYMGE4khrx0p/ej1/oHKFceNOizJU1KyVBZyG/cIICfYtRtHUBBjo2SDcfsvSy7AYSW4Un0HYPnrGb2fpFTxjs7WiB091ddDt5REj1J9fJ1Q4SkeWXohkLeST7HqkgJdasiA9JirPU+h0gfwdCj+aecmDSsQdh5W6X8JE8bZfOc8gVWsnFM9eDG6Cr52xahrh3neToXaIPu/AzXQdD7u7jKCc39zLBe7SVRe+7Y26zZLRFDMvZBMys/NjxB7jwrck2UTPky41COgjDf/Y65eQwHJHRJT5An2lGfY0N6Qd7AihywWykCpZgFr4+b82kfiLgJKem3ZyBJ4XPLrfGr4wVBtGZ00HtL/V1WW8QvsRl39k5IgChEAQWckboRPjz6+tZZBWMtsDgZ0ypdmhYw5tJDQOMBvyTlmpL/UqEi9ernx45wdPakz9YLhShrqwMw9MF0Lg8DasVMoBH+JEyBSDI7yuXmUeLHZPzgaUJ/OY6gXhg9Zb87e7AgvrqR25+HgoEj13TRgJp7Z8qvPscXjb6hEPDEZwC1XdVjS4iB0GOZv57qN5xmIYgg2m/xY5q7R+djCjXs0nYBEC2CDgeHqY90O/HTq6VyTP/q8aKLqXJFV+rtXNC1OypgYluofL3MhrUUv3cw1UZ1ecFczk/bXInHw5R+zvGvR0raZX6ZDRj/ps3WJVg8Ok1/p+wyA5u/MLe/jJq6YKcu4+Wx3Qwax/RtviwiaGUH+cT2sq0tnO8W9X1WZRWkK9AJh6+uprqSJUzOj5enCWprc00KBhlCIRxg9t8V+AAypSH2MpOO5+JxU8XZy7jiiea4tTlC0TQYQlWHq3bphLZhZ1ccTI6ZwPI08Rvb3Wp/DTj7alaBqwajCQzk X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: d4e13b29-904d-42f6-d3e4-08dbf74ec8b9 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Dec 2023 18:03:15.1951 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: YpYMkmZkyeEXimkQSeaIavwaVjwVEFkWI8BApk4OYFTmL4lf2Igjlo69pO0fmWrK X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB7667 This API was defined to formalize the access to internal iommu details on some Tegra SOCs, but a few callers got missed. Add them. The helper already masks by 0xFFFF so remove this code from the callers. Suggested-by: Thierry Reding Reviewed-by: Thierry Reding Signed-off-by: Jason Gunthorpe --- drivers/dma/tegra186-gpc-dma.c | 8 +++----- drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp10b.c | 9 ++------- drivers/memory/tegra/tegra186.c | 14 ++++++++------ 3 files changed, 13 insertions(+), 18 deletions(-) diff --git a/drivers/dma/tegra186-gpc-dma.c b/drivers/dma/tegra186-gpc-dma.c index fa4d4142a68a21..88547a23825b18 100644 --- a/drivers/dma/tegra186-gpc-dma.c +++ b/drivers/dma/tegra186-gpc-dma.c @@ -1348,8 +1348,8 @@ static int tegra_dma_program_sid(struct tegra_dma_channel *tdc, int stream_id) static int tegra_dma_probe(struct platform_device *pdev) { const struct tegra_dma_chip_data *cdata = NULL; - struct iommu_fwspec *iommu_spec; - unsigned int stream_id, i; + unsigned int i; + u32 stream_id; struct tegra_dma *tdma; int ret; @@ -1378,12 +1378,10 @@ static int tegra_dma_probe(struct platform_device *pdev) tdma->dma_dev.dev = &pdev->dev; - iommu_spec = dev_iommu_fwspec_get(&pdev->dev); - if (!iommu_spec) { + if (!tegra_dev_iommu_get_stream_id(&pdev->dev, &stream_id)) { dev_err(&pdev->dev, "Missing iommu stream-id\n"); return -EINVAL; } - stream_id = iommu_spec->ids[0] & 0xffff; ret = device_property_read_u32(&pdev->dev, "dma-channel-mask", &tdma->chan_mask); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp10b.c b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp10b.c index e7e8fdf3adab7a..29682722b0b36b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp10b.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp10b.c @@ -28,19 +28,14 @@ static void gp10b_ltc_init(struct nvkm_ltc *ltc) { struct nvkm_device *device = ltc->subdev.device; - struct iommu_fwspec *spec; + u32 sid; nvkm_wr32(device, 0x17e27c, ltc->ltc_nr); nvkm_wr32(device, 0x17e000, ltc->ltc_nr); nvkm_wr32(device, 0x100800, ltc->ltc_nr); - spec = dev_iommu_fwspec_get(device->dev); - if (spec) { - u32 sid = spec->ids[0] & 0xffff; - - /* stream ID */ + if (tegra_dev_iommu_get_stream_id(device->dev, &sid)) nvkm_wr32(device, 0x160000, sid << 2); - } } static const struct nvkm_ltc_func diff --git a/drivers/memory/tegra/tegra186.c b/drivers/memory/tegra/tegra186.c index 533f85a4b2bdb7..9cbf22a10a8270 100644 --- a/drivers/memory/tegra/tegra186.c +++ b/drivers/memory/tegra/tegra186.c @@ -111,9 +111,12 @@ static void tegra186_mc_client_sid_override(struct tegra_mc *mc, static int tegra186_mc_probe_device(struct tegra_mc *mc, struct device *dev) { #if IS_ENABLED(CONFIG_IOMMU_API) - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); struct of_phandle_args args; unsigned int i, index = 0; + u32 sid; + + if (!tegra_dev_iommu_get_stream_id(dev, &sid)) + return 0; while (!of_parse_phandle_with_args(dev->of_node, "interconnects", "#interconnect-cells", index, &args)) { @@ -121,11 +124,10 @@ static int tegra186_mc_probe_device(struct tegra_mc *mc, struct device *dev) for (i = 0; i < mc->soc->num_clients; i++) { const struct tegra_mc_client *client = &mc->soc->clients[i]; - if (client->id == args.args[0]) { - u32 sid = fwspec->ids[0] & MC_SID_STREAMID_OVERRIDE_MASK; - - tegra186_mc_client_sid_override(mc, client, sid); - } + if (client->id == args.args[0]) + tegra186_mc_client_sid_override( + mc, client, + sid & MC_SID_STREAMID_OVERRIDE_MASK); } }