From patchwork Fri Dec 15 09:53:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vignesh Viswanathan X-Patchwork-Id: 754416 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B5409182CC; Fri, 15 Dec 2023 09:54:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="Zp65zpEj" Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BF6clEI020333; Fri, 15 Dec 2023 09:53:57 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding:content-type; s=qcppdkim1; bh=irrdVr6 6tDbhPurQgzzQPKMKNs2gfbQhgBvmOcZQvjY=; b=Zp65zpEjZSRDwjdzpdf1etB A8Ri0qipf+XptrIkevgocjhG/2+zuumEpesaiZrMATMP0pbIzTF2tPCP9LeIwgeK wpz9b3her4Aabo24f2OGYHmPyn2sxjWhpynQF0z/ueisc+QAQtJgiITQzfG4sTIN 0EmpOZEldSm2gBJ6tSUW83phkSMuvuaX3Iuz6Gt5WTH73vud+f1t/00oSe55t6HK vHBVT74bd7OTBZQZx7VRHhk+oLVOa5g6Hqvf+fR00m9YOFUpAgT6QiSJpWb0Gl6Q xUDo2tLqo1WhUjF0PuPBRmCjj40Mrtmjo34l/twlIVO64zPgvtz1TpAX4+atmQg= = Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3v0hqcgmag-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 15 Dec 2023 09:53:57 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3BF9ruOR032698 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 15 Dec 2023 09:53:57 GMT Received: from hu-viswanat-blr.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Fri, 15 Dec 2023 01:53:53 -0800 From: Vignesh Viswanathan To: , , , , , , , , CC: , , Vignesh Viswanathan Subject: [PATCH] arm64: dts: qcom: ipq9574: Enable Inline Crypto Engine for MMC Date: Fri, 15 Dec 2023 15:23:39 +0530 Message-ID: <20231215095339.3055554-1-quic_viswanat@quicinc.com> X-Mailer: git-send-email 2.41.0 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: Ucp0-Wx-aQOo_foIVGn-qU4GFwRvC4j9 X-Proofpoint-GUID: Ucp0-Wx-aQOo_foIVGn-qU4GFwRvC4j9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_01,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 mlxscore=0 phishscore=0 adultscore=0 priorityscore=1501 impostorscore=0 lowpriorityscore=0 mlxlogscore=496 clxscore=1011 suspectscore=0 spamscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312150066 Add Inline Crypto Engine reg and clocks in MMC node and enable CQE support as Inline Crypto Engine requires CQE to be enabled. Signed-off-by: Vignesh Viswanathan --- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 5f83ee42a719..7f2e5cbf3bbb 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -321,8 +321,10 @@ tcsr: syscon@1937000 { sdhc_1: mmc@7804000 { compatible = "qcom,ipq9574-sdhci", "qcom,sdhci-msm-v5"; - reg = <0x07804000 0x1000>, <0x07805000 0x1000>; - reg-names = "hc", "cqhci"; + reg = <0x07804000 0x1000>, + <0x07805000 0x1000>, + <0x07808000 0x2000>; + reg-names = "hc", "cqhci", "ice"; interrupts = , ; @@ -330,9 +332,11 @@ sdhc_1: mmc@7804000 { clocks = <&gcc GCC_SDCC1_AHB_CLK>, <&gcc GCC_SDCC1_APPS_CLK>, - <&xo_board_clk>; - clock-names = "iface", "core", "xo"; + <&xo_board_clk>, + <&gcc GCC_SDCC1_ICE_CORE_CLK>; + clock-names = "iface", "core", "xo", "ice"; non-removable; + supports-cqe; status = "disabled"; };