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[209.51.188.17]) by mx.google.com with ESMTPS id v4si10298435ejb.275.2019.09.04.04.22.03 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 04 Sep 2019 04:22:03 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="H7t/DE89"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:56218 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5TMQ-0007VG-07 for patch@linaro.org; Wed, 04 Sep 2019 07:22:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36503) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5TLf-00076E-Pr for qemu-devel@nongnu.org; Wed, 04 Sep 2019 07:21:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i5TLd-0007E1-Fx for qemu-devel@nongnu.org; Wed, 04 Sep 2019 07:21:15 -0400 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]:37870) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i5TLd-0007Cl-8D for qemu-devel@nongnu.org; Wed, 04 Sep 2019 07:21:13 -0400 Received: by mail-wm1-x335.google.com with SMTP id r195so3238684wme.2 for ; Wed, 04 Sep 2019 04:21:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=k8unDVXpqLg5lphwGOo47n1fiubp2aXlLo/SotwPOPg=; b=H7t/DE89yjsHHkLoLe7eOvU/ei+v20trln0fY4LNKV62HDVgcVHpCl9AF/cZWjBV23 6kbK3qBEt9zti5fO7MMqIyHHCBMH4dVEbM/6mD/PwnL0YBX65K18AcMyRLZcfgjHH/RR YsI8cz9c84iTUSMjB+H0W7HeG8H7tdNSQtyVjYa8eZF+9h2Rkkrhcct/5rxneVuTjpjm exJVpnc9rptHamN/Q9pl7bFcKgN1K5s+K6gQl6Gyt3No+wFLr6Jq2IvWKesCFl4PhPHO ao3hu4++24FvHJB6Nx5/xmMcQkdCm2vNG0+J3K51b3W8hcALWygKLRbCAIi1TlrIuGNb dpOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=k8unDVXpqLg5lphwGOo47n1fiubp2aXlLo/SotwPOPg=; b=gCMUeH7spdsH4mjBoCDrjjcUsDoWynTmJwQX9GuTmaBbr/thzvXwJzP4Of2HB0Wgq2 4XLNQRO2f2PxHjqqNdFWEEnM73fk0qF3qooFaXeeGKhimmMBuBP3AKuwdh3wYbZlqvTo 68CfsAsasPdTZYb6dDSl6cZy9MZnYM6h2ydnXbOa4IFgyhkLrqGXX0bixm8gs+IiaJ48 0EwxYDIlK3bAJ3DoatryO+81j+dKqjV3ucYlc2zEQrss9D/QjWOmQc4YLNzGpfAMRDRJ GR7wntjhoFatkMwHzy55miuoI0dvy+iBSwYwDAvpDHEncn+UCAf5RJp/uK1RoU3BJijQ MEXg== X-Gm-Message-State: APjAAAXPHHSwkC60DGhZqQlZeHflOYgDnMa8zrn45w+PghsbJTX1CFJ/ NSaL7eKvgbZfuETLwWVjBPJgsA== X-Received: by 2002:a1c:e709:: with SMTP id e9mr3987262wmh.65.1567596072093; Wed, 04 Sep 2019 04:21:12 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id a205sm1678669wmd.44.2019.09.04.04.21.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 04:21:09 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 23C091FF8C; Wed, 4 Sep 2019 12:21:09 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:21:04 +0100 Message-Id: <20190904112108.2341-2-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190904112108.2341-1-alex.bennee@linaro.org> References: <20190904112108.2341-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::335 Subject: [Qemu-devel] [PATCH v2 1/5] target/arm: handle M-profile semihosting at translate time X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We do this for other semihosting calls so we might as well do it for M-profile as well. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- v2 - update for change to gen_exception_internal_insn API --- target/arm/m_helper.c | 18 ++++++------------ target/arm/translate.c | 20 +++++++++++++++++++- 2 files changed, 25 insertions(+), 13 deletions(-) -- 2.20.1 diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 884d35d2b02..27cd2f3f964 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -2114,19 +2114,13 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) break; } break; + case EXCP_SEMIHOST: + qemu_log_mask(CPU_LOG_INT, + "...handling as semihosting call 0x%x\n", + env->regs[0]); + env->regs[0] = do_arm_semihosting(env); + return; case EXCP_BKPT: - if (semihosting_enabled()) { - int nr; - nr = arm_lduw_code(env, env->regs[15], arm_sctlr_b(env)) & 0xff; - if (nr == 0xab) { - env->regs[15] += 2; - qemu_log_mask(CPU_LOG_INT, - "...handling as semihosting call 0x%x\n", - env->regs[0]); - env->regs[0] = do_arm_semihosting(env); - return; - } - } armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG, false); break; case EXCP_IRQ: diff --git a/target/arm/translate.c b/target/arm/translate.c index 615859e23c5..816d46b2205 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10931,6 +10931,24 @@ illegal_op: unallocated_encoding(s); } +/* + * Thumb BKPT. On M-profile CPUs this may be a semihosting call which + * we can process much the same way as gen_hlt() above. + */ +static inline void gen_thumb_bkpt(DisasContext *s, int imm8) +{ + if (arm_dc_feature(s, ARM_FEATURE_M) && + semihosting_enabled() && +#ifndef CONFIG_USER_ONLY + s->current_el != 0 && +#endif + (imm8 == 0xab)) { + gen_exception_internal_insn(s, s->base.pc_next, EXCP_SEMIHOST); + return; + } + gen_exception_bkpt_insn(s, syn_aa32_bkpt(imm8, true)); +} + static void disas_thumb_insn(DisasContext *s, uint32_t insn) { uint32_t val, op, rm, rn, rd, shift, cond; @@ -11553,7 +11571,7 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) { int imm8 = extract32(insn, 0, 8); ARCH(5); - gen_exception_bkpt_insn(s, syn_aa32_bkpt(imm8, true)); + gen_thumb_bkpt(s, imm8); break; } From patchwork Wed Sep 4 11:21:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 172919 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp1093650ily; Wed, 4 Sep 2019 04:24:00 -0700 (PDT) X-Google-Smtp-Source: APXvYqzsbd2tXCxn8LZhAHZHwWlrhO1xeXKnyCSoK2ZxGsgpmdKnNorZ2t8wso5wugHhWx21Il1Y X-Received: by 2002:ac8:4757:: with SMTP id k23mr10775259qtp.40.1567596240813; Wed, 04 Sep 2019 04:24:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567596240; cv=none; d=google.com; s=arc-20160816; b=h/8vMH4lQgO2bfYm8Ncc9HwGnWTD2t91FxkA1O9wV2b0/yaLPhLABKQN/TaPGkINwD fKidCXlvy1Q7Gqwu7PTWA+nuOTxAodaR+e8897UKF5bckk578YHR4VY5a3weusXB0Mmh 8uBDxEMIJfYQ2mlRKt30j7X672fi2JlAYFnUPOm/UbdtqUhyRP1ZaWRk69MMEtchyafs L+2wD2KrwMuAcTscM4mjCIiADko2FhLU9qiNelO1hKiOeBigIxuygpWlO2Aye5SKOza5 /IF0DW5PX8mVcOa18rJM4/8b3dqFVtRrAyDAy86KFEoVl+KtN1pdUyljzUOZBy26iZuC X7ug== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=9Ge+XWvDG5sVV+m6AqlxOZT4JsJcjtpuvEGkiH2jJk8=; b=kQBX5g6TQGt7sawQWfM1j9sh7gJHQm2AP4Hb9f2KfmavcFzkk9NxpRzE+FIRuyRjdr hopwJRuAIln9RqQ5Lmu42YGjUlpBjdHKSNvCvKO1gix6KVPLJP1B24t/2H7fpdkso8X/ OVuzjHJ4wGmnaJRnin49yO/NeEod20WgURHCGp84csrGsXnjGX2Rx231AH32rhnkNHez 6lrzI9VHytMlGnMHdgkXixKDOKHIuQZQlDqjqsrfaVqfYabjTez3mISAS28NfxjBZ4du DjVp1Bu8P+HA59McceK2SOr6bSLjH2mgF3ix98ycHDRaythdpmC/Q40omwR6lRTuDsbd zaaA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=O6FI0Ztt; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:4864:20::442 Subject: [Qemu-devel] [PATCH v2 2/5] target/arm: handle A-profile T32 semihosting at translate time X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" As for the other semihosting calls we can resolve this at translate time. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- v2 - update for change to gen_exception_internal_insn API --- target/arm/translate.c | 24 ++++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) -- 2.20.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 816d46b2205..673994ed1a1 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10949,6 +10949,24 @@ static inline void gen_thumb_bkpt(DisasContext *s, int imm8) gen_exception_bkpt_insn(s, syn_aa32_bkpt(imm8, true)); } +/* + * Thumb SWI. On A-profile CPUs this may be a semihosting call. + */ +static inline void gen_thumb_swi(DisasContext *s, int imm8) +{ + if (semihosting_enabled() && +#ifndef CONFIG_USER_ONLY + s->current_el != 0 && +#endif + (imm8 == 0xab)) { + gen_exception_internal_insn(s, s->base.pc_next, EXCP_SEMIHOST); + return; + } + gen_set_pc_im(s, s->base.pc_next); + s->svc_imm = imm8; + s->base.is_jmp = DISAS_SWI; +} + static void disas_thumb_insn(DisasContext *s, uint32_t insn) { uint32_t val, op, rm, rn, rd, shift, cond; @@ -11700,10 +11718,8 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) goto undef; if (cond == 0xf) { - /* swi */ - gen_set_pc_im(s, s->base.pc_next); - s->svc_imm = extract32(insn, 0, 8); - s->base.is_jmp = DISAS_SWI; + /* swi/svc */ + gen_thumb_swi(s, extract32(insn, 0, 8)); break; } /* generate a conditional jump to next instruction */ From patchwork Wed Sep 4 11:21:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 172920 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp1093778ily; Wed, 4 Sep 2019 04:24:08 -0700 (PDT) X-Google-Smtp-Source: APXvYqzG+Aizi37KNneT5BKPctOXy7XxKieQEqxTXUnZ1RIAKBKWgVgrbZPjEPhhjc8yiX2zn42W X-Received: by 2002:ac8:33c3:: with SMTP id d3mr29864558qtb.41.1567596248652; Wed, 04 Sep 2019 04:24:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567596248; cv=none; d=google.com; s=arc-20160816; b=FuxJW/bFZzckd9F6uEzJbx7kDm9CEkNyCzzwHKriF/4YRfSmdQuUoZYhQtqHrUVDQU dKFJi85rWbVT70ryalec/qeCgzyKbr4+SjfX+HuiJcsw9miknd5fpzzD0IO6hqQuusFm uBOYpA4TBeQhBmKgfeFnMMNK9DaT6wvsg6Ro32LqgqGynQB+1ctDMg0Jm1Tb+L+5cvrs ojq0DLLWLjKEI8elzmbVBYm+RFDckm3BF1iqdZxoSgJhCK65CIH2c+kIY788MH7+qDo1 JhzZwy7pWaR0L7MVnVywqFHTVYKqpYOQZX0PFyCiCRdZSeWC7g6Ud4VF6OdQPXmBCVuP Gd+w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=HTKrWQY9yW6MYIS8zgDhcyDleaXQJ6g1pyLY7/mvmEw=; b=SSw/T06zuqfIlQKckDuOCXS1KCGqFg71gJXC3XA9XsWZ/ZSCU6M12bKOLAOPwsrYI0 F6buDmDEz4TrCFeNwVSTsVPZp8kc40szQTCXURRtLwva9UaZ5zN4YIIRx4SamUBGMrHc YAyIsyz/vcsw0blkClCWpnxqty9jjawDAmKNidvpliAweAi2tC/g/tekd06xOxh6Taa7 Nv2sXhnuj8r6d0NJ9zTQ/7uxOchNQO2ysYPrqMT54tFMESYupYAaaQ5tXmkJXwUT+Hj9 O4ZqXxVIPt34NEsorsFwKkMfOeLYLpQmcNmP8YiwC2yFYzD8Z2n3vpqjUcdWlFqL9z8D T32A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=c0iTk3h8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id y30si14063756qve.167.2019.09.04.04.24.08 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 04 Sep 2019 04:24:08 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=c0iTk3h8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:56264 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5TOS-0001Lw-6F for patch@linaro.org; Wed, 04 Sep 2019 07:24:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36527) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5TLh-00076e-3X for qemu-devel@nongnu.org; Wed, 04 Sep 2019 07:21:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i5TLe-0007Fl-Ma for qemu-devel@nongnu.org; Wed, 04 Sep 2019 07:21:16 -0400 Received: from mail-wr1-x441.google.com ([2a00:1450:4864:20::441]:33083) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i5TLd-0007DS-V6 for qemu-devel@nongnu.org; Wed, 04 Sep 2019 07:21:14 -0400 Received: by mail-wr1-x441.google.com with SMTP id u16so20841823wrr.0 for ; Wed, 04 Sep 2019 04:21:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HTKrWQY9yW6MYIS8zgDhcyDleaXQJ6g1pyLY7/mvmEw=; b=c0iTk3h8iuUJigERyboXNR8krGbUfi2N/BJbQAAqiN2gVHFbxSzQ1aZiU08kNEoWy8 4a2eHIIl8eK7TlwnW3bXUEu5P+iN3HoADHWKk4LYy8QXzYVrZG3bzeP1Y8HDPjGMlneT 1Q/P4UfhWTvUOzoDmmexTdCZ0lIBsOvjN5gjcyTYdCVr0Frb78YCp+3yf+AccB36cAOE cKpg/lMJYT1PkYa6qij15ENcHl8kWD61TmlanUFgDgmeT313jq/3OONETde3sA+uTgQ4 Jh2fm9KgYA/eFY/YcMwzRp32NCXG/qDXiZSKsCp4ZyhKGX2/FnHs6zbnsGcWreqizfXX un2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HTKrWQY9yW6MYIS8zgDhcyDleaXQJ6g1pyLY7/mvmEw=; b=ITh4QnGPFj0Oy/kWELjGV+nHiHRsGOVVDk30v0o9UTANm6neJ+UecI6OzogaKftTcM VX6xu2XbHyWdlOfUIjkTqGLcnzpPnqx0M4FvaX04EL6dvzMGK1XSeDZMp5ILaWNV91Xy FRx3yqOMbagT6c133wTW2epUJrCbfNNx0zH267RioFt3MIeyY2X1uABICC1a/x6wTDDs CS/zsm4a0yJgaD7nkgKT5FLBEGGoeL8NLdOiqRkJCtm/GBOY/TGPEIO6ZbWcOlPSj8O+ AnTWSzeZ6PSBwMP7hM8IriMkMrbn00qfqzHn7FEQnNDtt2ITdCNlNVPJ7hVZnU4TCEVA WMZg== X-Gm-Message-State: APjAAAU4c/bRjNJRnL9J9CgH6I80d8FgKitNySa7TBnydmv1Ft2CH82x swyUMUkFvnbQiSKCtGzyb17vHegJVyQ= X-Received: by 2002:a5d:5606:: with SMTP id l6mr20200805wrv.108.1567596072636; Wed, 04 Sep 2019 04:21:12 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id n12sm2582678wmc.24.2019.09.04.04.21.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 04:21:10 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 4E1AF1FF90; Wed, 4 Sep 2019 12:21:09 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:21:06 +0100 Message-Id: <20190904112108.2341-4-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190904112108.2341-1-alex.bennee@linaro.org> References: <20190904112108.2341-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 Subject: [Qemu-devel] [PATCH v2 3/5] target/arm: handle A-profile A32 semihosting at translate time X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" As for the other semihosting calls we can resolve this at translate time. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- v2 - update for change to gen_exception_internal_insn API --- target/arm/translate.c | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) -- 2.20.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 673994ed1a1..03396a1dde3 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7683,6 +7683,22 @@ static void arm_skip_unless(DisasContext *s, uint32_t cond) arm_gen_test_cc(cond ^ 1, s->condlabel); } +static inline void gen_arm_swi(DisasContext *s, int imm24) +{ + if (semihosting_enabled() && +#ifndef CONFIG_USER_ONLY + s->current_el != 0 && +#endif + (imm24 == 0x123456)) { + gen_exception_internal_insn(s, s->base.pc_next, EXCP_SEMIHOST); + return; + } + + gen_set_pc_im(s, s->base.pc_next); + s->svc_imm = imm24; + s->base.is_jmp = DISAS_SWI; +} + static void disas_arm_insn(DisasContext *s, unsigned int insn) { unsigned int cond, val, op1, i, shift, rm, rs, rn, rd, sh; @@ -9230,9 +9246,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) break; case 0xf: /* swi */ - gen_set_pc_im(s, s->base.pc_next); - s->svc_imm = extract32(insn, 0, 24); - s->base.is_jmp = DISAS_SWI; + gen_arm_swi(s, extract32(insn, 0, 24)); break; default: illegal_op: From patchwork Wed Sep 4 11:21:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 172921 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp1095400ily; Wed, 4 Sep 2019 04:25:56 -0700 (PDT) X-Google-Smtp-Source: APXvYqwidQdCuOV+0s4gJx23/f4gYNk5voKyxkgnyG3KXFSbMyEoTZw5ZknMmDl79Xb5NmVfYfSy X-Received: by 2002:ac8:614c:: with SMTP id d12mr38670176qtm.178.1567596356037; Wed, 04 Sep 2019 04:25:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567596356; cv=none; d=google.com; s=arc-20160816; b=LYgs/wRfuBmLwJuNKO4eMbmD1J3fOeTtyLH9WAZvedWrkf8co+Ez5EVE86NKuKZqBT +gCsJEe4lOgyXdTGpaOX8YHnVWK5CmOt61mb96db0qqpSMFznSrysBuxZGRp4JTIp/94 UZq+8oMkKEFuEHEWx7YxdGJVUZg2Th+Dv82M8eVytc7F8qKe80jPju61MYIk4uIl4/0y MunGU7KGhGt2HD2ru8ABwDB6AC56+hRJg9/4cbR2jlJz/2zpFcgRXKYHJSiPSFw5O0FR dpp6Fcws8VA0rgEu0/1hMChybx+rqjVufQQmCNjiC/rBXJmm+DBnTnXwxihCNHsYrPbN E1MA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=zlpCkLPxW/plsVCAFKM/m8fldNY7IYpuz4hZ7EfXmKg=; b=Z1pRyK512nuyAVBB8jZUOoL7/2/s5ZJhARtY+E/Ug/b3hlMIegYWPITl5McIMvFHng gNbN+Nu43nbeyoN27WqCjut50BnJFrg6XuWG3wYKwil+IsXdZsTHOm2J43duvASjPoTe gCS7bPj/x9T4ha6IXIOSoG97ESyQ6EXoBNtVC1idgMJqGY68dfKDQ/bfinMzM1krE9aM DG0cldMKfdOm7e5FGi1TA3yPEHq01zwkyAUCjI3DHMoKbHkOrJKOjqrQW+1Fa1v2PRr4 v67A/LMIbrJKX0Se+bxftWK1KFJTlMqdQdG6F/Zb0KcXHClqN+wNvcAwV8e1oBxm78vd 1Bvw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=eeOTZqfh; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:4864:20::442 Subject: [Qemu-devel] [PATCH v2 4/5] target/arm: remove run time semihosting checks X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Now we do all our checking and use a common EXCP_SEMIHOST for semihosting operations we can make helper code a lot simpler. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- v2 - fix re-base conflicts - hoist EXCP_SEMIHOST check - comment cleanups v5 - move CONFIG_TCG ifdefs --- target/arm/helper.c | 96 +++++++++++---------------------------------- 1 file changed, 22 insertions(+), 74 deletions(-) -- 2.20.1 diff --git a/target/arm/helper.c b/target/arm/helper.c index 507026c9154..a87ae6d46a1 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8339,88 +8339,32 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) new_el, env->pc, pstate_read(env)); } -static inline bool check_for_semihosting(CPUState *cs) -{ +/* + * Do semihosting call and set the appropriate return value. All the + * permission and validity checks have been done at translate time. + * + * We only see semihosting exceptions in TCG only as they are not + * trapped to the hypervisor in KVM. + */ #ifdef CONFIG_TCG - /* Check whether this exception is a semihosting call; if so - * then handle it and return true; otherwise return false. - */ +static void handle_semihosting(CPUState *cs) +{ ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; if (is_a64(env)) { - if (cs->exception_index == EXCP_SEMIHOST) { - /* This is always the 64-bit semihosting exception. - * The "is this usermode" and "is semihosting enabled" - * checks have been done at translate time. - */ - qemu_log_mask(CPU_LOG_INT, - "...handling as semihosting call 0x%" PRIx64 "\n", - env->xregs[0]); - env->xregs[0] = do_arm_semihosting(env); - return true; - } - return false; + qemu_log_mask(CPU_LOG_INT, + "...handling as semihosting call 0x%" PRIx64 "\n", + env->xregs[0]); + env->xregs[0] = do_arm_semihosting(env); } else { - uint32_t imm; - - /* Only intercept calls from privileged modes, to provide some - * semblance of security. - */ - if (cs->exception_index != EXCP_SEMIHOST && - (!semihosting_enabled() || - ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR))) { - return false; - } - - switch (cs->exception_index) { - case EXCP_SEMIHOST: - /* This is always a semihosting call; the "is this usermode" - * and "is semihosting enabled" checks have been done at - * translate time. - */ - break; - case EXCP_SWI: - /* Check for semihosting interrupt. */ - if (env->thumb) { - imm = arm_lduw_code(env, env->regs[15] - 2, arm_sctlr_b(env)) - & 0xff; - if (imm == 0xab) { - break; - } - } else { - imm = arm_ldl_code(env, env->regs[15] - 4, arm_sctlr_b(env)) - & 0xffffff; - if (imm == 0x123456) { - break; - } - } - return false; - case EXCP_BKPT: - /* See if this is a semihosting syscall. */ - if (env->thumb) { - imm = arm_lduw_code(env, env->regs[15], arm_sctlr_b(env)) - & 0xff; - if (imm == 0xab) { - env->regs[15] += 2; - break; - } - } - return false; - default: - return false; - } - qemu_log_mask(CPU_LOG_INT, "...handling as semihosting call 0x%x\n", env->regs[0]); env->regs[0] = do_arm_semihosting(env); - return true; } -#else - return false; -#endif } +#endif /* Handle a CPU exception for A and R profile CPUs. * Do any appropriate logging, handle PSCI calls, and then hand off @@ -8451,13 +8395,17 @@ void arm_cpu_do_interrupt(CPUState *cs) return; } - /* Semihosting semantics depend on the register width of the - * code that caused the exception, not the target exception level, - * so must be handled here. + /* + * Semihosting semantics depend on the register width of the code + * that caused the exception, not the target exception level, so + * must be handled here. */ - if (check_for_semihosting(cs)) { +#ifdef CONFIG_TCG + if (cs->exception_index == EXCP_SEMIHOST) { + handle_semihosting(cs); return; } +#endif /* Hooks may change global state so BQL should be held, also the * BQL needs to be held for any modification of From patchwork Wed Sep 4 11:21:08 2019 Content-Type: text/plain; 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X-Received-From: 2a00:1450:4864:20::42e Subject: [Qemu-devel] [PATCH v2 5/5] atomic_template: fix indentation in GEN_ATOMIC_HELPER X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , "Emilio G. Cota" , qemu-arm@nongnu.org, Paolo Bonzini , =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: "Emilio G. Cota" Reviewed-by: Alex Bennée Signed-off-by: Emilio G. Cota Reviewed-by: Richard Henderson Signed-off-by: Alex Bennée --- accel/tcg/atomic_template.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.20.1 diff --git a/accel/tcg/atomic_template.h b/accel/tcg/atomic_template.h index df9c8388178..287433d809b 100644 --- a/accel/tcg/atomic_template.h +++ b/accel/tcg/atomic_template.h @@ -149,7 +149,7 @@ ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, target_ulong addr, #define GEN_ATOMIC_HELPER(X) \ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr, \ - ABI_TYPE val EXTRA_ARGS) \ + ABI_TYPE val EXTRA_ARGS) \ { \ ATOMIC_MMU_DECLS; \ DATA_TYPE *haddr = ATOMIC_MMU_LOOKUP; \