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Note that the current bindings only document the SoC (armada380, armada385, armada388). This is undesirable, instead there should be entries for actual boards. For now only convert to yaml, the content can be corrected separately. Signed-off-by: Josua Mayer --- .../devicetree/bindings/arm/marvell/armada-38x.txt | 27 ------------------ .../bindings/arm/marvell/armada-38x.yaml | 33 ++++++++++++++++++++++ 2 files changed, 33 insertions(+), 27 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/marvell/armada-38x.txt b/Documentation/devicetree/bindings/arm/marvell/armada-38x.txt deleted file mode 100644 index 202953f1887e..000000000000 --- a/Documentation/devicetree/bindings/arm/marvell/armada-38x.txt +++ /dev/null @@ -1,27 +0,0 @@ -Marvell Armada 38x Platforms Device Tree Bindings -------------------------------------------------- - -Boards with a SoC of the Marvell Armada 38x family shall have the -following property: - -Required root node property: - - - compatible: must contain "marvell,armada380" - -In addition, boards using the Marvell Armada 385 SoC shall have the -following property before the previous one: - -Required root node property: - -compatible: must contain "marvell,armada385" - -In addition, boards using the Marvell Armada 388 SoC shall have the -following property before the previous one: - -Required root node property: - -compatible: must contain "marvell,armada388" - -Example: - -compatible = "marvell,a385-rd", "marvell,armada385", "marvell,armada380"; diff --git a/Documentation/devicetree/bindings/arm/marvell/armada-38x.yaml b/Documentation/devicetree/bindings/arm/marvell/armada-38x.yaml new file mode 100644 index 000000000000..5af222e6db18 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/marvell/armada-38x.yaml @@ -0,0 +1,33 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/marvell/armada-38x.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Armada 38x Platforms + +maintainers: + - Gregory CLEMENT + +properties: + $nodename: + const: '/' + compatible: + oneOf: + + - description: Armada 380 SoC + items: + - const: marvell,armada380 + + - description: Armada 385 SoC + items: + - const: marvell,armada385 + - const: marvell,armada380 + + - description: Armada 388 SoC + items: + - const: marvell,armada388 + - const: marvell,armada385 + - const: marvell,armada380 + +additionalProperties: true From patchwork Tue Dec 26 18:11:34 2023 Content-Type: text/plain; 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There are already 3 distinct dts in tree for these *two* boards, declaring particular compatible strings: - armada-388-clearfog.dts: compatible = "solidrun,clearfog-a1", "marvell,armada388", "marvell,armada385, "marvell,armada380"; - armada-388-clearfog-base.dts: compatible = "solidrun,clearfog-base-a1", "solidrun,clearfog-a1", "marvell,armada388", "marvell,armada385, "marvell,armada380"; - armada-388-clearfog-pro.dts: compatible = "solidrun,clearfog-base-a1", "solidrun,clearfog-a1", "marvell,armada388", "marvell,armada385, "marvell,armada380"; This has historic reasons, the first entry is a legacy name for the "pro" version, old versions of u-boot built when only one variant existed explicitly boot by this name. Note that both compatibles and model field include the string "A1". At least up to revision 2.0 of the board, this had been printed on the pcb. However in marketing material and conversations it is usually omitted. "Clearfog Pro" and "Clearfog Pro A1" always mean exactly the same product. Technically Base and Pro variants are similar enough that they can successfully boot with each other's dts. Hence it makes (some) sense for them to share the "clearfog-a1" compatible. Add bindings for the explicit variants including base / pro suffix. The legacy "armada-388-clearfog.dts" is not supported by these bindings" as it does not make sense having two bindings for one board. Signed-off-by: Josua Mayer --- .../devicetree/bindings/arm/marvell/armada-38x.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/marvell/armada-38x.yaml b/Documentation/devicetree/bindings/arm/marvell/armada-38x.yaml index 5bc69c4fe34d..f77976138bb3 100644 --- a/Documentation/devicetree/bindings/arm/marvell/armada-38x.yaml +++ b/Documentation/devicetree/bindings/arm/marvell/armada-38x.yaml @@ -38,4 +38,16 @@ properties: - const: marvell,armada385 - const: marvell,armada380 + - description: + SolidRun Armada 388 based single-board computers + + items: + - enum: + - solidrun,clearfog-base-a1 + - solidrun,clearfog-pro-a1 + - const: solidrun,clearfog-a1 + - const: marvell,armada388 + - const: marvell,armada385 + - const: marvell,armada380 + additionalProperties: true From patchwork Tue Dec 26 18:11:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Josua Mayer X-Patchwork-Id: 758426 Received: from EUR05-DB8-obe.outbound.protection.outlook.com (mail-db8eur05on2068.outbound.protection.outlook.com [40.107.20.68]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4D9E353E05; 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DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?q?BAtb9o6M0RjJgkexVZmXn00Dg1n3?= =?utf-8?q?tmYbHSrXBRF0U2eVPvlyDGpliwzWMF1DOEwvWcj1wgCnrB0ZrF3K69mCtt3bZy7xC?= =?utf-8?q?l1PtO5y9yR0Vvg2meBTvyVy0MVPE07HmLGhUqjKUQ+k3f97UvnsnzrmSqLZt9Cw85?= =?utf-8?q?vksAZ/GV9RcwfKsn3jlOo1RGbyvQyjM+qsQ/lBaSE0btWU5XXtqyXKW1dcVybpAAX?= =?utf-8?q?5tl8Dgrn2LiCpnuB02TBq4Il0Kd0WXUB9xj6e7Z7iQVp9KW8EDpPCdo/eUZ+41LNC?= =?utf-8?q?PZKQ6xe++itCvl1JzHwCQTk9eNpG4JgRl0UwAj+nFdxeIlOIfm75bhT+/IIj4ocuD?= =?utf-8?q?PJVO83otmepCTa4Ofda0jm2NCyXZRPYT1TOKq9Dnty155DUTi6imCUUvJwYiiqoHp?= =?utf-8?q?C13MQXzWVz4U6RwJkSAQrEqTqoMzQ9m3XRfanWdhDJyqsb/cR0Xs7dr3fOfiWP3U6?= =?utf-8?q?65aK0MsRLlWb0sK+OBrsS0OnEnuDdVcnZb03DFo5tYNnadYIdyKSMIgRJzIu/qjLv?= =?utf-8?q?x6Dg0BOh1EqQua1CzrYv5e7WR1nyrv3fE8oLkI4S48jnQhu+C9nk66ZZo8pPVdFbz?= =?utf-8?q?rju7bJlH/EWRIF4JovV1BCYR0iA6nJ77G0eQ2lDwMO6VqO3iaY0LwCmPFmK9Rxujp?= =?utf-8?q?ygoFjlE8vZjE7gOB9DY93itEc6hEMB3oWHGHQb4dC0b8/6VPN61cjSPcdhpAlXE+j?= =?utf-8?q?Xsul2Ev3D5nft4hrRRtX87AhYgm20vjdJe3rZGMwrEjYKoxmxH/xzb5i5IoSyuon1?= =?utf-8?q?wYzSF+s+Qb+aVOOA10p3mHcAEFE80vXjOEEzny4uBkDIiYPtM3Vt3YOHPN0XgiEt+?= =?utf-8?q?NbFCgiATyw1QyuMFkXvNqfBcVffxteyuyxjR0Wf1oOfTaJd8w19xIaX5GMGKKC3Px?= =?utf-8?q?ZmnIAflBPQzB00YG4yZKofnfo4cHhEQUoTW2ktEMtjsVnc7KqwgVQbIgpxnblfRF6?= =?utf-8?q?Z2TrMlkYcMRWxk7a3cKhz3YBEKIY+joWBwk8V0yAg+PWQ67PAUYxIw7ID9oN5a2Tk?= =?utf-8?q?7Iz/h2psFf1PnI4nf1RnmbcpS0BEgo79iIwVyTvmGmBiiYYPFdlUovkv2e+zN9Ll4?= =?utf-8?q?3hVPJJWYCnNxFWNuO2OLnDUxvyu0Ttxib26cW4bfc/kqW/MrHqNFV13uKvFPfW4yt?= =?utf-8?q?ZHNnjJeiWgOn3fG4/31ZZ3rR46qYszfXfJnToy+ZkBxk1lq0NvGja6UPOdByeBTBf?= =?utf-8?q?XfiVLCbNEdZR5BXcUBvvVMJjn/CJCFmllooHRJ8OhqxBMAstSB94Mo4IXmwVnJXrp?= =?utf-8?q?LCsNYaUQSwsLXPtZWK6vZppRh4mwZUXGJXo5h1zKy7C58hKXd4Jy06hxsnuU8TQzz?= =?utf-8?q?K01wilAYJlPX8Smzf3tXypT6TscQAmgZFo7wOYy5ATRPMc/LFH/LAzhnSDPWWort/?= =?utf-8?q?mMRl+2tbi3TR9A2THQjhUzffvdvJj4pktbOjc0AzVFWnasFs1Dszdq96hlYY/E2U8?= =?utf-8?q?Chr2UBcHxlHoHhWuwFwtPMdHKrbEFCVryOZdjsQwVn2gPJxDlD1qPsSKA12pmIF1W?= =?utf-8?q?DXRYDlFjywpV?= X-OriginatorOrg: solid-run.com X-MS-Exchange-CrossTenant-Network-Message-Id: 164ab316-89f9-4e86-2221-08dc063e234b X-MS-Exchange-CrossTenant-AuthSource: AS8PR04MB8963.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Dec 2023 18:11:53.0633 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: a4a8aaf3-fd27-4e27-add2-604707ce5b82 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: PDynqOqrvJ5OI6RgxxO2RD3HFCXNpkI6WSIg4ZM412jnMuKQHOkEenfb42+uLP3L1HJysa7O3Y4tAYUDLg7ABQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9PR04MB9868 Most arm board have a board-specific compatible string that allows e.g. userspace to match specific firmware variants or apply specific policies. Add board-specific properties to both variants of the Clearfog GTR: - solidrun,clearfog-gtr-l8 - solidrun,clearfog-gtr-s4 Introduction of a common parent (e.g. "solidrun,clearfog-gtr") is omitted for brevity. Since announcement of the two products no additional variants were added it is assumed that there will always be just two. Signed-off-by: Josua Mayer --- arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-l8.dts | 2 ++ arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-s4.dts | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-l8.dts b/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-l8.dts index 1990f7d0cc79..cd5b070f1218 100644 --- a/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-l8.dts +++ b/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-l8.dts @@ -4,6 +4,8 @@ / { model = "SolidRun Clearfog GTR L8"; + compatible = "solidrun,clearfog-gtr-l8", "marvell,armada385", + "marvell,armada380"; }; &mdio { diff --git a/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-s4.dts b/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-s4.dts index b795ad573891..4a9736ec99b6 100644 --- a/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-s4.dts +++ b/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-s4.dts @@ -4,6 +4,8 @@ / { model = "SolidRun Clearfog GTR S4"; + compatible = "solidrun,clearfog-gtr-s4", "marvell,armada385", + "marvell,armada380"; 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Since U-Boot is shared between multiple board variants, i.e. a388 clearfog pro / base, clearfog gtr l8 / s4, it is better to explicitly configure functions. Add explicit pinctrl entries for all gpios currently in use. Additionally the loss-of-signal gpio specified is invalid, in fact los only has a pull-up on the board but no gpio connection to the cpu. Remove this stray reference. Signed-off-by: Josua Mayer --- .../boot/dts/marvell/armada-385-clearfog-gtr.dtsi | 42 ++++++++++++++++++++-- 1 file changed, 39 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr.dtsi b/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr.dtsi index 8eabb60765b0..39ac97edb463 100644 --- a/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr.dtsi +++ b/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr.dtsi @@ -162,6 +162,22 @@ cf_gtr_isolation_pins: cf-gtr-isolation-pins { marvell,function = "gpio"; }; + cf_gtr_led_pins: led-pins { + marvell,pins = "mpp42", "mpp52"; + marvell,function = "gpio"; + }; + + cf_gtr_lte_disable_pins: lte-disable-pins { + marvell,pins = "mpp34"; + marvell,function = "gpio"; + }; + + cf_gtr_pci_pins: pci-pins { + // pci reset + marvell,pins = "mpp33", "mpp35", "mpp44"; + marvell,function = "gpio"; + }; + cf_gtr_poe_reset_pins: cf-gtr-poe-reset-pins { marvell,pins = "mpp48"; marvell,function = "gpio"; @@ -179,6 +195,12 @@ cf_gtr_sdhci_pins: cf-gtr-sdhci-pins { marvell,function = "sd0"; }; + cf_gtr_sfp0_pins: sfp0-pins { + /* sfp modabs, txdisable */ + marvell,pins = "mpp25", "mpp46"; + marvell,function = "gpio"; + }; + cf_gtr_spi1_cs_pins: spi1-cs-pins { marvell,pins = "mpp59"; marvell,function = "spi1"; @@ -193,6 +215,11 @@ cf_gtr_usb3_con_vbus: cf-gtr-usb3-con-vbus { marvell,pins = "mpp22"; marvell,function = "gpio"; }; + + cf_gtr_wifi_disable_pins: wifi-disable-pins { + marvell,pins = "mpp30", "mpp31"; + marvell,function = "gpio"; + }; }; sdhci@d8000 { @@ -221,21 +248,26 @@ usb3@f8000 { }; pcie { + pinctrl-0 = <&cf_gtr_pci_pins>; + pinctrl-names = "default"; status = "okay"; /* * The PCIe units are accessible through * the mini-PCIe connectors on the board. */ + /* CON3 - serdes 0 */ pcie@1,0 { reset-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; status = "okay"; }; + /* CON4 - serdes 2 */ pcie@2,0 { reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; status = "okay"; }; + /* CON2 - serdes 4 */ pcie@3,0 { reset-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; status = "okay"; @@ -243,10 +275,12 @@ pcie@3,0 { }; }; + /* CON5 */ sfp0: sfp { compatible = "sff,sfp"; + pinctrl-0 = <&cf_gtr_sfp0_pins>; + pinctrl-names = "default"; i2c-bus = <&i2c1>; - los-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>; mod-def0-gpio = <&gpio0 25 GPIO_ACTIVE_LOW>; tx-disable-gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; }; @@ -273,6 +307,8 @@ button-1 { gpio-leds { compatible = "gpio-leds"; + pinctrl-0 = <&cf_gtr_led_pins>; + pinctrl-names = "default"; led1 { function = LED_FUNCTION_CPU; @@ -408,7 +444,7 @@ &ahci1 { }; &gpio0 { - pinctrl-0 = <&cf_gtr_fan_pwm>; + pinctrl-0 = <&cf_gtr_fan_pwm &cf_gtr_wifi_disable_pins>; pinctrl-names = "default"; wifi-disable { @@ -420,7 +456,7 @@ wifi-disable { }; &gpio1 { - pinctrl-0 = <&cf_gtr_isolation_pins &cf_gtr_poe_reset_pins>; + pinctrl-0 = <&cf_gtr_isolation_pins &cf_gtr_poe_reset_pins &cf_gtr_lte_disable_pins>; pinctrl-names = "default"; lte-disable { From patchwork Tue Dec 26 18:11:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Josua Mayer X-Patchwork-Id: 758424 Received: from EUR05-DB8-obe.outbound.protection.outlook.com (mail-db8eur05on2068.outbound.protection.outlook.com [40.107.20.68]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C1F6754BD1; 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The "lan" ports on the 8-port switch in device-tree were numbered in reverse wrt. enclosure. Update all device-tree labels to match. Signed-off-by: Josua Mayer --- arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-l8.dts | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-l8.dts b/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-l8.dts index 2df388f222ec..da6981677b03 100644 --- a/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-l8.dts +++ b/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-l8.dts @@ -32,49 +32,49 @@ ports { port@1 { reg = <1>; - label = "lan8"; + label = "lan1"; phy-handle = <&switch0phy0>; }; port@2 { reg = <2>; - label = "lan7"; + label = "lan2"; phy-handle = <&switch0phy1>; }; port@3 { reg = <3>; - label = "lan6"; + label = "lan3"; phy-handle = <&switch0phy2>; }; port@4 { reg = <4>; - label = "lan5"; + label = "lan4"; phy-handle = <&switch0phy3>; }; port@5 { reg = <5>; - label = "lan4"; + label = "lan5"; phy-handle = <&switch0phy4>; }; port@6 { reg = <6>; - label = "lan3"; + label = "lan6"; phy-handle = <&switch0phy5>; }; port@7 { reg = <7>; - label = "lan2"; + label = "lan7"; phy-handle = <&switch0phy6>; }; port@8 { reg = <8>; - label = "lan1"; + label = "lan8"; phy-handle = <&switch0phy7>; };