From patchwork Wed Dec 27 22:28:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 758477 Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2ED744988C for ; Wed, 27 Dec 2023 22:28:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="yH2Gd9ys" Received: by mail-wm1-f45.google.com with SMTP id 5b1f17b1804b1-40d2e5e8d1dso68137225e9.0 for ; Wed, 27 Dec 2023 14:28:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1703716112; x=1704320912; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=JWBf1IzDI4te1Z7yJaMLFE48TcXMDUCVA44V+FdpVh4=; b=yH2Gd9yskgZMRRwSw8ak+G4cdUbiIE0tBLQSDLz03v8ILNkDUI3a5US1Do2G6vPcQL 2fivac16cWoQn3D7IHvUJw6OvA1PH9fe+0Z5lIsZ4VlkKB1B4Pscrn+KsY/JhQjF73di oHjSsrBAQf3Wx3b82cdpTJgbekWD3jV7+0cY2fKvDPhPDoAuewOmeafholg/5yYoT8ZT 11y9EMvIpyFbuzPNlyHWilFhSSBvtxMQSOO0QCiZGjx+ZlewcOgzJ1cxBRlz7pZq61gB 1Y1bOzHDXOdAeDJAe5flDoARjOVsrBqvtRuySpwSGGeN5UALHiGoPK+Kv9xh99sNP8QQ MopA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703716112; x=1704320912; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JWBf1IzDI4te1Z7yJaMLFE48TcXMDUCVA44V+FdpVh4=; b=CUiYY4lr3CayTnBT9cku0X6hnIVKA6cw97n1PT+4rlUe5KdMS5MyIUFfZElk9kutyX O+0zqaTo0fNsEUxFzs/aMDhMrM5g+UhYk4m4PucvbGjACRncEQQNfzfbVoBk3jz/T2i5 CShGnNc5jSKY6wpz28eg/mviZ9etvp7qKF7B4+63KeoiH8FYbSaauZ0NG0vXfaU/OPAw 8tsvXi6t23urrrmI5inej6nDNCaTR2f1zjhlhRRA6O5j7T+hmOJ4hKlqygWZDlwf5A6K 2ZCJgtiogKFdXIbJEWZT0dUqAllxv4n/7VOy7PVQF4U9/FCSTBv0L5asAPccP1z2uJM1 jLqQ== X-Gm-Message-State: AOJu0YxO3V8VGOlKhWIc37I91NEiY7lq8w4mZbHh9QOOLu6Lv0PLTzpn 5RKve2emkbuFV+RM4oZGrWJnDCia5877EKjhDtUavo7Xoc8= X-Google-Smtp-Source: AGHT+IHbV/5Chz0sLyqxzfmlkvFL4ccOTbdKjsDuBJqfmkah87Uf3n1sasarFyJxfznS5JD8hv9poA== X-Received: by 2002:a7b:cbc5:0:b0:40d:6221:868f with SMTP id n5-20020a7bcbc5000000b0040d6221868fmr186298wmi.279.1703716112496; Wed, 27 Dec 2023 14:28:32 -0800 (PST) Received: from [10.167.154.1] (178235179028.dynamic-4-waw-k-1-3-0.vectranet.pl. [178.235.179.28]) by smtp.gmail.com with ESMTPSA id fb20-20020a1709073a1400b00a26a061ae1esm6854252ejc.97.2023.12.27.14.28.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Dec 2023 14:28:32 -0800 (PST) From: Konrad Dybcio Date: Wed, 27 Dec 2023 23:28:26 +0100 Subject: [PATCH 1/3] arm64: dts: qcom: sc8280xp: Fix PCIe PHY power-domains Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20231227-topic-8280_pcie_dts-v1-1-13d12b1698ff@linaro.org> References: <20231227-topic-8280_pcie_dts-v1-0-13d12b1698ff@linaro.org> In-Reply-To: <20231227-topic-8280_pcie_dts-v1-0-13d12b1698ff@linaro.org> To: Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Johan Hovold Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Konrad Dybcio , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1703716109; l=2255; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=kMvRAvWfpP/DEkU3LU/WsYqL/aUkUp2LCfdAhZy7cI4=; b=on07lEwMe5d6HDnWJbd3ihCw4sDHjf6qoR6QPRX9iQ0Vnh0ruqYLUNj+EZc5bK1Y5UyUQikEE 6Fwi+MxoF+pDhYo9Felu72ulAdl/i+cto7szIDueMCbObm95l0u4r++ X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= The PCIe GDSCs are only related to the RCs. The PCIe PHYs on the other hand, are powered by VDD_MX and their specific VDDA_PHY/PLL regulators. Fix the power-domains assignment to stop potentially toggling the GDSC unnecessarily. Fixes: 813e83157001 ("arm64: dts: qcom: sc8280xp/sa8540p: add PCIe2-4 nodes") Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index febf28356ff8..72c5818b67f2 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -1797,7 +1797,7 @@ pcie4_phy: phy@1c06000 { assigned-clocks = <&gcc GCC_PCIE4_PHY_RCHNG_CLK>; assigned-clock-rates = <100000000>; - power-domains = <&gcc PCIE_4_GDSC>; + power-domains = <&rpmhpd SC8280XP_MX>; resets = <&gcc GCC_PCIE_4_PHY_BCR>; reset-names = "phy"; @@ -1895,7 +1895,7 @@ pcie3b_phy: phy@1c0e000 { assigned-clocks = <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>; assigned-clock-rates = <100000000>; - power-domains = <&gcc PCIE_3B_GDSC>; + power-domains = <&rpmhpd SC8280XP_MX>; resets = <&gcc GCC_PCIE_3B_PHY_BCR>; reset-names = "phy"; @@ -1994,7 +1994,7 @@ pcie3a_phy: phy@1c14000 { assigned-clocks = <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>; assigned-clock-rates = <100000000>; - power-domains = <&gcc PCIE_3A_GDSC>; + power-domains = <&rpmhpd SC8280XP_MX>; resets = <&gcc GCC_PCIE_3A_PHY_BCR>; reset-names = "phy"; @@ -2094,7 +2094,7 @@ pcie2b_phy: phy@1c1e000 { assigned-clocks = <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>; assigned-clock-rates = <100000000>; - power-domains = <&gcc PCIE_2B_GDSC>; + power-domains = <&rpmhpd SC8280XP_MX>; resets = <&gcc GCC_PCIE_2B_PHY_BCR>; reset-names = "phy"; @@ -2193,7 +2193,7 @@ pcie2a_phy: phy@1c24000 { assigned-clocks = <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>; assigned-clock-rates = <100000000>; - power-domains = <&gcc PCIE_2A_GDSC>; + power-domains = <&rpmhpd SC8280XP_MX>; resets = <&gcc GCC_PCIE_2A_PHY_BCR>; reset-names = "phy"; From patchwork Wed Dec 27 22:28:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 759129 Received: from mail-lf1-f52.google.com (mail-lf1-f52.google.com [209.85.167.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 428E8498B3 for ; Wed, 27 Dec 2023 22:28:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="y/1G+ZkL" Received: by mail-lf1-f52.google.com with SMTP id 2adb3069b0e04-50e80d40a41so2149180e87.1 for ; Wed, 27 Dec 2023 14:28:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1703716114; x=1704320914; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=TOTPntAbgy3PGTrBl7b5lPQZPt4hEISp0YHsUMdQkVM=; b=y/1G+ZkLNtycsSFhItAY+ChHXfVzhDzHBQyyZC7DpRU2ZpViK3G4G4F7uqzcN5BWkq ZLUHSE8dIhTOx7dHWWw6V8d2K/4aPwDVo/KdRg1qe8NX4CHFNMQ9hgnVKZs73FYzTnM5 AjnjpKYKOKnmszsG/IQ5DJS1IYrL3oatfJ073TYxqZdxYiCdfegPVgRvFgTTuMOfv2y8 0rt1L5fgoGGVdfo3lHVWib10iLFmjfNCvXhHFCgichd0kF4vcNSvYcOVd8Xcxbjsbqdt CNFfQmhrEaKJApQSCxkD+rQw9tIHhCTgkmyY4mYSIFiuc36wHj50zDDI4gIBoiko1fPz o89w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703716114; x=1704320914; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TOTPntAbgy3PGTrBl7b5lPQZPt4hEISp0YHsUMdQkVM=; b=RqhOEsOisuSCTwM4mHqFu2bGI0ZBJlfvd8EH62b6J/gWEWmjOZMo+nI31j6YCAif89 535IxusGu9JhK1RPkumZ0kArKU+jxzM73um0ptu/eZjdN2jL0kt3ELIvtvsUZXyPD2Ov k8a68gaz3t01iBrOvbDE6yPI7Xcm0+hJuglMD3qewQCP80jyOnwTg5Mw51HAv4sqdjpZ lWh5jr3tzBFgAXfmMDHtDeL5S7lVIsc41Q/DSooYI74kVoRQ7KV66HauH74RUU0ip6n+ uQh8mgYg/o3QnNZS8gahym46TbRs1kVeOzQSfF4Ovnp/CMHnV84Bva3PWu6mKROJqsry 4/vw== X-Gm-Message-State: AOJu0Yyi2DpLlv21OfNmaa4QSHO+ZMVmGniRxaznS4L59FCeYVqmFG8u 1qUe6v7fZdTPCEFDsfs1Da1j89yocwrjdA== X-Google-Smtp-Source: AGHT+IFxv4uwzP6m/2NhBZ/hQfP7o4P9KB8ewzGheiFQDGEPXlumAnMgjcJYCSm5estmRSaCu+hBkw== X-Received: by 2002:ac2:548b:0:b0:50e:36bc:747a with SMTP id t11-20020ac2548b000000b0050e36bc747amr3788065lfk.128.1703716113720; Wed, 27 Dec 2023 14:28:33 -0800 (PST) Received: from [10.167.154.1] (178235179028.dynamic-4-waw-k-1-3-0.vectranet.pl. [178.235.179.28]) by smtp.gmail.com with ESMTPSA id fb20-20020a1709073a1400b00a26a061ae1esm6854252ejc.97.2023.12.27.14.28.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Dec 2023 14:28:33 -0800 (PST) From: Konrad Dybcio Date: Wed, 27 Dec 2023 23:28:27 +0100 Subject: [PATCH 2/3] arm64: dts: qcom: sc8280xp: Correct USB PHY power domains Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20231227-topic-8280_pcie_dts-v1-2-13d12b1698ff@linaro.org> References: <20231227-topic-8280_pcie_dts-v1-0-13d12b1698ff@linaro.org> In-Reply-To: <20231227-topic-8280_pcie_dts-v1-0-13d12b1698ff@linaro.org> To: Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Johan Hovold Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Konrad Dybcio , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1703716109; l=1965; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=VmfNU1/o30xTIL8Pi0ZpiDYz44NQF133gdGRmB0j+A0=; b=hkt2IT7RGZcKOjV7EFH8npQu9Q5Lojs0lNc697VJjqDjCIZ3m9BCDB/PTok2jUH2kpcYbGaLK HDW9gz58IuoBeaUtaWlu6ytDk67tB1yKYyVUV8yfVqnYEpj03699D7n X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= The USB GDSCs are only related to the controllers. The PHYs on the other hand, are powered by VDD_MX and their specific VDDA_PHY/PLL regulators. Fix the power-domains assignment to stop potentially toggling the GDSC unnecessarily. Fixes: 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform") Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 72c5818b67f2..4b18a0762ca7 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -2597,7 +2597,7 @@ usb_2_qmpphy0: phy@88ef000 { <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>; reset-names = "phy", "phy_phy"; - power-domains = <&gcc USB30_MP_GDSC>; + power-domains = <&rpmhpd SC8280XP_MX>; #clock-cells = <0>; clock-output-names = "usb2_phy0_pipe_clk"; @@ -2621,7 +2621,7 @@ usb_2_qmpphy1: phy@88f1000 { <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>; reset-names = "phy", "phy_phy"; - power-domains = <&gcc USB30_MP_GDSC>; + power-domains = <&rpmhpd SC8280XP_MX>; #clock-cells = <0>; clock-output-names = "usb2_phy1_pipe_clk"; @@ -3109,7 +3109,7 @@ usb_0_qmpphy: phy@88eb000 { <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; clock-names = "aux", "ref", "com_aux", "usb3_pipe"; - power-domains = <&gcc USB30_PRIM_GDSC>; + power-domains = <&rpmhpd SC8280XP_MX>; resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, <&gcc GCC_USB4_DP_PHY_PRIM_BCR>; @@ -3162,7 +3162,7 @@ usb_1_qmpphy: phy@8903000 { <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; clock-names = "aux", "ref", "com_aux", "usb3_pipe"; - power-domains = <&gcc USB30_SEC_GDSC>; + power-domains = <&rpmhpd SC8280XP_MX>; resets = <&gcc GCC_USB3_PHY_SEC_BCR>, <&gcc GCC_USB4_1_DP_PHY_PRIM_BCR>; From patchwork Wed Dec 27 22:28:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 758476 Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D504D49F62 for ; Wed, 27 Dec 2023 22:28:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="Blm0wOcc" Received: by mail-wm1-f49.google.com with SMTP id 5b1f17b1804b1-40d2764c0f2so73759765e9.2 for ; Wed, 27 Dec 2023 14:28:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1703716115; x=1704320915; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=tK6odd1OtAVKiOdlxNNM68RkmR7ig1R/23WAvAxgt60=; b=Blm0wOccePPpXVB8N/zFnmMQWlTFTzPz6sTAkkEgiqXxXmPKrP+2fbPFl7oGOLOHAR ebUAz3GstHQKEVnNNB9JO+w7ddgn2GK2vHld5lvaiBxAohrPUoVcaXS3/AfvJlRlJrEM KqfAjRixns6qGJxb3h933QstokGdXnjiFDxXO+t624vrPvWveSVSPt+uwBULfZHu+rrm ESZvd04UWUr7sjvQLtHn4AhfStrF9dFJU8uhcFmRNfcdyOWD9y8YmJJbeymjXgy3XzdT 4jWle++IjZlmxfOb3ypB9VP89EsgiqWIpZ7dI3qQVxl4L6Sh8nlzj4+GZ15bZdQ/6loH G2Xg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703716115; x=1704320915; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tK6odd1OtAVKiOdlxNNM68RkmR7ig1R/23WAvAxgt60=; b=cDi3I5AZwNBnPF748cEJzP+ljvbp+R7cwz29hq1Au9mC2kkKOkw2Gs6MB1mO2pbxE/ 4kNuQ5NN50Z/iJ4tbohDvZsIUacbKI6QNFg+3TYtoY1oI1a+jZ8fpLETJthiMhTCUhpH 8HMa3kBs5d0MsClxfaGB4Pp+kviMI/bZGQVwTezk8jVOmQq9NRUnYJTukbHtxmSaobDy MS5RWX+WHFAxqd8tQw+lrsP5Je/XQujBUsmSsbTeALExZDKFLsjfjoMhIbs7DBFQ9yWu EM646uwen+WD1DMXw/V+uBvy+x4wfy5+xl0wR1GoKciTzqiTTxPms2gtP4RfIXNvJGNT 7mTQ== X-Gm-Message-State: AOJu0Yw5RQPohiLxAA7RfRf2jJH4A9mMAHrc9jmobcjoeprZGL6FFX0P nCCxBVPNrtU6X/ukx8XYi/m3Ff6sJu9m4A== X-Google-Smtp-Source: AGHT+IEU/XUIqOL++xPi8/jutwJk5h4bHe8DFhWyvqha2kXnhOFAt+AX45R/bH+Cj4w0+Tdtu+nCnQ== X-Received: by 2002:a05:600c:524a:b0:40d:5fe9:b374 with SMTP id fc10-20020a05600c524a00b0040d5fe9b374mr584909wmb.71.1703716115176; Wed, 27 Dec 2023 14:28:35 -0800 (PST) Received: from [10.167.154.1] (178235179028.dynamic-4-waw-k-1-3-0.vectranet.pl. [178.235.179.28]) by smtp.gmail.com with ESMTPSA id fb20-20020a1709073a1400b00a26a061ae1esm6854252ejc.97.2023.12.27.14.28.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Dec 2023 14:28:34 -0800 (PST) From: Konrad Dybcio Date: Wed, 27 Dec 2023 23:28:28 +0100 Subject: [PATCH 3/3] arm64: dts: qcom: sc8280xp-crd: Add PCIe CLKREQ# sleep state Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20231227-topic-8280_pcie_dts-v1-3-13d12b1698ff@linaro.org> References: <20231227-topic-8280_pcie_dts-v1-0-13d12b1698ff@linaro.org> In-Reply-To: <20231227-topic-8280_pcie_dts-v1-0-13d12b1698ff@linaro.org> To: Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Johan Hovold Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Konrad Dybcio , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1703716109; l=3813; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=wNNlr9q+wppYjS6msbjrsQS3RolKg1AY+hca/Z4U7jI=; b=qvq7xUeQksr7Wqrk/el2CPvZx9ZDK+mjMvIO6NWtJvxBebD4JEsJG5MRUsJQywBQ4No1d6d8u drvcG+ZKWDZB+kZyoUxuGcD2bA1JsYUTbQtbPJGX9VjDZf0OxLFEE2c X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= The CLKREQ pin should not be muxed to its active function when the RC is asleep. Add the missing pin sleep states to resolve that. Fixes: d907fe5acbf1 ("arm64: dts: qcom: sc8280xp-crd: enable WiFi controller") Fixes: 17e2ccaf65d1 ("arm64: dts: qcom: sc8280xp-crd: enable SDX55 modem") Fixes: 6a1ec5eca73c ("arm64: dts: qcom: sc8280xp-crd: enable NVMe SSD") Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 78 ++++++++++++++++++++----------- 1 file changed, 51 insertions(+), 27 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts index ffc4406422ae..58c0c2d10cb3 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts @@ -530,8 +530,9 @@ &pcie2a { vddpe-3v3-supply = <&vreg_nvme>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie2a_default>; + pinctrl-0 = <&pcie2a_default>, <&pcie2a_clkreq_default>; + pinctrl-1 = <&pcie2a_default>, <&pcie2a_clkreq_sleep>; + pinctrl-names = "default", "sleep"; status = "okay"; }; @@ -549,8 +550,9 @@ &pcie3a { vddpe-3v3-supply = <&vreg_wwan>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie3a_default>; + pinctrl-0 = <&pcie3a_default>, <&pcie3a_clkreq_default>; + pinctrl-1 = <&pcie3a_default>, <&pcie3a_clkreq_sleep>; + pinctrl-names = "default", "sleep"; status = "okay"; }; @@ -568,8 +570,9 @@ &pcie4 { vddpe-3v3-supply = <&vreg_wlan>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie4_default>; + pinctrl-0 = <&pcie4_default>, <&pcie4_clkreq_default>; + pinctrl-1 = <&pcie4_default>, <&pcie4_clkreq_sleep>; + pinctrl-names = "default", "sleep"; status = "okay"; }; @@ -835,13 +838,6 @@ nvme_reg_en: nvme-reg-en-state { }; pcie2a_default: pcie2a-default-state { - clkreq-n-pins { - pins = "gpio142"; - function = "pcie2a_clkreq"; - drive-strength = <2>; - bias-pull-up; - }; - perst-n-pins { pins = "gpio143"; function = "gpio"; @@ -857,14 +853,21 @@ wake-n-pins { }; }; - pcie3a_default: pcie3a-default-state { - clkreq-n-pins { - pins = "gpio150"; - function = "pcie3a_clkreq"; - drive-strength = <2>; - bias-pull-up; - }; + pcie2a_clkreq_default: pcie2a-clkreq-default-state { + pins = "gpio142"; + function = "pcie2a_clkreq"; + drive-strength = <2>; + bias-pull-up; + }; + + pcie2a_clkreq_sleep: pcie2a-clkreq-sleep-state { + pins = "gpio142"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + pcie3a_default: pcie3a-default-state { perst-n-pins { pins = "gpio151"; function = "gpio"; @@ -880,14 +883,21 @@ wake-n-pins { }; }; - pcie4_default: pcie4-default-state { - clkreq-n-pins { - pins = "gpio140"; - function = "pcie4_clkreq"; - drive-strength = <2>; - bias-pull-up; - }; + pcie3a_clkreq_default: pcie3a-clkreq-default-state { + pins = "gpio150"; + function = "pcie3a_clkreq"; + drive-strength = <2>; + bias-pull-up; + }; + pcie3a_clkreq_sleep: pcie3a-clkreq-sleep-state { + pins = "gpio150"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + pcie4_default: pcie4-default-state { perst-n-pins { pins = "gpio141"; function = "gpio"; @@ -903,6 +913,20 @@ wake-n-pins { }; }; + pcie4_clkreq_default: pcie4-clkreq-default-state { + pins = "gpio140"; + function = "pcie4_clkreq"; + drive-strength = <2>; + bias-pull-up; + }; + + pcie4_clkreq_sleep: pcie4-clkreq-sleep-state { + pins = "gpio140"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + sdc2_default_state: sdc2-default-state { clk-pins { pins = "sdc2_clk";