From patchwork Tue Dec 26 08:08:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiang Yu X-Patchwork-Id: 759141 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7BF614C639; Tue, 26 Dec 2023 08:09:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="ZeITLUr+" Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BQ4x14q023783; Tue, 26 Dec 2023 08:08:56 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id; s=qcppdkim1; bh=c5fduS4p21uD M5qrrybe9DZ+cK1J6aDtDvytzGc52Vs=; b=ZeITLUr+FgPWEVsO9gzc7zeKyPTx n+dasP4iYVHlx1q2pd0omwUrAkK/bbTDGYtxh/9kfvXHC7MXhEliUaT4xocJAoQ3 8YIceo14bBYO7IwcfFkjgNpfevwozado7nTdkWITt7SgjL0ozTY93uQIxCZfnMfg bNmKzVJpZ7NFand7/CY/8ktNmraiXciWXnokwSChLfTP4CgXy2tdmtyZSJm1XFEP JnFDJbBFNzImkmemz8wFKkg0FKoIUiJi44NAc69CNDo6hyTZrAcjrRC4oK8aSqBx KWklKmkrIYQkEj+U4nsShQtqr0AXDK3pNtJXdsySoN5p70EpvOyAxo8KIQ== Received: from aptaippmta01.qualcomm.com (tpe-colo-wan-fw-bordernet.qualcomm.com [103.229.16.4]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3v7gd99393-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 26 Dec 2023 08:08:56 +0000 (GMT) Received: from pps.filterd (APTAIPPMTA01.qualcomm.com [127.0.0.1]) by APTAIPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 3BQ88s2f025373; Tue, 26 Dec 2023 08:08:54 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APTAIPPMTA01.qualcomm.com (PPS) with ESMTP id 3v5rmkdp3e-1; Tue, 26 Dec 2023 08:08:54 +0000 Received: from APTAIPPMTA01.qualcomm.com (APTAIPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 3BQ88sLs025368; Tue, 26 Dec 2023 08:08:54 GMT Received: from cbsp-sh-gv.qualcomm.com (CBSP-SH-gv.ap.qualcomm.com [10.231.249.68]) by APTAIPPMTA01.qualcomm.com (PPS) with ESMTP id 3BQ88rWS025365; Tue, 26 Dec 2023 08:08:54 +0000 Received: by cbsp-sh-gv.qualcomm.com (Postfix, from userid 4098150) id 30C02562E; Tue, 26 Dec 2023 16:08:53 +0800 (CST) From: Qiang Yu To: andersson@kernel.org, konrad.dybcio@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, quic_cang@quicinc.com, quic_mrana@quicinc.com, quic_qianyu@quicinc.com Subject: [PATCH] arm64: dts: qcom: sm8550: Increase supported MSI interrupts. Date: Tue, 26 Dec 2023 16:08:51 +0800 Message-Id: <1703578131-14747-1-git-send-email-quic_qianyu@quicinc.com> X-Mailer: git-send-email 2.7.4 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: vzKoac1a3mDw81xi2B4eDyIjmtm8-aj5 X-Proofpoint-GUID: vzKoac1a3mDw81xi2B4eDyIjmtm8-aj5 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_01,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 lowpriorityscore=0 adultscore=0 priorityscore=1501 clxscore=1011 bulkscore=0 phishscore=0 mlxscore=0 mlxlogscore=324 malwarescore=0 impostorscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312260059 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: On sm8550, synopsys MSI controller supports 256 MSI interrupts. Hence, enable all GIC interrupts required by MSI controller for PCIe0 and PCIe1. Signed-off-by: Qiang Yu --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 24 ++++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index ee1ba5a..80e31fb 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -1713,8 +1713,16 @@ linux,pci-domain = <0>; num-lanes = <2>; - interrupts = ; - interrupt-names = "msi"; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi0", "msi1", "msi2", "msi3", + "msi4", "msi5", "msi6", "msi7"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; @@ -1804,8 +1812,16 @@ linux,pci-domain = <1>; num-lanes = <2>; - interrupts = ; - interrupt-names = "msi"; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi0", "msi1", "msi2", "msi3", + "msi4", "msi5", "msi6", "msi7"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>;