From patchwork Mon Jan 8 18:32:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Davis X-Patchwork-Id: 761645 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D3C9247793; Mon, 8 Jan 2024 18:33:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="tIC3FO5N" Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 408IX5ms041769; Mon, 8 Jan 2024 12:33:05 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1704738785; bh=Gdhx6GMh4rVP3km5x1uoGL2Uoq7UqUUHtltyRBPwCl8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=tIC3FO5NGBdpNDZlL287om+LGb2BYGIgBzpWR4Jj6OVKhN1b5dqIyLqSNRd3Asg27 PYv3+qbzz6maBy2EnNEuv8N8WDCe6hqy8SionOywnJa55CZ2Gmu/CwUGPkD1dzCZ/v emN536JMSU2ovagvBOND/1UjP9UZWTchj78/WjV4= Received: from DFLE111.ent.ti.com (dfle111.ent.ti.com [10.64.6.32]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 408IX5mU022175 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 8 Jan 2024 12:33:05 -0600 Received: from DFLE108.ent.ti.com (10.64.6.29) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 8 Jan 2024 12:33:05 -0600 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 8 Jan 2024 12:33:05 -0600 Received: from lelvsmtp5.itg.ti.com ([10.249.40.136]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 408IX3hA051691; Mon, 8 Jan 2024 12:33:04 -0600 From: Andrew Davis To: Frank Binns , Donald Robson , Matt Coster , "H . Nikolaus Schaller" , Adam Ford , Ivaylo Dimitrov , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , =?utf-8?q?Beno=C3=AEt_Cousson?= , Tony Lindgren , Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Paul Cercueil CC: , , , , , , , Andrew Davis Subject: [PATCH RFC v2 01/11] dt-bindings: gpu: Rename img,powervr to img,powervr-rogue Date: Mon, 8 Jan 2024 12:32:52 -0600 Message-ID: <20240108183302.255055-2-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240108183302.255055-1-afd@ti.com> References: <20240108183302.255055-1-afd@ti.com> Precedence: bulk X-Mailing-List: linux-omap@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Signed-off-by: Andrew Davis --- .../bindings/gpu/{img,powervr.yaml => img,powervr-rogue.yaml} | 4 ++-- MAINTAINERS | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) rename Documentation/devicetree/bindings/gpu/{img,powervr.yaml => img,powervr-rogue.yaml} (91%) diff --git a/Documentation/devicetree/bindings/gpu/img,powervr.yaml b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml similarity index 91% rename from Documentation/devicetree/bindings/gpu/img,powervr.yaml rename to Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml index a13298f1a1827..03a8308b41ae7 100644 --- a/Documentation/devicetree/bindings/gpu/img,powervr.yaml +++ b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml @@ -2,10 +2,10 @@ # Copyright (c) 2023 Imagination Technologies Ltd. %YAML 1.2 --- -$id: http://devicetree.org/schemas/gpu/img,powervr.yaml# +$id: http://devicetree.org/schemas/gpu/img,powervr-rogue.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Imagination Technologies PowerVR and IMG GPU +title: Imagination Technologies PowerVR Rogue and IMG GPUs maintainers: - Frank Binns diff --git a/MAINTAINERS b/MAINTAINERS index fa67e2624723f..5b205795da04e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -10461,7 +10461,7 @@ M: Donald Robson M: Matt Coster S: Supported T: git git://anongit.freedesktop.org/drm/drm-misc -F: Documentation/devicetree/bindings/gpu/img,powervr.yaml +F: Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml F: Documentation/gpu/imagination/ F: drivers/gpu/drm/imagination/ F: include/uapi/drm/pvr_drm.h From patchwork Mon Jan 8 18:32:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Davis X-Patchwork-Id: 761641 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3E56B55E52; Mon, 8 Jan 2024 18:33:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="FWjdeP1C" Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 408IX6FU118807; Mon, 8 Jan 2024 12:33:06 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1704738786; bh=yg38KC2ZKTFR0ScGRWiccjiUlUuHqrkcGMhyumVCTFE=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=FWjdeP1CM2quAtrMyPQL9SmnaBqF9OLzRI4+dQDl+c4Err+eH9yIPuCsMAe/ADM63 6oNONabE0rlS8XYF/TYcHJC36MlEJtAvdUe/pXw2SM/HFk8lExk4si9xR0Y9GHpPNY /OOrDfQP6NXf2HX3yHPgFskKXW3FZ7dW2AWPBLI8= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 408IX6aZ123884 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 8 Jan 2024 12:33:06 -0600 Received: from DFLE114.ent.ti.com (10.64.6.35) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 8 Jan 2024 12:33:06 -0600 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 8 Jan 2024 12:33:06 -0600 Received: from lelvsmtp5.itg.ti.com ([10.249.40.136]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 408IX3hB051691; Mon, 8 Jan 2024 12:33:05 -0600 From: Andrew Davis To: Frank Binns , Donald Robson , Matt Coster , "H . Nikolaus Schaller" , Adam Ford , Ivaylo Dimitrov , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , =?utf-8?q?Beno=C3=AEt_Cousson?= , Tony Lindgren , Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Paul Cercueil CC: , , , , , , , Andrew Davis Subject: [PATCH RFC v2 02/11] dt-bindings: gpu: Add PowerVR Series5 SGX GPUs Date: Mon, 8 Jan 2024 12:32:53 -0600 Message-ID: <20240108183302.255055-3-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240108183302.255055-1-afd@ti.com> References: <20240108183302.255055-1-afd@ti.com> Precedence: bulk X-Mailing-List: linux-omap@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 The Imagination PowerVR Series5 "SGX" GPU is part of several SoCs from multiple vendors. Describe how the SGX GPU is integrated in these SoC, including register space and interrupts. Clocks, reset, and power domain information is SoC specific. Signed-off-by: Andrew Davis --- .../bindings/gpu/img,powervr-sgx.yaml | 124 ++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 125 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpu/img,powervr-sgx.yaml diff --git a/Documentation/devicetree/bindings/gpu/img,powervr-sgx.yaml b/Documentation/devicetree/bindings/gpu/img,powervr-sgx.yaml new file mode 100644 index 0000000000000..bb821e1184de9 --- /dev/null +++ b/Documentation/devicetree/bindings/gpu/img,powervr-sgx.yaml @@ -0,0 +1,124 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (c) 2023 Imagination Technologies Ltd. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpu/img,powervr-sgx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Imagination Technologies PowerVR SGX GPUs + +maintainers: + - Frank Binns + +properties: + compatible: + oneOf: + - items: + - enum: + - ti,omap3430-gpu # Rev 121 + - ti,omap3630-gpu # Rev 125 + - const: img,powervr-sgx530 + - items: + - enum: + - ingenic,jz4780-gpu # Rev 130 + - ti,omap4430-gpu # Rev 120 + - const: img,powervr-sgx540 + - items: + - enum: + - allwinner,sun6i-a31-gpu # MP2 Rev 115 + - ti,omap4470-gpu # MP1 Rev 112 + - ti,omap5432-gpu # MP2 Rev 105 + - ti,am5728-gpu # MP2 Rev 116 + - ti,am6548-gpu # MP1 Rev 117 + - const: img,powervr-sgx544 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: true + + clock-names: + minItems: 1 + items: + - const: core + - const: mem + - const: sys + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +allOf: + - if: + properties: + compatible: + contains: + const: ti,am6548-gpu + then: + required: + - power-domains + else: + properties: + power-domains: false + - if: + properties: + compatible: + contains: + enum: + - allwinner,sun6i-a31-gpu + - ingenic,jz4780-gpu + then: + allOf: + - if: + properties: + compatible: + contains: + const: allwinner,sun6i-a31-gpu + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + clock-names: + minItems: 2 + maxItems: 2 + - if: + properties: + compatible: + contains: + const: ingenic,jz4780-gpu + then: + properties: + clocks: + maxItems: 1 + clock-names: + maxItems: 1 + required: + - clocks + - clock-names + else: + properties: + clocks: false + clock-names: false + +examples: + - | + #include + #include + #include + + gpu@7000000 { + compatible = "ti,am6548-gpu", "img,powervr-sgx544"; + reg = <0x7000000 0x10000>; + interrupts = ; + power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 5b205795da04e..00ba13e019fa6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -10462,6 +10462,7 @@ M: Matt Coster S: Supported T: git git://anongit.freedesktop.org/drm/drm-misc F: Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml +F: Documentation/devicetree/bindings/gpu/img,powervr-sgx.yaml F: Documentation/gpu/imagination/ F: drivers/gpu/drm/imagination/ F: include/uapi/drm/pvr_drm.h From patchwork Mon Jan 8 18:32:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Davis X-Patchwork-Id: 760990 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A983955764; Mon, 8 Jan 2024 18:33:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Mon, 8 Jan 2024 12:33:07 -0600 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 8 Jan 2024 12:33:07 -0600 Received: from lelvsmtp5.itg.ti.com ([10.249.40.136]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 408IX3hC051691; Mon, 8 Jan 2024 12:33:06 -0600 From: Andrew Davis To: Frank Binns , Donald Robson , Matt Coster , "H . Nikolaus Schaller" , Adam Ford , Ivaylo Dimitrov , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , =?utf-8?q?Beno=C3=AEt_Cousson?= , Tony Lindgren , Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Paul Cercueil CC: , , , , , , , Andrew Davis Subject: [PATCH RFC v2 03/11] ARM: dts: omap3: Add device tree entry for SGX GPU Date: Mon, 8 Jan 2024 12:32:54 -0600 Message-ID: <20240108183302.255055-4-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240108183302.255055-1-afd@ti.com> References: <20240108183302.255055-1-afd@ti.com> Precedence: bulk X-Mailing-List: linux-omap@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Add SGX GPU device entries to base OMAP3 dtsi files. Signed-off-by: Andrew Davis Reviewed-by: Javier Martinez Canillas --- arch/arm/boot/dts/ti/omap/am3517.dtsi | 11 ++++++----- arch/arm/boot/dts/ti/omap/omap34xx.dtsi | 11 ++++++----- arch/arm/boot/dts/ti/omap/omap36xx.dtsi | 9 +++++---- 3 files changed, 17 insertions(+), 14 deletions(-) diff --git a/arch/arm/boot/dts/ti/omap/am3517.dtsi b/arch/arm/boot/dts/ti/omap/am3517.dtsi index 77e58e686fb17..19aad715dff70 100644 --- a/arch/arm/boot/dts/ti/omap/am3517.dtsi +++ b/arch/arm/boot/dts/ti/omap/am3517.dtsi @@ -162,12 +162,13 @@ sgx_module: target-module@50000000 { clock-names = "fck", "ick"; #address-cells = <1>; #size-cells = <1>; - ranges = <0 0x50000000 0x4000>; + ranges = <0 0x50000000 0x10000>; - /* - * Closed source PowerVR driver, no child device - * binding or driver in mainline - */ + gpu@0 { + compatible = "ti,omap3430-gpu", "img,powervr-sgx530"; + reg = <0x0 0x10000>; /* 64kB */ + interrupts = <21>; + }; }; }; }; diff --git a/arch/arm/boot/dts/ti/omap/omap34xx.dtsi b/arch/arm/boot/dts/ti/omap/omap34xx.dtsi index fc7233ac183a8..acdd0ee34421d 100644 --- a/arch/arm/boot/dts/ti/omap/omap34xx.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap34xx.dtsi @@ -164,12 +164,13 @@ sgx_module: target-module@50000000 { clock-names = "fck", "ick"; #address-cells = <1>; #size-cells = <1>; - ranges = <0 0x50000000 0x4000>; + ranges = <0 0x50000000 0x10000>; - /* - * Closed source PowerVR driver, no child device - * binding or driver in mainline - */ + gpu@0 { + compatible = "ti,omap3430-gpu", "img,powervr-sgx530"; + reg = <0x0 0x10000>; /* 64kB */ + interrupts = <21>; + }; }; }; diff --git a/arch/arm/boot/dts/ti/omap/omap36xx.dtsi b/arch/arm/boot/dts/ti/omap/omap36xx.dtsi index e6d8070c1bf88..c3d79ecd56e39 100644 --- a/arch/arm/boot/dts/ti/omap/omap36xx.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap36xx.dtsi @@ -211,10 +211,11 @@ sgx_module: target-module@50000000 { #size-cells = <1>; ranges = <0 0x50000000 0x2000000>; - /* - * Closed source PowerVR driver, no child device - * binding or driver in mainline - */ + gpu@0 { + compatible = "ti,omap3630-gpu", "img,powervr-sgx530"; + reg = <0x0 0x2000000>; /* 32MB */ + interrupts = <21>; + }; }; }; From patchwork Mon Jan 8 18:32:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Davis X-Patchwork-Id: 761644 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B8F4355786; Mon, 8 Jan 2024 18:33:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="MRE+pV3S" Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 408IX8A9009981; Mon, 8 Jan 2024 12:33:08 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1704738788; bh=IvOnC4lLIEjNUz1mnrO+cPAxILKA9wZcK1lUrScpP9Q=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=MRE+pV3SgTB/edyNUqBzfYck8AeafJwgJVY+aAOHf1SzZ1P2CP7RbJXp3MyGsb4Ez ssQSICwiAFsY/R9m9zx+O5n/1Lcf7isVTX3yXODL6/ShF4dbFm/Z4eBQwiWmvXzAqd STyI67BJFboosy6L4XI40FgkK5RAVdCJfUZM3zL4= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 408IX88X061373 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 8 Jan 2024 12:33:08 -0600 Received: from DFLE105.ent.ti.com (10.64.6.26) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 8 Jan 2024 12:33:08 -0600 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 8 Jan 2024 12:33:08 -0600 Received: from lelvsmtp5.itg.ti.com ([10.249.40.136]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 408IX3hD051691; Mon, 8 Jan 2024 12:33:07 -0600 From: Andrew Davis To: Frank Binns , Donald Robson , Matt Coster , "H . Nikolaus Schaller" , Adam Ford , Ivaylo Dimitrov , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , =?utf-8?q?Beno=C3=AEt_Cousson?= , Tony Lindgren , Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Paul Cercueil CC: , , , , , , , Andrew Davis Subject: [PATCH RFC v2 04/11] ARM: dts: omap4: Add device tree entry for SGX GPU Date: Mon, 8 Jan 2024 12:32:55 -0600 Message-ID: <20240108183302.255055-5-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240108183302.255055-1-afd@ti.com> References: <20240108183302.255055-1-afd@ti.com> Precedence: bulk X-Mailing-List: linux-omap@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Add SGX GPU device entry to base OMAP4 dtsi file. Signed-off-by: Andrew Davis --- arch/arm/boot/dts/ti/omap/omap4.dtsi | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/ti/omap/omap4.dtsi b/arch/arm/boot/dts/ti/omap/omap4.dtsi index 2bbff9032be3e..559b2bfe4ca7c 100644 --- a/arch/arm/boot/dts/ti/omap/omap4.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap4.dtsi @@ -501,10 +501,11 @@ sgx_module: target-module@56000000 { #size-cells = <1>; ranges = <0 0x56000000 0x2000000>; - /* - * Closed source PowerVR driver, no child device - * binding or driver in mainline - */ + gpu@0 { + compatible = "ti,omap4430-gpu", "img,powervr-sgx540"; + reg = <0x0 0x2000000>; /* 32MB */ + interrupts = ; + }; }; /* From patchwork Mon Jan 8 18:32:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Davis X-Patchwork-Id: 760992 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 437CF55799; Mon, 8 Jan 2024 18:33:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="No7B14dK" Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 408IX9Mi118821; Mon, 8 Jan 2024 12:33:09 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1704738789; bh=rD4bivD5C51EnE3KF9h6/z4d298ojSSuekhNSL43VNI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=No7B14dK47ocDvqPFUnEsXekJUOv/ZqLK3aBKm5dfPy456i45wR0jRC1SsBjvaMGI Ep/Prge+GnKhNcoFI5pj/QARtlG1RaSQxtAh0nSAgfC9MTYu/MfHDrcMOK2LjS35S9 /DlG0L4O6gkEW+ItdzfSfPfwEY6xUQC3bWt+TPyo= Received: from DLEE115.ent.ti.com (dlee115.ent.ti.com [157.170.170.26]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 408IX9gC061377 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 8 Jan 2024 12:33:09 -0600 Received: from DLEE112.ent.ti.com (157.170.170.23) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 8 Jan 2024 12:33:09 -0600 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 8 Jan 2024 12:33:09 -0600 Received: from lelvsmtp5.itg.ti.com ([10.249.40.136]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 408IX3hE051691; Mon, 8 Jan 2024 12:33:08 -0600 From: Andrew Davis To: Frank Binns , Donald Robson , Matt Coster , "H . Nikolaus Schaller" , Adam Ford , Ivaylo Dimitrov , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , =?utf-8?q?Beno=C3=AEt_Cousson?= , Tony Lindgren , Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Paul Cercueil CC: , , , , , , , Andrew Davis Subject: [PATCH RFC v2 05/11] ARM: dts: omap5: Add device tree entry for SGX GPU Date: Mon, 8 Jan 2024 12:32:56 -0600 Message-ID: <20240108183302.255055-6-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240108183302.255055-1-afd@ti.com> References: <20240108183302.255055-1-afd@ti.com> Precedence: bulk X-Mailing-List: linux-omap@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Add SGX GPU device entry to base OMAP5 dtsi file. Signed-off-by: Andrew Davis Reviewed-by: Javier Martinez Canillas --- arch/arm/boot/dts/ti/omap/omap5.dtsi | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/ti/omap/omap5.dtsi b/arch/arm/boot/dts/ti/omap/omap5.dtsi index bac6fa8387936..6a66214ad0e2f 100644 --- a/arch/arm/boot/dts/ti/omap/omap5.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap5.dtsi @@ -453,10 +453,11 @@ target-module@56000000 { #size-cells = <1>; ranges = <0 0x56000000 0x2000000>; - /* - * Closed source PowerVR driver, no child device - * binding or driver in mainline - */ + gpu@0 { + compatible = "ti,omap5432-gpu", "img,powervr-sgx544"; + reg = <0x0 0x2000000>; /* 32MB */ + interrupts = ; + }; }; target-module@58000000 { From patchwork Mon Jan 8 18:32:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Davis X-Patchwork-Id: 760993 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E8BB845BFB; Mon, 8 Jan 2024 18:33:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="F+tymD53" Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 408IXA0G041777; Mon, 8 Jan 2024 12:33:10 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1704738790; bh=183/U8yFjhqcv3r3cgkjKf06VYZJwr02E2I/oTrAoLY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=F+tymD53Odf+R0XH9Yi3405CYXjLzF2Yeo6X2iniEqLFWKThv7dLeix8yEBqOqCfJ 6Dc9E4ld+Ln6aLqpJ0abr4kvsaC75JZAdZO4gdkc9iz2QFaTDln3RKHymdqlyBDERa jYIogX9wF8G74kYNOjoHtJfaXAqHe7ekEUEEz604= Received: from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 408IXAXf022380 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 8 Jan 2024 12:33:10 -0600 Received: from DLEE106.ent.ti.com (157.170.170.36) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 8 Jan 2024 12:33:09 -0600 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 8 Jan 2024 12:33:10 -0600 Received: from lelvsmtp5.itg.ti.com ([10.249.40.136]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 408IX3hF051691; Mon, 8 Jan 2024 12:33:09 -0600 From: Andrew Davis To: Frank Binns , Donald Robson , Matt Coster , "H . Nikolaus Schaller" , Adam Ford , Ivaylo Dimitrov , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , =?utf-8?q?Beno=C3=AEt_Cousson?= , Tony Lindgren , Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Paul Cercueil CC: , , , , , , , Andrew Davis Subject: [PATCH RFC v2 06/11] ARM: dts: AM33xx: Add device tree entry for SGX GPU Date: Mon, 8 Jan 2024 12:32:57 -0600 Message-ID: <20240108183302.255055-7-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240108183302.255055-1-afd@ti.com> References: <20240108183302.255055-1-afd@ti.com> Precedence: bulk X-Mailing-List: linux-omap@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Add SGX GPU device entry to base AM33xx dtsi file. Signed-off-by: Andrew Davis Reviewed-by: Javier Martinez Canillas --- arch/arm/boot/dts/ti/omap/am33xx.dtsi | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/ti/omap/am33xx.dtsi b/arch/arm/boot/dts/ti/omap/am33xx.dtsi index 5b9e01a8aa5d5..989d5a6edeed9 100644 --- a/arch/arm/boot/dts/ti/omap/am33xx.dtsi +++ b/arch/arm/boot/dts/ti/omap/am33xx.dtsi @@ -640,10 +640,11 @@ target-module@56000000 { #size-cells = <1>; ranges = <0 0x56000000 0x1000000>; - /* - * Closed source PowerVR driver, no child device - * binding or driver in mainline - */ + gpu@0 { + compatible = "ti,omap3630-gpu", "img,powervr-sgx530"; + reg = <0x0 0x10000>; /* 64kB */ + interrupts = <37>; + }; }; }; }; From patchwork Mon Jan 8 18:32:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Davis X-Patchwork-Id: 761643 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8EACD55C02; Mon, 8 Jan 2024 18:33:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="Q+N/VumY" Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 408IXB3f118827; Mon, 8 Jan 2024 12:33:11 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1704738791; bh=/DHNdb2h/H27I/9d/VEE7PByu6B0S/1IcDh2mFWNTsA=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Q+N/VumYrDVvQrG3H8VtK2FcGaR/oPbAJNQcA3+rxlDGsVvWE3xhwwUYhuDIYFmZ5 VtOz0SgS3mryyHl9xHJBeULWl5+zBYTH9egL72oN/9NHGTxwVwMunQVcG40bNIExos 53uWGNxi7pXSSg2UEkRr90M5HiIQAM2XeeifUSzI= Received: from DFLE109.ent.ti.com (dfle109.ent.ti.com [10.64.6.30]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 408IXBST057389 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 8 Jan 2024 12:33:11 -0600 Received: from DFLE101.ent.ti.com (10.64.6.22) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 8 Jan 2024 12:33:10 -0600 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 8 Jan 2024 12:33:10 -0600 Received: from lelvsmtp5.itg.ti.com ([10.249.40.136]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 408IX3hG051691; Mon, 8 Jan 2024 12:33:09 -0600 From: Andrew Davis To: Frank Binns , Donald Robson , Matt Coster , "H . Nikolaus Schaller" , Adam Ford , Ivaylo Dimitrov , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , =?utf-8?q?Beno=C3=AEt_Cousson?= , Tony Lindgren , Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Paul Cercueil CC: , , , , , , , Andrew Davis Subject: [PATCH RFC v2 07/11] ARM: dts: AM437x: Add device tree entry for SGX GPU Date: Mon, 8 Jan 2024 12:32:58 -0600 Message-ID: <20240108183302.255055-8-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240108183302.255055-1-afd@ti.com> References: <20240108183302.255055-1-afd@ti.com> Precedence: bulk X-Mailing-List: linux-omap@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Add SGX GPU device entry to base AM437x dtsi file. Signed-off-by: Andrew Davis --- arch/arm/boot/dts/ti/omap/am4372.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/ti/omap/am4372.dtsi b/arch/arm/boot/dts/ti/omap/am4372.dtsi index 9d2c064534f7d..5fd1b380ece62 100644 --- a/arch/arm/boot/dts/ti/omap/am4372.dtsi +++ b/arch/arm/boot/dts/ti/omap/am4372.dtsi @@ -719,6 +719,12 @@ target-module@56000000 { #address-cells = <1>; #size-cells = <1>; ranges = <0 0x56000000 0x1000000>; + + gpu@0 { + compatible = "ti,omap3630-gpu", "img,powervr-sgx530"; + reg = <0x0 0x10000>; /* 64kB */ + interrupts = ; + }; }; }; }; From patchwork Mon Jan 8 18:32:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Davis X-Patchwork-Id: 760989 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 129A856B6A; Mon, 8 Jan 2024 18:33:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="KhN99XDn" Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 408IXCGj126863; Mon, 8 Jan 2024 12:33:12 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1704738792; bh=2nMLoHZjmVIC5bz7SNEGOj0N9pS9iZCge0lbcW6Gklw=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=KhN99XDnNgcw3jsBL59qL7fpLl9nPGHgZzCGjOySufVIgwfUbsn2gCTFASCDwTLPX o03qgn2KXtLyapu4MUyhazV+/coAieRkpdXYXtkH+snx59ladhR1/9bWB2TwHHUGok OJNrPWVPLA9fZrXPl2ZPG9S5yV+fwjvfVAsWIxtI= Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 408IXCUk057415 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 8 Jan 2024 12:33:12 -0600 Received: from DFLE107.ent.ti.com (10.64.6.28) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 8 Jan 2024 12:33:11 -0600 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 8 Jan 2024 12:33:11 -0600 Received: from lelvsmtp5.itg.ti.com ([10.249.40.136]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 408IX3hH051691; Mon, 8 Jan 2024 12:33:10 -0600 From: Andrew Davis To: Frank Binns , Donald Robson , Matt Coster , "H . Nikolaus Schaller" , Adam Ford , Ivaylo Dimitrov , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , =?utf-8?q?Beno=C3=AEt_Cousson?= , Tony Lindgren , Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Paul Cercueil CC: , , , , , , , Andrew Davis Subject: [PATCH RFC v2 08/11] ARM: dts: DRA7xx: Add device tree entry for SGX GPU Date: Mon, 8 Jan 2024 12:32:59 -0600 Message-ID: <20240108183302.255055-9-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240108183302.255055-1-afd@ti.com> References: <20240108183302.255055-1-afd@ti.com> Precedence: bulk X-Mailing-List: linux-omap@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Add SGX GPU device entry to base DRA7x dtsi file. Signed-off-by: Andrew Davis Reviewed-by: Javier Martinez Canillas --- arch/arm/boot/dts/ti/omap/dra7.dtsi | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/ti/omap/dra7.dtsi b/arch/arm/boot/dts/ti/omap/dra7.dtsi index 6509c742fb58c..8527643cb69a8 100644 --- a/arch/arm/boot/dts/ti/omap/dra7.dtsi +++ b/arch/arm/boot/dts/ti/omap/dra7.dtsi @@ -850,12 +850,19 @@ target-module@56000000 { ; ti,sysc-sidle = , , - ; + , + ; clocks = <&gpu_clkctrl DRA7_GPU_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x56000000 0x2000000>; + + gpu@0 { + compatible = "ti,am5728-gpu", "img,powervr-sgx544"; + reg = <0x0 0x10000>; /* 64kB */ + interrupts = ; + }; }; crossbar_mpu: crossbar@4a002a48 { From patchwork Mon Jan 8 18:33:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Davis X-Patchwork-Id: 761646 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 95EAA208A0; Mon, 8 Jan 2024 18:33:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="cgq1sizL" Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 408IXDkP041791; Mon, 8 Jan 2024 12:33:13 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1704738793; bh=L0ZN/p9i33lJE43x/uNLzJJqV9lS8X7UChbk/Kn2v8E=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=cgq1sizLi9L9xNPqysc/V6wRjFq2Ehu0MQXUtGhthmuKMshRYvMvMy1XbPwLACBSF qL4+UxLfnTTHBiYE7W8guRr+kZJeNhg9JWSVSEo66xGuwUfLIcYaT6ZQ78F91cBGtd pubW+dut6Ug1hZSGqdH9g/lnv9kGlPVuJARFYDFA= Received: from DFLE113.ent.ti.com (dfle113.ent.ti.com [10.64.6.34]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 408IXDqp123990 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 8 Jan 2024 12:33:13 -0600 Received: from DFLE103.ent.ti.com (10.64.6.24) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 8 Jan 2024 12:33:12 -0600 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 8 Jan 2024 12:33:12 -0600 Received: from lelvsmtp5.itg.ti.com ([10.249.40.136]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 408IX3hI051691; Mon, 8 Jan 2024 12:33:11 -0600 From: Andrew Davis To: Frank Binns , Donald Robson , Matt Coster , "H . Nikolaus Schaller" , Adam Ford , Ivaylo Dimitrov , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , =?utf-8?q?Beno=C3=AEt_Cousson?= , Tony Lindgren , Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Paul Cercueil CC: , , , , , , , Andrew Davis Subject: [PATCH RFC v2 09/11] arm64: dts: ti: k3-am654-main: Add device tree entry for SGX GPU Date: Mon, 8 Jan 2024 12:33:00 -0600 Message-ID: <20240108183302.255055-10-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240108183302.255055-1-afd@ti.com> References: <20240108183302.255055-1-afd@ti.com> Precedence: bulk X-Mailing-List: linux-omap@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Add SGX GPU device entry to base AM654 dtsi file. Signed-off-by: Andrew Davis --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index fcea544656360..64b52c8dafc6c 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -1050,6 +1050,13 @@ dss_ports: ports { }; }; + gpu: gpu@7000000 { + compatible = "ti,am6548-gpu", "img,powervr-sgx544"; + reg = <0x0 0x7000000 0x0 0x10000>; + interrupts = ; + power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>; + }; + ehrpwm0: pwm@3000000 { compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; #pwm-cells = <3>; From patchwork Mon Jan 8 18:33:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Davis X-Patchwork-Id: 760994 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DDF5B38DC3; Mon, 8 Jan 2024 18:33:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="KME0vviq" Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 408IXDoB041796; Mon, 8 Jan 2024 12:33:13 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1704738794; bh=K3M9sI7ldpwxKdZlqbzDASUN2Gy2vGqDMV0YI/zfTo4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=KME0vviqbdcwJlAQ8bWNbObioH1VBKu2jzYv6sic48MxvNnBTDeOtUlPIRWvdytmn 0MOjzIFmD1VMrfQRNjSAJwSIcl7B9VHdiv9N+ZlY7wIa6dtrQqFYhOO+FxpDm0ZOru r0juZZMEEBEg4w89gXIoKG5h4Wicb02AOTBcTJkI= Received: from DFLE108.ent.ti.com (dfle108.ent.ti.com [10.64.6.29]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 408IXD7f022473 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 8 Jan 2024 12:33:13 -0600 Received: from DFLE102.ent.ti.com (10.64.6.23) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 8 Jan 2024 12:33:13 -0600 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 8 Jan 2024 12:33:13 -0600 Received: from lelvsmtp5.itg.ti.com ([10.249.40.136]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 408IX3hJ051691; Mon, 8 Jan 2024 12:33:12 -0600 From: Andrew Davis To: Frank Binns , Donald Robson , Matt Coster , "H . Nikolaus Schaller" , Adam Ford , Ivaylo Dimitrov , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , =?utf-8?q?Beno=C3=AEt_Cousson?= , Tony Lindgren , Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Paul Cercueil CC: , , , , , , , Andrew Davis Subject: [PATCH RFC v2 10/11] ARM: dts: sun6i: Add device tree entry for SGX GPU Date: Mon, 8 Jan 2024 12:33:01 -0600 Message-ID: <20240108183302.255055-11-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240108183302.255055-1-afd@ti.com> References: <20240108183302.255055-1-afd@ti.com> Precedence: bulk X-Mailing-List: linux-omap@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Add SGX GPU device entry to base sun6i-a31 dtsi file. Signed-off-by: Andrew Davis --- arch/arm/boot/dts/allwinner/sun6i-a31.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/allwinner/sun6i-a31.dtsi b/arch/arm/boot/dts/allwinner/sun6i-a31.dtsi index 5cce4918f84c9..e6998783b89aa 100644 --- a/arch/arm/boot/dts/allwinner/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/allwinner/sun6i-a31.dtsi @@ -962,6 +962,15 @@ mdio: mdio { }; }; + gpu: gpu@1c40000 { + compatible = "allwinner,sun6i-a31-gpu", "img,powervr-sgx544"; + reg = <0x01c40000 0x10000>; + interrupts = ; + clocks = <&ccu CLK_GPU_CORE>, <&ccu CLK_GPU_MEMORY>; + clock-names = "core", "mem"; + status = "disabled"; + }; + crypto: crypto-engine@1c15000 { compatible = "allwinner,sun6i-a31-crypto", "allwinner,sun4i-a10-crypto"; From patchwork Mon Jan 8 18:33:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Davis X-Patchwork-Id: 761642 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A529455C09; Mon, 8 Jan 2024 18:33:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="lbQcTlLh" Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 408IXEMq010030; Mon, 8 Jan 2024 12:33:14 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1704738794; bh=PWj0D2WMvRJ11gnfwf0SZ44vgMNZaHz/OZM54jmoFVs=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=lbQcTlLhFLWFWfmynTQ/fLKR5FgIXclptYPQDZ4h6j0pXsN23aLT3bKn3EpSGT1Eh Jy9RaM4+e4Iu3nU9Ph6+pRhRmjuvcL72wjNo7fHO6mq3m09p5cboGlbYWH3QUd5XrV /mOGPr4d+1qObwgPtZ3iRdVNRkimiTeKpXE7KTww= Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 408IXEak124040 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 8 Jan 2024 12:33:14 -0600 Received: from DFLE112.ent.ti.com (10.64.6.33) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 8 Jan 2024 12:33:14 -0600 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 8 Jan 2024 12:33:14 -0600 Received: from lelvsmtp5.itg.ti.com ([10.249.40.136]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 408IX3hK051691; Mon, 8 Jan 2024 12:33:13 -0600 From: Andrew Davis To: Frank Binns , Donald Robson , Matt Coster , "H . Nikolaus Schaller" , Adam Ford , Ivaylo Dimitrov , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , =?utf-8?q?Beno=C3=AEt_Cousson?= , Tony Lindgren , Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Paul Cercueil CC: , , , , , , , Andrew Davis Subject: [PATCH RFC v2 11/11] MIPS: DTS: jz4780: Add device tree entry for SGX GPU Date: Mon, 8 Jan 2024 12:33:02 -0600 Message-ID: <20240108183302.255055-12-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240108183302.255055-1-afd@ti.com> References: <20240108183302.255055-1-afd@ti.com> Precedence: bulk X-Mailing-List: linux-omap@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Add SGX GPU device entry to base jz4780 dtsi file. Signed-off-by: Andrew Davis --- arch/mips/boot/dts/ingenic/jz4780.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi b/arch/mips/boot/dts/ingenic/jz4780.dtsi index 18affff85ce38..5ea6833f5e872 100644 --- a/arch/mips/boot/dts/ingenic/jz4780.dtsi +++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi @@ -460,6 +460,17 @@ hdmi: hdmi@10180000 { status = "disabled"; }; + gpu: gpu@13040000 { + compatible = "ingenic,jz4780-gpu", "img,powervr-sgx540"; + reg = <0x13040000 0x4000>; + + clocks = <&cgu JZ4780_CLK_GPU>; + clock-names = "core"; + + interrupt-parent = <&intc>; + interrupts = <63>; + }; + lcdc0: lcdc0@13050000 { compatible = "ingenic,jz4780-lcd"; reg = <0x13050000 0x1800>;