From patchwork Wed Jan 17 10:41:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sibi Sankar X-Patchwork-Id: 763333 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9EAF91C6BA; Wed, 17 Jan 2024 10:45:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705488334; cv=none; b=Bc8J2GiA4UQldNVmspEW6IHJXf9MhHyCMknUkCnbaGg1HuUfxxgMd3dcis99CdkVN6cCAF47opZQvkSzz2pcZHzOMDdTPXYBLK1Vq03jQnOcWZC6gBp6GVS2E0Hv8S1+jov/kz08JyeGyiMEgxpBTd/QD+nuN76edgLsnK/XseA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705488334; c=relaxed/simple; bh=BpCA0vwZl69dRLI4dnWA0LBDKY4aswlh97aPkxwupXA=; h=Received:DKIM-Signature:Received:Received:Received:From:To:CC: Subject:Date:Message-ID:X-Mailer:In-Reply-To:References: MIME-Version:Content-Transfer-Encoding:Content-Type: X-Originating-IP:X-ClientProxiedBy:X-QCInternal: X-Proofpoint-Virus-Version:X-Proofpoint-GUID: X-Proofpoint-ORIG-GUID:X-Proofpoint-Virus-Version: X-Proofpoint-Spam-Details; b=T4HzUuWe5M6w6FVPAzQyvVZvhVwDEw6jaKHI0YSnPcCyJXiRwS/pi64WptdivkeqIMLq+iFKaf9meIfboV/YhjtL87NUPiggWhyqH//BMG7FhmPppw9jNMa8WWRLBOoKIxfAfXbkCZ+ECrt7Wv8F9Lz5hhywFkvVrHu95e6uLj4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=WrAl0nkd; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="WrAl0nkd" Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 40H4rENU010679; Wed, 17 Jan 2024 10:45:21 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= qcppdkim1; bh=de9oS+lk9gffGLo4TJesF3FDP09M3GDm6E7fNkq1Fho=; b=Wr Al0nkd45aamSUGML21bLuMoa+zLZwDPsBGGHtxVVVNw2ic5WHlaVsgOm+oKCPD5a H2evsuU8z1xj1srqfV4wq/JNAqEl94WD9luhQRnnvklQLPpZjiS+8ZX/XEKOiINU 5lKDRQt/W8YmIwuJKJvYOV5oDdBc/VbVnrnK7viKRdhPGEtVxi9jpAX79FxQANjc a/f9A/whPkklZ/pONO4JqRaghqXjtcif3lji/Ufj4B9fRcEzPG2r62C3GeWmlM6+ ptov0FNaymZ3of1begb5deR0URe6y+xSlBDw0CBL+Gvus9gBxkKeQfhuc0+DyyJb FJume9MoAn+2RrjuYCCw== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3vnrndb1nf-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 17 Jan 2024 10:45:20 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 40HAjKd1021085 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 17 Jan 2024 10:45:20 GMT Received: from hu-sibis-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 17 Jan 2024 02:45:15 -0800 From: Sibi Sankar To: , , , , , , CC: , , , , , Sibi Sankar Subject: [PATCH V2 1/4] firmware: arm_scmi: Add perf_notify_support interface Date: Wed, 17 Jan 2024 16:11:13 +0530 Message-ID: <20240117104116.2055349-2-quic_sibis@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240117104116.2055349-1-quic_sibis@quicinc.com> References: <20240117104116.2055349-1-quic_sibis@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: zwZn1dXK8tA7kGj5gSfKLVlGr8oSVcfK X-Proofpoint-ORIG-GUID: zwZn1dXK8tA7kGj5gSfKLVlGr8oSVcfK X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-01-17_05,2024-01-17_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 lowpriorityscore=0 mlxscore=0 suspectscore=0 mlxlogscore=999 clxscore=1015 adultscore=0 impostorscore=0 malwarescore=0 bulkscore=0 phishscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2401170075 Add a new perf_notify_support interface to the existing perf_ops to export info regarding limit/level change notification support. Signed-off-by: Sibi Sankar --- drivers/firmware/arm_scmi/perf.c | 16 ++++++++++++++++ include/linux/scmi_protocol.h | 8 ++++++++ 2 files changed, 24 insertions(+) diff --git a/drivers/firmware/arm_scmi/perf.c b/drivers/firmware/arm_scmi/perf.c index 211e8e0aef2c..ae7681eda276 100644 --- a/drivers/firmware/arm_scmi/perf.c +++ b/drivers/firmware/arm_scmi/perf.c @@ -962,6 +962,21 @@ scmi_power_scale_get(const struct scmi_protocol_handle *ph) return pi->power_scale; } +static int scmi_notify_support(const struct scmi_protocol_handle *ph, u32 domain, + struct scmi_perf_notify_info *info) +{ + struct perf_dom_info *dom; + + dom = scmi_perf_domain_lookup(ph, domain); + if (IS_ERR(dom)) + return -EINVAL; + + info->perf_limit_notify = dom->perf_limit_notify; + info->perf_level_notify = dom->perf_level_notify; + + return 0; +} + static const struct scmi_perf_proto_ops perf_proto_ops = { .num_domains_get = scmi_perf_num_domains_get, .info_get = scmi_perf_info_get, @@ -976,6 +991,7 @@ static const struct scmi_perf_proto_ops perf_proto_ops = { .est_power_get = scmi_dvfs_est_power_get, .fast_switch_possible = scmi_fast_switch_possible, .power_scale_get = scmi_power_scale_get, + .perf_notify_support = scmi_notify_support, }; static int scmi_perf_set_notify_enabled(const struct scmi_protocol_handle *ph, diff --git a/include/linux/scmi_protocol.h b/include/linux/scmi_protocol.h index f2f05fb42d28..b0947d004826 100644 --- a/include/linux/scmi_protocol.h +++ b/include/linux/scmi_protocol.h @@ -117,6 +117,11 @@ struct scmi_perf_domain_info { bool set_perf; }; +struct scmi_perf_notify_info { + bool perf_limit_notify; + bool perf_level_notify; +}; + /** * struct scmi_perf_proto_ops - represents the various operations provided * by SCMI Performance Protocol @@ -139,6 +144,7 @@ struct scmi_perf_domain_info { * for a given device * @power_scale_mw_get: indicates if the power values provided are in milliWatts * or in some other (abstract) scale + * @perf_notify_support: indicates if limit and level change notification is supported */ struct scmi_perf_proto_ops { int (*num_domains_get)(const struct scmi_protocol_handle *ph); @@ -165,6 +171,8 @@ struct scmi_perf_proto_ops { bool (*fast_switch_possible)(const struct scmi_protocol_handle *ph, u32 domain); enum scmi_power_scale (*power_scale_get)(const struct scmi_protocol_handle *ph); + int (*perf_notify_support)(const struct scmi_protocol_handle *ph, u32 domain, + struct scmi_perf_notify_info *info); }; /** From patchwork Wed Jan 17 10:41:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sibi Sankar X-Patchwork-Id: 764325 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BD3E71CD0F; Wed, 17 Jan 2024 10:45:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705488334; cv=none; b=NrzoQHZWCdWF+V6Hf2QEaUxs5NArONhFYkDYNliYTSSCKrJtRJDimS+vEkO8Nw5i+vMmfiFhTxEbUI0UH7RzASJfLptmbv0CphLxwHbzoHndH0vKGZDgkueodWM+JqDgHX9ggNaAXCr7SZ68rfFbEaAsDdkfDC57P8bGcN6k0rI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705488334; c=relaxed/simple; bh=XcfLDOJO0KheGlrqed/VY433fhHBdiZrnxl+NAWu0Uk=; h=Received:DKIM-Signature:Received:Received:Received:From:To:CC: Subject:Date:Message-ID:X-Mailer:In-Reply-To:References: MIME-Version:Content-Transfer-Encoding:Content-Type: X-Originating-IP:X-ClientProxiedBy:X-QCInternal: X-Proofpoint-Virus-Version:X-Proofpoint-ORIG-GUID: X-Proofpoint-GUID:X-Proofpoint-Virus-Version: X-Proofpoint-Spam-Details; b=iEginncWW1emutUwaKKjnqOhAJbX29BLLSa6ln3b3r7S82451ImSWtJXAq4WIZT7IBPHZaXULanXuTtAVPzupapP1Vkop87uatdJBhZv/NezfveL4aklaA7XTuMy+vB/3NyCFXLgaxVVWv6V1wJ9LIopfb6IwhiCfyesSiIg9Ww= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=Uj/WFvS3; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="Uj/WFvS3" Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 40H8qVfD001973; Wed, 17 Jan 2024 10:45:25 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= qcppdkim1; bh=t5KP79QWXsw25d4MuM/1hHxIP2v8PSUSFp5/Jfqbles=; b=Uj /WFvS3qToQSj3ctD0/ojxmr2vh+Lksjm6gCih179kGUhOfTOkyKD0Mh4I7b+MnSN qQYyeOpvB6JNsBnnlvT8IPEZDuK/m+wwkun7Fa5QafmGjgmyxF+Tc7xv6CE6wwG3 awsaQddYzWB4TO2vFDSi+uImqk/NAsUZxiaEKCTJkradE7OnUcCmZBdnmKlUXt0x gH88ZAFYCE0oF8pfWEIQV+2tYKnVU7al78y3TMHeYwnk9Jqw6DoKwX4+8J+gq34X PfK9tA1PBOB7id4rGHllio8nsosQIsg8AmSL/yrlnFOkKu+GbjrxpE7aUVZgiPkH RhmOsqUlKYkFCea8Hmjw== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3vp83frnsw-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 17 Jan 2024 10:45:25 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 40HAjOxk021761 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 17 Jan 2024 10:45:24 GMT Received: from hu-sibis-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 17 Jan 2024 02:45:20 -0800 From: Sibi Sankar To: , , , , , , CC: , , , , , Sibi Sankar Subject: [PATCH V2 2/4] firmware: arm_scmi: Add perf_freq_xlate interface Date: Wed, 17 Jan 2024 16:11:14 +0530 Message-ID: <20240117104116.2055349-3-quic_sibis@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240117104116.2055349-1-quic_sibis@quicinc.com> References: <20240117104116.2055349-1-quic_sibis@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: VGrwATozEGT5m7ahFDPsXj_aDfhyd3KC X-Proofpoint-GUID: VGrwATozEGT5m7ahFDPsXj_aDfhyd3KC X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-01-17_05,2024-01-17_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 mlxlogscore=999 clxscore=1015 malwarescore=0 bulkscore=0 adultscore=0 spamscore=0 phishscore=0 priorityscore=1501 lowpriorityscore=0 mlxscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2401170075 Add a new perf_freq_xlate interface to the existing perf_ops to translate a given perf index to frequency. This can be used by the cpufreq driver and framework to determine the throttled frequency from a given perf index and apply HW pressure accordingly. Signed-off-by: Sibi Sankar --- v2: * Rename opp_xlate -> freq_xlate [Viresh] drivers/firmware/arm_scmi/perf.c | 21 +++++++++++++++++++++ include/linux/scmi_protocol.h | 3 +++ 2 files changed, 24 insertions(+) diff --git a/drivers/firmware/arm_scmi/perf.c b/drivers/firmware/arm_scmi/perf.c index ae7681eda276..e286f04ee6e3 100644 --- a/drivers/firmware/arm_scmi/perf.c +++ b/drivers/firmware/arm_scmi/perf.c @@ -977,6 +977,26 @@ static int scmi_notify_support(const struct scmi_protocol_handle *ph, u32 domain return 0; } +static int scmi_perf_freq_xlate(const struct scmi_protocol_handle *ph, u32 domain, + int idx, unsigned long *freq) +{ + struct perf_dom_info *dom; + + dom = scmi_perf_domain_lookup(ph, domain); + if (IS_ERR(dom)) + return PTR_ERR(dom); + + if (idx >= dom->opp_count) + return -ERANGE; + + if (!dom->level_indexing_mode) + *freq = dom->opp[idx].perf * dom->mult_factor; + else + *freq = dom->opp[idx].indicative_freq * dom->mult_factor; + + return 0; +} + static const struct scmi_perf_proto_ops perf_proto_ops = { .num_domains_get = scmi_perf_num_domains_get, .info_get = scmi_perf_info_get, @@ -992,6 +1012,7 @@ static const struct scmi_perf_proto_ops perf_proto_ops = { .fast_switch_possible = scmi_fast_switch_possible, .power_scale_get = scmi_power_scale_get, .perf_notify_support = scmi_notify_support, + .perf_freq_xlate = scmi_perf_freq_xlate, }; static int scmi_perf_set_notify_enabled(const struct scmi_protocol_handle *ph, diff --git a/include/linux/scmi_protocol.h b/include/linux/scmi_protocol.h index b0947d004826..6221d391386c 100644 --- a/include/linux/scmi_protocol.h +++ b/include/linux/scmi_protocol.h @@ -145,6 +145,7 @@ struct scmi_perf_notify_info { * @power_scale_mw_get: indicates if the power values provided are in milliWatts * or in some other (abstract) scale * @perf_notify_support: indicates if limit and level change notification is supported + * @perf_freq_xlate: translates the given perf index to frequency in Hz */ struct scmi_perf_proto_ops { int (*num_domains_get)(const struct scmi_protocol_handle *ph); @@ -173,6 +174,8 @@ struct scmi_perf_proto_ops { enum scmi_power_scale (*power_scale_get)(const struct scmi_protocol_handle *ph); int (*perf_notify_support)(const struct scmi_protocol_handle *ph, u32 domain, struct scmi_perf_notify_info *info); + int (*perf_freq_xlate)(const struct scmi_protocol_handle *ph, u32 domain, + int idx, unsigned long *freq); }; /** From patchwork Wed Jan 17 10:41:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sibi Sankar X-Patchwork-Id: 763332 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 79D851DFE3; Wed, 17 Jan 2024 10:45:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705488338; cv=none; b=r4odsnrNB8ZyVuMMFTd5jOdrTsPvoQx9lqDLs1N+lAOlR5o1ibPV76pzUIoXUg8CMhvnGtN4WRHX2lIz7leHeRKl36XUlc51PHcncakqrBf1qEe6d2tySCxrUUDQNBRMWxBZ2ksZc7J8ZGGWcL9zvLE3jawVv7w3htwhQEKyu94= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705488338; c=relaxed/simple; bh=Fz3iaZzzJ7//KORWCiTXcEASDzK0xI8KU8CRn/qrt7M=; h=Received:DKIM-Signature:Received:Received:Received:From:To:CC: Subject:Date:Message-ID:X-Mailer:In-Reply-To:References: MIME-Version:Content-Transfer-Encoding:Content-Type: X-Originating-IP:X-ClientProxiedBy:X-QCInternal: X-Proofpoint-Virus-Version:X-Proofpoint-GUID: X-Proofpoint-ORIG-GUID:X-Proofpoint-Virus-Version: X-Proofpoint-Spam-Details; b=MBEP4l34Hj1yCwwbHHiSvUyc9ggybbb9nM2RWmRmIg2XblxDYW/LQdbLHqW+clqUKQH83qQ7bltFSOnFABbF57WHPSLIeRVhypqCKCCKTIpgtiLr/PPESJpuylR5/eCe08FdvOfiSNKBIKBzDVaYwyhviLmJYuYGiYnQR70As4o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=Ew1B2G7H; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="Ew1B2G7H" Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 40H9rfUo006335; Wed, 17 Jan 2024 10:45:30 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= qcppdkim1; bh=tl+tO8RuoXRoEWn+uAJ3Ru+OjYumeFt2x5eT73JhPPM=; b=Ew 1B2G7HtaYG9q+FCoKxACEKjsfUAwSDwOgeW2yRODCHp4ryukTRBiQRfbRESTOH4K fJfsY+h8ximsd9TmPC8ue9R3+AO9+3QhVhrKcqLbhtERukMlLy/wZSRH9kWzv/ms vzYP71CHbcZIb7W8ex9m0AVrLLMYg0/swnKP8m0P/PmoUetPgz6RzdwnFbHPEK3T ajMPOX+rik0fcNjjf2AdmbQ+Tcj8RX1y2aITGmGBfz1rYvuyoh/r0AOtbUa1t++6 hnT9Xg5cP+mBunSqqEyHSaiG46X2Lgqlh08aEJZCZaWXYfExvRd1NIWh3Hvz4uTR 8qwmDDyLaRtt0iz5vYlw== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3vnrndb1nr-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 17 Jan 2024 10:45:29 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 40HAjTAF021810 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 17 Jan 2024 10:45:29 GMT Received: from hu-sibis-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 17 Jan 2024 02:45:24 -0800 From: Sibi Sankar To: , , , , , , CC: , , , , , Sibi Sankar Subject: [PATCH V2 3/4] cpufreq: Export cpufreq_update_pressure Date: Wed, 17 Jan 2024 16:11:15 +0530 Message-ID: <20240117104116.2055349-4-quic_sibis@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240117104116.2055349-1-quic_sibis@quicinc.com> References: <20240117104116.2055349-1-quic_sibis@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: eRomCy9t0CtFfzHtYworNelut6eGK2XQ X-Proofpoint-ORIG-GUID: eRomCy9t0CtFfzHtYworNelut6eGK2XQ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-01-17_05,2024-01-17_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 lowpriorityscore=0 mlxscore=0 suspectscore=0 mlxlogscore=695 clxscore=1015 adultscore=0 impostorscore=0 malwarescore=0 bulkscore=0 phishscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2401170075 The SCMI cpufreq driver doesn't require any additional signal smoothing provided by arch_update_hw_pressure interface, export cpufreq_update_pressure so that it can be called upon directly instead. Suggested-by: Lukasz Luba Signed-off-by: Sibi Sankar --- v2: * Export cpufreq_update_pressure and use it directly [Lukasz] drivers/cpufreq/cpufreq.c | 3 ++- include/linux/cpufreq.h | 2 ++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/cpufreq/cpufreq.c b/drivers/cpufreq/cpufreq.c index f4eee3d107f1..c051d1719a06 100644 --- a/drivers/cpufreq/cpufreq.c +++ b/drivers/cpufreq/cpufreq.c @@ -2571,7 +2571,7 @@ DEFINE_PER_CPU(unsigned long, cpufreq_pressure); * * Update the value of cpufreq pressure for all @cpus in the policy. */ -static void cpufreq_update_pressure(struct cpufreq_policy *policy) +void cpufreq_update_pressure(struct cpufreq_policy *policy) { unsigned long max_capacity, capped_freq, pressure; u32 max_freq; @@ -2596,6 +2596,7 @@ static void cpufreq_update_pressure(struct cpufreq_policy *policy) for_each_cpu(cpu, policy->related_cpus) WRITE_ONCE(per_cpu(cpufreq_pressure, cpu), pressure); } +EXPORT_SYMBOL(cpufreq_update_pressure); /** * cpufreq_set_policy - Modify cpufreq policy parameters. diff --git a/include/linux/cpufreq.h b/include/linux/cpufreq.h index b1d97edd3253..c6395b698863 100644 --- a/include/linux/cpufreq.h +++ b/include/linux/cpufreq.h @@ -241,6 +241,7 @@ struct kobject *get_governor_parent_kobj(struct cpufreq_policy *policy); void cpufreq_enable_fast_switch(struct cpufreq_policy *policy); void cpufreq_disable_fast_switch(struct cpufreq_policy *policy); bool has_target_index(void); +void cpufreq_update_pressure(struct cpufreq_policy *policy); DECLARE_PER_CPU(unsigned long, cpufreq_pressure); static inline unsigned long cpufreq_get_pressure(int cpu) @@ -269,6 +270,7 @@ static inline bool cpufreq_supports_freq_invariance(void) return false; } static inline void disable_cpufreq(void) { } +static inline void cpufreq_update_pressure(struct cpufreq_policy *policy) { } static inline unsigned long cpufreq_get_pressure(int cpu) { return 0; From patchwork Wed Jan 17 10:41:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sibi Sankar X-Patchwork-Id: 764324 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1F6FF1E89F; Wed, 17 Jan 2024 10:45:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705488344; cv=none; b=Xmp+CCEDa71qEAv/8+pXoSep2M4Q/mUwdHU2cVXSgR4gXCc0slrKrzKDGx+Yw+C63SHZloCRKST8g4Yp/4kMsbAPqcUN2IDglt8QJ9HxcV+GKXLHVlJqj5loSTwRSw1Omw2jLA4I3ng3IUTNBRv6Ocjd0N1dwEA2kdYRYma2s7Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705488344; c=relaxed/simple; bh=Ev/G7YkqVnj6LyyIzJAKaxRPGl6XNLa62IS6wWs+0/o=; h=Received:DKIM-Signature:Received:Received:Received:From:To:CC: Subject:Date:Message-ID:X-Mailer:In-Reply-To:References: MIME-Version:Content-Transfer-Encoding:Content-Type: X-Originating-IP:X-ClientProxiedBy:X-QCInternal: X-Proofpoint-Virus-Version:X-Proofpoint-GUID: X-Proofpoint-ORIG-GUID:X-Proofpoint-Virus-Version: X-Proofpoint-Spam-Details; b=SU7rUsL1DqkW3ew0VfuKkre5QAzuVBaNonda2aeEskZUlyCQijC1av1ZZxRMn/BXNl6x5BxEfupTjdv1oYpI277RZzIoysG4/pY6zTRMaKHe2Lk07XjUs2pW3kwv6le0PSvgaod2wF07VqOsQbPKqQXS8Hj9kuhkqcVRrC+JaNI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=FjkEUpgY; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="FjkEUpgY" Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 40H79vY6006351; Wed, 17 Jan 2024 10:45:35 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= qcppdkim1; bh=jOlwglCt4leERfiObcjYf6erEXXX2+qP0gHWqy5dMHg=; b=Fj kEUpgYLLOEXzW8uh2Ez7uSGemIKa6RyHJh0TwGOlgROf0Ba2Q8Txmj6OaQscLJu6 fSF5dJCTG9zWML5bzc3NHvZ9rrKQ8TSyb2XBT4JlAqZabKkYGhaPSYqgriw5IBuS QS7Oz/tJbf8RLZoX1QZYVhzo/BWuI6/amOsTgDrwz7uMZoSHnKztKz1/LiJ6T771 NSuIR9BlU0TcARoWdZw3bKbJig+S58+JNdwZffxi+kfHwW+zoeSclLT/JmZm5/x+ O7w6vCJ1+KhdtmJsVkR5bAAdlvLcPG5BN45fi60GBBaxhEVt4nUplFWhYro/Y94Q sj4kTQM4cn9LbdLVGTzg== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3vpa1erer1-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 17 Jan 2024 10:45:34 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 40HAjXe3023691 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 17 Jan 2024 10:45:33 GMT Received: from hu-sibis-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 17 Jan 2024 02:45:29 -0800 From: Sibi Sankar To: , , , , , , CC: , , , , , Sibi Sankar Subject: [PATCH V2 4/4] cpufreq: scmi: Register for limit change notifications Date: Wed, 17 Jan 2024 16:11:16 +0530 Message-ID: <20240117104116.2055349-5-quic_sibis@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240117104116.2055349-1-quic_sibis@quicinc.com> References: <20240117104116.2055349-1-quic_sibis@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: v8jC1YldiZ1CpvO-ai1XGUi5OZ9oVPeJ X-Proofpoint-ORIG-GUID: v8jC1YldiZ1CpvO-ai1XGUi5OZ9oVPeJ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-01-17_05,2024-01-17_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 mlxscore=0 adultscore=0 mlxlogscore=999 clxscore=1015 phishscore=0 malwarescore=0 lowpriorityscore=0 priorityscore=1501 bulkscore=0 spamscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2401170075 Register for limit change notifications if supported with the help of perf_notify_support interface and determine the throttled frequency using the perf_freq_xlate to apply HW pressure. Signed-off-by: Sibi Sankar --- v2: * Export cpufreq_update_pressure and use it directly [Lukasz] drivers/cpufreq/scmi-cpufreq.c | 42 +++++++++++++++++++++++++++++++++- 1 file changed, 41 insertions(+), 1 deletion(-) diff --git a/drivers/cpufreq/scmi-cpufreq.c b/drivers/cpufreq/scmi-cpufreq.c index 4ee23f4ebf4a..e0aa85764451 100644 --- a/drivers/cpufreq/scmi-cpufreq.c +++ b/drivers/cpufreq/scmi-cpufreq.c @@ -25,9 +25,13 @@ struct scmi_data { int domain_id; int nr_opp; struct device *cpu_dev; + struct cpufreq_policy *policy; cpumask_var_t opp_shared_cpus; + struct notifier_block limit_notify_nb; }; +const struct scmi_handle *handle; +static struct scmi_device *scmi_dev; static struct scmi_protocol_handle *ph; static const struct scmi_perf_proto_ops *perf_ops; @@ -144,6 +148,22 @@ scmi_get_cpu_power(struct device *cpu_dev, unsigned long *power, return 0; } +static int scmi_limit_notify_cb(struct notifier_block *nb, unsigned long event, void *data) +{ + unsigned long freq_hz; + struct scmi_perf_limits_report *limit_notify = data; + struct scmi_data *priv = container_of(nb, struct scmi_data, limit_notify_nb); + struct cpufreq_policy *policy = priv->policy; + + if (perf_ops->perf_freq_xlate(ph, priv->domain_id, limit_notify->range_max, &freq_hz)) + return NOTIFY_OK; + + policy->max = freq_hz / HZ_PER_KHZ; + cpufreq_update_pressure(policy); + + return NOTIFY_OK; +} + static int scmi_cpufreq_init(struct cpufreq_policy *policy) { int ret, nr_opp, domain; @@ -151,6 +171,7 @@ static int scmi_cpufreq_init(struct cpufreq_policy *policy) struct device *cpu_dev; struct scmi_data *priv; struct cpufreq_frequency_table *freq_table; + struct scmi_perf_notify_info info = {}; cpu_dev = get_cpu_device(policy->cpu); if (!cpu_dev) { @@ -250,6 +271,25 @@ static int scmi_cpufreq_init(struct cpufreq_policy *policy) policy->fast_switch_possible = perf_ops->fast_switch_possible(ph, domain); + ret = perf_ops->perf_notify_support(ph, domain, &info); + if (ret) + dev_warn(cpu_dev, "failed to get supported notifications: %d\n", ret); + + if (info.perf_limit_notify) { + priv->limit_notify_nb.notifier_call = scmi_limit_notify_cb; + ret = handle->notify_ops->devm_event_notifier_register(scmi_dev, SCMI_PROTOCOL_PERF, + SCMI_EVENT_PERFORMANCE_LIMITS_CHANGED, + &domain, + &priv->limit_notify_nb); + if (ret) { + dev_err(cpu_dev, "Error in registering limit change notifier for domain %d\n", + domain); + return ret; + } + } + + priv->policy = policy; + return 0; out_free_opp: @@ -321,8 +361,8 @@ static int scmi_cpufreq_probe(struct scmi_device *sdev) { int ret; struct device *dev = &sdev->dev; - const struct scmi_handle *handle; + scmi_dev = sdev; handle = sdev->handle; if (!handle)