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[83.30.41.51]) by smtp.gmail.com with ESMTPSA id k6-20020a170906128600b00a2b0b0fc80esm12547134ejb.193.2024.01.21.11.44.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Jan 2024 11:44:58 -0800 (PST) From: Adam Skladowski To: Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Adam Skladowski , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Krishna Manikandan , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/8] dt-bindings: dsi-controller-main: Document missing msm8976 compatible Date: Sun, 21 Jan 2024 20:41:00 +0100 Message-Id: <20240121194221.13513-3-a39.skl@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240121194221.13513-1-a39.skl@gmail.com> References: <20240121194221.13513-1-a39.skl@gmail.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 When all dsi-ctrl compats were added msm8976 was missed, include it too. Signed-off-by: Adam Skladowski Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/display/msm/dsi-controller-main.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml index 4219936eda5a..1fa28e976559 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml @@ -19,6 +19,7 @@ properties: - qcom,msm8916-dsi-ctrl - qcom,msm8953-dsi-ctrl - qcom,msm8974-dsi-ctrl + - qcom,msm8976-dsi-ctrl - qcom,msm8996-dsi-ctrl - qcom,msm8998-dsi-ctrl - qcom,qcm2290-dsi-ctrl @@ -248,6 +249,7 @@ allOf: contains: enum: - qcom,msm8953-dsi-ctrl + - qcom,msm8976-dsi-ctrl then: properties: clocks: From patchwork Sun Jan 21 19:41:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Skladowski X-Patchwork-Id: 764484 Received: from mail-wm1-f42.google.com (mail-wm1-f42.google.com [209.85.128.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7FE7B383A9; Sun, 21 Jan 2024 19:45:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705866328; cv=none; b=lWFahgQjCsJyRVCyvSwSm5oXf4aKiR3BnJVgRAB93akYB58f5mH+w7TLfT83yNU+xt+tbS7QfxFro9p7QO5dlMloKG8DNu4Xhawt6ngnRMSTsKn5w+7qV4WfDR5ndkPKlqawH8mvWuCxBi7Z/CrRjwJI2b58vNcbNjSAxjTPdK4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705866328; c=relaxed/simple; bh=OWMhH7Nexg5Sr8mmHYOlhHtYbSSfcvk2YC6krZrvN24=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=YOsbN3ee4xnQGkFOXrxe1hEujt38txef8RJ4lOFk/KrW10LIe7JqT7JWeQcX2Z/Z3PPj88oicVbx8RXyW5MRg29QOu5dKOIAy/D/em9ux99PwhKfLCiFSvK0O0ZUQCH0FyFCrRDODiM7Im2K+KYs6RxphJeh03+DTeldxKvcTx4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=HNZEuJsR; arc=none smtp.client-ip=209.85.128.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="HNZEuJsR" Received: by mail-wm1-f42.google.com with SMTP id 5b1f17b1804b1-40e80046264so32667375e9.0; Sun, 21 Jan 2024 11:45:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1705866324; x=1706471124; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qry+IoFMR9xixm+CmJmEcM3m/KbtxBNh2E+r7IudFD4=; b=HNZEuJsRuj3KxsvSVXJ5kheetfhyw9pOFpZfDff1FiSwjbbFVi4qbw+qbt4Se9+U8g AvvJWyb8iaUeqYTtjYMwsZHbd1PdvC3kJeLiamcF5wnFxSde0wtsKDEkk7aTngkqF4+P bMRBKAoMbPXRCPhn6nIPCa9lxtuG/lXXK1/0cZr/4AT6+DsoDJ+XFkl3VJX8uATZYeZ+ p7YjHTW7E+6Y0NR1mu9c4QNjT930urwiaG+NHiEMQJ+xcw/5ZXmTQAagPUKaWzPYZLpX lq6SjFv7XV/vzabTGZxoBKuzG3UDbFfHHEn9e1RKQrcqMRixwNF8Bt229coOIqoSckDj /QcA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1705866324; x=1706471124; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qry+IoFMR9xixm+CmJmEcM3m/KbtxBNh2E+r7IudFD4=; b=A17okJ8RgyfMuqPVF4nsUMTNtE6UCkp7Lg9kj2xY6svgv9VFRuxUwrUG/jhgL2A6aX y7favy1qA9rapWw2uYqYbHzd/IYWkOrz5WtTD0B43U7hsprmqFAvdJASb+TIi5zI5vJN P+vFM8zeNu7C1wo4R91aNrKNwbJl3d0v73tA95CmdRy3mE7+aXAbjEd09bwEAeFbowow XpBzvMMTZFSb8BTNvWEGMl4NkXxtOtS7iJxm8J3BYRWr9rr2vAeEZf4XrNeG4WyMcN8/ xp56CfrLmHIR1V1XKpAAckN5B2L64abdgP8eN668v/KIhhIijusCMJ+IJseuyiig9HI2 v1PQ== X-Gm-Message-State: AOJu0YwOCZ4vwgNuqcMFHOapvXQg5iVgi+VWuiN8MoYdGehdDyWYlpZw 7OGXVMXKi9eFtQ+yEBTFGyW2yk5+uF5vtXIX1++DhpzxEuQQYZmPFbtCx8sIW6U= X-Google-Smtp-Source: AGHT+IFZxVchAXAfLQIn8QiWKiuD4HWs4BPKHmCzu518ih7OsipVFzZjmc88iWQgOy+6/7RuKKdgYw== X-Received: by 2002:a05:600c:3513:b0:40e:4672:5227 with SMTP id h19-20020a05600c351300b0040e46725227mr1931625wmq.96.1705866324560; Sun, 21 Jan 2024 11:45:24 -0800 (PST) Received: from localhost.localdomain (byv51.neoplus.adsl.tpnet.pl. [83.30.41.51]) by smtp.gmail.com with ESMTPSA id k6-20020a170906128600b00a2b0b0fc80esm12547134ejb.193.2024.01.21.11.45.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Jan 2024 11:45:24 -0800 (PST) From: Adam Skladowski To: Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Adam Skladowski , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Krishna Manikandan , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/8] arm64: dts: qcom: msm8976: Add MDSS nodes Date: Sun, 21 Jan 2024 20:41:02 +0100 Message-Id: <20240121194221.13513-5-a39.skl@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240121194221.13513-1-a39.skl@gmail.com> References: <20240121194221.13513-1-a39.skl@gmail.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add MDSS nodes to support displays on MSM8976 SoC. Signed-off-by: Adam Skladowski --- arch/arm64/boot/dts/qcom/msm8976.dtsi | 268 +++++++++++++++++++++++++- 1 file changed, 264 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8976.dtsi b/arch/arm64/boot/dts/qcom/msm8976.dtsi index 118174cfd4d3..2d71ce34f00e 100644 --- a/arch/arm64/boot/dts/qcom/msm8976.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8976.dtsi @@ -785,10 +785,10 @@ gcc: clock-controller@1800000 { clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&rpmcc RPM_SMD_XO_A_CLK_SRC>, - <0>, - <0>, - <0>, - <0>; + <&mdss_dsi0_phy 1>, + <&mdss_dsi0_phy 0>, + <&mdss_dsi1_phy 1>, + <&mdss_dsi1_phy 0>; clock-names = "xo", "xo_a", "dsi0pll", @@ -808,6 +808,266 @@ tcsr: syscon@1937000 { reg = <0x01937000 0x30000>; }; + mdss: display-subsystem@1a00000 { + compatible = "qcom,mdss"; + + reg = <0x01a00000 0x1000>, + <0x01ab0000 0x3000>; + reg-names = "mdss_phys", "vbif_phys"; + + power-domains = <&gcc MDSS_GDSC>; + interrupts = ; + + interrupt-controller; + #interrupt-cells = <1>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>, + <&gcc GCC_MDSS_MDP_CLK>; + clock-names = "iface", + "bus", + "vsync", + "core"; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + status = "disabled"; + + mdss_mdp: display-controller@1a01000 { + compatible = "qcom,msm8976-mdp5", "qcom,mdp5"; + reg = <0x01a01000 0x89000>; + reg-names = "mdp_phys"; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>, + <&gcc GCC_MDP_TBU_CLK>, + <&gcc GCC_MDP_RT_TBU_CLK>; + clock-names = "iface", + "bus", + "core", + "vsync", + "tbu", + "tbu_rt"; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&gcc MDSS_GDSC>; + + iommus = <&apps_iommu 22>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_mdp5_intf1_out: endpoint { + remote-endpoint = <&mdss_dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + mdss_mdp5_intf2_out: endpoint { + remote-endpoint = <&mdss_dsi1_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-177780000 { + opp-hz = /bits/ 64 <177780000>; + required-opps = <&rpmpd_opp_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmpd_opp_svs_plus>; + }; + + opp-320000000 { + opp-hz = /bits/ 64 <320000000>; + required-opps = <&rpmpd_opp_nom>; + }; + opp-360000000 { + opp-hz = /bits/ 64 <360000000>; + required-opps = <&rpmpd_opp_turbo>; + }; + }; + }; + + mdss_dsi0: dsi@1a94000 { + compatible = "qcom,msm8976-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x01a94000 0x25c>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_BYTE0_CLK>, + <&gcc GCC_MDSS_PCLK0_CLK>, + <&gcc GCC_MDSS_ESC0_CLK>; + clock-names = "mdp_core", + "iface", + "bus", + "byte", + "pixel", + "core"; + + assigned-clocks = <&gcc GCC_MDSS_BYTE0_CLK_SRC>, + <&gcc GCC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>; + + phys = <&mdss_dsi0_phy>; + + operating-points-v2 = <&dsi0_opp_table>; + power-domains = <&gcc MDSS_GDSC>; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dsi0_in: endpoint { + remote-endpoint = <&mdss_mdp5_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dsi0_out: endpoint { + }; + }; + }; + + dsi0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-125000000 { + opp-hz = /bits/ 64 <125000000>; + required-opps = <&rpmpd_opp_svs>; + + }; + + opp-161250000 { + opp-hz = /bits/ 64 <161250000>; + required-opps = <&rpmpd_opp_svs_plus>; + }; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmpd_opp_nom>; + }; + }; + }; + + mdss_dsi1: dsi@1a96000 { + compatible = "qcom,msm8976-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x01a96000 0x300>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <5>; + + clocks = <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_BYTE1_CLK>, + <&gcc GCC_MDSS_PCLK1_CLK>, + <&gcc GCC_MDSS_ESC1_CLK>; + clock-names = "mdp_core", + "iface", + "bus", + "byte", + "pixel", + "core"; + + assigned-clocks = <&gcc GCC_MDSS_BYTE1_CLK_SRC>, + <&gcc GCC_MDSS_PCLK1_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi1_phy 0>, + <&mdss_dsi1_phy 1>; + + phys = <&mdss_dsi1_phy>; + + power-domains = <&gcc MDSS_GDSC>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dsi1_in: endpoint { + remote-endpoint = <&mdss_mdp5_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dsi1_out: endpoint { + }; + }; + }; + }; + + mdss_dsi0_phy: phy@1a94a00 { + compatible = "qcom,dsi-phy-28nm-hpm-fam-b"; + reg = <0x01a94a00 0xd4>, + <0x01a94400 0x280>, + <0x01a94b80 0x30>; + reg-names = "dsi_pll", + "dsi_phy", + "dsi_phy_regulator"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + + mdss_dsi1_phy: phy@1a96a00 { + compatible = "qcom,dsi-phy-28nm-hpm-fam-b"; + reg = <0x01a96a00 0xd4>, + <0x01a96400 0x280>, + <0x01a96b80 0x30>; + reg-names = "dsi_pll", + "dsi_phy", + "dsi_phy_regulator"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + }; + apps_iommu: iommu@1e20000 { compatible = "qcom,msm8976-iommu", "qcom,msm-iommu-v2"; ranges = <0 0x01e20000 0x20000>; From patchwork Sun Jan 21 19:41:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Skladowski X-Patchwork-Id: 764483 Received: from mail-ej1-f54.google.com (mail-ej1-f54.google.com [209.85.218.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 713E238F97; Sun, 21 Jan 2024 19:45:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.54 ARC-Seal: i=1; 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[83.30.41.51]) by smtp.gmail.com with ESMTPSA id k6-20020a170906128600b00a2b0b0fc80esm12547134ejb.193.2024.01.21.11.45.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Jan 2024 11:45:47 -0800 (PST) From: Adam Skladowski To: Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Adam Skladowski , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Krishna Manikandan , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 6/8] arm64: dts: qcom: msm8976: Add Adreno GPU Date: Sun, 21 Jan 2024 20:41:04 +0100 Message-Id: <20240121194221.13513-7-a39.skl@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240121194221.13513-1-a39.skl@gmail.com> References: <20240121194221.13513-1-a39.skl@gmail.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add Adreno GPU node. Signed-off-by: Adam Skladowski --- arch/arm64/boot/dts/qcom/msm8976.dtsi | 66 +++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8976.dtsi b/arch/arm64/boot/dts/qcom/msm8976.dtsi index 2d71ce34f00e..765c90ac14cb 100644 --- a/arch/arm64/boot/dts/qcom/msm8976.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8976.dtsi @@ -1068,6 +1068,72 @@ mdss_dsi1_phy: phy@1a96a00 { }; }; + adreno_gpu: gpu@1c00000 { + compatible = "qcom,adreno-510.0", "qcom,adreno"; + + reg = <0x01c00000 0x40000>; + reg-names = "kgsl_3d0_reg_memory"; + + interrupts = ; + interrupt-names = "kgsl_3d0_irq"; + + clock-names = "core", + "iface", + "mem", + "mem_iface", + "rbbmtimer", + "alwayson"; + + clocks = <&gcc GCC_GFX3D_OXILI_CLK>, + <&gcc GCC_GFX3D_OXILI_AHB_CLK>, + <&gcc GCC_GFX3D_OXILI_GMEM_CLK>, + <&gcc GCC_GFX3D_BIMC_CLK>, + <&gcc GCC_GFX3D_OXILI_TIMER_CLK>, + <&gcc GCC_GFX3D_OXILI_AON_CLK>; + + power-domains = <&rpmpd MSM8976_VDDCX>; + + iommus = <&gpu_iommu 0>; + + status = "disabled"; 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[83.30.41.51]) by smtp.gmail.com with ESMTPSA id k6-20020a170906128600b00a2b0b0fc80esm12547134ejb.193.2024.01.21.11.46.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Jan 2024 11:46:11 -0800 (PST) From: Adam Skladowski To: Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Adam Skladowski , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Krishna Manikandan , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 8/8] arm64: dts: qcom: msm8976: Add WCNSS node Date: Sun, 21 Jan 2024 20:41:06 +0100 Message-Id: <20240121194221.13513-9-a39.skl@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240121194221.13513-1-a39.skl@gmail.com> References: <20240121194221.13513-1-a39.skl@gmail.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add node describing wireless connectivity subsystem. Signed-off-by: Adam Skladowski --- arch/arm64/boot/dts/qcom/msm8976.dtsi | 96 +++++++++++++++++++++++++++ 1 file changed, 96 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8976.dtsi b/arch/arm64/boot/dts/qcom/msm8976.dtsi index 5a7be93a0115..73ddfaecd3ad 100644 --- a/arch/arm64/boot/dts/qcom/msm8976.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8976.dtsi @@ -861,6 +861,36 @@ data-pins { bias-pull-up; }; }; + + wcss_wlan_default: wcss-wlan-default-state { + wcss_wlan2-pins { + pins = "gpio40"; + function = "wcss_wlan2"; + drive-strength = <6>; + bias-pull-up; + }; + + wcss_wlan1-pins { + pins = "gpio41"; + function = "wcss_wlan1"; + drive-strength = <6>; + bias-pull-up; + }; + + wcss_wlan0-pins { + pins = "gpio42"; + function = "wcss_wlan0"; + drive-strength = <6>; + bias-pull-up; + }; + + wcss_wlan-pins { + pins = "gpio43", "gpio44"; + function = "wcss_wlan"; + drive-strength = <6>; + bias-pull-up; + }; + }; }; gcc: clock-controller@1800000 { @@ -1540,6 +1570,72 @@ blsp2_i2c4: i2c@7af8000 { status = "disabled"; }; + wcnss: remoteproc@a204000 { + compatible = "qcom,pronto-v3-pil", "qcom,pronto"; + reg = <0xa204000 0x2000>, <0xa202000 0x1000>, <0xa21b000 0x3000>; + reg-names = "ccu", "dxe", "pmu"; + + memory-region = <&wcnss_fw_mem>; + + interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; + + power-domains = <&rpmpd MSM8976_VDDCX>, + <&rpmpd MSM8976_VDDMX>; + power-domain-names = "cx", "mx"; + + qcom,smem-states = <&wcnss_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + pinctrl-names = "default"; + pinctrl-0 = <&wcss_wlan_default>; + + status = "disabled"; + + wcnss_iris: iris { + /* Separate chip, compatible is board-specific */ + clocks = <&rpmcc RPM_SMD_RF_CLK2>; + clock-names = "xo"; + }; + + smd-edge { + interrupts = ; + + qcom,ipc = <&apcs 8 17>; + qcom,smd-edge = <6>; + qcom,remote-pid = <4>; + + label = "pronto"; + + wcnss_ctrl: wcnss { + compatible = "qcom,wcnss"; + qcom,smd-channels = "WCNSS_CTRL"; + + qcom,mmio = <&wcnss>; + + wcnss_bt: bluetooth { + compatible = "qcom,wcnss-bt"; + }; + + wcnss_wifi: wifi { + compatible = "qcom,wcnss-wlan"; + + interrupts = , + ; + interrupt-names = "tx", "rx"; + + qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; + qcom,smem-state-names = "tx-enable", + "tx-rings-empty"; + }; + }; + }; + }; + intc: interrupt-controller@b000000 { compatible = "qcom,msm-qgic2"; reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;