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[83.30.41.51]) by smtp.gmail.com with ESMTPSA id k6-20020a170906128600b00a2b0b0fc80esm12547134ejb.193.2024.01.21.11.44.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Jan 2024 11:44:48 -0800 (PST) From: Adam Skladowski To: Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Adam Skladowski , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Krishna Manikandan , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/8] arm64: dts: qcom: msm8976: Add IOMMU nodes Date: Sun, 21 Jan 2024 20:40:59 +0100 Message-Id: <20240121194221.13513-2-a39.skl@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240121194221.13513-1-a39.skl@gmail.com> References: <20240121194221.13513-1-a39.skl@gmail.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add the nodes describing the apps and gpu iommu and its context banks that are found on msm8976 SoCs. Signed-off-by: Adam Skladowski --- arch/arm64/boot/dts/qcom/msm8976.dtsi | 80 +++++++++++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8976.dtsi b/arch/arm64/boot/dts/qcom/msm8976.dtsi index d2bb1ada361a..118174cfd4d3 100644 --- a/arch/arm64/boot/dts/qcom/msm8976.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8976.dtsi @@ -808,6 +808,86 @@ tcsr: syscon@1937000 { reg = <0x01937000 0x30000>; }; + apps_iommu: iommu@1e20000 { + compatible = "qcom,msm8976-iommu", "qcom,msm-iommu-v2"; + ranges = <0 0x01e20000 0x20000>; + + clocks = <&gcc GCC_SMMU_CFG_CLK>, + <&gcc GCC_APSS_TCU_CLK>; + clock-names = "iface", "bus"; + + qcom,iommu-secure-id = <17>; + + #address-cells = <1>; + #size-cells = <1>; + #iommu-cells = <1>; + + /* VFE */ + iommu-ctx@15000 { + compatible = "qcom,msm-iommu-v2-ns"; + reg = <0x15000 0x1000>; + qcom,ctx-asid = <20>; + interrupts = ; + }; + + /* VENUS NS */ + iommu-ctx@16000 { + compatible = "qcom,msm-iommu-v2-ns"; + reg = <0x16000 0x1000>; + qcom,ctx-asid = <21>; + interrupts = ; + }; + + /* MDP0 */ + iommu-ctx@17000 { + compatible = "qcom,msm-iommu-v2-ns"; + reg = <0x17000 0x1000>; + qcom,ctx-asid = <22>; + interrupts = ; + }; + }; + + gpu_iommu: iommu@1f08000 { + compatible = "qcom,msm8976-iommu", "qcom,msm-iommu-v2"; + ranges = <0 0x01f08000 0x8000>; + + clocks = <&gcc GCC_SMMU_CFG_CLK>, + <&gcc GCC_GFX3D_TCU_CLK>; + clock-names = "iface", "bus"; + + power-domains = <&gcc OXILI_GX_GDSC>; + + qcom,iommu-secure-id = <18>; + + #address-cells = <1>; + #size-cells = <1>; + #iommu-cells = <1>; + + /* gfx3d user */ + iommu-ctx@0 { + compatible = "qcom,msm-iommu-v2-ns"; + reg = <0x0 0x1000>; + qcom,ctx-asid = <0>; + interrupts = ; + }; + + /* gfx3d secure */ + iommu-ctx@1000 { + compatible = "qcom,msm-iommu-v2-sec"; + reg = <0x1000 0x1000>; + qcom,ctx-asid = <2>; + interrupts = ; + }; + + /* gfx3d priv */ + iommu-ctx@2000 { + compatible = "qcom,msm-iommu-v2-sec"; + reg = <0x2000 0x1000>; + qcom,ctx-asid = <1>; + interrupts = ; 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[83.30.41.51]) by smtp.gmail.com with ESMTPSA id k6-20020a170906128600b00a2b0b0fc80esm12547134ejb.193.2024.01.21.11.44.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Jan 2024 11:44:58 -0800 (PST) From: Adam Skladowski To: Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Adam Skladowski , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Krishna Manikandan , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/8] dt-bindings: dsi-controller-main: Document missing msm8976 compatible Date: Sun, 21 Jan 2024 20:41:00 +0100 Message-Id: <20240121194221.13513-3-a39.skl@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240121194221.13513-1-a39.skl@gmail.com> References: <20240121194221.13513-1-a39.skl@gmail.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 When all dsi-ctrl compats were added msm8976 was missed, include it too. Signed-off-by: Adam Skladowski Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/display/msm/dsi-controller-main.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml index 4219936eda5a..1fa28e976559 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml @@ -19,6 +19,7 @@ properties: - qcom,msm8916-dsi-ctrl - qcom,msm8953-dsi-ctrl - qcom,msm8974-dsi-ctrl + - qcom,msm8976-dsi-ctrl - qcom,msm8996-dsi-ctrl - qcom,msm8998-dsi-ctrl - qcom,qcm2290-dsi-ctrl @@ -248,6 +249,7 @@ allOf: contains: enum: - qcom,msm8953-dsi-ctrl + - qcom,msm8976-dsi-ctrl then: properties: clocks: From patchwork Sun Jan 21 19:41:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Skladowski X-Patchwork-Id: 764822 Received: from mail-wr1-f42.google.com (mail-wr1-f42.google.com [209.85.221.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A7E2438DF8; Sun, 21 Jan 2024 19:45:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705866315; cv=none; b=oJZqlPP7XcPfbQJOa7G6zK79i+XAsNuo2SpLQ5ZwzwsFkj/+qB5rYl2VzqPAV/IsrNGi3bw05zkVfwOUVx2LyuLDbWU+j9Sq5JnPfqRMcEahDoey5fuIuSS9J1DMk9RQmRKHDrOOlDKs0oF7Z6cm26GgQpHiViPDj3zh6hIlo8k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705866315; c=relaxed/simple; bh=UC94Wx9bEdnTNb8+XYn/4CYrJy/OEJGMp4Nv9V4ecE8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=hNKpxQyS9BzCWm4nvjXnxzAnw++Io+pe77IEAy6r8PctCPboZUxEsybZu5M3r720PDqu6cmyetqt17auWFX+o2g6ITsXHegBcxAlAVKOvg6kaSyQLhdKTO5ouXoiuiokHsChWuZOVKYy78yMwoEwS70X94pEPcjh1XiNwV4R1fs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=WqR+VBCt; arc=none smtp.client-ip=209.85.221.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="WqR+VBCt" Received: by mail-wr1-f42.google.com with SMTP id ffacd0b85a97d-339289fead2so1546311f8f.3; Sun, 21 Jan 2024 11:45:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1705866312; x=1706471112; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=n1xj7QKpcdq4XanNhyH8PlkFLqxpi5ERSOGj9kIBnKk=; b=WqR+VBCtdM0Mbw5yMJccIyzF0opbw5rZzLAuV00bb99lnktHm+S8rY0bFz+75IsBlp jZD86bNmRKGqV4Q1WpDViFu1QugnNDO5r/GrVlGtvn3VpHd6FcQvm0yXLO+fk6FPPNRO hYehFoMkV9RZYBAoJ3M8q39pfeCGjYR5YVToiUoo6eDUb+k2HOMFJdtaXeB4xlTj8w+6 KSswO8PA22pf+iHqV5Bxzn0/Y2Mx1YFavYcY0ckAYcWEHHL/tyJNTigSzVa970QHi9lp rzAcltd9yCuMQ4g273OIP5o8WPdOE7gVxO9NOF3bbKCpIqZREPkkte3PCYLvvWCmw1AA CPcg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1705866312; x=1706471112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=n1xj7QKpcdq4XanNhyH8PlkFLqxpi5ERSOGj9kIBnKk=; b=UskzlD4o8u3KBvaZHfmgK8/glmObjhzDMorjJFwjNAMoCare1D43GC636wcHcYfHUp kQuCxFY7fHvJR2xg/SSHng1P7XALHuSxZvYlkFkdY6qWA3iMddxhofkxeEEkOCuCaG/c nUQ+9Gvfsg6XgySa80XnvVDmWLroyAFhk7ikuCvPL0u2cIhX/mwEoBXimp2R5m9YlHZc UoRRM1CLehybzXDWbpVCfdRtLXP9qSfiZvCW4atnFVPgtI3+STd3eH8cJzJiEpAZBgwP O9IJRq+S8h3I0MhA2FWnCUCZxUdhIbFG8jT3fTfGauIwKpQeKXOK081o/F9p/suBYLPh RA0g== X-Gm-Message-State: AOJu0Yyd1igAtr4/a+D4d7SNfP3FVK4Pzha1CUIKMBsPxMXOh48Ve1QR h+BHW/TCWJ2cBVmg+Xho4Mw0yGRfYU+cT+yIQMyJbMu88iYDGBUn1HRcGkHS+d0= X-Google-Smtp-Source: AGHT+IFXVwttOkq/35bDzPfwT/wM4HP0z056E5OBcpImQRqU9YowudzK8lxKlAYn532chvCaTf3H8g== X-Received: by 2002:a05:600c:3c9e:b0:40e:a36d:ccd1 with SMTP id bg30-20020a05600c3c9e00b0040ea36dccd1mr1487870wmb.207.1705866311866; Sun, 21 Jan 2024 11:45:11 -0800 (PST) Received: from localhost.localdomain (byv51.neoplus.adsl.tpnet.pl. [83.30.41.51]) by smtp.gmail.com with ESMTPSA id k6-20020a170906128600b00a2b0b0fc80esm12547134ejb.193.2024.01.21.11.45.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Jan 2024 11:45:11 -0800 (PST) From: Adam Skladowski To: Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Adam Skladowski , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Krishna Manikandan , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/8] dt-bindings: msm: qcom,mdss: Include ommited fam-b compatible Date: Sun, 21 Jan 2024 20:41:01 +0100 Message-Id: <20240121194221.13513-4-a39.skl@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240121194221.13513-1-a39.skl@gmail.com> References: <20240121194221.13513-1-a39.skl@gmail.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 During conversion 28nm-hpm-fam-b compat got lost, add it. Signed-off-by: Adam Skladowski --- Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml index 0999ea07f47b..e4576546bf0d 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml @@ -127,6 +127,7 @@ patternProperties: - qcom,dsi-phy-20nm - qcom,dsi-phy-28nm-8226 - qcom,dsi-phy-28nm-hpm + - qcom,dsi-phy-28nm-hpm-fam-b - qcom,dsi-phy-28nm-lp - qcom,hdmi-phy-8084 - qcom,hdmi-phy-8660 From patchwork Sun Jan 21 19:41:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Skladowski X-Patchwork-Id: 764517 Received: from mail-wm1-f42.google.com (mail-wm1-f42.google.com [209.85.128.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7FE7B383A9; Sun, 21 Jan 2024 19:45:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705866328; cv=none; b=lWFahgQjCsJyRVCyvSwSm5oXf4aKiR3BnJVgRAB93akYB58f5mH+w7TLfT83yNU+xt+tbS7QfxFro9p7QO5dlMloKG8DNu4Xhawt6ngnRMSTsKn5w+7qV4WfDR5ndkPKlqawH8mvWuCxBi7Z/CrRjwJI2b58vNcbNjSAxjTPdK4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705866328; c=relaxed/simple; bh=OWMhH7Nexg5Sr8mmHYOlhHtYbSSfcvk2YC6krZrvN24=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=YOsbN3ee4xnQGkFOXrxe1hEujt38txef8RJ4lOFk/KrW10LIe7JqT7JWeQcX2Z/Z3PPj88oicVbx8RXyW5MRg29QOu5dKOIAy/D/em9ux99PwhKfLCiFSvK0O0ZUQCH0FyFCrRDODiM7Im2K+KYs6RxphJeh03+DTeldxKvcTx4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=HNZEuJsR; arc=none smtp.client-ip=209.85.128.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="HNZEuJsR" Received: by mail-wm1-f42.google.com with SMTP id 5b1f17b1804b1-40e80046264so32667375e9.0; Sun, 21 Jan 2024 11:45:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1705866324; x=1706471124; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qry+IoFMR9xixm+CmJmEcM3m/KbtxBNh2E+r7IudFD4=; b=HNZEuJsRuj3KxsvSVXJ5kheetfhyw9pOFpZfDff1FiSwjbbFVi4qbw+qbt4Se9+U8g AvvJWyb8iaUeqYTtjYMwsZHbd1PdvC3kJeLiamcF5wnFxSde0wtsKDEkk7aTngkqF4+P bMRBKAoMbPXRCPhn6nIPCa9lxtuG/lXXK1/0cZr/4AT6+DsoDJ+XFkl3VJX8uATZYeZ+ p7YjHTW7E+6Y0NR1mu9c4QNjT930urwiaG+NHiEMQJ+xcw/5ZXmTQAagPUKaWzPYZLpX lq6SjFv7XV/vzabTGZxoBKuzG3UDbFfHHEn9e1RKQrcqMRixwNF8Bt229coOIqoSckDj /QcA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1705866324; x=1706471124; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qry+IoFMR9xixm+CmJmEcM3m/KbtxBNh2E+r7IudFD4=; b=A17okJ8RgyfMuqPVF4nsUMTNtE6UCkp7Lg9kj2xY6svgv9VFRuxUwrUG/jhgL2A6aX y7favy1qA9rapWw2uYqYbHzd/IYWkOrz5WtTD0B43U7hsprmqFAvdJASb+TIi5zI5vJN P+vFM8zeNu7C1wo4R91aNrKNwbJl3d0v73tA95CmdRy3mE7+aXAbjEd09bwEAeFbowow XpBzvMMTZFSb8BTNvWEGMl4NkXxtOtS7iJxm8J3BYRWr9rr2vAeEZf4XrNeG4WyMcN8/ xp56CfrLmHIR1V1XKpAAckN5B2L64abdgP8eN668v/KIhhIijusCMJ+IJseuyiig9HI2 v1PQ== X-Gm-Message-State: AOJu0YwOCZ4vwgNuqcMFHOapvXQg5iVgi+VWuiN8MoYdGehdDyWYlpZw 7OGXVMXKi9eFtQ+yEBTFGyW2yk5+uF5vtXIX1++DhpzxEuQQYZmPFbtCx8sIW6U= X-Google-Smtp-Source: AGHT+IFZxVchAXAfLQIn8QiWKiuD4HWs4BPKHmCzu518ih7OsipVFzZjmc88iWQgOy+6/7RuKKdgYw== X-Received: by 2002:a05:600c:3513:b0:40e:4672:5227 with SMTP id h19-20020a05600c351300b0040e46725227mr1931625wmq.96.1705866324560; Sun, 21 Jan 2024 11:45:24 -0800 (PST) Received: from localhost.localdomain (byv51.neoplus.adsl.tpnet.pl. [83.30.41.51]) by smtp.gmail.com with ESMTPSA id k6-20020a170906128600b00a2b0b0fc80esm12547134ejb.193.2024.01.21.11.45.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Jan 2024 11:45:24 -0800 (PST) From: Adam Skladowski To: Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Adam Skladowski , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Krishna Manikandan , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/8] arm64: dts: qcom: msm8976: Add MDSS nodes Date: Sun, 21 Jan 2024 20:41:02 +0100 Message-Id: <20240121194221.13513-5-a39.skl@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240121194221.13513-1-a39.skl@gmail.com> References: <20240121194221.13513-1-a39.skl@gmail.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add MDSS nodes to support displays on MSM8976 SoC. Signed-off-by: Adam Skladowski --- arch/arm64/boot/dts/qcom/msm8976.dtsi | 268 +++++++++++++++++++++++++- 1 file changed, 264 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8976.dtsi b/arch/arm64/boot/dts/qcom/msm8976.dtsi index 118174cfd4d3..2d71ce34f00e 100644 --- a/arch/arm64/boot/dts/qcom/msm8976.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8976.dtsi @@ -785,10 +785,10 @@ gcc: clock-controller@1800000 { clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&rpmcc RPM_SMD_XO_A_CLK_SRC>, - <0>, - <0>, - <0>, - <0>; + <&mdss_dsi0_phy 1>, + <&mdss_dsi0_phy 0>, + <&mdss_dsi1_phy 1>, + <&mdss_dsi1_phy 0>; clock-names = "xo", "xo_a", "dsi0pll", @@ -808,6 +808,266 @@ tcsr: syscon@1937000 { reg = <0x01937000 0x30000>; }; + mdss: display-subsystem@1a00000 { + compatible = "qcom,mdss"; + + reg = <0x01a00000 0x1000>, + <0x01ab0000 0x3000>; + reg-names = "mdss_phys", "vbif_phys"; + + power-domains = <&gcc MDSS_GDSC>; + interrupts = ; + + interrupt-controller; + #interrupt-cells = <1>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>, + <&gcc GCC_MDSS_MDP_CLK>; + clock-names = "iface", + "bus", + "vsync", + "core"; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + status = "disabled"; + + mdss_mdp: display-controller@1a01000 { + compatible = "qcom,msm8976-mdp5", "qcom,mdp5"; + reg = <0x01a01000 0x89000>; + reg-names = "mdp_phys"; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>, + <&gcc GCC_MDP_TBU_CLK>, + <&gcc GCC_MDP_RT_TBU_CLK>; + clock-names = "iface", + "bus", + "core", + "vsync", + "tbu", + "tbu_rt"; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&gcc MDSS_GDSC>; + + iommus = <&apps_iommu 22>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_mdp5_intf1_out: endpoint { + remote-endpoint = <&mdss_dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + mdss_mdp5_intf2_out: endpoint { + remote-endpoint = <&mdss_dsi1_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-177780000 { + opp-hz = /bits/ 64 <177780000>; + required-opps = <&rpmpd_opp_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmpd_opp_svs_plus>; + }; + + opp-320000000 { + opp-hz = /bits/ 64 <320000000>; + required-opps = <&rpmpd_opp_nom>; + }; + opp-360000000 { + opp-hz = /bits/ 64 <360000000>; + required-opps = <&rpmpd_opp_turbo>; + }; + }; + }; + + mdss_dsi0: dsi@1a94000 { + compatible = "qcom,msm8976-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x01a94000 0x25c>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_BYTE0_CLK>, + <&gcc GCC_MDSS_PCLK0_CLK>, + <&gcc GCC_MDSS_ESC0_CLK>; + clock-names = "mdp_core", + "iface", + "bus", + "byte", + "pixel", + "core"; + + assigned-clocks = <&gcc GCC_MDSS_BYTE0_CLK_SRC>, + <&gcc GCC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>; + + phys = <&mdss_dsi0_phy>; + + operating-points-v2 = <&dsi0_opp_table>; + power-domains = <&gcc MDSS_GDSC>; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dsi0_in: endpoint { + remote-endpoint = <&mdss_mdp5_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dsi0_out: endpoint { + }; + }; + }; + + dsi0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-125000000 { + opp-hz = /bits/ 64 <125000000>; + required-opps = <&rpmpd_opp_svs>; + + }; + + opp-161250000 { + opp-hz = /bits/ 64 <161250000>; + required-opps = <&rpmpd_opp_svs_plus>; + }; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmpd_opp_nom>; + }; + }; + }; + + mdss_dsi1: dsi@1a96000 { + compatible = "qcom,msm8976-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x01a96000 0x300>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <5>; + + clocks = <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_BYTE1_CLK>, + <&gcc GCC_MDSS_PCLK1_CLK>, + <&gcc GCC_MDSS_ESC1_CLK>; + clock-names = "mdp_core", + "iface", + "bus", + "byte", + "pixel", + "core"; + + assigned-clocks = <&gcc GCC_MDSS_BYTE1_CLK_SRC>, + <&gcc GCC_MDSS_PCLK1_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi1_phy 0>, + <&mdss_dsi1_phy 1>; + + phys = <&mdss_dsi1_phy>; + + power-domains = <&gcc MDSS_GDSC>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dsi1_in: endpoint { + remote-endpoint = <&mdss_mdp5_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dsi1_out: endpoint { + }; + }; + }; + }; + + mdss_dsi0_phy: phy@1a94a00 { + compatible = "qcom,dsi-phy-28nm-hpm-fam-b"; + reg = <0x01a94a00 0xd4>, + <0x01a94400 0x280>, + <0x01a94b80 0x30>; + reg-names = "dsi_pll", + "dsi_phy", + "dsi_phy_regulator"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + + mdss_dsi1_phy: phy@1a96a00 { + compatible = "qcom,dsi-phy-28nm-hpm-fam-b"; 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[83.30.41.51]) by smtp.gmail.com with ESMTPSA id k6-20020a170906128600b00a2b0b0fc80esm12547134ejb.193.2024.01.21.11.45.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Jan 2024 11:45:36 -0800 (PST) From: Adam Skladowski To: Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Adam Skladowski , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Krishna Manikandan , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 5/8] dt-bindings: drm/msm/gpu: Document AON clock for A506/A510 Date: Sun, 21 Jan 2024 20:41:03 +0100 Message-Id: <20240121194221.13513-6-a39.skl@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240121194221.13513-1-a39.skl@gmail.com> References: <20240121194221.13513-1-a39.skl@gmail.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Adreno 506(MSM8953) and Adreno 510(MSM8976) require Always-on branch clock to be enabled, describe it. Signed-off-by: Adam Skladowski --- Documentation/devicetree/bindings/display/msm/gpu.yaml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Documentation/devicetree/bindings/display/msm/gpu.yaml index b019db954793..9e36f54a5caf 100644 --- a/Documentation/devicetree/bindings/display/msm/gpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml @@ -133,7 +133,7 @@ allOf: properties: clocks: minItems: 2 - maxItems: 7 + maxItems: 8 clock-names: items: @@ -148,6 +148,8 @@ allOf: description: GPU Memory Interface clock - const: alt_mem_iface description: GPU Alternative Memory Interface clock + - const: alwayson + description: GPU Always-On clock - const: gfx3d description: GPU 3D engine clock - const: rbbmtimer @@ -155,7 +157,7 @@ allOf: - const: rbcpr description: GPU RB Core Power Reduction clock minItems: 2 - maxItems: 7 + maxItems: 8 required: - clocks From patchwork Sun Jan 21 19:41:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Skladowski X-Patchwork-Id: 764516 Received: from mail-ej1-f54.google.com (mail-ej1-f54.google.com [209.85.218.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 713E238F97; Sun, 21 Jan 2024 19:45:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705866351; cv=none; b=Lmtw/V/IDHnihxjdfnhviTLN4iokSKwNMDIpopuviqgjldwzj9cRtBc8JzzunQIHeZ4IwvDm4kccIM/mh809pKfaVVyYkVXsuNRF13PdzUkmNayzL6wmF7yBZQdUt4P5NBIQ+OgHkFQTIqeZqABA+XxaRUVynxdscGX8KeYyCqw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705866351; c=relaxed/simple; bh=jiG8dNM4EeCqicvJq35Mwv8i8fdhtFDvlbFQpXu1o1o=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ga3ZdKol7jUZ6qlUJbIQUJtYkji0OP3/FyhKFtAaIAusJFr5/DNy+I4MWJXiiqSCXAKJuRnMg2T9Id0DuDYVbzHgC0Nrx7JkPXLrd6dPR9hGKg9+UIR7xjLfjMP6ja0eEJ1mzeKzRokFzTaFBYOSH8uI/MK/QMcW6AG2MiIpAu8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=L2qZz7Ie; arc=none smtp.client-ip=209.85.218.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="L2qZz7Ie" Received: by mail-ej1-f54.google.com with SMTP id a640c23a62f3a-a3046221b0eso22095266b.1; Sun, 21 Jan 2024 11:45:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1705866347; x=1706471147; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RSqr1Vk76fk8EOA0eDt1nJ6pOVxZRQ6awuBBes4l838=; b=L2qZz7IebjbkAMEBRU9dwlq/SpT2DD1LnR9sfr2N7iV1c+7XxIrj9Rt+sXUl7Vwiq+ T53DUX5zr3TnRFnZGydxr+uzbG0vGu+W/zuPX1IXPGTHMCBE+OWiOO6MJ8zlSl3qo4lj QMmJn0+PdgY+aFYnC0GsKVhXZyRT8DFIrvBSBDHhIbG+0mgrYxknV4Ijj9A/rwHubgHV 9zGNW1pcyLPr9jBwfTBUNwhFFCqV9Y73oLlur5KNs1+kCtfkJs5jn5om/lC4rUAdpW/P WClB6KhBoE871yhDbA16A95SmTTZyKckweANK786oysb7cneZNvxVZRl8h2Pb5cKSQPp FqUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1705866347; x=1706471147; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RSqr1Vk76fk8EOA0eDt1nJ6pOVxZRQ6awuBBes4l838=; b=W+Gp8K6psLyOASJlwxmqLgP8MfPtscnbGfQFFpLtsiC639oMBoPHN3y/BpPq5ZoTp0 oM+2AaG+wIdOq0omxKAAyWQvzw5B3CjRqUXYpDnghZTocX0TCygGtVGYv6hrgtKOm+eE LYQgcbY1kysDq2DzmhYOz/3hnGzpZqDwL8OruzECDpxhFzcl0S3yLsVXv9Dlh7H4NjTU SG3vmqxUgzG0Ve0UZJpkmDJk61IUMPh3OzDoofjHTFnUYwdgySqKEdGNtm0SCPFV0yeF N0AHCC/UHqAQ2p/9Y5C4spEH/VYoGRck5J5ZnTG5TYLSCgyP4FBfCV4/+NG7kHnip98K 8pOQ== X-Gm-Message-State: AOJu0YwEwT1uDbc/SYY341MAhbxWKJu1memlpGUB8TzpGTGw2mOwYNfN VrcAu/YUpntBP7tgmIX384Uef9r8tDA1JQBSbT9Jl07ppx/ORI+t6z+xsSeFlBY= X-Google-Smtp-Source: AGHT+IGsCmZv1novA+/rF0kwFG7flhcKuCUpSzseVeBQ6O+PKFUlzXtm9pZWAynzdjUeKyHkgZsWqw== X-Received: by 2002:a17:906:f24c:b0:a28:fc03:f199 with SMTP id gy12-20020a170906f24c00b00a28fc03f199mr1456478ejb.107.1705866347749; Sun, 21 Jan 2024 11:45:47 -0800 (PST) Received: from localhost.localdomain (byv51.neoplus.adsl.tpnet.pl. [83.30.41.51]) by smtp.gmail.com with ESMTPSA id k6-20020a170906128600b00a2b0b0fc80esm12547134ejb.193.2024.01.21.11.45.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Jan 2024 11:45:47 -0800 (PST) From: Adam Skladowski To: Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Adam Skladowski , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Krishna Manikandan , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 6/8] arm64: dts: qcom: msm8976: Add Adreno GPU Date: Sun, 21 Jan 2024 20:41:04 +0100 Message-Id: <20240121194221.13513-7-a39.skl@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240121194221.13513-1-a39.skl@gmail.com> References: <20240121194221.13513-1-a39.skl@gmail.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add Adreno GPU node. Signed-off-by: Adam Skladowski --- arch/arm64/boot/dts/qcom/msm8976.dtsi | 66 +++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8976.dtsi b/arch/arm64/boot/dts/qcom/msm8976.dtsi index 2d71ce34f00e..765c90ac14cb 100644 --- a/arch/arm64/boot/dts/qcom/msm8976.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8976.dtsi @@ -1068,6 +1068,72 @@ mdss_dsi1_phy: phy@1a96a00 { }; }; + adreno_gpu: gpu@1c00000 { + compatible = "qcom,adreno-510.0", "qcom,adreno"; + + reg = <0x01c00000 0x40000>; + reg-names = "kgsl_3d0_reg_memory"; + + interrupts = ; + interrupt-names = "kgsl_3d0_irq"; + + clock-names = "core", + "iface", + "mem", + "mem_iface", + "rbbmtimer", + "alwayson"; + + clocks = <&gcc GCC_GFX3D_OXILI_CLK>, + <&gcc GCC_GFX3D_OXILI_AHB_CLK>, + <&gcc GCC_GFX3D_OXILI_GMEM_CLK>, + <&gcc GCC_GFX3D_BIMC_CLK>, + <&gcc GCC_GFX3D_OXILI_TIMER_CLK>, + <&gcc GCC_GFX3D_OXILI_AON_CLK>; + + power-domains = <&rpmpd MSM8976_VDDCX>; + + iommus = <&gpu_iommu 0>; + + status = "disabled"; + + operating-points-v2 = <&gpu_opp_table>; + + gpu_opp_table: opp-table { + compatible ="operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-level = ; + opp-supported-hw = <0xff>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-level = ; + opp-supported-hw = <0xff>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-level = ; + opp-supported-hw = <0xff>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + opp-level = ; + opp-supported-hw = <0xff>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + opp-level = ; + opp-supported-hw = <0xff>; + }; + }; + }; + apps_iommu: iommu@1e20000 { compatible = "qcom,msm8976-iommu", "qcom,msm-iommu-v2"; ranges = <0 0x01e20000 0x20000>; From patchwork Sun Jan 21 19:41:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Skladowski X-Patchwork-Id: 764820 Received: from mail-ed1-f51.google.com (mail-ed1-f51.google.com [209.85.208.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4199938381; 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[83.30.41.51]) by smtp.gmail.com with ESMTPSA id k6-20020a170906128600b00a2b0b0fc80esm12547134ejb.193.2024.01.21.11.45.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Jan 2024 11:45:58 -0800 (PST) From: Adam Skladowski To: Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Adam Skladowski , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Krishna Manikandan , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 7/8] arm64: dts: qcom: msm8976: Declare and wire SDC pins Date: Sun, 21 Jan 2024 20:41:05 +0100 Message-Id: <20240121194221.13513-8-a39.skl@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240121194221.13513-1-a39.skl@gmail.com> References: <20240121194221.13513-1-a39.skl@gmail.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Declare pinctrls for SDC pins and wire them to consumers. Signed-off-by: Adam Skladowski --- arch/arm64/boot/dts/qcom/msm8976.dtsi | 100 ++++++++++++++++++++++++++ 1 file changed, 100 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8976.dtsi b/arch/arm64/boot/dts/qcom/msm8976.dtsi index 765c90ac14cb..5a7be93a0115 100644 --- a/arch/arm64/boot/dts/qcom/msm8976.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8976.dtsi @@ -771,6 +771,96 @@ blsp2_i2c4_sleep: blsp2-i2c4-sleep-state { drive-strength = <2>; bias-disable; }; + + sdc1_default: sdc1-default-state { + clk-pins { + pins = "sdc1_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd-pins { + pins = "sdc1_cmd"; + drive-strength = <10>; + bias-pull-up; + }; + + data-pins { + pins = "sdc1_data"; + drive-strength = <10>; + bias-pull-up; + }; + + rclk-pins { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc1_sleep: sdc1-sleep-state { + clk-pins { + pins = "sdc1_clk"; + drive-strength = <2>; + bias-disable; + }; + + cmd-pins { + pins = "sdc1_cmd"; + drive-strength = <2>; + bias-pull-up; + }; + + data-pins { + pins = "sdc1_data"; + drive-strength = <2>; + bias-pull-up; + }; + + rclk-pins { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc2_default: sdc2-default-state { + clk-pins { + pins = "sdc2_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd-pins { + pins = "sdc2_cmd"; + drive-strength = <10>; + bias-pull-up; + }; + + data-pins { + pins = "sdc2_data"; + drive-strength = <10>; + bias-pull-up; + }; + }; + + sdc2_sleep: sdc2-sleep-state { + clk-pins { + pins = "sdc2_clk"; + drive-strength = <2>; + bias-disable; + }; + + cmd-pins { + pins = "sdc2_cmd"; + drive-strength = <2>; + bias-pull-up; + }; + + data-pins { + pins = "sdc2_data"; + drive-strength = <2>; + bias-pull-up; + }; + }; }; gcc: clock-controller@1800000 { @@ -1246,6 +1336,11 @@ sdhc_1: mmc@7824900 { <&gcc GCC_SDCC1_APPS_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; clock-names = "iface", "core", "xo"; + + pinctrl-0 = <&sdc1_default>; + pinctrl-1 = <&sdc1_sleep>; + pinctrl-names = "default", "sleep"; + status = "disabled"; }; @@ -1262,6 +1357,11 @@ sdhc_2: mmc@7864900 { <&gcc GCC_SDCC2_APPS_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; clock-names = "iface", "core", "xo"; + + pinctrl-0 = <&sdc2_default>; + pinctrl-1 = <&sdc2_sleep>; + pinctrl-names = "default", "sleep"; + status = "disabled"; }; From patchwork Sun Jan 21 19:41:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Skladowski X-Patchwork-Id: 764515 Received: from mail-ej1-f44.google.com (mail-ej1-f44.google.com [209.85.218.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 665943839C; Sun, 21 Jan 2024 19:46:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705866375; cv=none; b=d2aF7IkVSAGD8PUeEbqp7U+G/+cG8uY30772vywZ+g/F0W1/fI/OMyxq31xn1zbuxOF2g0rrh4GcSHtYjDm3oMouEUYGXPJAVnsg0C4sdhm6m/t79eA2ay0S3bnquoSK1LYb+Xoo92ZDpP5QPBoX74O+2Obf73lgf3RSj/cfS+U= ARC-Message-Signature: i=1; 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[83.30.41.51]) by smtp.gmail.com with ESMTPSA id k6-20020a170906128600b00a2b0b0fc80esm12547134ejb.193.2024.01.21.11.46.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Jan 2024 11:46:11 -0800 (PST) From: Adam Skladowski To: Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Adam Skladowski , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Krishna Manikandan , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 8/8] arm64: dts: qcom: msm8976: Add WCNSS node Date: Sun, 21 Jan 2024 20:41:06 +0100 Message-Id: <20240121194221.13513-9-a39.skl@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240121194221.13513-1-a39.skl@gmail.com> References: <20240121194221.13513-1-a39.skl@gmail.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add node describing wireless connectivity subsystem. Signed-off-by: Adam Skladowski --- arch/arm64/boot/dts/qcom/msm8976.dtsi | 96 +++++++++++++++++++++++++++ 1 file changed, 96 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8976.dtsi b/arch/arm64/boot/dts/qcom/msm8976.dtsi index 5a7be93a0115..73ddfaecd3ad 100644 --- a/arch/arm64/boot/dts/qcom/msm8976.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8976.dtsi @@ -861,6 +861,36 @@ data-pins { bias-pull-up; }; }; + + wcss_wlan_default: wcss-wlan-default-state { + wcss_wlan2-pins { + pins = "gpio40"; + function = "wcss_wlan2"; + drive-strength = <6>; + bias-pull-up; + }; + + wcss_wlan1-pins { + pins = "gpio41"; + function = "wcss_wlan1"; + drive-strength = <6>; + bias-pull-up; + }; + + wcss_wlan0-pins { + pins = "gpio42"; + function = "wcss_wlan0"; + drive-strength = <6>; + bias-pull-up; + }; + + wcss_wlan-pins { + pins = "gpio43", "gpio44"; + function = "wcss_wlan"; + drive-strength = <6>; + bias-pull-up; + }; + }; }; gcc: clock-controller@1800000 { @@ -1540,6 +1570,72 @@ blsp2_i2c4: i2c@7af8000 { status = "disabled"; }; + wcnss: remoteproc@a204000 { + compatible = "qcom,pronto-v3-pil", "qcom,pronto"; + reg = <0xa204000 0x2000>, <0xa202000 0x1000>, <0xa21b000 0x3000>; + reg-names = "ccu", "dxe", "pmu"; + + memory-region = <&wcnss_fw_mem>; + + interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; + + power-domains = <&rpmpd MSM8976_VDDCX>, + <&rpmpd MSM8976_VDDMX>; + power-domain-names = "cx", "mx"; + + qcom,smem-states = <&wcnss_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + pinctrl-names = "default"; + pinctrl-0 = <&wcss_wlan_default>; + + status = "disabled"; + + wcnss_iris: iris { + /* Separate chip, compatible is board-specific */ + clocks = <&rpmcc RPM_SMD_RF_CLK2>; + clock-names = "xo"; + }; + + smd-edge { + interrupts = ; + + qcom,ipc = <&apcs 8 17>; + qcom,smd-edge = <6>; + qcom,remote-pid = <4>; + + label = "pronto"; + + wcnss_ctrl: wcnss { + compatible = "qcom,wcnss"; + qcom,smd-channels = "WCNSS_CTRL"; + + qcom,mmio = <&wcnss>; + + wcnss_bt: bluetooth { + compatible = "qcom,wcnss-bt"; + }; + + wcnss_wifi: wifi { + compatible = "qcom,wcnss-wlan"; + + interrupts = , + ; + interrupt-names = "tx", "rx"; + + qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; + qcom,smem-state-names = "tx-enable", + "tx-rings-empty"; + }; + }; + }; + }; + intc: interrupt-controller@b000000 { compatible = "qcom,msm-qgic2"; reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;